From af1a266670d040d2f4083ff309d732d648afba2a Mon Sep 17 00:00:00 2001 From: Angelos Mouzakitis Date: Tue, 10 Oct 2023 14:33:42 +0000 Subject: Add submodule dependency files Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec --- roms/u-boot/drivers/ram/Kconfig | 102 + roms/u-boot/drivers/ram/Makefile | 24 + roms/u-boot/drivers/ram/aspeed/Kconfig | 69 + roms/u-boot/drivers/ram/aspeed/Makefile | 4 + roms/u-boot/drivers/ram/aspeed/sdram_ast2500.c | 440 + roms/u-boot/drivers/ram/aspeed/sdram_ast2600.c | 1062 ++ roms/u-boot/drivers/ram/bmips_ram.c | 177 + roms/u-boot/drivers/ram/imxrt_sdram.c | 445 + roms/u-boot/drivers/ram/k3-am654-ddrss.c | 1086 ++ roms/u-boot/drivers/ram/k3-am654-ddrss.h | 1200 ++ .../drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h | 108 + .../ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h | 14 + .../ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h | 15 + .../k3-ddrss/16bit/lpddr4_address_slice_0_macros.h | 624 ++ .../k3-ddrss/16bit/lpddr4_address_slice_1_macros.h | 624 ++ .../k3-ddrss/16bit/lpddr4_address_slice_2_macros.h | 624 ++ .../drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h | 1306 +++ .../ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h | 23 + .../k3-ddrss/16bit/lpddr4_data_slice_0_macros.h | 2036 ++++ .../k3-ddrss/16bit/lpddr4_data_slice_1_macros.h | 2036 ++++ .../k3-ddrss/16bit/lpddr4_ddr_controller_macros.h | 6436 +++++++++++ .../ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h | 1838 ++++ .../drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h | 5784 ++++++++++ .../drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h | 91 + .../ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h | 14 + .../ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h | 15 + .../k3-ddrss/32bit/lpddr4_address_slice_0_macros.h | 824 ++ .../drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h | 1545 +++ .../ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h | 23 + .../k3-ddrss/32bit/lpddr4_data_slice_0_macros.h | 2372 ++++ .../k3-ddrss/32bit/lpddr4_data_slice_1_macros.h | 2372 ++++ .../k3-ddrss/32bit/lpddr4_data_slice_2_macros.h | 2372 ++++ .../k3-ddrss/32bit/lpddr4_data_slice_3_macros.h | 2372 ++++ .../k3-ddrss/32bit/lpddr4_ddr_controller_macros.h | 7792 +++++++++++++ .../ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h | 2060 ++++ .../drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h | 5396 +++++++++ roms/u-boot/drivers/ram/k3-ddrss/Makefile | 17 + roms/u-boot/drivers/ram/k3-ddrss/cps_drv_lpddr4.h | 102 + roms/u-boot/drivers/ram/k3-ddrss/k3-ddrss.c | 478 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4.c | 1079 ++ roms/u-boot/drivers/ram/k3-ddrss/lpddr4.h | 73 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.c | 396 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.h | 33 + .../ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c | 1309 +++ .../drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h | 257 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.c | 302 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.h | 30 + .../ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c | 1548 +++ .../drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h | 223 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_if.h | 144 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.c | 51 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.h | 86 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_private.h | 60 + roms/u-boot/drivers/ram/k3-ddrss/lpddr4_sanity.h | 445 + .../drivers/ram/k3-ddrss/lpddr4_structs_if.h | 51 + roms/u-boot/drivers/ram/mediatek/Makefile | 7 + roms/u-boot/drivers/ram/mediatek/ddr3-mt7629.c | 768 ++ roms/u-boot/drivers/ram/mpc83xx_sdram.c | 1100 ++ roms/u-boot/drivers/ram/octeon/Kconfig | 17 + roms/u-boot/drivers/ram/octeon/Makefile | 8 + roms/u-boot/drivers/ram/octeon/dimm_spd_eeprom.c | 407 + roms/u-boot/drivers/ram/octeon/octeon3_lmc.c | 11024 +++++++++++++++++++ roms/u-boot/drivers/ram/octeon/octeon_ddr.c | 2729 +++++ roms/u-boot/drivers/ram/ram-uclass.c | 27 + roms/u-boot/drivers/ram/rockchip/Kconfig | 52 + roms/u-boot/drivers/ram/rockchip/Makefile | 15 + roms/u-boot/drivers/ram/rockchip/dmc-rk3368.c | 1006 ++ .../ram/rockchip/sdram-px30-ddr3-detect-333.inc | 72 + .../ram/rockchip/sdram-px30-ddr4-detect-333.inc | 75 + .../drivers/ram/rockchip/sdram-px30-ddr_skew.inc | 121 + .../ram/rockchip/sdram-px30-lpddr2-detect-333.inc | 73 + .../ram/rockchip/sdram-px30-lpddr3-detect-333.inc | 74 + .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1586 +++ .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1586 +++ roms/u-boot/drivers/ram/rockchip/sdram_common.c | 442 + roms/u-boot/drivers/ram/rockchip/sdram_pctl_px30.c | 206 + roms/u-boot/drivers/ram/rockchip/sdram_phy_px30.c | 206 + roms/u-boot/drivers/ram/rockchip/sdram_px30.c | 762 ++ roms/u-boot/drivers/ram/rockchip/sdram_rk3128.c | 58 + roms/u-boot/drivers/ram/rockchip/sdram_rk3188.c | 960 ++ roms/u-boot/drivers/ram/rockchip/sdram_rk322x.c | 855 ++ roms/u-boot/drivers/ram/rockchip/sdram_rk3288.c | 1130 ++ roms/u-boot/drivers/ram/rockchip/sdram_rk3308.c | 55 + roms/u-boot/drivers/ram/rockchip/sdram_rk3328.c | 621 ++ roms/u-boot/drivers/ram/rockchip/sdram_rk3399.c | 3185 ++++++ roms/u-boot/drivers/ram/sandbox_ram.c | 38 + roms/u-boot/drivers/ram/sifive/Kconfig | 13 + roms/u-boot/drivers/ram/sifive/Makefile | 6 + roms/u-boot/drivers/ram/sifive/sifive_ddr.c | 411 + roms/u-boot/drivers/ram/stm32_sdram.c | 418 + roms/u-boot/drivers/ram/stm32mp1/Kconfig | 49 + roms/u-boot/drivers/ram/stm32mp1/Makefile | 15 + roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.c | 846 ++ roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.h | 206 + .../drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 369 + .../drivers/ram/stm32mp1/stm32mp1_interactive.c | 497 + roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ram.c | 243 + roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.c | 1504 +++ roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.h | 34 + roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tuning.c | 1540 +++ 100 files changed, 95425 insertions(+) create mode 100644 roms/u-boot/drivers/ram/Kconfig create mode 100644 roms/u-boot/drivers/ram/Makefile create mode 100644 roms/u-boot/drivers/ram/aspeed/Kconfig create mode 100644 roms/u-boot/drivers/ram/aspeed/Makefile create mode 100644 roms/u-boot/drivers/ram/aspeed/sdram_ast2500.c create mode 100644 roms/u-boot/drivers/ram/aspeed/sdram_ast2600.c create mode 100644 roms/u-boot/drivers/ram/bmips_ram.c create mode 100644 roms/u-boot/drivers/ram/imxrt_sdram.c create mode 100644 roms/u-boot/drivers/ram/k3-am654-ddrss.c create mode 100644 roms/u-boot/drivers/ram/k3-am654-ddrss.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/Makefile create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/cps_drv_lpddr4.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/k3-ddrss.c create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4.c create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.c create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.c create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.c create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_private.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_sanity.h create mode 100644 roms/u-boot/drivers/ram/k3-ddrss/lpddr4_structs_if.h create mode 100644 roms/u-boot/drivers/ram/mediatek/Makefile create mode 100644 roms/u-boot/drivers/ram/mediatek/ddr3-mt7629.c create mode 100644 roms/u-boot/drivers/ram/mpc83xx_sdram.c create mode 100644 roms/u-boot/drivers/ram/octeon/Kconfig create mode 100644 roms/u-boot/drivers/ram/octeon/Makefile create mode 100644 roms/u-boot/drivers/ram/octeon/dimm_spd_eeprom.c create mode 100644 roms/u-boot/drivers/ram/octeon/octeon3_lmc.c create mode 100644 roms/u-boot/drivers/ram/octeon/octeon_ddr.c create mode 100644 roms/u-boot/drivers/ram/ram-uclass.c create mode 100644 roms/u-boot/drivers/ram/rockchip/Kconfig create mode 100644 roms/u-boot/drivers/ram/rockchip/Makefile create mode 100644 roms/u-boot/drivers/ram/rockchip/dmc-rk3368.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr3-detect-333.inc create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr4-detect-333.inc create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr_skew.inc create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr2-detect-333.inc create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_common.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_pctl_px30.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_phy_px30.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_px30.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_rk3128.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_rk3188.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_rk322x.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_rk3288.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_rk3308.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_rk3328.c create mode 100644 roms/u-boot/drivers/ram/rockchip/sdram_rk3399.c create mode 100644 roms/u-boot/drivers/ram/sandbox_ram.c create mode 100644 roms/u-boot/drivers/ram/sifive/Kconfig create mode 100644 roms/u-boot/drivers/ram/sifive/Makefile create mode 100644 roms/u-boot/drivers/ram/sifive/sifive_ddr.c create mode 100644 roms/u-boot/drivers/ram/stm32_sdram.c create mode 100644 roms/u-boot/drivers/ram/stm32mp1/Kconfig create mode 100644 roms/u-boot/drivers/ram/stm32mp1/Makefile create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.c create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.h create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_interactive.c create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ram.c create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.c create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.h create mode 100644 roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tuning.c (limited to 'roms/u-boot/drivers/ram') diff --git a/roms/u-boot/drivers/ram/Kconfig b/roms/u-boot/drivers/ram/Kconfig new file mode 100644 index 000000000..a79594d35 --- /dev/null +++ b/roms/u-boot/drivers/ram/Kconfig @@ -0,0 +1,102 @@ +config RAM + bool "Enable RAM drivers using Driver Model" + depends on DM + help + This allows drivers to be provided for SDRAM and other RAM + controllers and their type to be specified in the board's device + tree. Generally some parameters are required to set up the RAM and + the RAM size can either be statically defined or dynamically + detected. + +config SPL_RAM + bool "Enable RAM support in SPL" + depends on RAM && SPL_DM + help + The RAM subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use RAM drivers in + SPL, enable this option. It might provide a cleaner interface to + setting up RAM (e.g. SDRAM / DDR) within SPL. + +config TPL_RAM + bool "Enable RAM support in TPL" + depends on RAM + help + The RAM subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use RAM drivers in + TPL, enable this option. It might provide a cleaner interface to + setting up RAM (e.g. SDRAM / DDR) within TPL. + +config STM32_SDRAM + bool "Enable STM32 SDRAM support" + depends on RAM + help + STM32F7 family devices support flexible memory controller(FMC) to + support external memories like sdram, psram & nand. + This driver is for the sdram memory interface with the FMC. + +config MPC83XX_SDRAM + bool "Enable MPC83XX SDRAM support" + depends on RAM + help + Enable support for the internal DDR Memory Controller of the MPC83xx + family of SoCs. Both static configurations, as well as configuring + the RAM through the use of SPD (Serial Presence Detect) is supported + via device tree settings. + +config K3_AM654_DDRSS + bool "Enable AM654 DDRSS support" + depends on RAM && SOC_K3_AM6 + help + K3 based AM654 devices has DDR memory subsystem that comprises + Synopys DDR controller, Synopsis DDR phy and wrapper logic to + intergrate these blocks into the device. This DDR subsystem + provides an interface to external SDRAM devices. Enabling this + config add support for the initialization of the external + SDRAM devices connected to DDR subsystem. + +config K3_DDRSS + bool "Enable K3 DDRSS support" + depends on RAM + +choice + depends on K3_DDRSS + prompt "K3 DDRSS Arch Support" + + default K3_J721E_DDRSS if SOC_K3_J721E + default K3_AM64_DDRSS if SOC_K3_AM642 + +config K3_J721E_DDRSS + bool "Enable J721E DDRSS support" + help + The J721E DDR subsystem comprises DDR controller, DDR PHY and + wrapper logic to integrate these blocks in the device. The DDR + subsystem is used to provide an interface to external SDRAM + devices which can be utilized for storing program or data. + Enabling this config adds support for the DDR memory controller + on J721E family of SoCs. + +config K3_AM64_DDRSS + bool "Enable AM64 DDRSS support" + help + The AM64 DDR subsystem comprises DDR controller, DDR PHY and + wrapper logic to integrate these blocks in the device. The DDR + subsystem is used to provide an interface to external SDRAM + devices which can be utilized for storing program or data. + Enabling this config adds support for the DDR memory controller + on AM642 family of SoCs. + +endchoice + +config IMXRT_SDRAM + bool "Enable i.MXRT SDRAM support" + depends on RAM + help + i.MXRT family devices support smart external memory controller(SEMC) + to support external memories like sdram, psram & nand. + This driver is for the sdram memory interface with the SEMC. + +source "drivers/ram/aspeed/Kconfig" +source "drivers/ram/rockchip/Kconfig" +source "drivers/ram/sifive/Kconfig" +source "drivers/ram/stm32mp1/Kconfig" +source "drivers/ram/octeon/Kconfig" diff --git a/roms/u-boot/drivers/ram/Makefile b/roms/u-boot/drivers/ram/Makefile new file mode 100644 index 000000000..5a3961134 --- /dev/null +++ b/roms/u-boot/drivers/ram/Makefile @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2015 Google, Inc +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +obj-$(CONFIG_RAM) += ram-uclass.o +obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o +obj-$(CONFIG_SANDBOX) += sandbox_ram.o +obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ +obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o +obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o + +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ + +obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ +obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_K3_DDRSS) += k3-ddrss/ + +obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o + +obj-$(CONFIG_RAM_SIFIVE) += sifive/ + +obj-$(CONFIG_ARCH_OCTEON) += octeon/ diff --git a/roms/u-boot/drivers/ram/aspeed/Kconfig b/roms/u-boot/drivers/ram/aspeed/Kconfig new file mode 100644 index 000000000..049b9dc24 --- /dev/null +++ b/roms/u-boot/drivers/ram/aspeed/Kconfig @@ -0,0 +1,69 @@ +if RAM || SPL_RAM + +config ASPEED_DDR4_DUALX8 + bool "Enable Dual X8 DDR4 die" + depends on DM && OF_CONTROL && ARCH_ASPEED + default n + help + Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram + controller needs to know if the memory chip mounted on the board is dual + x8 die or not. Or it may get the wrong size of the memory space. + +if ASPEED_AST2600 + +choice + prompt "DDR4 target date rate" + default ASPEED_DDR4_1600 + +config ASPEED_DDR4_400 + bool "DDR4 targets at 400Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 400M + +config ASPEED_DDR4_800 + bool "DDR4 targets at 800Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 800M + +config ASPEED_DDR4_1333 + bool "DDR4 targets at 1333Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 1333M + +config ASPEED_DDR4_1600 + bool "DDR4 targets at 1600Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 1600M +endchoice + +config ASPEED_BYPASS_SELFTEST + bool "bypass self test during DRAM initialization" + default n + help + Say Y here to bypass DRAM self test to speed up the boot time + +config ASPEED_ECC + bool "aspeed SDRAM error correcting code" + depends on DM && OF_CONTROL && ARCH_ASPEED + default n + help + enable SDRAM ECC function + +if ASPEED_ECC +config ASPEED_ECC_SIZE + int "ECC size: 0=driver auto-caluated" + depends on ASPEED_ECC + default 0 + help + SDRAM size with the error correcting code enabled. The unit is + in Megabytes. Noted that only the 8/9 of the configured size + can be used by the system. The remaining 1/9 will be used by + the ECC engine. If the size is set to 0, the sdram driver will + calculate the SDRAM size and set the whole range be ECC enabled. +endif # end of ASPEED_ECC +endif # end of ASPEED_AST2600 +endif # end of RAM || SPL_RAM diff --git a/roms/u-boot/drivers/ram/aspeed/Makefile b/roms/u-boot/drivers/ram/aspeed/Makefile new file mode 100644 index 000000000..7ac10af1c --- /dev/null +++ b/roms/u-boot/drivers/ram/aspeed/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o +obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o diff --git a/roms/u-boot/drivers/ram/aspeed/sdram_ast2500.c b/roms/u-boot/drivers/ram/aspeed/sdram_ast2500.c new file mode 100644 index 000000000..141b19b57 --- /dev/null +++ b/roms/u-boot/drivers/ram/aspeed/sdram_ast2500.c @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * Copyright 2016 Google, Inc + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* These configuration parameters are taken from Aspeed SDK */ +#define DDR4_MR46_MODE 0x08000000 +#define DDR4_MR5_MODE 0x400 +#define DDR4_MR13_MODE 0x101 +#define DDR4_MR02_MODE 0x410 +#define DDR4_TRFC 0x45457188 + +#define PHY_CFG_SIZE 15 + +static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000}; +static const struct { + u32 index[PHY_CFG_SIZE]; + u32 value[PHY_CFG_SIZE]; +} ddr4_phy_config = { + .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50}, + .value = { + 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24, + 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607, + 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e, + }, +}; + +#define SDRAM_MAX_SIZE (1024 * 1024 * 1024) +#define SDRAM_MIN_SIZE (128 * 1024 * 1024) + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Bandwidth configuration parameters for different SDRAM requests. + * These are hardcoded settings taken from Aspeed SDK. + */ +static const u32 ddr_max_grant_params[4] = { + 0x88448844, 0x24422288, 0x22222222, 0x22222222 +}; + +/* + * These registers are not documented by Aspeed at all. + * All writes and reads are taken pretty much as is from SDK. + */ +struct ast2500_ddr_phy { + u32 phy[117]; +}; + +struct dram_info { + struct ram_info info; + struct clk ddr_clk; + struct ast2500_sdrammc_regs *regs; + struct ast2500_scu *scu; + struct ast2500_ddr_phy *phy; + ulong clock_rate; +}; + +static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy) +{ + writel(0, &phy->phy[2]); + writel(0, &phy->phy[6]); + writel(0, &phy->phy[8]); + writel(0, &phy->phy[10]); + writel(0, &phy->phy[12]); + writel(0, &phy->phy[42]); + writel(0, &phy->phy[44]); + + writel(0x86000000, &phy->phy[16]); + writel(0x00008600, &phy->phy[17]); + writel(0x80000000, &phy->phy[18]); + writel(0x80808080, &phy->phy[19]); + + return 0; +} + +static void ast2500_ddr_phy_init_process(struct dram_info *info) +{ + struct ast2500_sdrammc_regs *regs = info->regs; + + writel(0, ®s->phy_ctrl[0]); + writel(0x4040, &info->phy->phy[51]); + + writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); + while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) + ; + writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE, + ®s->phy_ctrl[0]); +} + +static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref) +{ + writel(0, &info->regs->phy_ctrl[0]); + writel((vref << 8) | 0x6, &info->phy->phy[48]); + ast2500_ddr_phy_init_process(info); +} + +static int ast2500_ddr_cbr_test(struct dram_info *info) +{ + struct ast2500_sdrammc_regs *regs = info->regs; + int i; + const u32 test_params = SDRAM_TEST_EN + | SDRAM_TEST_ERRSTOP + | SDRAM_TEST_TWO_MODES; + int ret = 0; + + writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) | + (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing); + writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); + writel(0xff00ff00, ®s->test_init_val); + writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) | + SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl); + + while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) + ; + + if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { + ret = -EIO; + } else { + for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) { + writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params, + ®s->ecc_test_ctrl); + while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) + ; + if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { + ret = -EIO; + break; + } + } + } + + writel(0, ®s->refresh_timing); + writel(0, ®s->ecc_test_ctrl); + + return ret; +} + +static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info) +{ + int i; + int vref_min = 0xff; + int vref_max = 0; + int range_size = 0; + + for (i = 1; i < 0x40; ++i) { + int res; + + ast2500_sdrammc_set_vref(info, i); + res = ast2500_ddr_cbr_test(info); + if (res < 0) { + if (range_size > 0) + break; + } else { + ++range_size; + vref_min = min(vref_min, i); + vref_max = max(vref_max, i); + } + } + + /* Pick average setting */ + ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2); + + return 0; +} + +static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info) +{ + size_t vga_mem_size_base = 8 * 1024 * 1024; + u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK) + >> SCU_HWSTRAP_VGAMEM_SHIFT; + + return vga_mem_size_base << vga_hwconf; +} + +/* + * Find out RAM size and save it in dram_info + * + * The procedure is taken from Aspeed SDK + */ +static void ast2500_sdrammc_calc_size(struct dram_info *info) +{ + /* The controller supports 128/256/512/1024 MB ram */ + size_t ram_size = SDRAM_MIN_SIZE; + const int write_test_offset = 0x100000; + u32 test_pattern = 0xdeadbeef; + u32 cap_param = SDRAM_CONF_CAP_1024M; + u32 refresh_timing_param = DDR4_TRFC; + const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + writel(test_pattern, write_addr_base + (ram_size >> 1)); + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + /* One last write to overwrite all wrapped values */ + writel(test_pattern, write_addr_base); + + /* Reset the pattern and see which value was really written */ + test_pattern = 0xdeadbeef; + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) + break; + + --cap_param; + refresh_timing_param >>= 8; + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + clrsetbits_le32(&info->regs->ac_timing[1], + (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), + ((refresh_timing_param & SDRAM_AC_TRFC_MASK) + << SDRAM_AC_TRFC_SHIFT)); + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); + clrsetbits_le32(&info->regs->config, + (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), + ((cap_param & SDRAM_CONF_CAP_MASK) + << SDRAM_CONF_CAP_SHIFT)); +} + +static int ast2500_sdrammc_init_ddr4(struct dram_info *info) +{ + int i; + const u32 power_control = SDRAM_PCR_CKE_EN + | (1 << SDRAM_PCR_CKE_DELAY_SHIFT) + | (2 << SDRAM_PCR_TCKE_PW_SHIFT) + | SDRAM_PCR_RESETN_DIS + | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN; + const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT) +#ifdef CONFIG_ASPEED_DDR4_DUALX8 + | SDRAM_CONF_DUALX8 +#endif + | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4; + int ret; + + writel(conf, &info->regs->config); + for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) + writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]); + + writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting); + writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting); + writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting); + writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting); + + for (i = 0; i < PHY_CFG_SIZE; ++i) { + writel(ddr4_phy_config.value[i], + &info->phy->phy[ddr4_phy_config.index[i]]); + } + + writel(power_control, &info->regs->power_control); + + ast2500_ddr_phy_init_process(info); + + ret = ast2500_sdrammc_ddr4_calibrate_vref(info); + if (ret < 0) { + debug("Vref calibration failed!\n"); + return ret; + } + + writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) + | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT), + &info->regs->refresh_timing); + + setbits_le32(&info->regs->power_control, + SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON); + + ast2500_sdrammc_calc_size(info); + + setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN); + while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE)) + ; + setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN); + + writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control); + + /* Enable all requests except video & display */ + writel(SDRAM_REQ_USB20_EHCI1 + | SDRAM_REQ_USB20_EHCI2 + | SDRAM_REQ_CPU + | SDRAM_REQ_AHB2 + | SDRAM_REQ_AHB + | SDRAM_REQ_MAC0 + | SDRAM_REQ_MAC1 + | SDRAM_REQ_PCIE + | SDRAM_REQ_XDMA + | SDRAM_REQ_ENCRYPTION + | SDRAM_REQ_VIDEO_FLAG + | SDRAM_REQ_VIDEO_LOW_PRI_WRITE + | SDRAM_REQ_2D_RW + | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask); + + return 0; +} + +static void ast2500_sdrammc_unlock(struct dram_info *info) +{ + writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (!readl(&info->regs->protection_key)) + ; +} + +static void ast2500_sdrammc_lock(struct dram_info *info) +{ + writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (readl(&info->regs->protection_key)) + ; +} + +static int ast2500_sdrammc_probe(struct udevice *dev) +{ + struct reset_ctl reset_ctl; + struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); + struct ast2500_sdrammc_regs *regs = priv->regs; + int i; + int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); + + if (ret) { + debug("DDR:No CLK\n"); + return ret; + } + + priv->scu = ast_get_scu(); + if (IS_ERR(priv->scu)) { + debug("%s(): can't get SCU\n", __func__); + return PTR_ERR(priv->scu); + } + + clk_set_rate(&priv->ddr_clk, priv->clock_rate); + ret = reset_get_by_index(dev, 0, &reset_ctl); + if (ret) { + debug("%s(): Failed to get reset signal\n", __func__); + return ret; + } + + ret = reset_assert(&reset_ctl); + if (ret) { + debug("%s(): SDRAM reset failed: %u\n", __func__, ret); + return ret; + } + + ast2500_sdrammc_unlock(priv); + + writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS, + ®s->power_control); + writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); + + /* Mask all requests except CPU and AHB during PHY init */ + writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask); + + for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) + writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); + + setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); + + ast2500_sdrammc_init_phy(priv->phy); + if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) { + ast2500_sdrammc_init_ddr4(priv); + } else { + debug("Unsupported DRAM3\n"); + return -EINVAL; + } + + clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); + ast2500_sdrammc_lock(priv); + + return 0; +} + +static int ast2500_sdrammc_of_to_plat(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct regmap *map; + int ret; + + ret = regmap_init_mem(dev_ofnode(dev), &map); + if (ret) + return ret; + + priv->regs = regmap_get_range(map, 0); + priv->phy = regmap_get_range(map, 1); + + priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "clock-frequency", 0); + + if (!priv->clock_rate) { + debug("DDR Clock Rate not defined\n"); + return -EINVAL; + } + + return 0; +} + +static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops ast2500_sdrammc_ops = { + .get_info = ast2500_sdrammc_get_info, +}; + +static const struct udevice_id ast2500_sdrammc_ids[] = { + { .compatible = "aspeed,ast2500-sdrammc" }, + { } +}; + +U_BOOT_DRIVER(sdrammc_ast2500) = { + .name = "aspeed_ast2500_sdrammc", + .id = UCLASS_RAM, + .of_match = ast2500_sdrammc_ids, + .ops = &ast2500_sdrammc_ops, + .of_to_plat = ast2500_sdrammc_of_to_plat, + .probe = ast2500_sdrammc_probe, + .priv_auto = sizeof(struct dram_info), +}; diff --git a/roms/u-boot/drivers/ram/aspeed/sdram_ast2600.c b/roms/u-boot/drivers/ram/aspeed/sdram_ast2600.c new file mode 100644 index 000000000..9ad398d24 --- /dev/null +++ b/roms/u-boot/drivers/ram/aspeed/sdram_ast2600.c @@ -0,0 +1,1062 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea +#define DDR_PHY_TBL_END 0xaeededed + +#if defined(CONFIG_ASPEED_DDR4_800) +u32 ast2600_sdramphy_config[165] = { + 0x1e6e0100, // start address + 0x00000000, // phyr000 + 0x0c002062, // phyr004 + 0x1a7a0063, // phyr008 + 0x5a7a0063, // phyr00c + 0x1a7a0063, // phyr010 + 0x1a7a0063, // phyr014 + 0x20000000, // phyr018 + 0x20000000, // phyr01c + 0x20000000, // phyr020 + 0x20000000, // phyr024 + 0x00000008, // phyr028 + 0x00000000, // phyr02c + 0x00077600, // phyr030 + 0x00000000, // phyr034 + 0x00000000, // phyr038 + 0x20000000, // phyr03c + 0x50506000, // phyr040 + 0x50505050, // phyr044 + 0x00002f07, // phyr048 + 0x00003080, // phyr04c + 0x04000000, // phyr050 + 0x00000200, // phyr054 + 0x03140201, // phyr058 + 0x04800000, // phyr05c + 0x0800044e, // phyr060 + 0x00000000, // phyr064 + 0x00180008, // phyr068 + 0x00e00400, // phyr06c + 0x00140206, // phyr070 + 0x1d4c0000, // phyr074 + 0x493e0107, // phyr078 + 0x08060404, // phyr07c + 0x90000a00, // phyr080 + 0x06420618, // phyr084 + 0x00001002, // phyr088 + 0x05701016, // phyr08c + 0x10000000, // phyr090 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x00002020, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e01cc, // new address + 0x01010101, // phyr0cc + 0x01010101, // phyr0d0 + 0x80808080, // phyr0d4 + 0x80808080, // phyr0d8 + 0xaeeddeea, // change address + 0x1e6e0288, // new address + 0x80808080, // phyr188 + 0x80808080, // phyr18c + 0x80808080, // phyr190 + 0x80808080, // phyr194 + 0xaeeddeea, // change address + 0x1e6e02f8, // new address + 0x90909090, // phyr1f8 + 0x88888888, // phyr1fc + 0xaeeddeea, // change address + 0x1e6e0300, // new address + 0x00000000, // phyr200 + 0xaeeddeea, // change address + 0x1e6e0194, // new address + 0x80118260, // phyr094 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x80000000, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e0318, // new address + 0x09222719, // phyr218 + 0x00aa4403, // phyr21c + 0xaeeddeea, // change address + 0x1e6e0198, // new address + 0x08060000, // phyr098 + 0xaeeddeea, // change address + 0x1e6e01b0, // new address + 0x00000000, // phyr0b0 + 0x00000000, // phyr0b4 + 0x00000000, // phyr0b8 + 0x00000000, // phyr0bc + 0x00000000, // phyr0c0 + 0x00000000, // phyr0c4 + 0x000aff2c, // phyr0c8 + 0xaeeddeea, // change address + 0x1e6e01dc, // new address + 0x00080000, // phyr0dc + 0x00000000, // phyr0e0 + 0xaa55aa55, // phyr0e4 + 0x55aa55aa, // phyr0e8 + 0xaaaa5555, // phyr0ec + 0x5555aaaa, // phyr0f0 + 0xaa55aa55, // phyr0f4 + 0x55aa55aa, // phyr0f8 + 0xaaaa5555, // phyr0fc + 0x5555aaaa, // phyr100 + 0xaa55aa55, // phyr104 + 0x55aa55aa, // phyr108 + 0xaaaa5555, // phyr10c + 0x5555aaaa, // phyr110 + 0xaa55aa55, // phyr114 + 0x55aa55aa, // phyr118 + 0xaaaa5555, // phyr11c + 0x5555aaaa, // phyr120 + 0x20202020, // phyr124 + 0x20202020, // phyr128 + 0x20202020, // phyr12c + 0x20202020, // phyr130 + 0x20202020, // phyr134 + 0x20202020, // phyr138 + 0x20202020, // phyr13c + 0x20202020, // phyr140 + 0x20202020, // phyr144 + 0x20202020, // phyr148 + 0x20202020, // phyr14c + 0x20202020, // phyr150 + 0x20202020, // phyr154 + 0x20202020, // phyr158 + 0x20202020, // phyr15c + 0x20202020, // phyr160 + 0x20202020, // phyr164 + 0x20202020, // phyr168 + 0x20202020, // phyr16c + 0x20202020, // phyr170 + 0xaeeddeea, // change address + 0x1e6e0298, // new address + 0x20200800, // phyr198 + 0x20202020, // phyr19c + 0x20202020, // phyr1a0 + 0x20202020, // phyr1a4 + 0x20202020, // phyr1a8 + 0x20202020, // phyr1ac + 0x20202020, // phyr1b0 + 0x20202020, // phyr1b4 + 0x20202020, // phyr1b8 + 0x20202020, // phyr1bc + 0x20202020, // phyr1c0 + 0x20202020, // phyr1c4 + 0x20202020, // phyr1c8 + 0x20202020, // phyr1cc + 0x20202020, // phyr1d0 + 0x20202020, // phyr1d4 + 0x20202020, // phyr1d8 + 0x20202020, // phyr1dc + 0x20202020, // phyr1e0 + 0x20202020, // phyr1e4 + 0x00002020, // phyr1e8 + 0xaeeddeea, // change address + 0x1e6e0304, // new address + 0x00000800, // phyr204 + 0xaeeddeea, // change address + 0x1e6e027c, // new address + 0x4e400000, // phyr17c + 0x59595959, // phyr180 + 0x40404040, // phyr184 + 0xaeeddeea, // change address + 0x1e6e02f4, // new address + 0x00000059, // phyr1f4 + 0xaeededed, // end +}; +#else +u32 ast2600_sdramphy_config[165] = { + 0x1e6e0100, // start address + 0x00000000, // phyr000 + 0x0c002062, // phyr004 + 0x1a7a0063, // phyr008 + 0x5a7a0063, // phyr00c + 0x1a7a0063, // phyr010 + 0x1a7a0063, // phyr014 + 0x20000000, // phyr018 + 0x20000000, // phyr01c + 0x20000000, // phyr020 + 0x20000000, // phyr024 + 0x00000008, // phyr028 + 0x00000000, // phyr02c + 0x00077600, // phyr030 + 0x00000000, // phyr034 + 0x00000000, // phyr038 + 0x20000000, // phyr03c + 0x50506000, // phyr040 + 0x50505050, // phyr044 + 0x00002f07, // phyr048 + 0x00003080, // phyr04c + 0x04000000, // phyr050 + 0x00000200, // phyr054 + 0x03140501, // phyr058-rtt:40 + 0x04800000, // phyr05c + 0x0800044e, // phyr060 + 0x00000000, // phyr064 + 0x00180008, // phyr068 + 0x00e00400, // phyr06c + 0x00140206, // phyr070 + 0x1d4c0000, // phyr074 + 0x493e0107, // phyr078 + 0x08060404, // phyr07c + 0x90000a00, // phyr080 + 0x06420c30, // phyr084 + 0x00001002, // phyr088 + 0x05701016, // phyr08c + 0x10000000, // phyr090 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x00002020, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e01cc, // new address + 0x01010101, // phyr0cc + 0x01010101, // phyr0d0 + 0x80808080, // phyr0d4 + 0x80808080, // phyr0d8 + 0xaeeddeea, // change address + 0x1e6e0288, // new address + 0x80808080, // phyr188 + 0x80808080, // phyr18c + 0x80808080, // phyr190 + 0x80808080, // phyr194 + 0xaeeddeea, // change address + 0x1e6e02f8, // new address + 0x90909090, // phyr1f8 + 0x88888888, // phyr1fc + 0xaeeddeea, // change address + 0x1e6e0300, // new address + 0x00000000, // phyr200 + 0xaeeddeea, // change address + 0x1e6e0194, // new address + 0x801112e0, // phyr094 - bit12=1,15=0,- write window is ok + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x80000000, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e0318, // new address + 0x09222719, // phyr218 + 0x00aa4403, // phyr21c + 0xaeeddeea, // change address + 0x1e6e0198, // new address + 0x08060000, // phyr098 + 0xaeeddeea, // change address + 0x1e6e01b0, // new address + 0x00000000, // phyr0b0 + 0x00000000, // phyr0b4 + 0x00000000, // phyr0b8 + 0x00000000, // phyr0bc + 0x00000000, // phyr0c0 - ori + 0x00000000, // phyr0c4 + 0x000aff2c, // phyr0c8 + 0xaeeddeea, // change address + 0x1e6e01dc, // new address + 0x00080000, // phyr0dc + 0x00000000, // phyr0e0 + 0xaa55aa55, // phyr0e4 + 0x55aa55aa, // phyr0e8 + 0xaaaa5555, // phyr0ec + 0x5555aaaa, // phyr0f0 + 0xaa55aa55, // phyr0f4 + 0x55aa55aa, // phyr0f8 + 0xaaaa5555, // phyr0fc + 0x5555aaaa, // phyr100 + 0xaa55aa55, // phyr104 + 0x55aa55aa, // phyr108 + 0xaaaa5555, // phyr10c + 0x5555aaaa, // phyr110 + 0xaa55aa55, // phyr114 + 0x55aa55aa, // phyr118 + 0xaaaa5555, // phyr11c + 0x5555aaaa, // phyr120 + 0x20202020, // phyr124 + 0x20202020, // phyr128 + 0x20202020, // phyr12c + 0x20202020, // phyr130 + 0x20202020, // phyr134 + 0x20202020, // phyr138 + 0x20202020, // phyr13c + 0x20202020, // phyr140 + 0x20202020, // phyr144 + 0x20202020, // phyr148 + 0x20202020, // phyr14c + 0x20202020, // phyr150 + 0x20202020, // phyr154 + 0x20202020, // phyr158 + 0x20202020, // phyr15c + 0x20202020, // phyr160 + 0x20202020, // phyr164 + 0x20202020, // phyr168 + 0x20202020, // phyr16c + 0x20202020, // phyr170 + 0xaeeddeea, // change address + 0x1e6e0298, // new address + 0x20200800, // phyr198 + 0x20202020, // phyr19c + 0x20202020, // phyr1a0 + 0x20202020, // phyr1a4 + 0x20202020, // phyr1a8 + 0x20202020, // phyr1ac + 0x20202020, // phyr1b0 + 0x20202020, // phyr1b4 + 0x20202020, // phyr1b8 + 0x20202020, // phyr1bc + 0x20202020, // phyr1c0 + 0x20202020, // phyr1c4 + 0x20202020, // phyr1c8 + 0x20202020, // phyr1cc + 0x20202020, // phyr1d0 + 0x20202020, // phyr1d4 + 0x20202020, // phyr1d8 + 0x20202020, // phyr1dc + 0x20202020, // phyr1e0 + 0x20202020, // phyr1e4 + 0x00002020, // phyr1e8 + 0xaeeddeea, // change address + 0x1e6e0304, // new address + 0x00000800, // phyr204 + 0xaeeddeea, // change address + 0x1e6e027c, // new address + 0x4e400000, // phyr17c + 0x59595959, // phyr180 + 0x40404040, // phyr184 + 0xaeeddeea, // change address + 0x1e6e02f4, // new address + 0x00000059, // phyr1f4 + 0xaeededed, // end +}; +#endif + +/* MPLL configuration */ +#define SCU_MPLL_FREQ_400M 0x0008405F +#define SCU_MPLL_EXT_400M 0x0000002F +#define SCU_MPLL_FREQ_333M 0x00488299 +#define SCU_MPLL_EXT_333M 0x0000014C +#define SCU_MPLL_FREQ_200M 0x0078007F +#define SCU_MPLL_EXT_200M 0x0000003F +#define SCU_MPLL_FREQ_100M 0x0078003F +#define SCU_MPLL_EXT_100M 0x0000001F + +#if defined(CONFIG_ASPEED_DDR4_1600) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M +#elif defined(CONFIG_ASPEED_DDR4_1333) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M +#elif defined(CONFIG_ASPEED_DDR4_800) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M +#elif defined(CONFIG_ASPEED_DDR4_400) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M +#else +#error "undefined DDR4 target rate\n" +#endif + +/* + * AC timing and SDRAM mode register setting + * for real chip are derived from the model GDDR4-1600 + */ +#define DDR4_MR01_MODE 0x03010510 +#define DDR4_MR23_MODE 0x00000000 +#define DDR4_MR45_MODE 0x04000000 +#define DDR4_MR6_MODE 0x00000400 +#define DDR4_TRFC_1600 0x467299f1 +#define DDR4_TRFC_1333 0x3a5f80c9 +#define DDR4_TRFC_800 0x23394c78 +#define DDR4_TRFC_400 0x111c263c + +#if defined(CONFIG_ASPEED_DDR4_1600) +#define DDR4_TRFC DDR4_TRFC_1600 +#define DDR4_PHY_TRAIN_TRFC 0xc30 +#elif defined(CONFIG_ASPEED_DDR4_1333) +#define DDR4_TRFC DDR4_TRFC_1333 +#define DDR4_PHY_TRAIN_TRFC 0xa25 +#elif defined(CONFIG_ASPEED_DDR4_800) +#define DDR4_TRFC DDR4_TRFC_800 +#define DDR4_PHY_TRAIN_TRFC 0x618 +#elif defined(CONFIG_ASPEED_DDR4_400) +#define DDR4_TRFC DDR4_TRFC_400 +#define DDR4_PHY_TRAIN_TRFC 0x30c +#else +#error "undefined tRFC setting" +#endif + +/* supported SDRAM size */ +#define SDRAM_SIZE_1KB (1024U) +#define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) +#define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) +#define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 ddr4_ac_timing[4] = { + 0x040e0307, 0x0f4711f1, 0x0e060304, 0x00001240 }; +static const u32 ddr_max_grant_params[4] = { + 0x44444444, 0x44444444, 0x44444444, 0x44444444 }; + +struct dram_info { + struct ram_info info; + struct clk ddr_clk; + struct ast2600_sdrammc_regs *regs; + struct ast2600_scu *scu; + struct ast2600_ddr_phy *phy; + void __iomem *phy_setting; + void __iomem *phy_status; + ulong clock_rate; +}; + +static void ast2600_sdramphy_kick_training(struct dram_info *info) +{ + u32 data; + struct ast2600_sdrammc_regs *regs = info->regs; + + writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); + udelay(5); + writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); + udelay(1000); + + while (1) { + data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; + if (~data) + break; + } +} + +/** + * @brief load DDR-PHY configurations table to the PHY registers + * @param[in] p_tbl - pointer to the configuration table + * @param[in] info - pointer to the DRAM info struct + * + * There are two sets of MRS (Mode Registers) configuration in ast2600 memory + * system: one is in the SDRAM MC (memory controller) which is used in run + * time, and the other is in the DDR-PHY IP which is used during DDR-PHY + * training. + */ +static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) +{ + u32 reg_base = (u32)info->phy_setting; + u32 addr = p_tbl[0]; + u32 data; + int i = 1; + + writel(0, &info->regs->phy_ctrl[0]); + udelay(10); + + while (1) { + if (addr < reg_base) { + debug("invalid DDR-PHY addr: 0x%08x\n", addr); + break; + } + data = p_tbl[i++]; + + if (data == DDR_PHY_TBL_END) { + break; + } else if (data == DDR_PHY_TBL_CHG_ADDR) { + addr = p_tbl[i++]; + } else { + writel(data, addr); + addr += 4; + } + } + + data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); + data |= DDR4_PHY_TRAIN_TRFC; + writel(data, info->phy_setting + 0x84); +} + +static int ast2600_sdramphy_check_status(struct dram_info *info) +{ + u32 value, tmp; + u32 reg_base = (u32)info->phy_status; + int need_retrain = 0; + + debug("\nSDRAM PHY training report:\n"); + + /* training status */ + value = readl(reg_base + 0x00); + debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); + + if (value & BIT(3)) + debug("\tinitial PVT calibration fail\n"); + + if (value & BIT(5)) + debug("\truntime calibration fail\n"); + + /* PU & PD */ + value = readl(reg_base + 0x30); + debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); + debug(" PU = 0x%02x\n", value & 0xff); + debug(" PD = 0x%02x\n", (value >> 16) & 0xff); + + /* read eye window */ + value = readl(reg_base + 0x68); + if (0 == (value & GENMASK(7, 0))) + need_retrain = 1; + + debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); + debug(" rising edge of read data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + value = readl(reg_base + 0xC8); + debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); + debug(" falling edge of read data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + /* write eye window */ + value = readl(reg_base + 0x7c); + if (0 == (value & GENMASK(7, 0))) + need_retrain = 1; + + debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); + debug(" rising edge of write data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + /* read Vref training result */ + value = readl(reg_base + 0x88); + debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); + debug(" read Vref training result\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; + debug(" B1:%d%%\n", tmp); + + /* write Vref training result */ + value = readl(reg_base + 0x90); + debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); + + /* gate train */ + value = readl(reg_base + 0x50); + if ((0 == (value & GENMASK(15, 0))) || + (0 == (value & GENMASK(31, 16)))) { + need_retrain = 1; + } + + debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); + + return need_retrain; +} + +#ifndef CONFIG_ASPEED_BYPASS_SELFTEST +#define MC_TEST_PATTERN_N 8 +static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { + 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, + 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 }; + +#define TIMEOUT_DRAM 5000000 +int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) +{ + unsigned int data; + unsigned int timeout = 0; + struct ast2600_sdrammc_regs *regs = info->regs; + + writel(0, ®s->ecc_test_ctrl); + + if (mode == 0) + writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); + else + writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); + + do { + data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); + + if (data & BIT(13)) + return 0; + + if (++timeout > TIMEOUT_DRAM) { + debug("Timeout!!\n"); + writel(0, ®s->ecc_test_ctrl); + return -1; + } + } while (!data); + + writel(0, ®s->ecc_test_ctrl); + + return 0; +} + +int ast2600_sdrammc_cbr_test(struct dram_info *info) +{ + u32 i; + struct ast2600_sdrammc_regs *regs = info->regs; + + clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); + + /* single */ + for (i = 0; i < 8; i++) + if (ast2600_sdrammc_dg_test(info, i, 0)) + return -1; + + /* burst */ + for (i = 0; i < 8; i++) + if (ast2600_sdrammc_dg_test(info, i, i)) + return -1; + + return 0; +} + +static int ast2600_sdrammc_test(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + + u32 pass_cnt = 0; + u32 fail_cnt = 0; + u32 target_cnt = 2; + u32 test_cnt = 0; + u32 pattern; + u32 i = 0; + bool finish = false; + + debug("sdram mc test:\n"); + while (!finish) { + pattern = as2600_sdrammc_test_pattern[i++]; + i = i % MC_TEST_PATTERN_N; + debug(" pattern = %08X : ", pattern); + writel(pattern, ®s->test_init_val); + + if (ast2600_sdrammc_cbr_test(info)) { + debug("fail\n"); + fail_cnt++; + } else { + debug("pass\n"); + pass_cnt++; + } + + if (++test_cnt == target_cnt) + finish = true; + } + debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, + target_cnt); + + return fail_cnt; +} +#endif + +/* + * scu500[14:13] + * 2b'00: VGA memory size = 16MB + * 2b'01: VGA memory size = 16MB + * 2b'10: VGA memory size = 32MB + * 2b'11: VGA memory size = 64MB + * + * mcr04[3:2] + * 2b'00: VGA memory size = 8MB + * 2b'01: VGA memory size = 16MB + * 2b'10: VGA memory size = 32MB + * 2b'11: VGA memory size = 64MB + */ +static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) +{ + u32 vga_hwconf; + size_t vga_mem_size_base = 8 * 1024 * 1024; + + vga_hwconf = + (readl(&info->scu->hwstrap1) & SCU_HWSTRAP1_VGA_MEM_MASK) >> + SCU_HWSTRAP1_VGA_MEM_SHIFT; + + if (vga_hwconf == 0) { + vga_hwconf = 1; + writel(vga_hwconf << SCU_HWSTRAP1_VGA_MEM_SHIFT, + &info->scu->hwstrap1); + } + + clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, + ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & + SDRAM_CONF_VGA_SIZE_MASK)); + + /* no need to reserve VGA memory if efuse[VGA disable] is set */ + if (readl(&info->scu->efuse) & SCU_EFUSE_DIS_VGA) + return 0; + + return vga_mem_size_base << vga_hwconf; +} + +/* + * Find out RAM size and save it in dram_info + * + * The procedure is taken from Aspeed SDK + */ +static void ast2600_sdrammc_calc_size(struct dram_info *info) +{ + /* The controller supports 256/512/1024/2048 MB ram */ + size_t ram_size = SDRAM_MIN_SIZE; + const int write_test_offset = 0x100000; + u32 test_pattern = 0xdeadbeef; + u32 cap_param = SDRAM_CONF_CAP_2048M; + u32 refresh_timing_param = DDR4_TRFC; + const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + writel(test_pattern, write_addr_base + (ram_size >> 1)); + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + /* One last write to overwrite all wrapped values */ + writel(test_pattern, write_addr_base); + + /* Reset the pattern and see which value was really written */ + test_pattern = 0xdeadbeef; + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) + break; + + --cap_param; + refresh_timing_param >>= 8; + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + clrsetbits_le32(&info->regs->ac_timing[1], + (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), + ((refresh_timing_param & SDRAM_AC_TRFC_MASK) + << SDRAM_AC_TRFC_SHIFT)); + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); + + clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK, + ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); +} + +static int ast2600_sdrammc_init_ddr4(struct dram_info *info) +{ + const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | + MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | + MCR34_ODT_EN | MCR34_ODT_AUTO_ON | + (0x1 << MCR34_ODT_EXT_SHIFT); + + /* init SDRAM-PHY only on real chip */ + ast2600_sdramphy_init(ast2600_sdramphy_config, info); + writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), + &info->regs->power_ctrl); + udelay(5); + ast2600_sdramphy_kick_training(info); + udelay(500); + writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); + + writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, + &info->regs->mode_setting_control); + + writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | + (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), + &info->regs->refresh_timing); + + /* wait self-refresh idle */ + while (readl(&info->regs->power_ctrl) & + MCR34_SELF_REFRESH_STATUS_MASK) + ; + + writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | + SDRAM_REFRESH_ZQCS_EN | + (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | + (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), + &info->regs->refresh_timing); + + writel(power_ctrl, &info->regs->power_ctrl); + udelay(500); + + return 0; +} + +static void ast2600_sdrammc_unlock(struct dram_info *info) +{ + writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (!readl(&info->regs->protection_key)) + ; +} + +static void ast2600_sdrammc_lock(struct dram_info *info) +{ + writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (readl(&info->regs->protection_key)) + ; +} + +static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) +{ + int i; + + writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); + writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); + writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, + ®s->arbitration_ctrl); + writel(0xFFBBFFF4, ®s->req_limit_mask); + + for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) + writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); + + writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); + + writel(0x07FFFFFF, ®s->ecc_range_ctrl); + + writel(0, ®s->ecc_test_ctrl); + writel(0x80000001, ®s->test_addr); + writel(0, ®s->test_fail_dq_bit); + writel(0, ®s->test_init_val); + + writel(0xFFFFFFFF, ®s->req_input_ctrl); + writel(0, ®s->req_high_pri_ctrl); + + udelay(600); + +#ifdef CONFIG_ASPEED_DDR4_DUALX8 + writel(0x37, ®s->config); +#else + writel(0x17, ®s->config); +#endif + + /* load controller setting */ + for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) + writel(ddr4_ac_timing[i], ®s->ac_timing[i]); + + writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); + writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); + writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); + writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); +} + +/* + * Update size info according to the ECC HW setting + * + * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we + * don't need to calculate the ECC size again but read from MCR04 and derive the + * size from its value. + */ +static void ast2600_sdrammc_update_size(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + u32 conf = readl(®s->config); + u32 cap_param; + size_t ram_size = SDRAM_MAX_SIZE; + size_t hw_size; + + cap_param = (conf & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; + switch (cap_param) { + case SDRAM_CONF_CAP_2048M: + ram_size = 2048 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_1024M: + ram_size = 1024 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_512M: + ram_size = 512 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_256M: + ram_size = 256 * SDRAM_SIZE_1MB; + break; + } + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); + + if (0 == (conf & SDRAM_CONF_ECC_SETUP)) + return; + + hw_size = readl(®s->ecc_range_ctrl) & SDRAM_ECC_RANGE_ADDR_MASK; + hw_size += (1 << SDRAM_ECC_RANGE_ADDR_SHIFT); + + info->info.size = hw_size; +} + +#ifdef CONFIG_ASPEED_ECC +static void ast2600_sdrammc_ecc_enable(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + size_t conf_size; + u32 reg; + + conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; + if (conf_size > info->info.size) { + printf("warning: ECC configured %dMB but actual size is %dMB\n", + CONFIG_ASPEED_ECC_SIZE, + info->info.size / SDRAM_SIZE_1MB); + conf_size = info->info.size; + } else if (conf_size == 0) { + conf_size = info->info.size; + } + + info->info.size = (((conf_size / 9) * 8) >> 20) << 20; + writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); + reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; + writel(reg, ®s->config); + + writel(0, ®s->test_init_val); + writel(0x80000001, ®s->test_addr); + writel(0x221, ®s->ecc_test_ctrl); + while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) + ; + writel(0, ®s->ecc_test_ctrl); + writel(BIT(31), ®s->intr_ctrl); + writel(0, ®s->intr_ctrl); +} +#endif + +static int ast2600_sdrammc_probe(struct udevice *dev) +{ + int ret; + u32 reg; + struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); + struct ast2600_sdrammc_regs *regs = priv->regs; + struct udevice *clk_dev; + + /* find SCU base address from clock device */ + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(aspeed_ast2600_scu), &clk_dev); + if (ret) { + debug("clock device not defined\n"); + return ret; + } + + priv->scu = devfdt_get_addr_ptr(clk_dev); + if (IS_ERR(priv->scu)) { + debug("%s(): can't get SCU\n", __func__); + return PTR_ERR(priv->scu); + } + + if (readl(&priv->scu->dram_hdshk) & SCU_DRAM_HDSHK_RDY) { + printf("already initialized, "); + ast2600_sdrammc_update_size(priv); + return 0; + } + + reg = readl(&priv->scu->mpll); + reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK | + SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK); + reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG); + writel(reg, &priv->scu->mpll); + writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext); + udelay(100); + reg &= ~(SCU_PLL_RST | SCU_PLL_OFF); + writel(reg, &priv->scu->mpll); + + while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0) + ; + + ast2600_sdrammc_unlock(priv); + ast2600_sdrammc_common_init(regs); +L_ast2600_sdramphy_train: + ast2600_sdrammc_init_ddr4(priv); + + /* make sure DDR-PHY is ready before access */ + do { + reg = readl(priv->phy_status) & BIT(1); + } while (reg == 0); + + if (ast2600_sdramphy_check_status(priv) != 0) { + printf("DDR4 PHY training fail, retrain\n"); + goto L_ast2600_sdramphy_train; + } + + ast2600_sdrammc_calc_size(priv); + +#ifndef CONFIG_ASPEED_BYPASS_SELFTEST + if (ast2600_sdrammc_test(priv) != 0) { + printf("%s: DDR4 init fail\n", __func__); + return -EINVAL; + } +#endif + +#ifdef CONFIG_ASPEED_ECC + ast2600_sdrammc_ecc_enable(priv); +#endif + + writel(readl(&priv->scu->dram_hdshk) | SCU_DRAM_HDSHK_RDY, + &priv->scu->dram_hdshk); + + clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); + ast2600_sdrammc_lock(priv); + return 0; +} + +static int ast2600_sdrammc_of_to_plat(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); + priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); + priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); + + priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "clock-frequency", 0); + if (!priv->clock_rate) { + debug("DDR Clock Rate not defined\n"); + return -EINVAL; + } + + return 0; +} + +static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops ast2600_sdrammc_ops = { + .get_info = ast2600_sdrammc_get_info, +}; + +static const struct udevice_id ast2600_sdrammc_ids[] = { + { .compatible = "aspeed,ast2600-sdrammc" }, + { } +}; + +U_BOOT_DRIVER(sdrammc_ast2600) = { + .name = "aspeed_ast2600_sdrammc", + .id = UCLASS_RAM, + .of_match = ast2600_sdrammc_ids, + .ops = &ast2600_sdrammc_ops, + .of_to_plat = ast2600_sdrammc_of_to_plat, + .probe = ast2600_sdrammc_probe, + .priv_auto = sizeof(struct dram_info), +}; diff --git a/roms/u-boot/drivers/ram/bmips_ram.c b/roms/u-boot/drivers/ram/bmips_ram.c new file mode 100644 index 000000000..98045248e --- /dev/null +++ b/roms/u-boot/drivers/ram/bmips_ram.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/bcm63xx/cpu.c: + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2009 Florian Fainelli + */ + +#include +#include +#include +#include +#include +#include + +#define SDRAM_CFG_REG 0x0 +#define SDRAM_CFG_COL_SHIFT 4 +#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) +#define SDRAM_CFG_ROW_SHIFT 6 +#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) +#define SDRAM_CFG_32B_SHIFT 10 +#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) +#define SDRAM_CFG_BANK_SHIFT 13 +#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) +#define SDRAM_6318_SPACE_SHIFT 4 +#define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT) + +#define MEMC_CFG_REG 0x4 +#define MEMC_CFG_32B_SHIFT 1 +#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) +#define MEMC_CFG_COL_SHIFT 3 +#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) +#define MEMC_CFG_ROW_SHIFT 6 +#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) + +#define DDR_CSEND_REG 0x8 + +struct bmips_ram_priv; + +struct bmips_ram_hw { + ulong (*get_ram_size)(struct bmips_ram_priv *); +}; + +struct bmips_ram_priv { + void __iomem *regs; + u32 force_size; + const struct bmips_ram_hw *hw; +}; + +static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv) +{ + u32 val; + + val = readl_be(priv->regs + SDRAM_CFG_REG); + val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT; + + return (1 << (val + 20)); +} + +static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv) +{ + return readl_be(priv->regs + DDR_CSEND_REG) << 24; +} + +static ulong bmips_dram_size(unsigned int cols, unsigned int rows, + unsigned int is_32b, unsigned int banks) +{ + rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */ + cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */ + is_32b += 1; + + return 1 << (cols + rows + is_32b + banks); +} + +static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv) +{ + unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0; + u32 val; + + val = readl_be(priv->regs + SDRAM_CFG_REG); + rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; + cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; + is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; + banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; + + return bmips_dram_size(cols, rows, is_32b, banks); +} + +static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv) +{ + unsigned int cols = 0, rows = 0, is_32b = 0; + u32 val; + + val = readl_be(priv->regs + MEMC_CFG_REG); + rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; + cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; + is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1; + + return bmips_dram_size(cols, rows, is_32b, 2); +} + +static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info) +{ + struct bmips_ram_priv *priv = dev_get_priv(dev); + const struct bmips_ram_hw *hw = priv->hw; + + info->base = 0x80000000; + if (priv->force_size) + info->size = priv->force_size; + else + info->size = hw->get_ram_size(priv); + + return 0; +} + +static const struct ram_ops bmips_ram_ops = { + .get_info = bmips_ram_get_info, +}; + +static const struct bmips_ram_hw bmips_ram_bcm6318 = { + .get_ram_size = bcm6318_get_ram_size, +}; + +static const struct bmips_ram_hw bmips_ram_bcm6328 = { + .get_ram_size = bcm6328_get_ram_size, +}; + +static const struct bmips_ram_hw bmips_ram_bcm6338 = { + .get_ram_size = bcm6338_get_ram_size, +}; + +static const struct bmips_ram_hw bmips_ram_bcm6358 = { + .get_ram_size = bcm6358_get_ram_size, +}; + +static const struct udevice_id bmips_ram_ids[] = { + { + .compatible = "brcm,bcm6318-mc", + .data = (ulong)&bmips_ram_bcm6318, + }, { + .compatible = "brcm,bcm6328-mc", + .data = (ulong)&bmips_ram_bcm6328, + }, { + .compatible = "brcm,bcm6338-mc", + .data = (ulong)&bmips_ram_bcm6338, + }, { + .compatible = "brcm,bcm6358-mc", + .data = (ulong)&bmips_ram_bcm6358, + }, { /* sentinel */ } +}; + +static int bmips_ram_probe(struct udevice *dev) +{ + struct bmips_ram_priv *priv = dev_get_priv(dev); + const struct bmips_ram_hw *hw = + (const struct bmips_ram_hw *)dev_get_driver_data(dev); + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + + dev_read_u32(dev, "force-size", &priv->force_size); + + priv->hw = hw; + + return 0; +} + +U_BOOT_DRIVER(bmips_ram) = { + .name = "bmips-mc", + .id = UCLASS_RAM, + .of_match = bmips_ram_ids, + .probe = bmips_ram_probe, + .priv_auto = sizeof(struct bmips_ram_priv), + .ops = &bmips_ram_ops, +}; diff --git a/roms/u-boot/drivers/ram/imxrt_sdram.c b/roms/u-boot/drivers/ram/imxrt_sdram.c new file mode 100644 index 000000000..ca2eec767 --- /dev/null +++ b/roms/u-boot/drivers/ram/imxrt_sdram.c @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SDRAM Command Code */ +#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */ +#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */ +#define SD_CC_IRD 0x8 /* IP command - Read */ +#define SD_CC_IWR 0x9 /* IP command - Write */ +#define SD_CC_IMS 0xA /* IP command - Set Mode Register */ +#define SD_CC_IACT 0xB /* IP command - ACTIVE */ +#define SD_CC_IAF 0xC /* IP command - Auto Refresh */ +#define SD_CC_ISF 0xD /* IP Command - Self Refresh */ +#define SD_CC_IPRE 0xE /* IP command - Precharge */ +#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */ + +#define SEMC_MCR_MDIS BIT(1) +#define SEMC_MCR_DQSMD BIT(2) + +#define SEMC_INTR_IPCMDERR BIT(1) +#define SEMC_INTR_IPCMDDONE BIT(0) + +#define SEMC_IPCMD_KEY 0xA55A0000 + +struct imxrt_semc_regs { + /* 0x0 */ + u32 mcr; + u32 iocr; + u32 bmcr0; + u32 bmcr1; + u32 br[9]; + + /* 0x34 */ + u32 res1; + u32 inten; + u32 intr; + /* 0x40 */ + u32 sdramcr0; + u32 sdramcr1; + u32 sdramcr2; + u32 sdramcr3; + /* 0x50 */ + u32 nandcr0; + u32 nandcr1; + u32 nandcr2; + u32 nandcr3; + /* 0x60 */ + u32 norcr0; + u32 norcr1; + u32 norcr2; + u32 norcr3; + /* 0x70 */ + u32 sramcr0; + u32 sramcr1; + u32 sramcr2; + u32 sramcr3; + /* 0x80 */ + u32 dbicr0; + u32 dbicr1; + u32 res2[2]; + /* 0x90 */ + u32 ipcr0; + u32 ipcr1; + u32 ipcr2; + u32 ipcmd; + /* 0xA0 */ + u32 iptxdat; + u32 res3[3]; + /* 0xB0 */ + u32 iprxdat; + u32 res4[3]; + /* 0xC0 */ + u32 sts[16]; +}; + +#define SEMC_IOCR_MUX_A8_SHIFT 0 +#define SEMC_IOCR_MUX_CSX0_SHIFT 3 +#define SEMC_IOCR_MUX_CSX1_SHIFT 6 +#define SEMC_IOCR_MUX_CSX2_SHIFT 9 +#define SEMC_IOCR_MUX_CSX3_SHIFT 12 +#define SEMC_IOCR_MUX_RDY_SHIFT 15 + +struct imxrt_sdram_mux { + u8 a8; + u8 csx0; + u8 csx1; + u8 csx2; + u8 csx3; + u8 rdy; +}; + +#define SEMC_SDRAMCR0_PS_SHIFT 0 +#define SEMC_SDRAMCR0_BL_SHIFT 4 +#define SEMC_SDRAMCR0_COL_SHIFT 8 +#define SEMC_SDRAMCR0_CL_SHIFT 10 + +struct imxrt_sdram_control { + u8 memory_width; + u8 burst_len; + u8 no_columns; + u8 cas_latency; +}; + +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0 +#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4 +#define SEMC_SDRAMCR1_RFRC_SHIFT 8 +#define SEMC_SDRAMCR1_WRC_SHIFT 13 +#define SEMC_SDRAMCR1_CKEOFF_SHIFT 16 +#define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20 + +#define SEMC_SDRAMCR2_SRRC_SHIFT 0 +#define SEMC_SDRAMCR2_REF2REF_SHIFT 8 +#define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16 +#define SEMC_SDRAMCR2_ITO_SHIFT 24 + +#define SEMC_SDRAMCR3_REN BIT(0) +#define SEMC_SDRAMCR3_REBL_SHIFT 1 +#define SEMC_SDRAMCR3_PRESCALE_SHIFT 8 +#define SEMC_SDRAMCR3_RT_SHIFT 16 +#define SEMC_SDRAMCR3_UT_SHIFT 24 + +struct imxrt_sdram_timing { + u8 pre2act; + u8 act2rw; + u8 rfrc; + u8 wrc; + u8 ckeoff; + u8 act2pre; + + u8 srrc; + u8 ref2ref; + u8 act2act; + u8 ito; + + u8 rebl; + u8 prescale; + u8 rt; + u8 ut; +}; + +enum imxrt_semc_bank { + SDRAM_BANK1, + SDRAM_BANK2, + SDRAM_BANK3, + SDRAM_BANK4, + MAX_SDRAM_BANK, +}; + +#define SEMC_BR_VLD_MASK 1 +#define SEMC_BR_MS_SHIFT 1 + +struct bank_params { + enum imxrt_semc_bank target_bank; + u32 base_address; + u32 memory_size; +}; + +struct imxrt_sdram_params { + struct imxrt_semc_regs *base; + + struct imxrt_sdram_mux *sdram_mux; + struct imxrt_sdram_control *sdram_control; + struct imxrt_sdram_timing *sdram_timing; + + struct bank_params bank_params[MAX_SDRAM_BANK]; + u8 no_sdram_banks; +}; + +static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs) +{ + do { + readl(®s->intr); + + if (regs->intr & SEMC_INTR_IPCMDDONE) + return 0; + if (regs->intr & SEMC_INTR_IPCMDERR) + return -EIO; + + mdelay(50); + } while (1); +} + +static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr, + u32 ipcmd, u32 wd, u32 *rd) +{ + int ret; + + if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS) + writel(wd, ®s->iptxdat); + + /* set slave address for every command as specified on RM */ + writel(mem_addr, ®s->ipcr0); + + /* execute command */ + writel(SEMC_IPCMD_KEY | ipcmd, ®s->ipcmd); + + ret = imxrt_sdram_wait_ipcmd_done(regs); + if (ret < 0) + return ret; + + if (ipcmd == SD_CC_IRD) { + if (!rd) + return -EINVAL; + + *rd = readl(®s->iprxdat); + } + + return 0; +} + +int imxrt_sdram_init(struct udevice *dev) +{ + struct imxrt_sdram_params *params = dev_get_plat(dev); + struct imxrt_sdram_mux *mux = params->sdram_mux; + struct imxrt_sdram_control *ctrl = params->sdram_control; + struct imxrt_sdram_timing *time = params->sdram_timing; + struct imxrt_semc_regs *regs = params->base; + struct bank_params *bank_params; + u32 rd; + int i; + + /* enable the SEMC controller */ + clrbits_le32(®s->mcr, SEMC_MCR_MDIS); + /* set DQS mode from DQS pad */ + setbits_le32(®s->mcr, SEMC_MCR_DQSMD); + + for (i = 0, bank_params = params->bank_params; + i < params->no_sdram_banks; bank_params++, + i++) + writel((bank_params->base_address & 0xfffff000) + | bank_params->memory_size << SEMC_BR_MS_SHIFT + | SEMC_BR_VLD_MASK, + ®s->br[bank_params->target_bank]); + + writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT + | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT + | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT + | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT + | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT + | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT, + ®s->iocr); + + writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT + | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT + | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT + | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT, + ®s->sdramcr0); + + writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT + | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT + | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT + | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT + | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT + | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT, + ®s->sdramcr1); + + writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT + | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT + | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT + | time->ito << SEMC_SDRAMCR2_ITO_SHIFT, + ®s->sdramcr2); + + writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT + | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT + | time->rt << SEMC_SDRAMCR3_RT_SHIFT + | time->ut << SEMC_SDRAMCR3_UT_SHIFT + | SEMC_SDRAMCR3_REN, + ®s->sdramcr3); + + writel(2, ®s->ipcr1); + + for (i = 0, bank_params = params->bank_params; + i < params->no_sdram_banks; bank_params++, + i++) { + mdelay(250); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA, + 0, &rd); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF, + 0, &rd); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF, + 0, &rd); + imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS, + ctrl->burst_len | (ctrl->cas_latency << 4), + &rd); + mdelay(250); + } + + return 0; +} + +static int imxrt_semc_of_to_plat(struct udevice *dev) +{ + struct imxrt_sdram_params *params = dev_get_plat(dev); + ofnode bank_node; + u8 bank = 0; + + params->sdram_mux = + (struct imxrt_sdram_mux *) + dev_read_u8_array_ptr(dev, + "fsl,sdram-mux", + sizeof(struct imxrt_sdram_mux)); + if (!params->sdram_mux) { + pr_err("fsl,sdram-mux not found"); + return -EINVAL; + } + + params->sdram_control = + (struct imxrt_sdram_control *) + dev_read_u8_array_ptr(dev, + "fsl,sdram-control", + sizeof(struct imxrt_sdram_control)); + if (!params->sdram_control) { + pr_err("fsl,sdram-control not found"); + return -EINVAL; + } + + params->sdram_timing = + (struct imxrt_sdram_timing *) + dev_read_u8_array_ptr(dev, + "fsl,sdram-timing", + sizeof(struct imxrt_sdram_timing)); + if (!params->sdram_timing) { + pr_err("fsl,sdram-timing not found"); + return -EINVAL; + } + + dev_for_each_subnode(bank_node, dev) { + struct bank_params *bank_params; + char *bank_name; + int ret; + + /* extract the bank index from DT */ + bank_name = (char *)ofnode_get_name(bank_node); + strsep(&bank_name, "@"); + if (!bank_name) { + pr_err("missing sdram bank index"); + return -EINVAL; + } + + bank_params = ¶ms->bank_params[bank]; + strict_strtoul(bank_name, 10, + (unsigned long *)&bank_params->target_bank); + if (bank_params->target_bank >= MAX_SDRAM_BANK) { + pr_err("Found bank %d , but only bank 0,1,2,3 are supported", + bank_params->target_bank); + return -EINVAL; + } + + ret = ofnode_read_u32(bank_node, + "fsl,memory-size", + &bank_params->memory_size); + if (ret < 0) { + pr_err("fsl,memory-size not found"); + return -EINVAL; + } + + ret = ofnode_read_u32(bank_node, + "fsl,base-address", + &bank_params->base_address); + if (ret < 0) { + pr_err("fsl,base-address not found"); + return -EINVAL; + } + + debug("Found bank %s %u\n", bank_name, + bank_params->target_bank); + bank++; + } + + params->no_sdram_banks = bank; + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + + return 0; +} + +static int imxrt_semc_probe(struct udevice *dev) +{ + struct imxrt_sdram_params *params = dev_get_plat(dev); + int ret; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + params->base = (struct imxrt_semc_regs *)addr; + +#ifdef CONFIG_CLK + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } +#endif + ret = imxrt_sdram_init(dev); + if (ret) + return ret; + + return 0; +} + +static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info) +{ + return 0; +} + +static struct ram_ops imxrt_semc_ops = { + .get_info = imxrt_semc_get_info, +}; + +static const struct udevice_id imxrt_semc_ids[] = { + { .compatible = "fsl,imxrt-semc", .data = 0 }, + { } +}; + +U_BOOT_DRIVER(imxrt_semc) = { + .name = "imxrt_semc", + .id = UCLASS_RAM, + .of_match = imxrt_semc_ids, + .ops = &imxrt_semc_ops, + .of_to_plat = imxrt_semc_of_to_plat, + .probe = imxrt_semc_probe, + .plat_auto = sizeof(struct imxrt_sdram_params), +}; diff --git a/roms/u-boot/drivers/ram/k3-am654-ddrss.c b/roms/u-boot/drivers/ram/k3-am654-ddrss.c new file mode 100644 index 000000000..4ec12bf42 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-am654-ddrss.c @@ -0,0 +1,1086 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' AM654 DDRSS driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "k3-am654-ddrss.h" + +#define LDELAY 10000 + +/* DDRSS PHY configuration register fixed values */ +#define DDRSS_DDRPHY_RANKIDR_RANK0 0 + +/** + * struct am654_ddrss_desc - Description of ddrss integration. + * @dev: DDRSS device pointer + * @ddrss_ss_cfg: DDRSS wrapper logic region base address + * @ddrss_ctl_cfg: DDRSS controller region base address + * @ddrss_phy_cfg: DDRSS PHY region base address + * @ddrss_clk: DDRSS clock description + * @vtt_supply: VTT Supply regulator + * @ddrss_pwrdmn: DDRSS power domain description + * @params: SDRAM configuration parameters + */ +struct am654_ddrss_desc { + struct udevice *dev; + void __iomem *ddrss_ss_cfg; + void __iomem *ddrss_ctl_cfg; + void __iomem *ddrss_phy_cfg; + struct clk ddrss_clk; + struct udevice *vtt_supply; + struct power_domain ddrcfg_pwrdmn; + struct power_domain ddrdata_pwrdmn; + struct ddrss_params params; +}; + +static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset) +{ + return readl(addr + offset); +} + +static inline void ddrss_writel(void __iomem *addr, unsigned int offset, + u32 data) +{ + debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data); + writel(data, addr + offset); +} + +#define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val) +#define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off) + +static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss) +{ + return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK; +} + +/** + * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete + * + * After detecting the DDR type this function will pause until the + * initialization is complete. Each DDR type has mask of multiple bits. + * The size of the field depends on the DDR Type. If the initialization + * does not complete and error will be returned and will cause the boot to halt. + * + */ +static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss) +{ + u32 val, mask; + + val = am654_ddrss_get_type(ddrss); + + switch (val) { + case DDR_TYPE_LPDDR4: + case DDR_TYPE_DDR4: + mask = DDR4_STAT_MODE_MASK; + break; + case DDR_TYPE_DDR3: + mask = DDR3_STAT_MODE_MASK; + break; + default: + printf("Unsupported DDR type 0x%x\n", val); + return -EINVAL; + } + + if (!wait_on_value(mask, DDR_MODE_NORMAL, + ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY)) + return -ETIMEDOUT; + + return 0; +} + +/** + * am654_ddrss_ctrl_configuration() - Configure Controller specific registers + * @dev: corresponding ddrss device + */ +static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss) +{ + struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing; + struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg; + struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc; + struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc; + struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map; + u32 val; + + debug("%s: DDR controller register configuration started\n", __func__); + + ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr); + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0); + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg); + + ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0); + ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0); + ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1); + ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2); + + ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7); + + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17); + + ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0); + ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1); + + ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0); + ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1); + ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2); + ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc); + + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11); + + ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg); + ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap); + + /* Disable refreshes */ + val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3); + val |= 0x01; + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val); + + debug("%s: DDR controller configuration completed\n", __func__); +} + +#define ddrss_phy_writel(off, val) \ + do { \ + ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \ + sdelay(10); /* Delay at least 20 clock cycles */ \ + } while (0) + +#define ddrss_phy_readl(off) \ + ({ \ + u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \ + sdelay(10); /* Delay at least 20 clock cycles */ \ + val; \ + }) + +/** + * am654_ddrss_phy_configuration() - Configure PHY specific registers + * @ddrss: corresponding ddrss device + */ +static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) +{ + struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl; + struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing; + struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl; + struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg; + struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq; + + debug("%s: DDR phy register configuration started\n", __func__); + + ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6); + + ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2); + ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3); + ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4); + ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5); + ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6); + + ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr); + ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr); + + ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr); + + ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6); + + ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr); + ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0); + ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0); + + ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0); + ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1); + ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2); + ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3); + ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4); + ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5); + ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6); + ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11); + ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12); + ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13); + ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14); + ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22); + + ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1); + + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0); + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3); + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5); + ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1); + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2); + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3); + + ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4); + + ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5); + + ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0); + + ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr); + + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr); + + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2); + + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl); + + debug("%s: DDR phy register configuration completed\n", __func__); +} + +static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss, + u32 init_value, u32 sts_mask, + u32 err_mask) +{ + int ret; + + ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK); + + sdelay(5); /* Delay at least 10 clock cycles */ + + if (!wait_on_value(sts_mask, sts_mask, + ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY)) + return -ETIMEDOUT; + + sdelay(16); /* Delay at least 32 clock cycles */ + + ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0); + debug("%s: PGSR0 val = 0x%x\n", __func__, ret); + if (ret & err_mask) + return -EINVAL; + + return 0; +} + +int write_leveling(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: Write leveling started\n", __func__); + + ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK, + PGSR0_WLERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Write leveling timedout\n", + __func__); + else + printf("%s:ERROR: Write leveling failed\n", __func__); + return ret; + } + + debug("%s: Write leveling completed\n", __func__); + return 0; +} + +int read_dqs_training(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: Read DQS training started\n", __func__); + + ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK, + PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Read DQS timedout\n", __func__); + else + printf("%s:ERROR: Read DQS Gate training failed\n", + __func__); + return ret; + } + + debug("%s: Read DQS training completed\n", __func__); + return 0; +} + +int dqs2dq_training(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: DQS2DQ training started\n", __func__); + + ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK, + PGSR0_DQS2DQDONE_MASK, + PGSR0_DQS2DQERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: DQS2DQ training timedout\n", + __func__); + else + printf("%s:ERROR: DQS2DQ training failed\n", + __func__); + return ret; + } + + debug("%s: DQS2DQ training completed\n", __func__); + return 0; +} + +int write_leveling_adjustment(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: Write Leveling adjustment\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK, + PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s:ERROR: Write Leveling adjustment timedout\n", + __func__); + else + printf("%s: ERROR: Write Leveling adjustment failed\n", + __func__); + return ret; + } + return 0; +} + +int rest_training(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: Rest of the training started\n", __func__); + + debug("%s: Read Deskew adjustment\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK, + PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Read Deskew timedout\n", __func__); + else + printf("%s: ERROR: Read Deskew failed\n", __func__); + return ret; + } + + debug("%s: Write Deskew adjustment\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK, + PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Write Deskew timedout\n", __func__); + else + printf("%s: ERROR: Write Deskew failed\n", __func__); + return ret; + } + + debug("%s: Read Eye training\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK, + PGSR0_REDONE_MASK, PGSR0_REERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Read Eye training timedout\n", + __func__); + else + printf("%s: ERROR: Read Eye training failed\n", + __func__); + return ret; + } + + debug("%s: Write Eye training\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK, + PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Write Eye training timedout\n", + __func__); + else + printf("%s: ERROR: Write Eye training failed\n", + __func__); + return ret; + } + return 0; +} + +int VREF_training(struct am654_ddrss_desc *ddrss) +{ + int ret; + debug("%s: VREF training\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK, + PGSR0_VERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: VREF training timedout\n", __func__); + else + printf("%s: ERROR: VREF training failed\n", __func__); + return ret; + } + return 0; +} + +int enable_dqs_pd(struct am654_ddrss_desc *ddrss) +{ + u32 val; + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val); + + sdelay(16); + return 0; +} + +int disable_dqs_pd(struct am654_ddrss_desc *ddrss) +{ + u32 val; + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val); + + sdelay(16); + return 0; +} + +int cleanup_training(struct am654_ddrss_desc *ddrss) +{ + u32 val; + u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd; + + ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000); + dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2; + dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2; + dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2; + dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2; + + rddly = dgsl0; + if (dgsl1 < rddly) + rddly = dgsl1; + if (dgsl2 < rddly) + rddly = dgsl2; + if (dgsl3 < rddly) + rddly = dgsl3; + + rddly += 5; + + /* Update rddly based on dgsl values */ + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val); + + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val); + + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val); + + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val); + + /* + * Add system latency derived from training back into rd2wr and wr2rd + * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2 + * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2 + */ + + /* Select rank 0 */ + ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000); + + dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F); + dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F); + dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F); + dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F); + + /* Find maximum value across all bytes */ + rd2wr_wr2rd = dgsl0; + if (dgsl1 > rd2wr_wr2rd) + rd2wr_wr2rd = dgsl1; + if (dgsl2 > rd2wr_wr2rd) + rd2wr_wr2rd = dgsl2; + if (dgsl3 > rd2wr_wr2rd) + rd2wr_wr2rd = dgsl3; + + rd2wr_wr2rd >>= 1; + + /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */ + /* Clear VSWCTL.sw_done */ + ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL, + ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1); + /* Adjust rd2wr */ + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, + ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) + + (rd2wr_wr2rd << 8)); + /* Adjust wr2rd */ + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, + ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) + + rd2wr_wr2rd); + /* Set VSWCTL.sw_done */ + ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL, + ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1); + /* Wait until settings are applied */ + while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) { + /* Do nothing */ + }; + + debug("%s: Rest of the training completed\n", __func__); + return 0; +} + +/** + * am654_ddrss_init() - Initialization sequence for enabling the SDRAM + * device attached to ddrss. + * @dev: corresponding ddrss device + * + * Does all the initialization sequence that is required to get attached + * ddr in a working state. After this point, ddr should be accessible. + * Return: 0 if all went ok, else corresponding error message. + */ +static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) +{ + int ret; + u32 val; + struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg; + + debug("Starting DDR initialization...\n"); + + debug("%s(ddrss=%p)\n", __func__, ddrss); + + ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, + reg->ddrss_v2h_ctl_reg); + + am654_ddrss_ctrl_configuration(ddrss); + + /* Release the reset to the controller */ + clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG, + SS_CTL_REG_CTL_ARST_MASK); + + am654_ddrss_phy_configuration(ddrss); + + debug("Starting DDR training...\n"); + ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0); + if (ret) { + dev_err(ddrss->dev, "PHY initialization failed %d\n", ret); + return ret; + } + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + val = am654_ddrss_get_type(ddrss); + + switch (val) { + case DDR_TYPE_LPDDR4: + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + /* must perform DRAM_INIT twice for LPDDR4 */ + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + ret = write_leveling(ddrss); + if (ret) + return ret; + + ret = enable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = read_dqs_training(ddrss); + if (ret) + return ret; + + ret = disable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = dqs2dq_training(ddrss); + if (ret) + return ret; + + ret = write_leveling_adjustment(ddrss); + if (ret) + return ret; + + ret = rest_training(ddrss); + if (ret) + return ret; + + ret = VREF_training(ddrss); + if (ret) + return ret; + + debug("LPDDR4 training complete\n"); + break; + + case DDR_TYPE_DDR4: + + debug("Starting DDR4 training\n"); + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + ret = write_leveling(ddrss); + if (ret) + return ret; + + ret = read_dqs_training(ddrss); + if (ret) + return ret; + + ret = write_leveling_adjustment(ddrss); + if (ret) + return ret; + + ret = rest_training(ddrss); + if (ret) + return ret; + + ret = VREF_training(ddrss); + if (ret) + return ret; + debug("DDR4 training complete\n"); + break; + + case DDR_TYPE_DDR3: + + debug("Starting DDR3 training\n"); + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", + ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + ret = write_leveling(ddrss); + if (ret) + return ret; + + ret = enable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = read_dqs_training(ddrss); + if (ret) + return ret; + + ret = disable_dqs_pd(ddrss); + if (ret) + return ret; + + ret = write_leveling_adjustment(ddrss); + if (ret) + return ret; + + ret = rest_training(ddrss); + if (ret) + return ret; + + debug("DDR3 training complete\n"); + break; + default: + printf("%s: ERROR: Unsupported DDR type\n", __func__); + return -EINVAL; + } + + ret = cleanup_training(ddrss); + if (ret) + return ret; + + /* Enabling refreshes after training is done */ + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, + ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1); + + /* Disable PUBMODE after training is done */ + ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, + ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40); + + debug("Completed DDR training\n"); + + return 0; +} + +/** + * am654_ddrss_power_on() - Enable power and clocks for ddrss + * @dev: corresponding ddrss device + * + * Tries to enable all the corresponding clocks to the ddrss and sets it + * to the right frequency and then power on the ddrss. + * Return: 0 if all went ok, else corresponding error message. + */ +static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s(ddrss=%p)\n", __func__, ddrss); + + ret = clk_enable(&ddrss->ddrss_clk); + if (ret) { + dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret); + return ret; + } + + ret = power_domain_on(&ddrss->ddrcfg_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = power_domain_on(&ddrss->ddrdata_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + /* VTT enable */ +#if CONFIG_IS_ENABLED(DM_REGULATOR) + device_get_supply_regulator(ddrss->dev, "vtt-supply", + &ddrss->vtt_supply); + ret = regulator_set_value(ddrss->vtt_supply, 3300000); + if (ret) + return ret; + debug("VTT regulator enabled\n"); +#endif + + return 0; +} + +/** + * am654_ddrss_ofdata_to_priv() - generate private data from device tree + * @dev: corresponding ddrss device + * + * Return: 0 if all went ok, else corresponding error message. + */ +static int am654_ddrss_ofdata_to_priv(struct udevice *dev) +{ + struct am654_ddrss_desc *ddrss = dev_get_priv(dev); + phys_addr_t reg; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk); + if (ret) { + dev_err(dev, "clk_get failed: %d\n", ret); + return ret; + } + + ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + reg = devfdt_get_addr_name(dev, "ss"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for DDRSS wrapper logic\n"); + return -EINVAL; + } + ddrss->ddrss_ss_cfg = (void *)reg; + + reg = devfdt_get_addr_name(dev, "ctl"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for Controller region\n"); + return -EINVAL; + } + ddrss->ddrss_ctl_cfg = (void *)reg; + + reg = devfdt_get_addr_name(dev, "phy"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for PHY region\n"); + return -EINVAL; + } + ddrss->ddrss_phy_cfg = (void *)reg; + + ret = dev_read_u32_array(dev, "ti,ss-reg", + (u32 *)&ddrss->params.ss_reg, + sizeof(ddrss->params.ss_reg) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ss-reg params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-reg", + (u32 *)&ddrss->params.ctl_reg, + sizeof(ddrss->params.ctl_reg) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-reg params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-crc", + (u32 *)&ddrss->params.ctl_crc, + sizeof(ddrss->params.ctl_crc) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-crc params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-ecc", + (u32 *)&ddrss->params.ctl_ecc, + sizeof(ddrss->params.ctl_ecc) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-ecc params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-map", + (u32 *)&ddrss->params.ctl_map, + sizeof(ddrss->params.ctl_map) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-map params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-pwr", + (u32 *)&ddrss->params.ctl_pwr, + sizeof(ddrss->params.ctl_pwr) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-pwr params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-timing", + (u32 *)&ddrss->params.ctl_timing, + sizeof(ddrss->params.ctl_timing) / + sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-timing params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-cfg", + (u32 *)&ddrss->params.phy_cfg, + sizeof(ddrss->params.phy_cfg) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-cfg params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-ctl", + (u32 *)&ddrss->params.phy_ctrl, + sizeof(ddrss->params.phy_ctrl) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-ctl params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-ioctl", + (u32 *)&ddrss->params.phy_ioctl, + sizeof(ddrss->params.phy_ioctl) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-ioctl params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-timing", + (u32 *)&ddrss->params.phy_timing, + sizeof(ddrss->params.phy_timing) / + sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-timing params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq, + sizeof(ddrss->params.phy_zq) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-zq params\n"); + return ret; + } + + return ret; +} + +/** + * am654_ddrss_probe() - Basic probe + * @dev: corresponding ddrss device + * + * Return: 0 if all went ok, else corresponding error message + */ +static int am654_ddrss_probe(struct udevice *dev) +{ + struct am654_ddrss_desc *ddrss = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + ret = am654_ddrss_ofdata_to_priv(dev); + if (ret) + return ret; + + ddrss->dev = dev; + ret = am654_ddrss_power_on(ddrss); + if (ret) + return ret; + + ret = am654_ddrss_init(ddrss); + + return ret; +} + +static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info) +{ + return 0; +} + +static struct ram_ops am654_ddrss_ops = { + .get_info = am654_ddrss_get_info, +}; + +static const struct udevice_id am654_ddrss_ids[] = { + { .compatible = "ti,am654-ddrss" }, + { } +}; + +U_BOOT_DRIVER(am654_ddrss) = { + .name = "am654_ddrss", + .id = UCLASS_RAM, + .of_match = am654_ddrss_ids, + .ops = &am654_ddrss_ops, + .probe = am654_ddrss_probe, + .priv_auto = sizeof(struct am654_ddrss_desc), +}; diff --git a/roms/u-boot/drivers/ram/k3-am654-ddrss.h b/roms/u-boot/drivers/ram/k3-am654-ddrss.h new file mode 100644 index 000000000..c87f18629 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-am654-ddrss.h @@ -0,0 +1,1200 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AM654: DDRSS Register definitions and structures. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + * + */ + +#ifndef __K3_AM654_DDRSS_H +#define __K3_AM654_DDRSS_H + +/* DDRSS subsystem wrapper logic registers */ +#include +#define DDRSS_SS_ID_REV_REG 0x00000000 +#define DDRSS_SS_CTL_REG 0x00000004 +#define DDRSS_V2H_CTL_REG 0x00000020 + +#define SS_CTL_REG_CTL_ARST_SHIFT 0x0 +#define SS_CTL_REG_CTL_ARST_MASK BIT(SS_CTL_REG_CTL_ARST_SHIFT) + +/* DDRSS controller configuration registers */ +#define DDRSS_DDRCTL_MSTR 0x00000000 +#define DDRSS_DDRCTL_STAT 0x00000004 +#define DDRSS_DDRCTL_MRCTRL0 0x00000010 +#define DDRSS_DDRCTL_MRCTRL1 0x00000014 +#define DDRSS_DDRCTL_MRSTAT 0x00000018 +#define DDRSS_DDRCTL_MRCTRL2 0x0000001C +#define DDRSS_DDRCTL_DERATEEN 0x00000020 +#define DDRSS_DDRCTL_DERATEINT 0x00000024 +#define DDRSS_DDRCTL_MSTR2 0x00000028 +#define DDRSS_DDRCTL_PWRCTL 0x00000030 +#define DDRSS_DDRCTL_PWRTMG 0x00000034 +#define DDRSS_DDRCTL_HWLPCTL 0x00000038 +#define DDRSS_DDRCTL_RFSHCTL0 0x00000050 +#define DDRSS_DDRCTL_RFSHCTL1 0x00000054 +#define DDRSS_DDRCTL_RFSHCTL2 0x00000058 +#define DDRSS_DDRCTL_RFSHCTL3 0x00000060 +#define DDRSS_DDRCTL_RFSHTMG 0x00000064 +#define DDRSS_DDRCTL_ECCCFG0 0x00000070 +#define DDRSS_DDRCTL_ECCCFG1 0x00000074 +#define DDRSS_DDRCTL_ECCSTAT 0x00000078 +#define DDRSS_DDRCTL_ECCCLR 0x0000007C +#define DDRSS_DDRCTL_ECCERRCNT 0x00000080 +#define DDRSS_DDRCTL_ECCCADDR0 0x00000084 +#define DDRSS_DDRCTL_ECCCADDR1 0x00000088 +#define DDRSS_DDRCTL_ECCCSYN0 0x0000008C +#define DDRSS_DDRCTL_ECCCSYN2 0x00000094 +#define DDRSS_DDRCTL_ECCBITMASK0 0x00000098 +#define DDRSS_DDRCTL_ECCBITMASK2 0x000000A0 +#define DDRSS_DDRCTL_ECCUADDR0 0x000000A4 +#define DDRSS_DDRCTL_ECCUADDR1 0x000000A8 +#define DDRSS_DDRCTL_ECCUSYN0 0x000000AC +#define DDRSS_DDRCTL_ECCUSYN2 0x000000B4 +#define DDRSS_DDRCTL_ECCPOISONADDR0 0x000000B8 +#define DDRSS_DDRCTL_ECCPOISONADDR1 0x000000BC +#define DDRSS_DDRCTL_CRCPARCTL0 0x000000C0 +#define DDRSS_DDRCTL_CRCPARCTL1 0x000000C4 +#define DDRSS_DDRCTL_CRCPARCTL2 0x000000C8 +#define DDRSS_DDRCTL_CRCPARSTAT 0x000000CC +#define DDRSS_DDRCTL_INIT0 0x000000D0 +#define DDRSS_DDRCTL_INIT1 0x000000D4 +#define DDRSS_DDRCTL_INIT2 0x000000D8 +#define DDRSS_DDRCTL_INIT3 0x000000DC +#define DDRSS_DDRCTL_INIT4 0x000000E0 +#define DDRSS_DDRCTL_INIT5 0x000000E4 +#define DDRSS_DDRCTL_INIT6 0x000000E8 +#define DDRSS_DDRCTL_INIT7 0x000000EC +#define DDRSS_DDRCTL_DIMMCTL 0x000000F0 +#define DDRSS_DDRCTL_RANKCTL 0x000000F4 +#define DDRSS_DDRCTL_DRAMTMG0 0x00000100 +#define DDRSS_DDRCTL_DRAMTMG1 0x00000104 +#define DDRSS_DDRCTL_DRAMTMG2 0x00000108 +#define DDRSS_DDRCTL_DRAMTMG3 0x0000010C +#define DDRSS_DDRCTL_DRAMTMG4 0x00000110 +#define DDRSS_DDRCTL_DRAMTMG5 0x00000114 +#define DDRSS_DDRCTL_DRAMTMG6 0x00000118 +#define DDRSS_DDRCTL_DRAMTMG7 0x0000011C +#define DDRSS_DDRCTL_DRAMTMG8 0x00000120 +#define DDRSS_DDRCTL_DRAMTMG9 0x00000124 +#define DDRSS_DDRCTL_DRAMTMG10 0x00000128 +#define DDRSS_DDRCTL_DRAMTMG11 0x0000012C +#define DDRSS_DDRCTL_DRAMTMG12 0x00000130 +#define DDRSS_DDRCTL_DRAMTMG13 0x00000134 +#define DDRSS_DDRCTL_DRAMTMG14 0x00000138 +#define DDRSS_DDRCTL_DRAMTMG15 0x0000013C +#define DDRSS_DDRCTL_DRAMTMG17 0x00000144 +#define DDRSS_DDRCTL_ZQCTL0 0x00000180 +#define DDRSS_DDRCTL_ZQCTL1 0x00000184 +#define DDRSS_DDRCTL_ZQCTL2 0x00000188 +#define DDRSS_DDRCTL_ZQSTAT 0x0000018C +#define DDRSS_DDRCTL_DFITMG0 0x00000190 +#define DDRSS_DDRCTL_DFITMG1 0x00000194 +#define DDRSS_DDRCTL_DFILPCFG0 0x00000198 +#define DDRSS_DDRCTL_DFILPCFG1 0x0000019C +#define DDRSS_DDRCTL_DFIUPD0 0x000001A0 +#define DDRSS_DDRCTL_DFIUPD1 0x000001A4 +#define DDRSS_DDRCTL_DFIUPD2 0x000001A8 +#define DDRSS_DDRCTL_DFIMISC 0x000001B0 +#define DDRSS_DDRCTL_DFITMG2 0x000001B4 +#define DDRSS_DDRCTL_DFITMG3 0x000001B8 +#define DDRSS_DDRCTL_DFISTAT 0x000001BC +#define DDRSS_DDRCTL_DBICTL 0x000001C0 +#define DDRSS_DDRCTL_DFIPHYMSTR 0x000001C4 +#define DDRSS_DDRCTL_ADDRMAP0 0x00000200 +#define DDRSS_DDRCTL_ADDRMAP1 0x00000204 +#define DDRSS_DDRCTL_ADDRMAP2 0x00000208 +#define DDRSS_DDRCTL_ADDRMAP3 0x0000020C +#define DDRSS_DDRCTL_ADDRMAP4 0x00000210 +#define DDRSS_DDRCTL_ADDRMAP5 0x00000214 +#define DDRSS_DDRCTL_ADDRMAP6 0x00000218 +#define DDRSS_DDRCTL_ADDRMAP7 0x0000021C +#define DDRSS_DDRCTL_ADDRMAP8 0x00000220 +#define DDRSS_DDRCTL_ADDRMAP9 0x00000224 +#define DDRSS_DDRCTL_ADDRMAP10 0x00000228 +#define DDRSS_DDRCTL_ADDRMAP11 0x0000022C +#define DDRSS_DDRCTL_ODTCFG 0x00000240 +#define DDRSS_DDRCTL_ODTMAP 0x00000244 +#define DDRSS_DDRCTL_SCHED 0x00000250 +#define DDRSS_DDRCTL_SCHED1 0x00000254 +#define DDRSS_DDRCTL_PERFHPR1 0x0000025C +#define DDRSS_DDRCTL_PERFLPR1 0x00000264 +#define DDRSS_DDRCTL_PERFWR1 0x0000026C +#define DDRSS_DDRCTL_DQMAP0 0x00000280 +#define DDRSS_DDRCTL_DQMAP1 0x00000284 +#define DDRSS_DDRCTL_DQMAP4 0x00000290 +#define DDRSS_DDRCTL_DQMAP5 0x00000294 +#define DDRSS_DDRCTL_DBG0 0x00000300 +#define DDRSS_DDRCTL_DBG1 0x00000304 +#define DDRSS_DDRCTL_DBGCAM 0x00000308 +#define DDRSS_DDRCTL_DBGCMD 0x0000030C +#define DDRSS_DDRCTL_DBGSTAT 0x00000310 +#define DDRSS_DDRCTL_SWCTL 0x00000320 +#define DDRSS_DDRCTL_SWSTAT 0x00000324 +#define DDRSS_DDRCTL_ADVECCINDEX 0x00000374 +#define DDRSS_DDRCTL_ECCPOISONPAT0 0x0000037C +#define DDRSS_DDRCTL_ECCPOISONPAT2 0x00000384 +#define DDRSS_DDRCTL_CAPARPOISONCTL 0x000003A0 +#define DDRSS_DDRCTL_CAPARPOISONSTAT 0x000003A4 +#define DDRSS_DDRCTL_DERATEEN_SHDW 0x00002020 +#define DDRSS_DDRCTL_DERATEINT_SHDW 0x00002024 +#define DDRSS_DDRCTL_RFSHCTL0_SHDW 0x00002050 +#define DDRSS_DDRCTL_RFSHTMG_SHDW 0x00002064 +#define DDRSS_DDRCTL_INIT3_SHDW 0x000020DC +#define DDRSS_DDRCTL_INIT4_SHDW 0x000020E0 +#define DDRSS_DDRCTL_INIT6_SHDW 0x000020E8 +#define DDRSS_DDRCTL_INIT7_SHDW 0x000020EC +#define DDRSS_DDRCTL_DRAMTMG0_SHDW 0x00002100 +#define DDRSS_DDRCTL_DRAMTMG1_SHDW 0x00002104 +#define DDRSS_DDRCTL_DRAMTMG2_SHDW 0x00002108 +#define DDRSS_DDRCTL_DRAMTMG3_SHDW 0x0000210C +#define DDRSS_DDRCTL_DRAMTMG4_SHDW 0x00002110 +#define DDRSS_DDRCTL_DRAMTMG5_SHDW 0x00002114 +#define DDRSS_DDRCTL_DRAMTMG6_SHDW 0x00002118 +#define DDRSS_DDRCTL_DRAMTMG7_SHDW 0x0000211C +#define DDRSS_DDRCTL_DRAMTMG8_SHDW 0x00002120 +#define DDRSS_DDRCTL_DRAMTMG9_SHDW 0x00002124 +#define DDRSS_DDRCTL_DRAMTMG10_SHDW 0x00002128 +#define DDRSS_DDRCTL_DRAMTMG11_SHDW 0x0000212C +#define DDRSS_DDRCTL_DRAMTMG12_SHDW 0x00002130 +#define DDRSS_DDRCTL_DRAMTMG13_SHDW 0x00002134 +#define DDRSS_DDRCTL_DRAMTMG14_SHDW 0x00002138 +#define DDRSS_DDRCTL_DRAMTMG15_SHDW 0x0000213C +#define DDRSS_DDRCTL_ZQCTL0_SHDW 0x00002180 +#define DDRSS_DDRCTL_DFITMG0_SHDW 0x00002190 +#define DDRSS_DDRCTL_DFITMG1_SHDW 0x00002194 +#define DDRSS_DDRCTL_DFITMG2_SHDW 0x000021B4 +#define DDRSS_DDRCTL_DFITMG3_SHDW 0x000021B8 +#define DDRSS_DDRCTL_ODTCFG_SHDW 0x00002240 + +#define MSTR_DDR_TYPE_MASK GENMASK(5, 0) +#define DDR_TYPE_LPDDR4 0x20 +#define DDR_TYPE_DDR4 0x10 +#define DDR_TYPE_DDR3 0x1 + +#define DDR3_STAT_MODE_MASK GENMASK(1, 0) +#define DDR4_STAT_MODE_MASK GENMASK(2, 0) +#define DDR_MODE_NORMAL 0x1 + +/* DDRSS PHY configuration registers */ +#define DDRSS_DDRPHY_RIDR 0x00000000 +#define DDRSS_DDRPHY_PIR 0x00000004 +#define DDRSS_DDRPHY_PGCR0 0x00000010 +#define DDRSS_DDRPHY_PGCR1 0x00000014 +#define DDRSS_DDRPHY_PGCR2 0x00000018 +#define DDRSS_DDRPHY_PGCR3 0x0000001C +#define DDRSS_DDRPHY_PGCR4 0x00000020 +#define DDRSS_DDRPHY_PGCR5 0x00000024 +#define DDRSS_DDRPHY_PGCR6 0x00000028 +#define DDRSS_DDRPHY_PGCR7 0x0000002C +#define DDRSS_DDRPHY_PGSR0 0x00000030 +#define DDRSS_DDRPHY_PGSR1 0x00000034 +#define DDRSS_DDRPHY_PGSR2 0x00000038 +#define DDRSS_DDRPHY_PTR0 0x00000040 +#define DDRSS_DDRPHY_PTR1 0x00000044 +#define DDRSS_DDRPHY_PTR2 0x00000048 +#define DDRSS_DDRPHY_PTR3 0x0000004C +#define DDRSS_DDRPHY_PTR4 0x00000050 +#define DDRSS_DDRPHY_PTR5 0x00000054 +#define DDRSS_DDRPHY_PTR6 0x00000058 +#define DDRSS_DDRPHY_PLLCR0 0x00000068 +#define DDRSS_DDRPHY_PLLCR1 0x0000006C +#define DDRSS_DDRPHY_PLLCR2 0x00000070 +#define DDRSS_DDRPHY_PLLCR3 0x00000074 +#define DDRSS_DDRPHY_PLLCR4 0x00000078 +#define DDRSS_DDRPHY_PLLCR5 0x0000007C +#define DDRSS_DDRPHY_DXCCR 0x00000088 +#define DDRSS_DDRPHY_DSGCR 0x00000090 +#define DDRSS_DDRPHY_ODTCR 0x00000098 +#define DDRSS_DDRPHY_AACR 0x000000A0 +#define DDRSS_DDRPHY_GPR0 0x000000C0 +#define DDRSS_DDRPHY_GPR1 0x000000C4 +#define DDRSS_DDRPHY_DCR 0x00000100 +#define DDRSS_DDRPHY_DTPR0 0x00000110 +#define DDRSS_DDRPHY_DTPR1 0x00000114 +#define DDRSS_DDRPHY_DTPR2 0x00000118 +#define DDRSS_DDRPHY_DTPR3 0x0000011C +#define DDRSS_DDRPHY_DTPR4 0x00000120 +#define DDRSS_DDRPHY_DTPR5 0x00000124 +#define DDRSS_DDRPHY_DTPR6 0x00000128 +#define DDRSS_DDRPHY_RDIMMGCR0 0x00000140 +#define DDRSS_DDRPHY_RDIMMGCR1 0x00000144 +#define DDRSS_DDRPHY_RDIMMGCR2 0x00000148 +#define DDRSS_DDRPHY_RDIMMCR0 0x00000150 +#define DDRSS_DDRPHY_RDIMMCR1 0x00000154 +#define DDRSS_DDRPHY_RDIMMCR2 0x00000158 +#define DDRSS_DDRPHY_RDIMMCR3 0x0000015C +#define DDRSS_DDRPHY_RDIMMCR4 0x00000160 +#define DDRSS_DDRPHY_SCHCR0 0x00000168 +#define DDRSS_DDRPHY_SCHCR1 0x0000016C +#define DDRSS_DDRPHY_MR0 0x00000180 +#define DDRSS_DDRPHY_MR1 0x00000184 +#define DDRSS_DDRPHY_MR2 0x00000188 +#define DDRSS_DDRPHY_MR3 0x0000018C +#define DDRSS_DDRPHY_MR4 0x00000190 +#define DDRSS_DDRPHY_MR5 0x00000194 +#define DDRSS_DDRPHY_MR6 0x00000198 +#define DDRSS_DDRPHY_MR7 0x0000019C +#define DDRSS_DDRPHY_MR11 0x000001AC +#define DDRSS_DDRPHY_MR12 0x000001B0 +#define DDRSS_DDRPHY_MR13 0x000001B4 +#define DDRSS_DDRPHY_MR14 0x000001B8 +#define DDRSS_DDRPHY_MR22 0x000001D8 +#define DDRSS_DDRPHY_DTCR0 0x00000200 +#define DDRSS_DDRPHY_DTCR1 0x00000204 +#define DDRSS_DDRPHY_DTAR0 0x00000208 +#define DDRSS_DDRPHY_DTAR1 0x0000020C +#define DDRSS_DDRPHY_DTAR2 0x00000210 +#define DDRSS_DDRPHY_DTDR0 0x00000218 +#define DDRSS_DDRPHY_DTDR1 0x0000021C +#define DDRSS_DDRPHY_DTEDR0 0x00000230 +#define DDRSS_DDRPHY_DTEDR1 0x00000234 +#define DDRSS_DDRPHY_DTEDR2 0x00000238 +#define DDRSS_DDRPHY_VTDR 0x0000023C +#define DDRSS_DDRPHY_CATR0 0x00000240 +#define DDRSS_DDRPHY_CATR1 0x00000244 +#define DDRSS_DDRPHY_PGCR8 0x00000248 +#define DDRSS_DDRPHY_DQSDR0 0x00000250 +#define DDRSS_DDRPHY_DQSDR1 0x00000254 +#define DDRSS_DDRPHY_DQSDR2 0x00000258 +#define DDRSS_DDRPHY_DCUAR 0x00000300 +#define DDRSS_DDRPHY_DCUDR 0x00000304 +#define DDRSS_DDRPHY_DCURR 0x00000308 +#define DDRSS_DDRPHY_DCULR 0x0000030C +#define DDRSS_DDRPHY_DCUGCR 0x00000310 +#define DDRSS_DDRPHY_DCUTPR 0x00000314 +#define DDRSS_DDRPHY_DCUSR0 0x00000318 +#define DDRSS_DDRPHY_DCUSR1 0x0000031C +#define DDRSS_DDRPHY_BISTRR 0x00000400 +#define DDRSS_DDRPHY_BISTWCR 0x00000404 +#define DDRSS_DDRPHY_BISTMSKR0 0x00000408 +#define DDRSS_DDRPHY_BISTMSKR1 0x0000040C +#define DDRSS_DDRPHY_BISTMSKR2 0x00000410 +#define DDRSS_DDRPHY_BISTLSR 0x00000414 +#define DDRSS_DDRPHY_BISTAR0 0x00000418 +#define DDRSS_DDRPHY_BISTAR1 0x0000041C +#define DDRSS_DDRPHY_BISTAR2 0x00000420 +#define DDRSS_DDRPHY_BISTAR3 0x00000424 +#define DDRSS_DDRPHY_BISTAR4 0x00000428 +#define DDRSS_DDRPHY_BISTUDPR 0x0000042C +#define DDRSS_DDRPHY_BISTGSR 0x00000430 +#define DDRSS_DDRPHY_BISTWER0 0x00000434 +#define DDRSS_DDRPHY_BISTWER1 0x00000438 +#define DDRSS_DDRPHY_BISTBER0 0x0000043C +#define DDRSS_DDRPHY_BISTBER1 0x00000440 +#define DDRSS_DDRPHY_BISTBER2 0x00000444 +#define DDRSS_DDRPHY_BISTBER3 0x00000448 +#define DDRSS_DDRPHY_BISTBER4 0x0000044C +#define DDRSS_DDRPHY_BISTWCSR 0x00000450 +#define DDRSS_DDRPHY_BISTFWR0 0x00000454 +#define DDRSS_DDRPHY_BISTFWR1 0x00000458 +#define DDRSS_DDRPHY_BISTFWR2 0x0000045C +#define DDRSS_DDRPHY_BISTBER5 0x00000460 +#define DDRSS_DDRPHY_RANKIDR 0x000004DC +#define DDRSS_DDRPHY_RIOCR0 0x000004E0 +#define DDRSS_DDRPHY_RIOCR1 0x000004E4 +#define DDRSS_DDRPHY_RIOCR2 0x000004E8 +#define DDRSS_DDRPHY_RIOCR3 0x000004EC +#define DDRSS_DDRPHY_RIOCR4 0x000004F0 +#define DDRSS_DDRPHY_RIOCR5 0x000004F4 +#define DDRSS_DDRPHY_ACIOCR0 0x00000500 +#define DDRSS_DDRPHY_ACIOCR1 0x00000504 +#define DDRSS_DDRPHY_ACIOCR2 0x00000508 +#define DDRSS_DDRPHY_ACIOCR3 0x0000050C +#define DDRSS_DDRPHY_ACIOCR4 0x00000510 +#define DDRSS_DDRPHY_ACIOCR5 0x00000514 +#define DDRSS_DDRPHY_IOVCR0 0x00000520 +#define DDRSS_DDRPHY_IOVCR1 0x00000524 +#define DDRSS_DDRPHY_VTCR0 0x00000528 +#define DDRSS_DDRPHY_VTCR1 0x0000052C +#define DDRSS_DDRPHY_ACBDLR0 0x00000540 +#define DDRSS_DDRPHY_ACBDLR1 0x00000544 +#define DDRSS_DDRPHY_ACBDLR2 0x00000548 +#define DDRSS_DDRPHY_ACBDLR3 0x0000054C +#define DDRSS_DDRPHY_ACBDLR4 0x00000550 +#define DDRSS_DDRPHY_ACBDLR5 0x00000554 +#define DDRSS_DDRPHY_ACBDLR6 0x00000558 +#define DDRSS_DDRPHY_ACBDLR7 0x0000055C +#define DDRSS_DDRPHY_ACBDLR8 0x00000560 +#define DDRSS_DDRPHY_ACBDLR9 0x00000564 +#define DDRSS_DDRPHY_ACBDLR10 0x00000568 +#define DDRSS_DDRPHY_ACBDLR11 0x0000056C +#define DDRSS_DDRPHY_ACBDLR12 0x00000570 +#define DDRSS_DDRPHY_ACBDLR13 0x00000574 +#define DDRSS_DDRPHY_ACBDLR14 0x00000578 +#define DDRSS_DDRPHY_ACBDLR15 0x0000057C +#define DDRSS_DDRPHY_ACBDLR16 0x00000580 +#define DDRSS_DDRPHY_ACLCDLR 0x00000584 +#define DDRSS_DDRPHY_ACMDLR0 0x000005A0 +#define DDRSS_DDRPHY_ACMDLR1 0x000005A4 +#define DDRSS_DDRPHY_ZQCR 0x00000680 +#define DDRSS_DDRPHY_ZQ0PR0 0x00000684 +#define DDRSS_DDRPHY_ZQ0PR1 0x00000688 +#define DDRSS_DDRPHY_ZQ0DR0 0x0000068C +#define DDRSS_DDRPHY_ZQ0DR1 0x00000690 +#define DDRSS_DDRPHY_ZQ0OR0 0x00000694 +#define DDRSS_DDRPHY_ZQ0OR1 0x00000698 +#define DDRSS_DDRPHY_ZQ0SR 0x0000069C +#define DDRSS_DDRPHY_ZQ1PR0 0x000006A4 +#define DDRSS_DDRPHY_ZQ1PR1 0x000006A8 +#define DDRSS_DDRPHY_ZQ1DR0 0x000006AC +#define DDRSS_DDRPHY_ZQ1DR1 0x000006B0 +#define DDRSS_DDRPHY_ZQ1OR0 0x000006B4 +#define DDRSS_DDRPHY_ZQ1OR1 0x000006B8 +#define DDRSS_DDRPHY_ZQ1SR 0x000006BC +#define DDRSS_DDRPHY_ZQ2PR0 0x000006C4 +#define DDRSS_DDRPHY_ZQ2PR1 0x000006C8 +#define DDRSS_DDRPHY_ZQ2DR0 0x000006CC +#define DDRSS_DDRPHY_ZQ2DR1 0x000006D0 +#define DDRSS_DDRPHY_ZQ2OR0 0x000006D4 +#define DDRSS_DDRPHY_ZQ2OR1 0x000006D8 +#define DDRSS_DDRPHY_ZQ2SR 0x000006DC +#define DDRSS_DDRPHY_ZQ3PR0 0x000006E4 +#define DDRSS_DDRPHY_ZQ3PR1 0x000006E8 +#define DDRSS_DDRPHY_ZQ3DR0 0x000006EC +#define DDRSS_DDRPHY_ZQ3DR1 0x000006F0 +#define DDRSS_DDRPHY_ZQ3OR0 0x000006F4 +#define DDRSS_DDRPHY_ZQ3OR1 0x000006F8 +#define DDRSS_DDRPHY_ZQ3SR 0x000006FC +#define DDRSS_DDRPHY_DX0GCR0 0x00000700 +#define DDRSS_DDRPHY_DX0GCR1 0x00000704 +#define DDRSS_DDRPHY_DX0GCR2 0x00000708 +#define DDRSS_DDRPHY_DX0GCR3 0x0000070C +#define DDRSS_DDRPHY_DX0GCR4 0x00000710 +#define DDRSS_DDRPHY_DX0GCR5 0x00000714 +#define DDRSS_DDRPHY_DX0GCR6 0x00000718 +#define DDRSS_DDRPHY_DX0GCR7 0x0000071C +#define DDRSS_DDRPHY_DX0GCR8 0x00000720 +#define DDRSS_DDRPHY_DX0GCR9 0x00000724 +#define DDRSS_DDRPHY_DX0DQMAP0 0x00000728 +#define DDRSS_DDRPHY_DX0DQMAP1 0x0000072C +#define DDRSS_DDRPHY_DX0BDLR0 0x00000740 +#define DDRSS_DDRPHY_DX0BDLR1 0x00000744 +#define DDRSS_DDRPHY_DX0BDLR2 0x00000748 +#define DDRSS_DDRPHY_DX0BDLR3 0x00000750 +#define DDRSS_DDRPHY_DX0BDLR4 0x00000754 +#define DDRSS_DDRPHY_DX0BDLR5 0x00000758 +#define DDRSS_DDRPHY_DX0BDLR6 0x00000760 +#define DDRSS_DDRPHY_DX0BDLR7 0x00000764 +#define DDRSS_DDRPHY_DX0BDLR8 0x00000768 +#define DDRSS_DDRPHY_DX0BDLR9 0x0000076C +#define DDRSS_DDRPHY_DX0LCDLR0 0x00000780 +#define DDRSS_DDRPHY_DX0LCDLR1 0x00000784 +#define DDRSS_DDRPHY_DX0LCDLR2 0x00000788 +#define DDRSS_DDRPHY_DX0LCDLR3 0x0000078C +#define DDRSS_DDRPHY_DX0LCDLR4 0x00000790 +#define DDRSS_DDRPHY_DX0LCDLR5 0x00000794 +#define DDRSS_DDRPHY_DX0MDLR0 0x000007A0 +#define DDRSS_DDRPHY_DX0MDLR1 0x000007A4 +#define DDRSS_DDRPHY_DX0GTR0 0x000007C0 +#define DDRSS_DDRPHY_DX0RSR0 0x000007D0 +#define DDRSS_DDRPHY_DX0RSR1 0x000007D4 +#define DDRSS_DDRPHY_DX0RSR2 0x000007D8 +#define DDRSS_DDRPHY_DX0RSR3 0x000007DC +#define DDRSS_DDRPHY_DX0GSR0 0x000007E0 +#define DDRSS_DDRPHY_DX0GSR1 0x000007E4 +#define DDRSS_DDRPHY_DX0GSR2 0x000007E8 +#define DDRSS_DDRPHY_DX0GSR3 0x000007EC +#define DDRSS_DDRPHY_DX0GSR4 0x000007F0 +#define DDRSS_DDRPHY_DX0GSR5 0x000007F4 +#define DDRSS_DDRPHY_DX0GSR6 0x000007F8 +#define DDRSS_DDRPHY_DX1GCR0 0x00000800 +#define DDRSS_DDRPHY_DX1GCR1 0x00000804 +#define DDRSS_DDRPHY_DX1GCR2 0x00000808 +#define DDRSS_DDRPHY_DX1GCR3 0x0000080C +#define DDRSS_DDRPHY_DX1GCR4 0x00000810 +#define DDRSS_DDRPHY_DX1GCR5 0x00000814 +#define DDRSS_DDRPHY_DX1GCR6 0x00000818 +#define DDRSS_DDRPHY_DX1GCR7 0x0000081C +#define DDRSS_DDRPHY_DX1GCR8 0x00000820 +#define DDRSS_DDRPHY_DX1GCR9 0x00000824 +#define DDRSS_DDRPHY_DX1DQMAP0 0x00000828 +#define DDRSS_DDRPHY_DX1DQMAP1 0x0000082C +#define DDRSS_DDRPHY_DX1BDLR0 0x00000840 +#define DDRSS_DDRPHY_DX1BDLR1 0x00000844 +#define DDRSS_DDRPHY_DX1BDLR2 0x00000848 +#define DDRSS_DDRPHY_DX1BDLR3 0x00000850 +#define DDRSS_DDRPHY_DX1BDLR4 0x00000854 +#define DDRSS_DDRPHY_DX1BDLR5 0x00000858 +#define DDRSS_DDRPHY_DX1BDLR6 0x00000860 +#define DDRSS_DDRPHY_DX1BDLR7 0x00000864 +#define DDRSS_DDRPHY_DX1BDLR8 0x00000868 +#define DDRSS_DDRPHY_DX1BDLR9 0x0000086C +#define DDRSS_DDRPHY_DX1LCDLR0 0x00000880 +#define DDRSS_DDRPHY_DX1LCDLR1 0x00000884 +#define DDRSS_DDRPHY_DX1LCDLR2 0x00000888 +#define DDRSS_DDRPHY_DX1LCDLR3 0x0000088C +#define DDRSS_DDRPHY_DX1LCDLR4 0x00000890 +#define DDRSS_DDRPHY_DX1LCDLR5 0x00000894 +#define DDRSS_DDRPHY_DX1MDLR0 0x000008A0 +#define DDRSS_DDRPHY_DX1MDLR1 0x000008A4 +#define DDRSS_DDRPHY_DX1GTR0 0x000008C0 +#define DDRSS_DDRPHY_DX1RSR0 0x000008D0 +#define DDRSS_DDRPHY_DX1RSR1 0x000008D4 +#define DDRSS_DDRPHY_DX1RSR2 0x000008D8 +#define DDRSS_DDRPHY_DX1RSR3 0x000008DC +#define DDRSS_DDRPHY_DX1GSR0 0x000008E0 +#define DDRSS_DDRPHY_DX1GSR1 0x000008E4 +#define DDRSS_DDRPHY_DX1GSR2 0x000008E8 +#define DDRSS_DDRPHY_DX1GSR3 0x000008EC +#define DDRSS_DDRPHY_DX1GSR4 0x000008F0 +#define DDRSS_DDRPHY_DX1GSR5 0x000008F4 +#define DDRSS_DDRPHY_DX1GSR6 0x000008F8 +#define DDRSS_DDRPHY_DX2GCR0 0x00000900 +#define DDRSS_DDRPHY_DX2GCR1 0x00000904 +#define DDRSS_DDRPHY_DX2GCR2 0x00000908 +#define DDRSS_DDRPHY_DX2GCR3 0x0000090C +#define DDRSS_DDRPHY_DX2GCR4 0x00000910 +#define DDRSS_DDRPHY_DX2GCR5 0x00000914 +#define DDRSS_DDRPHY_DX2GCR6 0x00000918 +#define DDRSS_DDRPHY_DX2GCR7 0x0000091C +#define DDRSS_DDRPHY_DX2GCR8 0x00000920 +#define DDRSS_DDRPHY_DX2GCR9 0x00000924 +#define DDRSS_DDRPHY_DX2DQMAP0 0x00000928 +#define DDRSS_DDRPHY_DX2DQMAP1 0x0000092C +#define DDRSS_DDRPHY_DX2BDLR0 0x00000940 +#define DDRSS_DDRPHY_DX2BDLR1 0x00000944 +#define DDRSS_DDRPHY_DX2BDLR2 0x00000948 +#define DDRSS_DDRPHY_DX2BDLR3 0x00000950 +#define DDRSS_DDRPHY_DX2BDLR4 0x00000954 +#define DDRSS_DDRPHY_DX2BDLR5 0x00000958 +#define DDRSS_DDRPHY_DX2BDLR6 0x00000960 +#define DDRSS_DDRPHY_DX2BDLR7 0x00000964 +#define DDRSS_DDRPHY_DX2BDLR8 0x00000968 +#define DDRSS_DDRPHY_DX2BDLR9 0x0000096C +#define DDRSS_DDRPHY_DX2LCDLR0 0x00000980 +#define DDRSS_DDRPHY_DX2LCDLR1 0x00000984 +#define DDRSS_DDRPHY_DX2LCDLR2 0x00000988 +#define DDRSS_DDRPHY_DX2LCDLR3 0x0000098C +#define DDRSS_DDRPHY_DX2LCDLR4 0x00000990 +#define DDRSS_DDRPHY_DX2LCDLR5 0x00000994 +#define DDRSS_DDRPHY_DX2MDLR0 0x000009A0 +#define DDRSS_DDRPHY_DX2MDLR1 0x000009A4 +#define DDRSS_DDRPHY_DX2GTR0 0x000009C0 +#define DDRSS_DDRPHY_DX2RSR0 0x000009D0 +#define DDRSS_DDRPHY_DX2RSR1 0x000009D4 +#define DDRSS_DDRPHY_DX2RSR2 0x000009D8 +#define DDRSS_DDRPHY_DX2RSR3 0x000009DC +#define DDRSS_DDRPHY_DX2GSR0 0x000009E0 +#define DDRSS_DDRPHY_DX2GSR1 0x000009E4 +#define DDRSS_DDRPHY_DX2GSR2 0x000009E8 +#define DDRSS_DDRPHY_DX2GSR3 0x000009EC +#define DDRSS_DDRPHY_DX2GSR4 0x000009F0 +#define DDRSS_DDRPHY_DX2GSR5 0x000009F4 +#define DDRSS_DDRPHY_DX2GSR6 0x000009F8 +#define DDRSS_DDRPHY_DX3GCR0 0x00000A00 +#define DDRSS_DDRPHY_DX3GCR1 0x00000A04 +#define DDRSS_DDRPHY_DX3GCR2 0x00000A08 +#define DDRSS_DDRPHY_DX3GCR3 0x00000A0C +#define DDRSS_DDRPHY_DX3GCR4 0x00000A10 +#define DDRSS_DDRPHY_DX3GCR5 0x00000A14 +#define DDRSS_DDRPHY_DX3GCR6 0x00000A18 +#define DDRSS_DDRPHY_DX3GCR7 0x00000A1C +#define DDRSS_DDRPHY_DX3GCR8 0x00000A20 +#define DDRSS_DDRPHY_DX3GCR9 0x00000A24 +#define DDRSS_DDRPHY_DX3DQMAP0 0x00000A28 +#define DDRSS_DDRPHY_DX3DQMAP1 0x00000A2C +#define DDRSS_DDRPHY_DX3BDLR0 0x00000A40 +#define DDRSS_DDRPHY_DX3BDLR1 0x00000A44 +#define DDRSS_DDRPHY_DX3BDLR2 0x00000A48 +#define DDRSS_DDRPHY_DX3BDLR3 0x00000A50 +#define DDRSS_DDRPHY_DX3BDLR4 0x00000A54 +#define DDRSS_DDRPHY_DX3BDLR5 0x00000A58 +#define DDRSS_DDRPHY_DX3BDLR6 0x00000A60 +#define DDRSS_DDRPHY_DX3BDLR7 0x00000A64 +#define DDRSS_DDRPHY_DX3BDLR8 0x00000A68 +#define DDRSS_DDRPHY_DX3BDLR9 0x00000A6C +#define DDRSS_DDRPHY_DX3LCDLR0 0x00000A80 +#define DDRSS_DDRPHY_DX3LCDLR1 0x00000A84 +#define DDRSS_DDRPHY_DX3LCDLR2 0x00000A88 +#define DDRSS_DDRPHY_DX3LCDLR3 0x00000A8C +#define DDRSS_DDRPHY_DX3LCDLR4 0x00000A90 +#define DDRSS_DDRPHY_DX3LCDLR5 0x00000A94 +#define DDRSS_DDRPHY_DX3MDLR0 0x00000AA0 +#define DDRSS_DDRPHY_DX3MDLR1 0x00000AA4 +#define DDRSS_DDRPHY_DX3GTR0 0x00000AC0 +#define DDRSS_DDRPHY_DX3RSR0 0x00000AD0 +#define DDRSS_DDRPHY_DX3RSR1 0x00000AD4 +#define DDRSS_DDRPHY_DX3RSR2 0x00000AD8 +#define DDRSS_DDRPHY_DX3RSR3 0x00000ADC +#define DDRSS_DDRPHY_DX3GSR0 0x00000AE0 +#define DDRSS_DDRPHY_DX3GSR1 0x00000AE4 +#define DDRSS_DDRPHY_DX3GSR2 0x00000AE8 +#define DDRSS_DDRPHY_DX3GSR3 0x00000AEC +#define DDRSS_DDRPHY_DX3GSR4 0x00000AF0 +#define DDRSS_DDRPHY_DX3GSR5 0x00000AF4 +#define DDRSS_DDRPHY_DX3GSR6 0x00000AF8 +#define DDRSS_DDRPHY_DX4GCR0 0x00000B00 +#define DDRSS_DDRPHY_DX4GCR1 0x00000B04 +#define DDRSS_DDRPHY_DX4GCR2 0x00000B08 +#define DDRSS_DDRPHY_DX4GCR3 0x00000B0C +#define DDRSS_DDRPHY_DX4GCR4 0x00000B10 +#define DDRSS_DDRPHY_DX4GCR5 0x00000B14 +#define DDRSS_DDRPHY_DX4GCR6 0x00000B18 +#define DDRSS_DDRPHY_DX4GCR7 0x00000B1C +#define DDRSS_DDRPHY_DX4GCR8 0x00000B20 +#define DDRSS_DDRPHY_DX4GCR9 0x00000B24 +#define DDRSS_DDRPHY_DX4DQMAP0 0x00000B28 +#define DDRSS_DDRPHY_DX4DQMAP1 0x00000B2C +#define DDRSS_DDRPHY_DX4BDLR0 0x00000B40 +#define DDRSS_DDRPHY_DX4BDLR1 0x00000B44 +#define DDRSS_DDRPHY_DX4BDLR2 0x00000B48 +#define DDRSS_DDRPHY_DX4BDLR3 0x00000B50 +#define DDRSS_DDRPHY_DX4BDLR4 0x00000B54 +#define DDRSS_DDRPHY_DX4BDLR5 0x00000B58 +#define DDRSS_DDRPHY_DX4BDLR6 0x00000B60 +#define DDRSS_DDRPHY_DX4BDLR7 0x00000B64 +#define DDRSS_DDRPHY_DX4BDLR8 0x00000B68 +#define DDRSS_DDRPHY_DX4BDLR9 0x00000B6C +#define DDRSS_DDRPHY_DX4LCDLR0 0x00000B80 +#define DDRSS_DDRPHY_DX4LCDLR1 0x00000B84 +#define DDRSS_DDRPHY_DX4LCDLR2 0x00000B88 +#define DDRSS_DDRPHY_DX4LCDLR3 0x00000B8C +#define DDRSS_DDRPHY_DX4LCDLR4 0x00000B90 +#define DDRSS_DDRPHY_DX4LCDLR5 0x00000B94 +#define DDRSS_DDRPHY_DX4MDLR0 0x00000BA0 +#define DDRSS_DDRPHY_DX4MDLR1 0x00000BA4 +#define DDRSS_DDRPHY_DX4GTR0 0x00000BC0 +#define DDRSS_DDRPHY_DX4RSR0 0x00000BD0 +#define DDRSS_DDRPHY_DX4RSR1 0x00000BD4 +#define DDRSS_DDRPHY_DX4RSR2 0x00000BD8 +#define DDRSS_DDRPHY_DX4RSR3 0x00000BDC +#define DDRSS_DDRPHY_DX4GSR0 0x00000BE0 +#define DDRSS_DDRPHY_DX4GSR1 0x00000BE4 +#define DDRSS_DDRPHY_DX4GSR2 0x00000BE8 +#define DDRSS_DDRPHY_DX4GSR3 0x00000BEC +#define DDRSS_DDRPHY_DX4GSR4 0x00000BF0 +#define DDRSS_DDRPHY_DX4GSR5 0x00000BF4 +#define DDRSS_DDRPHY_DX4GSR6 0x00000BF8 +#define DDRSS_DDRPHY_DX5GCR0 0x00000C00 +#define DDRSS_DDRPHY_DX5GCR1 0x00000C04 +#define DDRSS_DDRPHY_DX5GCR2 0x00000C08 +#define DDRSS_DDRPHY_DX5GCR3 0x00000C0C +#define DDRSS_DDRPHY_DX5GCR4 0x00000C10 +#define DDRSS_DDRPHY_DX5GCR5 0x00000C14 +#define DDRSS_DDRPHY_DX5GCR6 0x00000C18 +#define DDRSS_DDRPHY_DX5GCR7 0x00000C1C +#define DDRSS_DDRPHY_DX5GCR8 0x00000C20 +#define DDRSS_DDRPHY_DX5GCR9 0x00000C24 +#define DDRSS_DDRPHY_DX5DQMAP0 0x00000C28 +#define DDRSS_DDRPHY_DX5DQMAP1 0x00000C2C +#define DDRSS_DDRPHY_DX5BDLR0 0x00000C40 +#define DDRSS_DDRPHY_DX5BDLR1 0x00000C44 +#define DDRSS_DDRPHY_DX5BDLR2 0x00000C48 +#define DDRSS_DDRPHY_DX5BDLR3 0x00000C50 +#define DDRSS_DDRPHY_DX5BDLR4 0x00000C54 +#define DDRSS_DDRPHY_DX5BDLR5 0x00000C58 +#define DDRSS_DDRPHY_DX5BDLR6 0x00000C60 +#define DDRSS_DDRPHY_DX5BDLR7 0x00000C64 +#define DDRSS_DDRPHY_DX5BDLR8 0x00000C68 +#define DDRSS_DDRPHY_DX5BDLR9 0x00000C6C +#define DDRSS_DDRPHY_DX5LCDLR0 0x00000C80 +#define DDRSS_DDRPHY_DX5LCDLR1 0x00000C84 +#define DDRSS_DDRPHY_DX5LCDLR2 0x00000C88 +#define DDRSS_DDRPHY_DX5LCDLR3 0x00000C8C +#define DDRSS_DDRPHY_DX5LCDLR4 0x00000C90 +#define DDRSS_DDRPHY_DX5LCDLR5 0x00000C94 +#define DDRSS_DDRPHY_DX5MDLR0 0x00000CA0 +#define DDRSS_DDRPHY_DX5MDLR1 0x00000CA4 +#define DDRSS_DDRPHY_DX5GTR0 0x00000CC0 +#define DDRSS_DDRPHY_DX5RSR0 0x00000CD0 +#define DDRSS_DDRPHY_DX5RSR1 0x00000CD4 +#define DDRSS_DDRPHY_DX5RSR2 0x00000CD8 +#define DDRSS_DDRPHY_DX5RSR3 0x00000CDC +#define DDRSS_DDRPHY_DX5GSR0 0x00000CE0 +#define DDRSS_DDRPHY_DX5GSR1 0x00000CE4 +#define DDRSS_DDRPHY_DX5GSR2 0x00000CE8 +#define DDRSS_DDRPHY_DX5GSR3 0x00000CEC +#define DDRSS_DDRPHY_DX5GSR4 0x00000CF0 +#define DDRSS_DDRPHY_DX5GSR5 0x00000CF4 +#define DDRSS_DDRPHY_DX5GSR6 0x00000CF8 +#define DDRSS_DDRPHY_DX6GCR0 0x00000D00 +#define DDRSS_DDRPHY_DX6GCR1 0x00000D04 +#define DDRSS_DDRPHY_DX6GCR2 0x00000D08 +#define DDRSS_DDRPHY_DX6GCR3 0x00000D0C +#define DDRSS_DDRPHY_DX6GCR4 0x00000D10 +#define DDRSS_DDRPHY_DX6GCR5 0x00000D14 +#define DDRSS_DDRPHY_DX6GCR6 0x00000D18 +#define DDRSS_DDRPHY_DX6GCR7 0x00000D1C +#define DDRSS_DDRPHY_DX6GCR8 0x00000D20 +#define DDRSS_DDRPHY_DX6GCR9 0x00000D24 +#define DDRSS_DDRPHY_DX6DQMAP0 0x00000D28 +#define DDRSS_DDRPHY_DX6DQMAP1 0x00000D2C +#define DDRSS_DDRPHY_DX6BDLR0 0x00000D40 +#define DDRSS_DDRPHY_DX6BDLR1 0x00000D44 +#define DDRSS_DDRPHY_DX6BDLR2 0x00000D48 +#define DDRSS_DDRPHY_DX6BDLR3 0x00000D50 +#define DDRSS_DDRPHY_DX6BDLR4 0x00000D54 +#define DDRSS_DDRPHY_DX6BDLR5 0x00000D58 +#define DDRSS_DDRPHY_DX6BDLR6 0x00000D60 +#define DDRSS_DDRPHY_DX6BDLR7 0x00000D64 +#define DDRSS_DDRPHY_DX6BDLR8 0x00000D68 +#define DDRSS_DDRPHY_DX6BDLR9 0x00000D6C +#define DDRSS_DDRPHY_DX6LCDLR0 0x00000D80 +#define DDRSS_DDRPHY_DX6LCDLR1 0x00000D84 +#define DDRSS_DDRPHY_DX6LCDLR2 0x00000D88 +#define DDRSS_DDRPHY_DX6LCDLR3 0x00000D8C +#define DDRSS_DDRPHY_DX6LCDLR4 0x00000D90 +#define DDRSS_DDRPHY_DX6LCDLR5 0x00000D94 +#define DDRSS_DDRPHY_DX6MDLR0 0x00000DA0 +#define DDRSS_DDRPHY_DX6MDLR1 0x00000DA4 +#define DDRSS_DDRPHY_DX6GTR0 0x00000DC0 +#define DDRSS_DDRPHY_DX6RSR0 0x00000DD0 +#define DDRSS_DDRPHY_DX6RSR1 0x00000DD4 +#define DDRSS_DDRPHY_DX6RSR2 0x00000DD8 +#define DDRSS_DDRPHY_DX6RSR3 0x00000DDC +#define DDRSS_DDRPHY_DX6GSR0 0x00000DE0 +#define DDRSS_DDRPHY_DX6GSR1 0x00000DE4 +#define DDRSS_DDRPHY_DX6GSR2 0x00000DE8 +#define DDRSS_DDRPHY_DX6GSR3 0x00000DEC +#define DDRSS_DDRPHY_DX6GSR4 0x00000DF0 +#define DDRSS_DDRPHY_DX6GSR5 0x00000DF4 +#define DDRSS_DDRPHY_DX6GSR6 0x00000DF8 +#define DDRSS_DDRPHY_DX7GCR0 0x00000E00 +#define DDRSS_DDRPHY_DX7GCR1 0x00000E04 +#define DDRSS_DDRPHY_DX7GCR2 0x00000E08 +#define DDRSS_DDRPHY_DX7GCR3 0x00000E0C +#define DDRSS_DDRPHY_DX7GCR4 0x00000E10 +#define DDRSS_DDRPHY_DX7GCR5 0x00000E14 +#define DDRSS_DDRPHY_DX7GCR6 0x00000E18 +#define DDRSS_DDRPHY_DX7GCR7 0x00000E1C +#define DDRSS_DDRPHY_DX7GCR8 0x00000E20 +#define DDRSS_DDRPHY_DX7GCR9 0x00000E24 +#define DDRSS_DDRPHY_DX7DQMAP0 0x00000E28 +#define DDRSS_DDRPHY_DX7DQMAP1 0x00000E2C +#define DDRSS_DDRPHY_DX7BDLR0 0x00000E40 +#define DDRSS_DDRPHY_DX7BDLR1 0x00000E44 +#define DDRSS_DDRPHY_DX7BDLR2 0x00000E48 +#define DDRSS_DDRPHY_DX7BDLR3 0x00000E50 +#define DDRSS_DDRPHY_DX7BDLR4 0x00000E54 +#define DDRSS_DDRPHY_DX7BDLR5 0x00000E58 +#define DDRSS_DDRPHY_DX7BDLR6 0x00000E60 +#define DDRSS_DDRPHY_DX7BDLR7 0x00000E64 +#define DDRSS_DDRPHY_DX7BDLR8 0x00000E68 +#define DDRSS_DDRPHY_DX7BDLR9 0x00000E6C +#define DDRSS_DDRPHY_DX7LCDLR0 0x00000E80 +#define DDRSS_DDRPHY_DX7LCDLR1 0x00000E84 +#define DDRSS_DDRPHY_DX7LCDLR2 0x00000E88 +#define DDRSS_DDRPHY_DX7LCDLR3 0x00000E8C +#define DDRSS_DDRPHY_DX7LCDLR4 0x00000E90 +#define DDRSS_DDRPHY_DX7LCDLR5 0x00000E94 +#define DDRSS_DDRPHY_DX7MDLR0 0x00000EA0 +#define DDRSS_DDRPHY_DX7MDLR1 0x00000EA4 +#define DDRSS_DDRPHY_DX7GTR0 0x00000EC0 +#define DDRSS_DDRPHY_DX7RSR0 0x00000ED0 +#define DDRSS_DDRPHY_DX7RSR1 0x00000ED4 +#define DDRSS_DDRPHY_DX7RSR2 0x00000ED8 +#define DDRSS_DDRPHY_DX7RSR3 0x00000EDC +#define DDRSS_DDRPHY_DX7GSR0 0x00000EE0 +#define DDRSS_DDRPHY_DX7GSR1 0x00000EE4 +#define DDRSS_DDRPHY_DX7GSR2 0x00000EE8 +#define DDRSS_DDRPHY_DX7GSR3 0x00000EEC +#define DDRSS_DDRPHY_DX7GSR4 0x00000EF0 +#define DDRSS_DDRPHY_DX7GSR5 0x00000EF4 +#define DDRSS_DDRPHY_DX7GSR6 0x00000EF8 +#define DDRSS_DDRPHY_DX8GCR0 0x00000F00 +#define DDRSS_DDRPHY_DX8GCR1 0x00000F04 +#define DDRSS_DDRPHY_DX8GCR2 0x00000F08 +#define DDRSS_DDRPHY_DX8GCR3 0x00000F0C +#define DDRSS_DDRPHY_DX8GCR4 0x00000F10 +#define DDRSS_DDRPHY_DX8GCR5 0x00000F14 +#define DDRSS_DDRPHY_DX8GCR6 0x00000F18 +#define DDRSS_DDRPHY_DX8GCR7 0x00000F1C +#define DDRSS_DDRPHY_DX8GCR8 0x00000F20 +#define DDRSS_DDRPHY_DX8GCR9 0x00000F24 +#define DDRSS_DDRPHY_DX8DQMAP0 0x00000F28 +#define DDRSS_DDRPHY_DX8DQMAP1 0x00000F2C +#define DDRSS_DDRPHY_DX8BDLR0 0x00000F40 +#define DDRSS_DDRPHY_DX8BDLR1 0x00000F44 +#define DDRSS_DDRPHY_DX8BDLR2 0x00000F48 +#define DDRSS_DDRPHY_DX8BDLR3 0x00000F50 +#define DDRSS_DDRPHY_DX8BDLR4 0x00000F54 +#define DDRSS_DDRPHY_DX8BDLR5 0x00000F58 +#define DDRSS_DDRPHY_DX8BDLR6 0x00000F60 +#define DDRSS_DDRPHY_DX8BDLR7 0x00000F64 +#define DDRSS_DDRPHY_DX8BDLR8 0x00000F68 +#define DDRSS_DDRPHY_DX8BDLR9 0x00000F6C +#define DDRSS_DDRPHY_DX8LCDLR0 0x00000F80 +#define DDRSS_DDRPHY_DX8LCDLR1 0x00000F84 +#define DDRSS_DDRPHY_DX8LCDLR2 0x00000F88 +#define DDRSS_DDRPHY_DX8LCDLR3 0x00000F8C +#define DDRSS_DDRPHY_DX8LCDLR4 0x00000F90 +#define DDRSS_DDRPHY_DX8LCDLR5 0x00000F94 +#define DDRSS_DDRPHY_DX8MDLR0 0x00000FA0 +#define DDRSS_DDRPHY_DX8MDLR1 0x00000FA4 +#define DDRSS_DDRPHY_DX8GTR0 0x00000FC0 +#define DDRSS_DDRPHY_DX8RSR0 0x00000FD0 +#define DDRSS_DDRPHY_DX8RSR1 0x00000FD4 +#define DDRSS_DDRPHY_DX8RSR2 0x00000FD8 +#define DDRSS_DDRPHY_DX8RSR3 0x00000FDC +#define DDRSS_DDRPHY_DX8GSR0 0x00000FE0 +#define DDRSS_DDRPHY_DX8GSR1 0x00000FE4 +#define DDRSS_DDRPHY_DX8GSR2 0x00000FE8 +#define DDRSS_DDRPHY_DX8GSR3 0x00000FEC +#define DDRSS_DDRPHY_DX8GSR4 0x00000FF0 +#define DDRSS_DDRPHY_DX8GSR5 0x00000FF4 +#define DDRSS_DDRPHY_DX8GSR6 0x00000FF8 +#define DDRSS_DDRPHY_DX8SL0OSC 0x00001400 +#define DDRSS_DDRPHY_DX8SL0PLLCR0 0x00001404 +#define DDRSS_DDRPHY_DX8SL0PLLCR1 0x00001408 +#define DDRSS_DDRPHY_DX8SL0PLLCR2 0x0000140C +#define DDRSS_DDRPHY_DX8SL0PLLCR3 0x00001410 +#define DDRSS_DDRPHY_DX8SL0PLLCR4 0x00001414 +#define DDRSS_DDRPHY_DX8SL0PLLCR5 0x00001418 +#define DDRSS_DDRPHY_DX8SL0DQSCTL 0x0000141C +#define DDRSS_DDRPHY_DX8SL0TRNCTL 0x00001420 +#define DDRSS_DDRPHY_DX8SL0DDLCTL 0x00001424 +#define DDRSS_DDRPHY_DX8SL0DXCTL1 0x00001428 +#define DDRSS_DDRPHY_DX8SL0DXCTL2 0x0000142C +#define DDRSS_DDRPHY_DX8SL0IOCR 0x00001430 +#define DDRSS_DDRPHY_DX4SL0IOCR 0x00001434 +#define DDRSS_DDRPHY_DX8SL1OSC 0x00001440 +#define DDRSS_DDRPHY_DX8SL1PLLCR0 0x00001444 +#define DDRSS_DDRPHY_DX8SL1PLLCR1 0x00001448 +#define DDRSS_DDRPHY_DX8SL1PLLCR2 0x0000144C +#define DDRSS_DDRPHY_DX8SL1PLLCR3 0x00001450 +#define DDRSS_DDRPHY_DX8SL1PLLCR4 0x00001454 +#define DDRSS_DDRPHY_DX8SL1PLLCR5 0x00001458 +#define DDRSS_DDRPHY_DX8SL1DQSCTL 0x0000145C +#define DDRSS_DDRPHY_DX8SL1TRNCTL 0x00001460 +#define DDRSS_DDRPHY_DX8SL1DDLCTL 0x00001464 +#define DDRSS_DDRPHY_DX8SL1DXCTL1 0x00001468 +#define DDRSS_DDRPHY_DX8SL1DXCTL2 0x0000146C +#define DDRSS_DDRPHY_DX8SL1IOCR 0x00001470 +#define DDRSS_DDRPHY_DX4SL1IOCR 0x00001474 +#define DDRSS_DDRPHY_DX8SL2OSC 0x00001480 +#define DDRSS_DDRPHY_DX8SL2PLLCR0 0x00001484 +#define DDRSS_DDRPHY_DX8SL2PLLCR1 0x00001488 +#define DDRSS_DDRPHY_DX8SL2PLLCR2 0x0000148C +#define DDRSS_DDRPHY_DX8SL2PLLCR3 0x00001490 +#define DDRSS_DDRPHY_DX8SL2PLLCR4 0x00001494 +#define DDRSS_DDRPHY_DX8SL2PLLCR5 0x00001498 +#define DDRSS_DDRPHY_DX8SL2DQSCTL 0x0000149C +#define DDRSS_DDRPHY_DX8SL2TRNCTL 0x000014A0 +#define DDRSS_DDRPHY_DX8SL2DDLCTL 0x000014A4 +#define DDRSS_DDRPHY_DX8SL2DXCTL1 0x000014A8 +#define DDRSS_DDRPHY_DX8SL2DXCTL2 0x000014AC +#define DDRSS_DDRPHY_DX8SL2IOCR 0x000014B0 +#define DDRSS_DDRPHY_DX4SL2IOCR 0x000014B4 +#define DDRSS_DDRPHY_DX8SL3OSC 0x000014C0 +#define DDRSS_DDRPHY_DX8SL3PLLCR0 0x000014C4 +#define DDRSS_DDRPHY_DX8SL3PLLCR1 0x000014C8 +#define DDRSS_DDRPHY_DX8SL3PLLCR2 0x000014CC +#define DDRSS_DDRPHY_DX8SL3PLLCR3 0x000014D0 +#define DDRSS_DDRPHY_DX8SL3PLLCR4 0x000014D4 +#define DDRSS_DDRPHY_DX8SL3PLLCR5 0x000014D8 +#define DDRSS_DDRPHY_DX8SL3DQSCTL 0x000014DC +#define DDRSS_DDRPHY_DX8SL3TRNCTL 0x000014E0 +#define DDRSS_DDRPHY_DX8SL3DDLCTL 0x000014E4 +#define DDRSS_DDRPHY_DX8SL3DXCTL1 0x000014E8 +#define DDRSS_DDRPHY_DX8SL3DXCTL2 0x000014EC +#define DDRSS_DDRPHY_DX8SL3IOCR 0x000014F0 +#define DDRSS_DDRPHY_DX4SL3IOCR 0x000014F4 +#define DDRSS_DDRPHY_DX8SL4OSC 0x00001500 +#define DDRSS_DDRPHY_DX8SL4PLLCR0 0x00001504 +#define DDRSS_DDRPHY_DX8SL4PLLCR1 0x00001508 +#define DDRSS_DDRPHY_DX8SL4PLLCR2 0x0000150C +#define DDRSS_DDRPHY_DX8SL4PLLCR3 0x00001510 +#define DDRSS_DDRPHY_DX8SL4PLLCR4 0x00001514 +#define DDRSS_DDRPHY_DX8SL4PLLCR5 0x00001518 +#define DDRSS_DDRPHY_DX8SL4DQSCTL 0x0000151C +#define DDRSS_DDRPHY_DX8SL4TRNCTL 0x00001520 +#define DDRSS_DDRPHY_DX8SL4DDLCTL 0x00001524 +#define DDRSS_DDRPHY_DX8SL4DXCTL1 0x00001528 +#define DDRSS_DDRPHY_DX8SL4DXCTL2 0x0000152C +#define DDRSS_DDRPHY_DX8SL4IOCR 0x00001530 +#define DDRSS_DDRPHY_DX4SL4IOCR 0x00001534 +#define DDRSS_DDRPHY_DX8SL5OSC 0x00001540 +#define DDRSS_DDRPHY_DX8SL5PLLCR0 0x00001544 +#define DDRSS_DDRPHY_DX8SL5PLLCR1 0x00001548 +#define DDRSS_DDRPHY_DX8SL5PLLCR2 0x0000154C +#define DDRSS_DDRPHY_DX8SL5PLLCR3 0x00001550 +#define DDRSS_DDRPHY_DX8SL5PLLCR4 0x00001554 +#define DDRSS_DDRPHY_DX8SL5PLLCR5 0x00001558 +#define DDRSS_DDRPHY_DX8SL5DQSCTL 0x0000155C +#define DDRSS_DDRPHY_DX8SL5TRNCTL 0x00001560 +#define DDRSS_DDRPHY_DX8SL5DDLCTL 0x00001564 +#define DDRSS_DDRPHY_DX8SL5DXCTL1 0x00001568 +#define DDRSS_DDRPHY_DX8SL5DXCTL2 0x0000156C +#define DDRSS_DDRPHY_DX8SL5IOCR 0x00001570 +#define DDRSS_DDRPHY_DX4SL5IOCR 0x00001574 +#define DDRSS_DDRPHY_DX8SL6OSC 0x00001580 +#define DDRSS_DDRPHY_DX8SL6PLLCR0 0x00001584 +#define DDRSS_DDRPHY_DX8SL6PLLCR1 0x00001588 +#define DDRSS_DDRPHY_DX8SL6PLLCR2 0x0000158C +#define DDRSS_DDRPHY_DX8SL6PLLCR3 0x00001590 +#define DDRSS_DDRPHY_DX8SL6PLLCR4 0x00001594 +#define DDRSS_DDRPHY_DX8SL6PLLCR5 0x00001598 +#define DDRSS_DDRPHY_DX8SL6DQSCTL 0x0000159C +#define DDRSS_DDRPHY_DX8SL6TRNCTL 0x000015A0 +#define DDRSS_DDRPHY_DX8SL6DDLCTL 0x000015A4 +#define DDRSS_DDRPHY_DX8SL6DXCTL1 0x000015A8 +#define DDRSS_DDRPHY_DX8SL6DXCTL2 0x000015AC +#define DDRSS_DDRPHY_DX8SL6IOCR 0x000015B0 +#define DDRSS_DDRPHY_DX4SL6IOCR 0x000015B4 +#define DDRSS_DDRPHY_DX8SL7OSC 0x000015C0 +#define DDRSS_DDRPHY_DX8SL7PLLCR0 0x000015C4 +#define DDRSS_DDRPHY_DX8SL7PLLCR1 0x000015C8 +#define DDRSS_DDRPHY_DX8SL7PLLCR2 0x000015CC +#define DDRSS_DDRPHY_DX8SL7PLLCR3 0x000015D0 +#define DDRSS_DDRPHY_DX8SL7PLLCR4 0x000015D4 +#define DDRSS_DDRPHY_DX8SL7PLLCR5 0x000015D8 +#define DDRSS_DDRPHY_DX8SL7DQSCTL 0x000015DC +#define DDRSS_DDRPHY_DX8SL7TRNCTL 0x000015E0 +#define DDRSS_DDRPHY_DX8SL7DDLCTL 0x000015E4 +#define DDRSS_DDRPHY_DX8SL7DXCTL1 0x000015E8 +#define DDRSS_DDRPHY_DX8SL7DXCTL2 0x000015EC +#define DDRSS_DDRPHY_DX8SL7IOCR 0x000015F0 +#define DDRSS_DDRPHY_DX4SL7IOCR 0x000015F4 +#define DDRSS_DDRPHY_DX8SL8OSC 0x00001600 +#define DDRSS_DDRPHY_DX8SL8PLLCR0 0x00001604 +#define DDRSS_DDRPHY_DX8SL8PLLCR1 0x00001608 +#define DDRSS_DDRPHY_DX8SL8PLLCR2 0x0000160C +#define DDRSS_DDRPHY_DX8SL8PLLCR3 0x00001610 +#define DDRSS_DDRPHY_DX8SL8PLLCR4 0x00001614 +#define DDRSS_DDRPHY_DX8SL8PLLCR5 0x00001618 +#define DDRSS_DDRPHY_DX8SL8DQSCTL 0x0000161C +#define DDRSS_DDRPHY_DX8SL8TRNCTL 0x00001620 +#define DDRSS_DDRPHY_DX8SL8DDLCTL 0x00001624 +#define DDRSS_DDRPHY_DX8SL8DXCTL1 0x00001628 +#define DDRSS_DDRPHY_DX8SL8DXCTL2 0x0000162C +#define DDRSS_DDRPHY_DX8SL8IOCR 0x00001630 +#define DDRSS_DDRPHY_DX4SL8IOCR 0x00001634 +#define DDRSS_DDRPHY_DX8SLBOSC 0x000017C0 +#define DDRSS_DDRPHY_DX8SLBPLLCR0 0x000017C4 +#define DDRSS_DDRPHY_DX8SLBPLLCR1 0x000017C8 +#define DDRSS_DDRPHY_DX8SLBPLLCR2 0x000017CC +#define DDRSS_DDRPHY_DX8SLBPLLCR3 0x000017D0 +#define DDRSS_DDRPHY_DX8SLBPLLCR4 0x000017D4 +#define DDRSS_DDRPHY_DX8SLBPLLCR5 0x000017D8 +#define DDRSS_DDRPHY_DX8SLBDQSCTL 0x000017DC +#define DDRSS_DDRPHY_DX8SLBTRNCTL 0x000017E0 +#define DDRSS_DDRPHY_DX8SLBDDLCTL 0x000017E4 +#define DDRSS_DDRPHY_DX8SLBDXCTL1 0x000017E8 +#define DDRSS_DDRPHY_DX8SLBDXCTL2 0x000017EC +#define DDRSS_DDRPHY_DX8SLBIOCR 0x000017F0 +#define DDRSS_DDRPHY_DX4SLBIOCR 0x000017F4 + +#define PIR_INIT_SHIFT 0 +#define PIR_INIT_MASK BIT(PIR_INIT_SHIFT) +#define PIR_ZCAL_SHIFT 1 +#define PIR_ZCAL_MASK BIT(PIR_ZCAL_SHIFT) +#define PIR_CA_SHIFT 2 +#define PIR_CA_MASK BIT(PIR_CA_SHIFT) +#define PIR_PLLINIT_SHIFT 4 +#define PIR_PLLINIT_MASK BIT(PIR_PLLINIT_SHIFT) +#define PIR_DCAL_SHIFT 5 +#define PIR_DCAL_MASK BIT(PIR_DCAL_SHIFT) +#define PIR_PHYRST_SHIFT 6 +#define PIR_PHYRST_MASK BIT(PIR_PHYRST_SHIFT) +#define PIR_DRAMRST_SHIFT 7 +#define PIR_DRAMRST_MASK BIT(PIR_DRAMRST_SHIFT) +#define PIR_DRAMINIT_SHIFT 8 +#define PIR_DRAMINIT_MASK BIT(PIR_DRAMINIT_SHIFT) +#define PIR_WL_SHIFT 9 +#define PIR_WL_MASK BIT(PIR_WL_SHIFT) +#define PIR_QSGATE_SHIFT 10 +#define PIR_QSGATE_MASK BIT(PIR_QSGATE_SHIFT) +#define PIR_WLADJ_SHIFT 11 +#define PIR_WLADJ_MASK BIT(PIR_WLADJ_SHIFT) +#define PIR_RDDSKW_SHIFT 12 +#define PIR_RDDSKW_MASK BIT(PIR_RDDSKW_SHIFT) +#define PIR_WRDSKW_SHIFT 13 +#define PIR_WRDSKW_MASK BIT(PIR_WRDSKW_SHIFT) +#define PIR_RDEYE_SHIFT 14 +#define PIR_RDEYE_MASK BIT(PIR_RDEYE_SHIFT) +#define PIR_WREYE_SHIFT 15 +#define PIR_WREYE_MASK BIT(PIR_WREYE_SHIFT) +#define PIR_SRD_SHIFT 16 +#define PIR_SRD_MASK BIT(PIR_SRD_SHIFT) +#define PIR_VREF_SHIFT 17 +#define PIR_VREF_MASK BIT(PIR_VREF_SHIFT) +#define PIR_CTLDINIT_SHIFT 18 +#define PIR_CTLDINIT_MASK BIT(PIR_CTLDINIT_SHIFT) +#define PIR_RDIMMINIT_SHIFT 19 +#define PIR_RDIMMINIT_MASK BIT(PIR_RDIMMINIT_SHIFT) +#define PIR_DQS2DQ_SHIFT 20 +#define PIR_DQS2DQ_MASK BIT(PIR_DQS2DQ_SHIFT) +#define PIR_DCALPSE_SHIFT 29 +#define PIR_DCALPSE_MASK BIT(PIR_DCALPSE_SHIFT) +#define PIR_ZCALBYP_SHIFT 30 +#define PIR_ZCALBYP_MASK BIT(PIR_ZCALBYP_SHIFT) + +#define PIR_PHY_INIT (PIR_ZCAL_MASK | PIR_PLLINIT_MASK | \ + PIR_DCAL_MASK | PIR_PHYRST_MASK) +#define PIR_DRAM_INIT (PIR_DRAMRST_MASK | PIR_DRAMINIT_MASK) +#define PIR_DATA_TR_INIT (PIR_WL_MASK | PIR_QSGATE_MASK | \ + PIR_WLADJ_MASK | PIR_RDDSKW_MASK | \ + PIR_WRDSKW_MASK | PIR_RDEYE_MASK \ + PIR_WREYE_MASK) + +#define PGSR0_IDONE_SHIFT 0 +#define PGSR0_IDONE_MASK BIT(PGSR0_IDONE_SHIFT) +#define PGSR0_PLDONE_SHIFT 1 +#define PGSR0_PLDONE_MASK BIT(PGSR0_PLDONE_SHIFT) +#define PGSR0_DCDONE_SHIFT 2 +#define PGSR0_DCDONE_MASK BIT(PGSR0_DCDONE_SHIFT) +#define PGSR0_ZCDONE_SHIFT 3 +#define PGSR0_ZCDONE_MASK BIT(PGSR0_ZCDONE_SHIFT) +#define PGSR0_DIDONE_SHIFT 4 +#define PGSR0_DIDONE_MASK BIT(PGSR0_DIDONE_SHIFT) +#define PGSR0_WLDONE_SHIFT 5 +#define PGSR0_WLDONE_MASK BIT(PGSR0_WLDONE_SHIFT) +#define PGSR0_QSGDONE_SHIFT 6 +#define PGSR0_QSGDONE_MASK BIT(PGSR0_QSGDONE_SHIFT) +#define PGSR0_WLADONE_SHIFT 7 +#define PGSR0_WLADONE_MASK BIT(PGSR0_WLADONE_SHIFT) +#define PGSR0_RDDONE_SHIFT 8 +#define PGSR0_RDDONE_MASK BIT(PGSR0_RDDONE_SHIFT) +#define PGSR0_WDDONE_SHIFT 9 +#define PGSR0_WDDONE_MASK BIT(PGSR0_WDDONE_SHIFT) +#define PGSR0_REDONE_SHIFT 10 +#define PGSR0_REDONE_MASK BIT(PGSR0_REDONE_SHIFT) +#define PGSR0_WEDONE_SHIFT 11 +#define PGSR0_WEDONE_MASK BIT(PGSR0_WEDONE_SHIFT) +#define PGSR0_CADONE_SHIFT 12 +#define PGSR0_CADONE_MASK BIT(PGSR0_CADONE_SHIFT) +#define PGSR0_SRDDONE_SHIFT 13 +#define PGSR0_SRDDONE_MASK BIT(PGSR0_SRDDONE_SHIFT) +#define PGSR0_VDONE_SHIFT 14 +#define PGSR0_VDONE_MASK BIT(PGSR0_VDONE_SHIFT) +#define PGSR0_DQS2DQDONE_SHIFT 15 +#define PGSR0_DQS2DQDONE_MASK BIT(PGSR0_DQS2DQDONE_SHIFT) +#define PGSR0_DQS2DQERR_SHIFT 18 +#define PGSR0_DQS2DQERR_MASK BIT(PGSR0_DQS2DQERR_SHIFT) +#define PGSR0_VERR_SHIFT 19 +#define PGSR0_VERR_MASK BIT(PGSR0_VERR_SHIFT) +#define PGSR0_ZCERR_SHIFT 20 +#define PGSR0_ZCERR_MASK BIT(PGSR0_ZCERR_SHIFT) +#define PGSR0_WLERR_SHIFT 21 +#define PGSR0_WLERR_MASK BIT(PGSR0_WLERR_SHIFT) +#define PGSR0_QSGERR_SHIFT 22 +#define PGSR0_QSGERR_MASK BIT(PGSR0_QSGERR_SHIFT) +#define PGSR0_WLAERR_SHIFT 23 +#define PGSR0_WLAERR_MASK BIT(PGSR0_WLAERR_SHIFT) +#define PGSR0_RDERR_SHIFT 24 +#define PGSR0_RDERR_MASK BIT(PGSR0_RDERR_SHIFT) +#define PGSR0_WDERR_SHIFT 25 +#define PGSR0_WDERR_MASK BIT(PGSR0_WDERR_SHIFT) +#define PGSR0_REERR_SHIFT 26 +#define PGSR0_REERR_MASK BIT(PGSR0_REERR_SHIFT) +#define PGSR0_WEERR_SHIFT 27 +#define PGSR0_WEERR_MASK BIT(PGSR0_WEERR_SHIFT) +#define PGSR0_CAERR_SHIFT 28 +#define PGSR0_CAERR_MASK BIT(PGSR0_CAERR_SHIFT) +#define PGSR0_CAWRN_SHIFT 29 +#define PGSR0_CAWRN_MASK BIT(PGSR0_CAWRN_SHIFT) +#define PGSR0_SRDERR_SHIFT 30 +#define PGSR0_SRDERR_MASK BIT(PGSR0_SRDERR_SHIFT) +#define PGSR0_APLOCK_SHIFT 31 +#define PGSR0_APLOCK_MASK BIT(PGSR0_APLOCK_SHIFT) + +#define PGSR0_PHY_INIT_MASK (PGSR0_IDONE_MASK | PGSR0_PLDONE_MASK |\ + PGSR0_DCDONE_MASK | PGSR0_ZCDONE_MASK |\ + PGSR0_APLOCK_MASK) +#define PGSR0_DRAM_INIT_MASK (PGSR0_PHY_INIT_MASK | \ + PGSR0_DIDONE_MASK) +#define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK) + +struct ddrss_ss_reg_params { + u32 ddrss_v2h_ctl_reg; +}; + +struct ddrss_ddrctl_reg_params { + u32 ddrctl_dfimisc; + u32 ddrctl_dfitmg0; + u32 ddrctl_dfitmg1; + u32 ddrctl_dfitmg2; + u32 ddrctl_init0; + u32 ddrctl_init1; + u32 ddrctl_init3; + u32 ddrctl_init4; + u32 ddrctl_init5; + u32 ddrctl_init6; + u32 ddrctl_init7; + u32 ddrctl_mstr; + u32 ddrctl_odtcfg; + u32 ddrctl_odtmap; + u32 ddrctl_rankctl; + u32 ddrctl_rfshctl0; + u32 ddrctl_rfshtmg; + u32 ddrctl_zqctl0; + u32 ddrctl_zqctl1; +}; + +struct ddrss_ddrctl_crc_params { + u32 ddrctl_crcparctl0; + u32 ddrctl_crcparctl1; + u32 ddrctl_crcparctl2; +}; + +struct ddrss_ddrctl_ecc_params { + u32 ddrctl_ecccfg0; +}; + +struct ddrss_ddrctl_map_params { + u32 ddrctl_addrmap0; + u32 ddrctl_addrmap1; + u32 ddrctl_addrmap2; + u32 ddrctl_addrmap3; + u32 ddrctl_addrmap4; + u32 ddrctl_addrmap5; + u32 ddrctl_addrmap6; + u32 ddrctl_addrmap7; + u32 ddrctl_addrmap8; + u32 ddrctl_addrmap9; + u32 ddrctl_addrmap10; + u32 ddrctl_addrmap11; + u32 ddrctl_dqmap0; + u32 ddrctl_dqmap1; + u32 ddrctl_dqmap4; + u32 ddrctl_dqmap5; +}; + +struct ddrss_ddrctl_pwr_params { + u32 ddrctl_pwrctl; +}; + +struct ddrss_ddrctl_timing_params { + u32 ddrctl_dramtmg0; + u32 ddrctl_dramtmg1; + u32 ddrctl_dramtmg2; + u32 ddrctl_dramtmg3; + u32 ddrctl_dramtmg4; + u32 ddrctl_dramtmg5; + u32 ddrctl_dramtmg6; + u32 ddrctl_dramtmg7; + u32 ddrctl_dramtmg8; + u32 ddrctl_dramtmg9; + u32 ddrctl_dramtmg11; + u32 ddrctl_dramtmg12; + u32 ddrctl_dramtmg13; + u32 ddrctl_dramtmg14; + u32 ddrctl_dramtmg15; + u32 ddrctl_dramtmg17; +}; + +struct ddrss_ddrphy_cfg_params { + u32 ddrphy_dcr; + u32 ddrphy_dsgcr; + u32 ddrphy_dx0gcr0; + u32 ddrphy_dx0gcr1; + u32 ddrphy_dx0gcr2; + u32 ddrphy_dx0gcr3; + u32 ddrphy_dx0gcr4; + u32 ddrphy_dx0gcr5; + u32 ddrphy_dx0gtr0; + u32 ddrphy_dx1gcr0; + u32 ddrphy_dx1gcr1; + u32 ddrphy_dx1gcr2; + u32 ddrphy_dx1gcr3; + u32 ddrphy_dx1gcr4; + u32 ddrphy_dx1gcr5; + u32 ddrphy_dx1gtr0; + u32 ddrphy_dx2gcr0; + u32 ddrphy_dx2gcr1; + u32 ddrphy_dx2gcr2; + u32 ddrphy_dx2gcr3; + u32 ddrphy_dx2gcr4; + u32 ddrphy_dx2gcr5; + u32 ddrphy_dx2gtr0; + u32 ddrphy_dx3gcr0; + u32 ddrphy_dx3gcr1; + u32 ddrphy_dx3gcr2; + u32 ddrphy_dx3gcr3; + u32 ddrphy_dx3gcr4; + u32 ddrphy_dx3gcr5; + u32 ddrphy_dx3gtr0; + u32 ddrphy_dx4gcr0; + u32 ddrphy_dx4gcr1; + u32 ddrphy_dx4gcr2; + u32 ddrphy_dx4gcr3; + u32 ddrphy_dx4gcr4; + u32 ddrphy_dx4gcr5; + u32 ddrphy_dx4gtr0; + u32 ddrphy_dx8sl0dxctl2; + u32 ddrphy_dx8sl0iocr; + u32 ddrphy_dx8sl0pllcr0; + u32 ddrphy_dx8sl0dqsctl; + u32 ddrphy_dx8sl1dxctl2; + u32 ddrphy_dx8sl1iocr; + u32 ddrphy_dx8sl1pllcr0; + u32 ddrphy_dx8sl1dqsctl; + u32 ddrphy_dx8sl2dxctl2; + u32 ddrphy_dx8sl2iocr; + u32 ddrphy_dx8sl2pllcr0; + u32 ddrphy_dx8sl2dqsctl; + u32 ddrphy_dxccr; + u32 ddrphy_odtcr; + u32 ddrphy_pgcr0; + u32 ddrphy_pgcr1; + u32 ddrphy_pgcr2; + u32 ddrphy_pgcr3; + u32 ddrphy_pgcr5; + u32 ddrphy_pgcr6; +}; + +struct ddrss_ddrphy_ctrl_params { + u32 ddrphy_dtcr0; + u32 ddrphy_dtcr1; + u32 ddrphy_mr0; + u32 ddrphy_mr1; + u32 ddrphy_mr2; + u32 ddrphy_mr3; + u32 ddrphy_mr4; + u32 ddrphy_mr5; + u32 ddrphy_mr6; + u32 ddrphy_mr11; + u32 ddrphy_mr12; + u32 ddrphy_mr13; + u32 ddrphy_mr14; + u32 ddrphy_mr22; + u32 ddrphy_pllcr0; + u32 ddrphy_vtcr0; +}; + +struct ddrss_ddrphy_ioctl_params { + u32 ddrphy_aciocr0; + u32 ddrphy_aciocr3; + u32 ddrphy_aciocr5; + u32 ddrphy_iovcr0; +}; + +struct ddrss_ddrphy_timing_params { + u32 ddrphy_dtpr0; + u32 ddrphy_dtpr1; + u32 ddrphy_dtpr2; + u32 ddrphy_dtpr3; + u32 ddrphy_dtpr4; + u32 ddrphy_dtpr5; + u32 ddrphy_dtpr6; + u32 ddrphy_ptr2; + u32 ddrphy_ptr3; + u32 ddrphy_ptr4; + u32 ddrphy_ptr5; + u32 ddrphy_ptr6; +}; + +struct ddrss_ddrphy_zq_params { + u32 ddrphy_zq0pr0; + u32 ddrphy_zq1pr0; + u32 ddrphy_zqcr; +}; + +struct ddrss_params { + struct ddrss_ss_reg_params ss_reg; + struct ddrss_ddrctl_reg_params ctl_reg; + struct ddrss_ddrctl_crc_params ctl_crc; + struct ddrss_ddrctl_ecc_params ctl_ecc; + struct ddrss_ddrctl_map_params ctl_map; + struct ddrss_ddrctl_pwr_params ctl_pwr; + struct ddrss_ddrctl_timing_params ctl_timing; + struct ddrss_ddrphy_cfg_params phy_cfg; + struct ddrss_ddrphy_ctrl_params phy_ctrl; + struct ddrss_ddrphy_ioctl_params phy_ioctl; + struct ddrss_ddrphy_timing_params phy_timing; + struct ddrss_ddrphy_zq_params phy_zq; +}; + +#endif /* __K3_AM654_DDRSS_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h new file mode 100644 index 000000000..94202c9d9 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_16BIT_IF_H +#define LPDDR4_16BIT_IF_H + +#include + +#define LPDDR4_INTR_MAX_CS (2U) + +#define LPDDR4_INTR_CTL_REG_COUNT (423U) + +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) + +#define LPDDR4_INTR_PHY_REG_COUNT (1406U) + +typedef enum { + LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U, + LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U, + LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U, + LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U, + LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U, + LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U, + LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U, + LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U, + LPDDR4_INTR_ECC_ERROR = 8U, + LPDDR4_INTR_LP_DONE = 9U, + LPDDR4_INTR_LP_TIMEOUT = 10U, + LPDDR4_INTR_PORT_TIMEOUT = 11U, + LPDDR4_INTR_RFIFO_TIMEOUT = 12U, + LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U, + LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U, + LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U, + LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U, + LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U, + LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U, + LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U, + LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U, + LPDDR4_INTR_USERIF_WRAP = 21U, + LPDDR4_INTR_USERIF_INVAL_SETTING = 22U, + LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U, + LPDDR4_INTR_MISC_SW_REQ_MODE = 24U, + LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U, + LPDDR4_INTR_MISC_TEMP_ALERT = 26U, + LPDDR4_INTR_MISC_REFRESH_STATUS = 27U, + LPDDR4_INTR_BIST_DONE = 28U, + LPDDR4_INTR_CRC = 29U, + LPDDR4_INTR_DFI_UPDATE_ERROR = 30U, + LPDDR4_INTR_DFI_PHY_ERROR = 31U, + LPDDR4_INTR_DFI_BUS_ERROR = 32U, + LPDDR4_INTR_DFI_STATE_CHANGE = 33U, + LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U, + LPDDR4_INTR_DFI_TIMEOUT = 35U, + LPDDR4_INTR_DIMM = 36U, + LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U, + LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U, + LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U, + LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U, + LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U, + LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U, + LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U, + LPDDR4_INTR_MC_INIT_DONE = 44U, + LPDDR4_INTR_INIT_POWER_ON_STATE = 45U, + LPDDR4_INTR_MRR_ERROR = 46U, + LPDDR4_INTR_MR_READ_DONE = 47U, + LPDDR4_INTR_MR_WRITE_DONE = 48U, + LPDDR4_INTR_PARITY_ERROR = 49U, + LPDDR4_INTR_LOR_BITS = 50U +} lpddr4_intr_ctlinterrupt; + +typedef enum { + LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U, + LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U, + LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U, + LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U, + LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U, + LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U, + LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U, + LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U, + LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U, + LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U, + LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U, + LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U, + LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U, + LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U, + LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U, + LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U, + LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U, + LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U, + LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U, + LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U, + LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U, + LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U, + LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U, + LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U, + LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U, + LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U +} lpddr4_intr_phyindepinterrupt; + +#endif /* LPDDR4_16BIT_IF_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h new file mode 100644 index 000000000..6c57dd9d0 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_16BIT_OBJ_IF_H +#define LPDDR4_16BIT_OBJ_IF_H + +#include "lpddr4_16bit_if.h" + +#endif /* LPDDR4_16BIT_OBJ_IF_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h new file mode 100644 index 000000000..52973484e --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_16BIT_STRUCTS_IF_H +#define LPDDR4_16BIT_STRUCTS_IF_H + +#include +#include "lpddr4_16bit_if.h" + +#endif /* LPDDR4_16BIT_STRUCTS_IF_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h new file mode 100644 index 000000000..f22a20a07 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h @@ -0,0 +1,624 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_512 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_512 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_512 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_513_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_513 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_514_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_514 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_514 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_514 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_515_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_515 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_516_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_516 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_516 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_516 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_516 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_517_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_517 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_517 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_517 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_517 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_518_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_518 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_518 +#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0 + +#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_518 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_518 +#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_519_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_519 +#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_520 +#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_521 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_522_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_522 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_523_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_523 +#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0 + +#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_523 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0 + +#define LPDDR4__DENALI_PHY_524_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_524 +#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0 + +#define LPDDR4__DENALI_PHY_525_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_525 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_526_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_526 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_526 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0 + +#define LPDDR4__DENALI_PHY_527_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_527 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0 + +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_527 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_527 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_528_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_528 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_528 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_528 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0 + +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_528 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_529_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS0_0__REG DENALI_PHY_529 +#define LPDDR4__PHY_ADR_CALVL_OBS0_0__FLD LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0 + +#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_530 +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0 + +#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_531 +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0 + +#define LPDDR4__DENALI_PHY_532_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_532 +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0 + +#define LPDDR4__DENALI_PHY_533_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_533 +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0 + +#define LPDDR4__DENALI_PHY_534_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_534 +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0 + +#define LPDDR4__DENALI_PHY_535_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_535 +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0 + +#define LPDDR4__DENALI_PHY_536_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_536 +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0 + +#define LPDDR4__DENALI_PHY_537_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_537 +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0 + +#define LPDDR4__DENALI_PHY_538_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_538 +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0 + +#define LPDDR4__DENALI_PHY_539_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_539 +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0 + +#define LPDDR4__DENALI_PHY_540_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_WIDTH 30U +#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_540 +#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0 + +#define LPDDR4__DENALI_PHY_541_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_541 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_541 +#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0 + +#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_541 +#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0 + +#define LPDDR4__DENALI_PHY_542_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_542 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_542 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_542 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_542 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_543_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_543 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_544_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_544 +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_544 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_544 +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_545_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_545 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_546_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_546 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_546 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_547_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_547 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_547 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_548_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_548 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_548 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_549_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_549 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_549 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_550_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_550 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_550 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_551 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_551 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_551 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_552 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_552 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_552 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_553_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_553 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_554_READ_MASK 0x0000010FU +#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x0000010FU +#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_554 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_554 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h new file mode 100644 index 000000000..df5ab9516 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h @@ -0,0 +1,624 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ + +#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_768 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_768 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_768 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1 + +#define LPDDR4__DENALI_PHY_769_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_769 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1 + +#define LPDDR4__DENALI_PHY_770_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_770 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1 + +#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_770 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1 + +#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_770 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_771_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_771 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_772_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_772 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1 + +#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_772 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_772 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1 + +#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_772 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_773_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_773 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1 + +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_773 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1 + +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_773 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1 + +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_773 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1 + +#define LPDDR4__DENALI_PHY_774_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_774 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_774 +#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1 + +#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_774 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1 + +#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_774 +#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1 + +#define LPDDR4__DENALI_PHY_775_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_775 +#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1 + +#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_776 +#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1 + +#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_777 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1 + +#define LPDDR4__DENALI_PHY_778_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_778 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_779_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_779 +#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1 + +#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_779 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1 + +#define LPDDR4__DENALI_PHY_780_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_780 +#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1 + +#define LPDDR4__DENALI_PHY_781_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_781 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1 + +#define LPDDR4__DENALI_PHY_782_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_782 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1 + +#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_782 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1 + +#define LPDDR4__DENALI_PHY_783_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_783 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1 + +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_783 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_783 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_784_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_784 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1 + +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_784 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1 + +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_784 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1 + +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_784 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_785_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS0_1__REG DENALI_PHY_785 +#define LPDDR4__PHY_ADR_CALVL_OBS0_1__FLD LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1 + +#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_786 +#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1 + +#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_787 +#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1 + +#define LPDDR4__DENALI_PHY_788_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_788 +#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1 + +#define LPDDR4__DENALI_PHY_789_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_789 +#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1 + +#define LPDDR4__DENALI_PHY_790_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_790 +#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1 + +#define LPDDR4__DENALI_PHY_791_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_791 +#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1 + +#define LPDDR4__DENALI_PHY_792_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_792 +#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1 + +#define LPDDR4__DENALI_PHY_793_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_793 +#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1 + +#define LPDDR4__DENALI_PHY_794_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_794 +#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1 + +#define LPDDR4__DENALI_PHY_795_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_795 +#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1 + +#define LPDDR4__DENALI_PHY_796_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_WIDTH 30U +#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_796 +#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1 + +#define LPDDR4__DENALI_PHY_797_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_797 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_797 +#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1 + +#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_797 +#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1 + +#define LPDDR4__DENALI_PHY_798_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_798 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1 + +#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_798 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1 + +#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_798 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1 + +#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_798 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1 + +#define LPDDR4__DENALI_PHY_799_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_799 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_800_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_800 +#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_800 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_800 +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_801_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_801 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_802_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_802 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_802 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_803_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_803 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_803 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_804_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_804 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_804 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_805_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_805 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_805 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_806_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_806 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_806 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1 + +#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_807 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1 + +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_807 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1 + +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_807 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1 + +#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_808 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1 + +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_808 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_808 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_809_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_809 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_810_READ_MASK 0x0000010FU +#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x0000010FU +#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_810 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_810 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h new file mode 100644 index 000000000..924013e35 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h @@ -0,0 +1,624 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2 + +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1024 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2 + +#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1025 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2 + +#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1028 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2 + +#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1031 +#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2 + +#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1032 +#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2 + +#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1033 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2 + +#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1034 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2 + +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2 + +#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1036 +#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2 + +#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1037 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2 + +#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2 + +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2 + +#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2 + +#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2 + +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS0_2__REG DENALI_PHY_1041 +#define LPDDR4__PHY_ADR_CALVL_OBS0_2__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2 + +#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1042 +#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2 + +#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1043 +#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2 + +#define LPDDR4__DENALI_PHY_1044_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1044 +#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2 + +#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1045 +#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2 + +#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1046 +#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2 + +#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1047 +#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2 + +#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1048 +#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2 + +#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1049 +#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2 + +#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1050 +#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2 + +#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1051 +#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2 + +#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_WIDTH 30U +#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1052 +#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2 + +#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1053 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1053 +#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2 + +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1053 +#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2 + +#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2 + +#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2 + +#define LPDDR4__DENALI_PHY_1056_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1056 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2 + +#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1056 +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1061 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1061 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1062 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1062 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2 + +#define LPDDR4__DENALI_PHY_1063_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1063_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1063 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2 + +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1063 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2 + +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1063 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2 + +#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2 + +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2 + +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2 + +#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x0000010FU +#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x0000010FU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h new file mode 100644 index 000000000..21e96c9a9 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h @@ -0,0 +1,1306 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_CTL_REGS_H_ +#define REG_LPDDR4_CTL_REGS_H_ + +#include "lpddr4_ddr_controller_macros.h" +#include "lpddr4_pi_macros.h" +#include "lpddr4_data_slice_0_macros.h" +#include "lpddr4_data_slice_1_macros.h" +#include "lpddr4_address_slice_0_macros.h" +#include "lpddr4_address_slice_1_macros.h" +#include "lpddr4_address_slice_2_macros.h" +#include "lpddr4_phy_core_macros.h" + +typedef struct __attribute__((packed)) lpddr4_ctlregs_s { + volatile u32 DENALI_CTL_0; + volatile u32 DENALI_CTL_1; + volatile u32 DENALI_CTL_2; + volatile u32 DENALI_CTL_3; + volatile u32 DENALI_CTL_4; + volatile u32 DENALI_CTL_5; + volatile u32 DENALI_CTL_6; + volatile u32 DENALI_CTL_7; + volatile u32 DENALI_CTL_8; + volatile u32 DENALI_CTL_9; + volatile u32 DENALI_CTL_10; + volatile u32 DENALI_CTL_11; + volatile u32 DENALI_CTL_12; + volatile u32 DENALI_CTL_13; + volatile u32 DENALI_CTL_14; + volatile u32 DENALI_CTL_15; + volatile u32 DENALI_CTL_16; + volatile u32 DENALI_CTL_17; + volatile u32 DENALI_CTL_18; + volatile u32 DENALI_CTL_19; + volatile u32 DENALI_CTL_20; + volatile u32 DENALI_CTL_21; + volatile u32 DENALI_CTL_22; + volatile u32 DENALI_CTL_23; + volatile u32 DENALI_CTL_24; + volatile u32 DENALI_CTL_25; + volatile u32 DENALI_CTL_26; + volatile u32 DENALI_CTL_27; + volatile u32 DENALI_CTL_28; + volatile u32 DENALI_CTL_29; + volatile u32 DENALI_CTL_30; + volatile u32 DENALI_CTL_31; + volatile u32 DENALI_CTL_32; + volatile u32 DENALI_CTL_33; + volatile u32 DENALI_CTL_34; + volatile u32 DENALI_CTL_35; + volatile u32 DENALI_CTL_36; + volatile u32 DENALI_CTL_37; + volatile u32 DENALI_CTL_38; + volatile u32 DENALI_CTL_39; + volatile u32 DENALI_CTL_40; + volatile u32 DENALI_CTL_41; + volatile u32 DENALI_CTL_42; + volatile u32 DENALI_CTL_43; + volatile u32 DENALI_CTL_44; + volatile u32 DENALI_CTL_45; + volatile u32 DENALI_CTL_46; + volatile u32 DENALI_CTL_47; + volatile u32 DENALI_CTL_48; + volatile u32 DENALI_CTL_49; + volatile u32 DENALI_CTL_50; + volatile u32 DENALI_CTL_51; + volatile u32 DENALI_CTL_52; + volatile u32 DENALI_CTL_53; + volatile u32 DENALI_CTL_54; + volatile u32 DENALI_CTL_55; + volatile u32 DENALI_CTL_56; + volatile u32 DENALI_CTL_57; + volatile u32 DENALI_CTL_58; + volatile u32 DENALI_CTL_59; + volatile u32 DENALI_CTL_60; + volatile u32 DENALI_CTL_61; + volatile u32 DENALI_CTL_62; + volatile u32 DENALI_CTL_63; + volatile u32 DENALI_CTL_64; + volatile u32 DENALI_CTL_65; + volatile u32 DENALI_CTL_66; + volatile u32 DENALI_CTL_67; + volatile u32 DENALI_CTL_68; + volatile u32 DENALI_CTL_69; + volatile u32 DENALI_CTL_70; + volatile u32 DENALI_CTL_71; + volatile u32 DENALI_CTL_72; + volatile u32 DENALI_CTL_73; + volatile u32 DENALI_CTL_74; + volatile u32 DENALI_CTL_75; + volatile u32 DENALI_CTL_76; + volatile u32 DENALI_CTL_77; + volatile u32 DENALI_CTL_78; + volatile u32 DENALI_CTL_79; + volatile u32 DENALI_CTL_80; + volatile u32 DENALI_CTL_81; + volatile u32 DENALI_CTL_82; + volatile u32 DENALI_CTL_83; + volatile u32 DENALI_CTL_84; + volatile u32 DENALI_CTL_85; + volatile u32 DENALI_CTL_86; + volatile u32 DENALI_CTL_87; + volatile u32 DENALI_CTL_88; + volatile u32 DENALI_CTL_89; + volatile u32 DENALI_CTL_90; + volatile u32 DENALI_CTL_91; + volatile u32 DENALI_CTL_92; + volatile u32 DENALI_CTL_93; + volatile u32 DENALI_CTL_94; + volatile u32 DENALI_CTL_95; + volatile u32 DENALI_CTL_96; + volatile u32 DENALI_CTL_97; + volatile u32 DENALI_CTL_98; + volatile u32 DENALI_CTL_99; + volatile u32 DENALI_CTL_100; + volatile u32 DENALI_CTL_101; + volatile u32 DENALI_CTL_102; + volatile u32 DENALI_CTL_103; + volatile u32 DENALI_CTL_104; + volatile u32 DENALI_CTL_105; + volatile u32 DENALI_CTL_106; + volatile u32 DENALI_CTL_107; + volatile u32 DENALI_CTL_108; + volatile u32 DENALI_CTL_109; + volatile u32 DENALI_CTL_110; + volatile u32 DENALI_CTL_111; + volatile u32 DENALI_CTL_112; + volatile u32 DENALI_CTL_113; + volatile u32 DENALI_CTL_114; + volatile u32 DENALI_CTL_115; + volatile u32 DENALI_CTL_116; + volatile u32 DENALI_CTL_117; + volatile u32 DENALI_CTL_118; + volatile u32 DENALI_CTL_119; + volatile u32 DENALI_CTL_120; + volatile u32 DENALI_CTL_121; + volatile u32 DENALI_CTL_122; + volatile u32 DENALI_CTL_123; + volatile u32 DENALI_CTL_124; + volatile u32 DENALI_CTL_125; + volatile u32 DENALI_CTL_126; + volatile u32 DENALI_CTL_127; + volatile u32 DENALI_CTL_128; + volatile u32 DENALI_CTL_129; + volatile u32 DENALI_CTL_130; + volatile u32 DENALI_CTL_131; + volatile u32 DENALI_CTL_132; + volatile u32 DENALI_CTL_133; + volatile u32 DENALI_CTL_134; + volatile u32 DENALI_CTL_135; + volatile u32 DENALI_CTL_136; + volatile u32 DENALI_CTL_137; + volatile u32 DENALI_CTL_138; + volatile u32 DENALI_CTL_139; + volatile u32 DENALI_CTL_140; + volatile u32 DENALI_CTL_141; + volatile u32 DENALI_CTL_142; + volatile u32 DENALI_CTL_143; + volatile u32 DENALI_CTL_144; + volatile u32 DENALI_CTL_145; + volatile u32 DENALI_CTL_146; + volatile u32 DENALI_CTL_147; + volatile u32 DENALI_CTL_148; + volatile u32 DENALI_CTL_149; + volatile u32 DENALI_CTL_150; + volatile u32 DENALI_CTL_151; + volatile u32 DENALI_CTL_152; + volatile u32 DENALI_CTL_153; + volatile u32 DENALI_CTL_154; + volatile u32 DENALI_CTL_155; + volatile u32 DENALI_CTL_156; + volatile u32 DENALI_CTL_157; + volatile u32 DENALI_CTL_158; + volatile u32 DENALI_CTL_159; + volatile u32 DENALI_CTL_160; + volatile u32 DENALI_CTL_161; + volatile u32 DENALI_CTL_162; + volatile u32 DENALI_CTL_163; + volatile u32 DENALI_CTL_164; + volatile u32 DENALI_CTL_165; + volatile u32 DENALI_CTL_166; + volatile u32 DENALI_CTL_167; + volatile u32 DENALI_CTL_168; + volatile u32 DENALI_CTL_169; + volatile u32 DENALI_CTL_170; + volatile u32 DENALI_CTL_171; + volatile u32 DENALI_CTL_172; + volatile u32 DENALI_CTL_173; + volatile u32 DENALI_CTL_174; + volatile u32 DENALI_CTL_175; + volatile u32 DENALI_CTL_176; + volatile u32 DENALI_CTL_177; + volatile u32 DENALI_CTL_178; + volatile u32 DENALI_CTL_179; + volatile u32 DENALI_CTL_180; + volatile u32 DENALI_CTL_181; + volatile u32 DENALI_CTL_182; + volatile u32 DENALI_CTL_183; + volatile u32 DENALI_CTL_184; + volatile u32 DENALI_CTL_185; + volatile u32 DENALI_CTL_186; + volatile u32 DENALI_CTL_187; + volatile u32 DENALI_CTL_188; + volatile u32 DENALI_CTL_189; + volatile u32 DENALI_CTL_190; + volatile u32 DENALI_CTL_191; + volatile u32 DENALI_CTL_192; + volatile u32 DENALI_CTL_193; + volatile u32 DENALI_CTL_194; + volatile u32 DENALI_CTL_195; + volatile u32 DENALI_CTL_196; + volatile u32 DENALI_CTL_197; + volatile u32 DENALI_CTL_198; + volatile u32 DENALI_CTL_199; + volatile u32 DENALI_CTL_200; + volatile u32 DENALI_CTL_201; + volatile u32 DENALI_CTL_202; + volatile u32 DENALI_CTL_203; + volatile u32 DENALI_CTL_204; + volatile u32 DENALI_CTL_205; + volatile u32 DENALI_CTL_206; + volatile u32 DENALI_CTL_207; + volatile u32 DENALI_CTL_208; + volatile u32 DENALI_CTL_209; + volatile u32 DENALI_CTL_210; + volatile u32 DENALI_CTL_211; + volatile u32 DENALI_CTL_212; + volatile u32 DENALI_CTL_213; + volatile u32 DENALI_CTL_214; + volatile u32 DENALI_CTL_215; + volatile u32 DENALI_CTL_216; + volatile u32 DENALI_CTL_217; + volatile u32 DENALI_CTL_218; + volatile u32 DENALI_CTL_219; + volatile u32 DENALI_CTL_220; + volatile u32 DENALI_CTL_221; + volatile u32 DENALI_CTL_222; + volatile u32 DENALI_CTL_223; + volatile u32 DENALI_CTL_224; + volatile u32 DENALI_CTL_225; + volatile u32 DENALI_CTL_226; + volatile u32 DENALI_CTL_227; + volatile u32 DENALI_CTL_228; + volatile u32 DENALI_CTL_229; + volatile u32 DENALI_CTL_230; + volatile u32 DENALI_CTL_231; + volatile u32 DENALI_CTL_232; + volatile u32 DENALI_CTL_233; + volatile u32 DENALI_CTL_234; + volatile u32 DENALI_CTL_235; + volatile u32 DENALI_CTL_236; + volatile u32 DENALI_CTL_237; + volatile u32 DENALI_CTL_238; + volatile u32 DENALI_CTL_239; + volatile u32 DENALI_CTL_240; + volatile u32 DENALI_CTL_241; + volatile u32 DENALI_CTL_242; + volatile u32 DENALI_CTL_243; + volatile u32 DENALI_CTL_244; + volatile u32 DENALI_CTL_245; + volatile u32 DENALI_CTL_246; + volatile u32 DENALI_CTL_247; + volatile u32 DENALI_CTL_248; + volatile u32 DENALI_CTL_249; + volatile u32 DENALI_CTL_250; + volatile u32 DENALI_CTL_251; + volatile u32 DENALI_CTL_252; + volatile u32 DENALI_CTL_253; + volatile u32 DENALI_CTL_254; + volatile u32 DENALI_CTL_255; + volatile u32 DENALI_CTL_256; + volatile u32 DENALI_CTL_257; + volatile u32 DENALI_CTL_258; + volatile u32 DENALI_CTL_259; + volatile u32 DENALI_CTL_260; + volatile u32 DENALI_CTL_261; + volatile u32 DENALI_CTL_262; + volatile u32 DENALI_CTL_263; + volatile u32 DENALI_CTL_264; + volatile u32 DENALI_CTL_265; + volatile u32 DENALI_CTL_266; + volatile u32 DENALI_CTL_267; + volatile u32 DENALI_CTL_268; + volatile u32 DENALI_CTL_269; + volatile u32 DENALI_CTL_270; + volatile u32 DENALI_CTL_271; + volatile u32 DENALI_CTL_272; + volatile u32 DENALI_CTL_273; + volatile u32 DENALI_CTL_274; + volatile u32 DENALI_CTL_275; + volatile u32 DENALI_CTL_276; + volatile u32 DENALI_CTL_277; + volatile u32 DENALI_CTL_278; + volatile u32 DENALI_CTL_279; + volatile u32 DENALI_CTL_280; + volatile u32 DENALI_CTL_281; + volatile u32 DENALI_CTL_282; + volatile u32 DENALI_CTL_283; + volatile u32 DENALI_CTL_284; + volatile u32 DENALI_CTL_285; + volatile u32 DENALI_CTL_286; + volatile u32 DENALI_CTL_287; + volatile u32 DENALI_CTL_288; + volatile u32 DENALI_CTL_289; + volatile u32 DENALI_CTL_290; + volatile u32 DENALI_CTL_291; + volatile u32 DENALI_CTL_292; + volatile u32 DENALI_CTL_293; + volatile u32 DENALI_CTL_294; + volatile u32 DENALI_CTL_295; + volatile u32 DENALI_CTL_296; + volatile u32 DENALI_CTL_297; + volatile u32 DENALI_CTL_298; + volatile u32 DENALI_CTL_299; + volatile u32 DENALI_CTL_300; + volatile u32 DENALI_CTL_301; + volatile u32 DENALI_CTL_302; + volatile u32 DENALI_CTL_303; + volatile u32 DENALI_CTL_304; + volatile u32 DENALI_CTL_305; + volatile u32 DENALI_CTL_306; + volatile u32 DENALI_CTL_307; + volatile u32 DENALI_CTL_308; + volatile u32 DENALI_CTL_309; + volatile u32 DENALI_CTL_310; + volatile u32 DENALI_CTL_311; + volatile u32 DENALI_CTL_312; + volatile u32 DENALI_CTL_313; + volatile u32 DENALI_CTL_314; + volatile u32 DENALI_CTL_315; + volatile u32 DENALI_CTL_316; + volatile u32 DENALI_CTL_317; + volatile u32 DENALI_CTL_318; + volatile u32 DENALI_CTL_319; + volatile u32 DENALI_CTL_320; + volatile u32 DENALI_CTL_321; + volatile u32 DENALI_CTL_322; + volatile u32 DENALI_CTL_323; + volatile u32 DENALI_CTL_324; + volatile u32 DENALI_CTL_325; + volatile u32 DENALI_CTL_326; + volatile u32 DENALI_CTL_327; + volatile u32 DENALI_CTL_328; + volatile u32 DENALI_CTL_329; + volatile u32 DENALI_CTL_330; + volatile u32 DENALI_CTL_331; + volatile u32 DENALI_CTL_332; + volatile u32 DENALI_CTL_333; + volatile u32 DENALI_CTL_334; + volatile u32 DENALI_CTL_335; + volatile u32 DENALI_CTL_336; + volatile u32 DENALI_CTL_337; + volatile u32 DENALI_CTL_338; + volatile u32 DENALI_CTL_339; + volatile u32 DENALI_CTL_340; + volatile u32 DENALI_CTL_341; + volatile u32 DENALI_CTL_342; + volatile u32 DENALI_CTL_343; + volatile u32 DENALI_CTL_344; + volatile u32 DENALI_CTL_345; + volatile u32 DENALI_CTL_346; + volatile u32 DENALI_CTL_347; + volatile u32 DENALI_CTL_348; + volatile u32 DENALI_CTL_349; + volatile u32 DENALI_CTL_350; + volatile u32 DENALI_CTL_351; + volatile u32 DENALI_CTL_352; + volatile u32 DENALI_CTL_353; + volatile u32 DENALI_CTL_354; + volatile u32 DENALI_CTL_355; + volatile u32 DENALI_CTL_356; + volatile u32 DENALI_CTL_357; + volatile u32 DENALI_CTL_358; + volatile u32 DENALI_CTL_359; + volatile u32 DENALI_CTL_360; + volatile u32 DENALI_CTL_361; + volatile u32 DENALI_CTL_362; + volatile u32 DENALI_CTL_363; + volatile u32 DENALI_CTL_364; + volatile u32 DENALI_CTL_365; + volatile u32 DENALI_CTL_366; + volatile u32 DENALI_CTL_367; + volatile u32 DENALI_CTL_368; + volatile u32 DENALI_CTL_369; + volatile u32 DENALI_CTL_370; + volatile u32 DENALI_CTL_371; + volatile u32 DENALI_CTL_372; + volatile u32 DENALI_CTL_373; + volatile u32 DENALI_CTL_374; + volatile u32 DENALI_CTL_375; + volatile u32 DENALI_CTL_376; + volatile u32 DENALI_CTL_377; + volatile u32 DENALI_CTL_378; + volatile u32 DENALI_CTL_379; + volatile u32 DENALI_CTL_380; + volatile u32 DENALI_CTL_381; + volatile u32 DENALI_CTL_382; + volatile u32 DENALI_CTL_383; + volatile u32 DENALI_CTL_384; + volatile u32 DENALI_CTL_385; + volatile u32 DENALI_CTL_386; + volatile u32 DENALI_CTL_387; + volatile u32 DENALI_CTL_388; + volatile u32 DENALI_CTL_389; + volatile u32 DENALI_CTL_390; + volatile u32 DENALI_CTL_391; + volatile u32 DENALI_CTL_392; + volatile u32 DENALI_CTL_393; + volatile u32 DENALI_CTL_394; + volatile u32 DENALI_CTL_395; + volatile u32 DENALI_CTL_396; + volatile u32 DENALI_CTL_397; + volatile u32 DENALI_CTL_398; + volatile u32 DENALI_CTL_399; + volatile u32 DENALI_CTL_400; + volatile u32 DENALI_CTL_401; + volatile u32 DENALI_CTL_402; + volatile u32 DENALI_CTL_403; + volatile u32 DENALI_CTL_404; + volatile u32 DENALI_CTL_405; + volatile u32 DENALI_CTL_406; + volatile u32 DENALI_CTL_407; + volatile u32 DENALI_CTL_408; + volatile u32 DENALI_CTL_409; + volatile u32 DENALI_CTL_410; + volatile u32 DENALI_CTL_411; + volatile u32 DENALI_CTL_412; + volatile u32 DENALI_CTL_413; + volatile u32 DENALI_CTL_414; + volatile u32 DENALI_CTL_415; + volatile u32 DENALI_CTL_416; + volatile u32 DENALI_CTL_417; + volatile u32 DENALI_CTL_418; + volatile u32 DENALI_CTL_419; + volatile u32 DENALI_CTL_420; + volatile u32 DENALI_CTL_421; + volatile u32 DENALI_CTL_422; + volatile char pad__0[0x1964U]; + volatile u32 DENALI_PI_0; + volatile u32 DENALI_PI_1; + volatile u32 DENALI_PI_2; + volatile u32 DENALI_PI_3; + volatile u32 DENALI_PI_4; + volatile u32 DENALI_PI_5; + volatile u32 DENALI_PI_6; + volatile u32 DENALI_PI_7; + volatile u32 DENALI_PI_8; + volatile u32 DENALI_PI_9; + volatile u32 DENALI_PI_10; + volatile u32 DENALI_PI_11; + volatile u32 DENALI_PI_12; + volatile u32 DENALI_PI_13; + volatile u32 DENALI_PI_14; + volatile u32 DENALI_PI_15; + volatile u32 DENALI_PI_16; + volatile u32 DENALI_PI_17; + volatile u32 DENALI_PI_18; + volatile u32 DENALI_PI_19; + volatile u32 DENALI_PI_20; + volatile u32 DENALI_PI_21; + volatile u32 DENALI_PI_22; + volatile u32 DENALI_PI_23; + volatile u32 DENALI_PI_24; + volatile u32 DENALI_PI_25; + volatile u32 DENALI_PI_26; + volatile u32 DENALI_PI_27; + volatile u32 DENALI_PI_28; + volatile u32 DENALI_PI_29; + volatile u32 DENALI_PI_30; + volatile u32 DENALI_PI_31; + volatile u32 DENALI_PI_32; + volatile u32 DENALI_PI_33; + volatile u32 DENALI_PI_34; + volatile u32 DENALI_PI_35; + volatile u32 DENALI_PI_36; + volatile u32 DENALI_PI_37; + volatile u32 DENALI_PI_38; + volatile u32 DENALI_PI_39; + volatile u32 DENALI_PI_40; + volatile u32 DENALI_PI_41; + volatile u32 DENALI_PI_42; + volatile u32 DENALI_PI_43; + volatile u32 DENALI_PI_44; + volatile u32 DENALI_PI_45; + volatile u32 DENALI_PI_46; + volatile u32 DENALI_PI_47; + volatile u32 DENALI_PI_48; + volatile u32 DENALI_PI_49; + volatile u32 DENALI_PI_50; + volatile u32 DENALI_PI_51; + volatile u32 DENALI_PI_52; + volatile u32 DENALI_PI_53; + volatile u32 DENALI_PI_54; + volatile u32 DENALI_PI_55; + volatile u32 DENALI_PI_56; + volatile u32 DENALI_PI_57; + volatile u32 DENALI_PI_58; + volatile u32 DENALI_PI_59; + volatile u32 DENALI_PI_60; + volatile u32 DENALI_PI_61; + volatile u32 DENALI_PI_62; + volatile u32 DENALI_PI_63; + volatile u32 DENALI_PI_64; + volatile u32 DENALI_PI_65; + volatile u32 DENALI_PI_66; + volatile u32 DENALI_PI_67; + volatile u32 DENALI_PI_68; + volatile u32 DENALI_PI_69; + volatile u32 DENALI_PI_70; + volatile u32 DENALI_PI_71; + volatile u32 DENALI_PI_72; + volatile u32 DENALI_PI_73; + volatile u32 DENALI_PI_74; + volatile u32 DENALI_PI_75; + volatile u32 DENALI_PI_76; + volatile u32 DENALI_PI_77; + volatile u32 DENALI_PI_78; + volatile u32 DENALI_PI_79; + volatile u32 DENALI_PI_80; + volatile u32 DENALI_PI_81; + volatile u32 DENALI_PI_82; + volatile u32 DENALI_PI_83; + volatile u32 DENALI_PI_84; + volatile u32 DENALI_PI_85; + volatile u32 DENALI_PI_86; + volatile u32 DENALI_PI_87; + volatile u32 DENALI_PI_88; + volatile u32 DENALI_PI_89; + volatile u32 DENALI_PI_90; + volatile u32 DENALI_PI_91; + volatile u32 DENALI_PI_92; + volatile u32 DENALI_PI_93; + volatile u32 DENALI_PI_94; + volatile u32 DENALI_PI_95; + volatile u32 DENALI_PI_96; + volatile u32 DENALI_PI_97; + volatile u32 DENALI_PI_98; + volatile u32 DENALI_PI_99; + volatile u32 DENALI_PI_100; + volatile u32 DENALI_PI_101; + volatile u32 DENALI_PI_102; + volatile u32 DENALI_PI_103; + volatile u32 DENALI_PI_104; + volatile u32 DENALI_PI_105; + volatile u32 DENALI_PI_106; + volatile u32 DENALI_PI_107; + volatile u32 DENALI_PI_108; + volatile u32 DENALI_PI_109; + volatile u32 DENALI_PI_110; + volatile u32 DENALI_PI_111; + volatile u32 DENALI_PI_112; + volatile u32 DENALI_PI_113; + volatile u32 DENALI_PI_114; + volatile u32 DENALI_PI_115; + volatile u32 DENALI_PI_116; + volatile u32 DENALI_PI_117; + volatile u32 DENALI_PI_118; + volatile u32 DENALI_PI_119; + volatile u32 DENALI_PI_120; + volatile u32 DENALI_PI_121; + volatile u32 DENALI_PI_122; + volatile u32 DENALI_PI_123; + volatile u32 DENALI_PI_124; + volatile u32 DENALI_PI_125; + volatile u32 DENALI_PI_126; + volatile u32 DENALI_PI_127; + volatile u32 DENALI_PI_128; + volatile u32 DENALI_PI_129; + volatile u32 DENALI_PI_130; + volatile u32 DENALI_PI_131; + volatile u32 DENALI_PI_132; + volatile u32 DENALI_PI_133; + volatile u32 DENALI_PI_134; + volatile u32 DENALI_PI_135; + volatile u32 DENALI_PI_136; + volatile u32 DENALI_PI_137; + volatile u32 DENALI_PI_138; + volatile u32 DENALI_PI_139; + volatile u32 DENALI_PI_140; + volatile u32 DENALI_PI_141; + volatile u32 DENALI_PI_142; + volatile u32 DENALI_PI_143; + volatile u32 DENALI_PI_144; + volatile u32 DENALI_PI_145; + volatile u32 DENALI_PI_146; + volatile u32 DENALI_PI_147; + volatile u32 DENALI_PI_148; + volatile u32 DENALI_PI_149; + volatile u32 DENALI_PI_150; + volatile u32 DENALI_PI_151; + volatile u32 DENALI_PI_152; + volatile u32 DENALI_PI_153; + volatile u32 DENALI_PI_154; + volatile u32 DENALI_PI_155; + volatile u32 DENALI_PI_156; + volatile u32 DENALI_PI_157; + volatile u32 DENALI_PI_158; + volatile u32 DENALI_PI_159; + volatile u32 DENALI_PI_160; + volatile u32 DENALI_PI_161; + volatile u32 DENALI_PI_162; + volatile u32 DENALI_PI_163; + volatile u32 DENALI_PI_164; + volatile u32 DENALI_PI_165; + volatile u32 DENALI_PI_166; + volatile u32 DENALI_PI_167; + volatile u32 DENALI_PI_168; + volatile u32 DENALI_PI_169; + volatile u32 DENALI_PI_170; + volatile u32 DENALI_PI_171; + volatile u32 DENALI_PI_172; + volatile u32 DENALI_PI_173; + volatile u32 DENALI_PI_174; + volatile u32 DENALI_PI_175; + volatile u32 DENALI_PI_176; + volatile u32 DENALI_PI_177; + volatile u32 DENALI_PI_178; + volatile u32 DENALI_PI_179; + volatile u32 DENALI_PI_180; + volatile u32 DENALI_PI_181; + volatile u32 DENALI_PI_182; + volatile u32 DENALI_PI_183; + volatile u32 DENALI_PI_184; + volatile u32 DENALI_PI_185; + volatile u32 DENALI_PI_186; + volatile u32 DENALI_PI_187; + volatile u32 DENALI_PI_188; + volatile u32 DENALI_PI_189; + volatile u32 DENALI_PI_190; + volatile u32 DENALI_PI_191; + volatile u32 DENALI_PI_192; + volatile u32 DENALI_PI_193; + volatile u32 DENALI_PI_194; + volatile u32 DENALI_PI_195; + volatile u32 DENALI_PI_196; + volatile u32 DENALI_PI_197; + volatile u32 DENALI_PI_198; + volatile u32 DENALI_PI_199; + volatile u32 DENALI_PI_200; + volatile u32 DENALI_PI_201; + volatile u32 DENALI_PI_202; + volatile u32 DENALI_PI_203; + volatile u32 DENALI_PI_204; + volatile u32 DENALI_PI_205; + volatile u32 DENALI_PI_206; + volatile u32 DENALI_PI_207; + volatile u32 DENALI_PI_208; + volatile u32 DENALI_PI_209; + volatile u32 DENALI_PI_210; + volatile u32 DENALI_PI_211; + volatile u32 DENALI_PI_212; + volatile u32 DENALI_PI_213; + volatile u32 DENALI_PI_214; + volatile u32 DENALI_PI_215; + volatile u32 DENALI_PI_216; + volatile u32 DENALI_PI_217; + volatile u32 DENALI_PI_218; + volatile u32 DENALI_PI_219; + volatile u32 DENALI_PI_220; + volatile u32 DENALI_PI_221; + volatile u32 DENALI_PI_222; + volatile u32 DENALI_PI_223; + volatile u32 DENALI_PI_224; + volatile u32 DENALI_PI_225; + volatile u32 DENALI_PI_226; + volatile u32 DENALI_PI_227; + volatile u32 DENALI_PI_228; + volatile u32 DENALI_PI_229; + volatile u32 DENALI_PI_230; + volatile u32 DENALI_PI_231; + volatile u32 DENALI_PI_232; + volatile u32 DENALI_PI_233; + volatile u32 DENALI_PI_234; + volatile u32 DENALI_PI_235; + volatile u32 DENALI_PI_236; + volatile u32 DENALI_PI_237; + volatile u32 DENALI_PI_238; + volatile u32 DENALI_PI_239; + volatile u32 DENALI_PI_240; + volatile u32 DENALI_PI_241; + volatile u32 DENALI_PI_242; + volatile u32 DENALI_PI_243; + volatile u32 DENALI_PI_244; + volatile u32 DENALI_PI_245; + volatile u32 DENALI_PI_246; + volatile u32 DENALI_PI_247; + volatile u32 DENALI_PI_248; + volatile u32 DENALI_PI_249; + volatile u32 DENALI_PI_250; + volatile u32 DENALI_PI_251; + volatile u32 DENALI_PI_252; + volatile u32 DENALI_PI_253; + volatile u32 DENALI_PI_254; + volatile u32 DENALI_PI_255; + volatile u32 DENALI_PI_256; + volatile u32 DENALI_PI_257; + volatile u32 DENALI_PI_258; + volatile u32 DENALI_PI_259; + volatile u32 DENALI_PI_260; + volatile u32 DENALI_PI_261; + volatile u32 DENALI_PI_262; + volatile u32 DENALI_PI_263; + volatile u32 DENALI_PI_264; + volatile u32 DENALI_PI_265; + volatile u32 DENALI_PI_266; + volatile u32 DENALI_PI_267; + volatile u32 DENALI_PI_268; + volatile u32 DENALI_PI_269; + volatile u32 DENALI_PI_270; + volatile u32 DENALI_PI_271; + volatile u32 DENALI_PI_272; + volatile u32 DENALI_PI_273; + volatile u32 DENALI_PI_274; + volatile u32 DENALI_PI_275; + volatile u32 DENALI_PI_276; + volatile u32 DENALI_PI_277; + volatile u32 DENALI_PI_278; + volatile u32 DENALI_PI_279; + volatile u32 DENALI_PI_280; + volatile u32 DENALI_PI_281; + volatile u32 DENALI_PI_282; + volatile u32 DENALI_PI_283; + volatile u32 DENALI_PI_284; + volatile u32 DENALI_PI_285; + volatile u32 DENALI_PI_286; + volatile u32 DENALI_PI_287; + volatile u32 DENALI_PI_288; + volatile u32 DENALI_PI_289; + volatile u32 DENALI_PI_290; + volatile u32 DENALI_PI_291; + volatile u32 DENALI_PI_292; + volatile u32 DENALI_PI_293; + volatile u32 DENALI_PI_294; + volatile u32 DENALI_PI_295; + volatile u32 DENALI_PI_296; + volatile u32 DENALI_PI_297; + volatile u32 DENALI_PI_298; + volatile u32 DENALI_PI_299; + volatile u32 DENALI_PI_300; + volatile u32 DENALI_PI_301; + volatile u32 DENALI_PI_302; + volatile u32 DENALI_PI_303; + volatile u32 DENALI_PI_304; + volatile u32 DENALI_PI_305; + volatile u32 DENALI_PI_306; + volatile u32 DENALI_PI_307; + volatile u32 DENALI_PI_308; + volatile u32 DENALI_PI_309; + volatile u32 DENALI_PI_310; + volatile u32 DENALI_PI_311; + volatile u32 DENALI_PI_312; + volatile u32 DENALI_PI_313; + volatile u32 DENALI_PI_314; + volatile u32 DENALI_PI_315; + volatile u32 DENALI_PI_316; + volatile u32 DENALI_PI_317; + volatile u32 DENALI_PI_318; + volatile u32 DENALI_PI_319; + volatile u32 DENALI_PI_320; + volatile u32 DENALI_PI_321; + volatile u32 DENALI_PI_322; + volatile u32 DENALI_PI_323; + volatile u32 DENALI_PI_324; + volatile u32 DENALI_PI_325; + volatile u32 DENALI_PI_326; + volatile u32 DENALI_PI_327; + volatile u32 DENALI_PI_328; + volatile u32 DENALI_PI_329; + volatile u32 DENALI_PI_330; + volatile u32 DENALI_PI_331; + volatile u32 DENALI_PI_332; + volatile u32 DENALI_PI_333; + volatile u32 DENALI_PI_334; + volatile u32 DENALI_PI_335; + volatile u32 DENALI_PI_336; + volatile u32 DENALI_PI_337; + volatile u32 DENALI_PI_338; + volatile u32 DENALI_PI_339; + volatile u32 DENALI_PI_340; + volatile u32 DENALI_PI_341; + volatile u32 DENALI_PI_342; + volatile u32 DENALI_PI_343; + volatile u32 DENALI_PI_344; + volatile char pad__1[0x1A9CU]; + volatile u32 DENALI_PHY_0; + volatile u32 DENALI_PHY_1; + volatile u32 DENALI_PHY_2; + volatile u32 DENALI_PHY_3; + volatile u32 DENALI_PHY_4; + volatile u32 DENALI_PHY_5; + volatile u32 DENALI_PHY_6; + volatile u32 DENALI_PHY_7; + volatile u32 DENALI_PHY_8; + volatile u32 DENALI_PHY_9; + volatile u32 DENALI_PHY_10; + volatile u32 DENALI_PHY_11; + volatile u32 DENALI_PHY_12; + volatile u32 DENALI_PHY_13; + volatile u32 DENALI_PHY_14; + volatile u32 DENALI_PHY_15; + volatile u32 DENALI_PHY_16; + volatile u32 DENALI_PHY_17; + volatile u32 DENALI_PHY_18; + volatile u32 DENALI_PHY_19; + volatile u32 DENALI_PHY_20; + volatile u32 DENALI_PHY_21; + volatile u32 DENALI_PHY_22; + volatile u32 DENALI_PHY_23; + volatile u32 DENALI_PHY_24; + volatile u32 DENALI_PHY_25; + volatile u32 DENALI_PHY_26; + volatile u32 DENALI_PHY_27; + volatile u32 DENALI_PHY_28; + volatile u32 DENALI_PHY_29; + volatile u32 DENALI_PHY_30; + volatile u32 DENALI_PHY_31; + volatile u32 DENALI_PHY_32; + volatile u32 DENALI_PHY_33; + volatile u32 DENALI_PHY_34; + volatile u32 DENALI_PHY_35; + volatile u32 DENALI_PHY_36; + volatile u32 DENALI_PHY_37; + volatile u32 DENALI_PHY_38; + volatile u32 DENALI_PHY_39; + volatile u32 DENALI_PHY_40; + volatile u32 DENALI_PHY_41; + volatile u32 DENALI_PHY_42; + volatile u32 DENALI_PHY_43; + volatile u32 DENALI_PHY_44; + volatile u32 DENALI_PHY_45; + volatile u32 DENALI_PHY_46; + volatile u32 DENALI_PHY_47; + volatile u32 DENALI_PHY_48; + volatile u32 DENALI_PHY_49; + volatile u32 DENALI_PHY_50; + volatile u32 DENALI_PHY_51; + volatile u32 DENALI_PHY_52; + volatile u32 DENALI_PHY_53; + volatile u32 DENALI_PHY_54; + volatile u32 DENALI_PHY_55; + volatile u32 DENALI_PHY_56; + volatile u32 DENALI_PHY_57; + volatile u32 DENALI_PHY_58; + volatile u32 DENALI_PHY_59; + volatile u32 DENALI_PHY_60; + volatile u32 DENALI_PHY_61; + volatile u32 DENALI_PHY_62; + volatile u32 DENALI_PHY_63; + volatile u32 DENALI_PHY_64; + volatile u32 DENALI_PHY_65; + volatile u32 DENALI_PHY_66; + volatile u32 DENALI_PHY_67; + volatile u32 DENALI_PHY_68; + volatile u32 DENALI_PHY_69; + volatile u32 DENALI_PHY_70; + volatile u32 DENALI_PHY_71; + volatile u32 DENALI_PHY_72; + volatile u32 DENALI_PHY_73; + volatile u32 DENALI_PHY_74; + volatile u32 DENALI_PHY_75; + volatile u32 DENALI_PHY_76; + volatile u32 DENALI_PHY_77; + volatile u32 DENALI_PHY_78; + volatile u32 DENALI_PHY_79; + volatile u32 DENALI_PHY_80; + volatile u32 DENALI_PHY_81; + volatile u32 DENALI_PHY_82; + volatile u32 DENALI_PHY_83; + volatile u32 DENALI_PHY_84; + volatile u32 DENALI_PHY_85; + volatile u32 DENALI_PHY_86; + volatile u32 DENALI_PHY_87; + volatile u32 DENALI_PHY_88; + volatile u32 DENALI_PHY_89; + volatile u32 DENALI_PHY_90; + volatile u32 DENALI_PHY_91; + volatile u32 DENALI_PHY_92; + volatile u32 DENALI_PHY_93; + volatile u32 DENALI_PHY_94; + volatile u32 DENALI_PHY_95; + volatile u32 DENALI_PHY_96; + volatile u32 DENALI_PHY_97; + volatile u32 DENALI_PHY_98; + volatile u32 DENALI_PHY_99; + volatile u32 DENALI_PHY_100; + volatile u32 DENALI_PHY_101; + volatile u32 DENALI_PHY_102; + volatile u32 DENALI_PHY_103; + volatile u32 DENALI_PHY_104; + volatile u32 DENALI_PHY_105; + volatile u32 DENALI_PHY_106; + volatile u32 DENALI_PHY_107; + volatile u32 DENALI_PHY_108; + volatile u32 DENALI_PHY_109; + volatile u32 DENALI_PHY_110; + volatile u32 DENALI_PHY_111; + volatile u32 DENALI_PHY_112; + volatile u32 DENALI_PHY_113; + volatile u32 DENALI_PHY_114; + volatile u32 DENALI_PHY_115; + volatile u32 DENALI_PHY_116; + volatile u32 DENALI_PHY_117; + volatile u32 DENALI_PHY_118; + volatile u32 DENALI_PHY_119; + volatile u32 DENALI_PHY_120; + volatile u32 DENALI_PHY_121; + volatile u32 DENALI_PHY_122; + volatile u32 DENALI_PHY_123; + volatile u32 DENALI_PHY_124; + volatile u32 DENALI_PHY_125; + volatile char pad__2[0x208U]; + volatile u32 DENALI_PHY_256; + volatile u32 DENALI_PHY_257; + volatile u32 DENALI_PHY_258; + volatile u32 DENALI_PHY_259; + volatile u32 DENALI_PHY_260; + volatile u32 DENALI_PHY_261; + volatile u32 DENALI_PHY_262; + volatile u32 DENALI_PHY_263; + volatile u32 DENALI_PHY_264; + volatile u32 DENALI_PHY_265; + volatile u32 DENALI_PHY_266; + volatile u32 DENALI_PHY_267; + volatile u32 DENALI_PHY_268; + volatile u32 DENALI_PHY_269; + volatile u32 DENALI_PHY_270; + volatile u32 DENALI_PHY_271; + volatile u32 DENALI_PHY_272; + volatile u32 DENALI_PHY_273; + volatile u32 DENALI_PHY_274; + volatile u32 DENALI_PHY_275; + volatile u32 DENALI_PHY_276; + volatile u32 DENALI_PHY_277; + volatile u32 DENALI_PHY_278; + volatile u32 DENALI_PHY_279; + volatile u32 DENALI_PHY_280; + volatile u32 DENALI_PHY_281; + volatile u32 DENALI_PHY_282; + volatile u32 DENALI_PHY_283; + volatile u32 DENALI_PHY_284; + volatile u32 DENALI_PHY_285; + volatile u32 DENALI_PHY_286; + volatile u32 DENALI_PHY_287; + volatile u32 DENALI_PHY_288; + volatile u32 DENALI_PHY_289; + volatile u32 DENALI_PHY_290; + volatile u32 DENALI_PHY_291; + volatile u32 DENALI_PHY_292; + volatile u32 DENALI_PHY_293; + volatile u32 DENALI_PHY_294; + volatile u32 DENALI_PHY_295; + volatile u32 DENALI_PHY_296; + volatile u32 DENALI_PHY_297; + volatile u32 DENALI_PHY_298; + volatile u32 DENALI_PHY_299; + volatile u32 DENALI_PHY_300; + volatile u32 DENALI_PHY_301; + volatile u32 DENALI_PHY_302; + volatile u32 DENALI_PHY_303; + volatile u32 DENALI_PHY_304; + volatile u32 DENALI_PHY_305; + volatile u32 DENALI_PHY_306; + volatile u32 DENALI_PHY_307; + volatile u32 DENALI_PHY_308; + volatile u32 DENALI_PHY_309; + volatile u32 DENALI_PHY_310; + volatile u32 DENALI_PHY_311; + volatile u32 DENALI_PHY_312; + volatile u32 DENALI_PHY_313; + volatile u32 DENALI_PHY_314; + volatile u32 DENALI_PHY_315; + volatile u32 DENALI_PHY_316; + volatile u32 DENALI_PHY_317; + volatile u32 DENALI_PHY_318; + volatile u32 DENALI_PHY_319; + volatile u32 DENALI_PHY_320; + volatile u32 DENALI_PHY_321; + volatile u32 DENALI_PHY_322; + volatile u32 DENALI_PHY_323; + volatile u32 DENALI_PHY_324; + volatile u32 DENALI_PHY_325; + volatile u32 DENALI_PHY_326; + volatile u32 DENALI_PHY_327; + volatile u32 DENALI_PHY_328; + volatile u32 DENALI_PHY_329; + volatile u32 DENALI_PHY_330; + volatile u32 DENALI_PHY_331; + volatile u32 DENALI_PHY_332; + volatile u32 DENALI_PHY_333; + volatile u32 DENALI_PHY_334; + volatile u32 DENALI_PHY_335; + volatile u32 DENALI_PHY_336; + volatile u32 DENALI_PHY_337; + volatile u32 DENALI_PHY_338; + volatile u32 DENALI_PHY_339; + volatile u32 DENALI_PHY_340; + volatile u32 DENALI_PHY_341; + volatile u32 DENALI_PHY_342; + volatile u32 DENALI_PHY_343; + volatile u32 DENALI_PHY_344; + volatile u32 DENALI_PHY_345; + volatile u32 DENALI_PHY_346; + volatile u32 DENALI_PHY_347; + volatile u32 DENALI_PHY_348; + volatile u32 DENALI_PHY_349; + volatile u32 DENALI_PHY_350; + volatile u32 DENALI_PHY_351; + volatile u32 DENALI_PHY_352; + volatile u32 DENALI_PHY_353; + volatile u32 DENALI_PHY_354; + volatile u32 DENALI_PHY_355; + volatile u32 DENALI_PHY_356; + volatile u32 DENALI_PHY_357; + volatile u32 DENALI_PHY_358; + volatile u32 DENALI_PHY_359; + volatile u32 DENALI_PHY_360; + volatile u32 DENALI_PHY_361; + volatile u32 DENALI_PHY_362; + volatile u32 DENALI_PHY_363; + volatile u32 DENALI_PHY_364; + volatile u32 DENALI_PHY_365; + volatile u32 DENALI_PHY_366; + volatile u32 DENALI_PHY_367; + volatile u32 DENALI_PHY_368; + volatile u32 DENALI_PHY_369; + volatile u32 DENALI_PHY_370; + volatile u32 DENALI_PHY_371; + volatile u32 DENALI_PHY_372; + volatile u32 DENALI_PHY_373; + volatile u32 DENALI_PHY_374; + volatile u32 DENALI_PHY_375; + volatile u32 DENALI_PHY_376; + volatile u32 DENALI_PHY_377; + volatile u32 DENALI_PHY_378; + volatile u32 DENALI_PHY_379; + volatile u32 DENALI_PHY_380; + volatile u32 DENALI_PHY_381; + volatile char pad__3[0x208U]; + volatile u32 DENALI_PHY_512; + volatile u32 DENALI_PHY_513; + volatile u32 DENALI_PHY_514; + volatile u32 DENALI_PHY_515; + volatile u32 DENALI_PHY_516; + volatile u32 DENALI_PHY_517; + volatile u32 DENALI_PHY_518; + volatile u32 DENALI_PHY_519; + volatile u32 DENALI_PHY_520; + volatile u32 DENALI_PHY_521; + volatile u32 DENALI_PHY_522; + volatile u32 DENALI_PHY_523; + volatile u32 DENALI_PHY_524; + volatile u32 DENALI_PHY_525; + volatile u32 DENALI_PHY_526; + volatile u32 DENALI_PHY_527; + volatile u32 DENALI_PHY_528; + volatile u32 DENALI_PHY_529; + volatile u32 DENALI_PHY_530; + volatile u32 DENALI_PHY_531; + volatile u32 DENALI_PHY_532; + volatile u32 DENALI_PHY_533; + volatile u32 DENALI_PHY_534; + volatile u32 DENALI_PHY_535; + volatile u32 DENALI_PHY_536; + volatile u32 DENALI_PHY_537; + volatile u32 DENALI_PHY_538; + volatile u32 DENALI_PHY_539; + volatile u32 DENALI_PHY_540; + volatile u32 DENALI_PHY_541; + volatile u32 DENALI_PHY_542; + volatile u32 DENALI_PHY_543; + volatile u32 DENALI_PHY_544; + volatile u32 DENALI_PHY_545; + volatile u32 DENALI_PHY_546; + volatile u32 DENALI_PHY_547; + volatile u32 DENALI_PHY_548; + volatile u32 DENALI_PHY_549; + volatile u32 DENALI_PHY_550; + volatile u32 DENALI_PHY_551; + volatile u32 DENALI_PHY_552; + volatile u32 DENALI_PHY_553; + volatile u32 DENALI_PHY_554; + volatile char pad__4[0x354U]; + volatile u32 DENALI_PHY_768; + volatile u32 DENALI_PHY_769; + volatile u32 DENALI_PHY_770; + volatile u32 DENALI_PHY_771; + volatile u32 DENALI_PHY_772; + volatile u32 DENALI_PHY_773; + volatile u32 DENALI_PHY_774; + volatile u32 DENALI_PHY_775; + volatile u32 DENALI_PHY_776; + volatile u32 DENALI_PHY_777; + volatile u32 DENALI_PHY_778; + volatile u32 DENALI_PHY_779; + volatile u32 DENALI_PHY_780; + volatile u32 DENALI_PHY_781; + volatile u32 DENALI_PHY_782; + volatile u32 DENALI_PHY_783; + volatile u32 DENALI_PHY_784; + volatile u32 DENALI_PHY_785; + volatile u32 DENALI_PHY_786; + volatile u32 DENALI_PHY_787; + volatile u32 DENALI_PHY_788; + volatile u32 DENALI_PHY_789; + volatile u32 DENALI_PHY_790; + volatile u32 DENALI_PHY_791; + volatile u32 DENALI_PHY_792; + volatile u32 DENALI_PHY_793; + volatile u32 DENALI_PHY_794; + volatile u32 DENALI_PHY_795; + volatile u32 DENALI_PHY_796; + volatile u32 DENALI_PHY_797; + volatile u32 DENALI_PHY_798; + volatile u32 DENALI_PHY_799; + volatile u32 DENALI_PHY_800; + volatile u32 DENALI_PHY_801; + volatile u32 DENALI_PHY_802; + volatile u32 DENALI_PHY_803; + volatile u32 DENALI_PHY_804; + volatile u32 DENALI_PHY_805; + volatile u32 DENALI_PHY_806; + volatile u32 DENALI_PHY_807; + volatile u32 DENALI_PHY_808; + volatile u32 DENALI_PHY_809; + volatile u32 DENALI_PHY_810; + volatile char pad__5[0x354U]; + volatile u32 DENALI_PHY_1024; + volatile u32 DENALI_PHY_1025; + volatile u32 DENALI_PHY_1026; + volatile u32 DENALI_PHY_1027; + volatile u32 DENALI_PHY_1028; + volatile u32 DENALI_PHY_1029; + volatile u32 DENALI_PHY_1030; + volatile u32 DENALI_PHY_1031; + volatile u32 DENALI_PHY_1032; + volatile u32 DENALI_PHY_1033; + volatile u32 DENALI_PHY_1034; + volatile u32 DENALI_PHY_1035; + volatile u32 DENALI_PHY_1036; + volatile u32 DENALI_PHY_1037; + volatile u32 DENALI_PHY_1038; + volatile u32 DENALI_PHY_1039; + volatile u32 DENALI_PHY_1040; + volatile u32 DENALI_PHY_1041; + volatile u32 DENALI_PHY_1042; + volatile u32 DENALI_PHY_1043; + volatile u32 DENALI_PHY_1044; + volatile u32 DENALI_PHY_1045; + volatile u32 DENALI_PHY_1046; + volatile u32 DENALI_PHY_1047; + volatile u32 DENALI_PHY_1048; + volatile u32 DENALI_PHY_1049; + volatile u32 DENALI_PHY_1050; + volatile u32 DENALI_PHY_1051; + volatile u32 DENALI_PHY_1052; + volatile u32 DENALI_PHY_1053; + volatile u32 DENALI_PHY_1054; + volatile u32 DENALI_PHY_1055; + volatile u32 DENALI_PHY_1056; + volatile u32 DENALI_PHY_1057; + volatile u32 DENALI_PHY_1058; + volatile u32 DENALI_PHY_1059; + volatile u32 DENALI_PHY_1060; + volatile u32 DENALI_PHY_1061; + volatile u32 DENALI_PHY_1062; + volatile u32 DENALI_PHY_1063; + volatile u32 DENALI_PHY_1064; + volatile u32 DENALI_PHY_1065; + volatile u32 DENALI_PHY_1066; + volatile char pad__6[0x354U]; + volatile u32 DENALI_PHY_1280; + volatile u32 DENALI_PHY_1281; + volatile u32 DENALI_PHY_1282; + volatile u32 DENALI_PHY_1283; + volatile u32 DENALI_PHY_1284; + volatile u32 DENALI_PHY_1285; + volatile u32 DENALI_PHY_1286; + volatile u32 DENALI_PHY_1287; + volatile u32 DENALI_PHY_1288; + volatile u32 DENALI_PHY_1289; + volatile u32 DENALI_PHY_1290; + volatile u32 DENALI_PHY_1291; + volatile u32 DENALI_PHY_1292; + volatile u32 DENALI_PHY_1293; + volatile u32 DENALI_PHY_1294; + volatile u32 DENALI_PHY_1295; + volatile u32 DENALI_PHY_1296; + volatile u32 DENALI_PHY_1297; + volatile u32 DENALI_PHY_1298; + volatile u32 DENALI_PHY_1299; + volatile u32 DENALI_PHY_1300; + volatile u32 DENALI_PHY_1301; + volatile u32 DENALI_PHY_1302; + volatile u32 DENALI_PHY_1303; + volatile u32 DENALI_PHY_1304; + volatile u32 DENALI_PHY_1305; + volatile u32 DENALI_PHY_1306; + volatile u32 DENALI_PHY_1307; + volatile u32 DENALI_PHY_1308; + volatile u32 DENALI_PHY_1309; + volatile u32 DENALI_PHY_1310; + volatile u32 DENALI_PHY_1311; + volatile u32 DENALI_PHY_1312; + volatile u32 DENALI_PHY_1313; + volatile u32 DENALI_PHY_1314; + volatile u32 DENALI_PHY_1315; + volatile u32 DENALI_PHY_1316; + volatile u32 DENALI_PHY_1317; + volatile u32 DENALI_PHY_1318; + volatile u32 DENALI_PHY_1319; + volatile u32 DENALI_PHY_1320; + volatile u32 DENALI_PHY_1321; + volatile u32 DENALI_PHY_1322; + volatile u32 DENALI_PHY_1323; + volatile u32 DENALI_PHY_1324; + volatile u32 DENALI_PHY_1325; + volatile u32 DENALI_PHY_1326; + volatile u32 DENALI_PHY_1327; + volatile u32 DENALI_PHY_1328; + volatile u32 DENALI_PHY_1329; + volatile u32 DENALI_PHY_1330; + volatile u32 DENALI_PHY_1331; + volatile u32 DENALI_PHY_1332; + volatile u32 DENALI_PHY_1333; + volatile u32 DENALI_PHY_1334; + volatile u32 DENALI_PHY_1335; + volatile u32 DENALI_PHY_1336; + volatile u32 DENALI_PHY_1337; + volatile u32 DENALI_PHY_1338; + volatile u32 DENALI_PHY_1339; + volatile u32 DENALI_PHY_1340; + volatile u32 DENALI_PHY_1341; + volatile u32 DENALI_PHY_1342; + volatile u32 DENALI_PHY_1343; + volatile u32 DENALI_PHY_1344; + volatile u32 DENALI_PHY_1345; + volatile u32 DENALI_PHY_1346; + volatile u32 DENALI_PHY_1347; + volatile u32 DENALI_PHY_1348; + volatile u32 DENALI_PHY_1349; + volatile u32 DENALI_PHY_1350; + volatile u32 DENALI_PHY_1351; + volatile u32 DENALI_PHY_1352; + volatile u32 DENALI_PHY_1353; + volatile u32 DENALI_PHY_1354; + volatile u32 DENALI_PHY_1355; + volatile u32 DENALI_PHY_1356; + volatile u32 DENALI_PHY_1357; + volatile u32 DENALI_PHY_1358; + volatile u32 DENALI_PHY_1359; + volatile u32 DENALI_PHY_1360; + volatile u32 DENALI_PHY_1361; + volatile u32 DENALI_PHY_1362; + volatile u32 DENALI_PHY_1363; + volatile u32 DENALI_PHY_1364; + volatile u32 DENALI_PHY_1365; + volatile u32 DENALI_PHY_1366; + volatile u32 DENALI_PHY_1367; + volatile u32 DENALI_PHY_1368; + volatile u32 DENALI_PHY_1369; + volatile u32 DENALI_PHY_1370; + volatile u32 DENALI_PHY_1371; + volatile u32 DENALI_PHY_1372; + volatile u32 DENALI_PHY_1373; + volatile u32 DENALI_PHY_1374; + volatile u32 DENALI_PHY_1375; + volatile u32 DENALI_PHY_1376; + volatile u32 DENALI_PHY_1377; + volatile u32 DENALI_PHY_1378; + volatile u32 DENALI_PHY_1379; + volatile u32 DENALI_PHY_1380; + volatile u32 DENALI_PHY_1381; + volatile u32 DENALI_PHY_1382; + volatile u32 DENALI_PHY_1383; + volatile u32 DENALI_PHY_1384; + volatile u32 DENALI_PHY_1385; + volatile u32 DENALI_PHY_1386; + volatile u32 DENALI_PHY_1387; + volatile u32 DENALI_PHY_1388; + volatile u32 DENALI_PHY_1389; + volatile u32 DENALI_PHY_1390; + volatile u32 DENALI_PHY_1391; + volatile u32 DENALI_PHY_1392; + volatile u32 DENALI_PHY_1393; + volatile u32 DENALI_PHY_1394; + volatile u32 DENALI_PHY_1395; + volatile u32 DENALI_PHY_1396; + volatile u32 DENALI_PHY_1397; + volatile u32 DENALI_PHY_1398; + volatile u32 DENALI_PHY_1399; + volatile u32 DENALI_PHY_1400; + volatile u32 DENALI_PHY_1401; + volatile u32 DENALI_PHY_1402; + volatile u32 DENALI_PHY_1403; + volatile u32 DENALI_PHY_1404; + volatile u32 DENALI_PHY_1405; +} lpddr4_ctlregs; + +#endif /* REG_LPDDR4_CTL_REGS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h new file mode 100644 index 000000000..d46b77b23 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_RW_MASKS_H_ +#define LPDDR4_RW_MASKS_H_ + +#include + +extern u32 g_lpddr4_ddr_controller_rw_mask[423]; +extern u32 g_lpddr4_pi_rw_mask[345]; +extern u32 g_lpddr4_data_slice_0_rw_mask[126]; +extern u32 g_lpddr4_data_slice_1_rw_mask[126]; +extern u32 g_lpddr4_address_slice_0_rw_mask[43]; +extern u32 g_lpddr4_address_slice_1_rw_mask[43]; +extern u32 g_lpddr4_address_slice_2_rw_mask[43]; +extern u32 g_lpddr4_phy_core_rw_mask[126]; + +#endif /* LPDDR4_RW_MASKS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h new file mode 100644 index 000000000..d3bf24e67 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h @@ -0,0 +1,2036 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_0_READ_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_WIDTH 7U +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1_READ_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0 + +#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_6_READ_MASK 0x030F0F1FU +#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x030F0F1FU +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_7_READ_MASK 0x01FF031FU +#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x01FF031FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_8_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0 + +#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__FLD LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0 + +#define LPDDR4__DENALI_PHY_9_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0 + +#define LPDDR4__DENALI_PHY_10_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0 + +#define LPDDR4__DENALI_PHY_11_READ_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_WIDTH 9U +#define LPDDR4__PHY_DQ_IDLE_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_DQ_IDLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0 + +#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOSET 0U +#define LPDDR4__PHY_PDA_MODE_EN_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_PDA_MODE_EN_0__FLD LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0 + +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_12_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0 + +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_13_READ_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0 + +#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0 + +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_14_READ_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0 + +#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_14 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_15_READ_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOSET 0U +#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_15 +#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_15__PHY_LPDDR_0 + +#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_15 +#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0 + +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_16_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_16 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0 + +#define LPDDR4__DENALI_PHY_17_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_17 +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0 + +#define LPDDR4__DENALI_PHY_18_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_18 +#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0 + +#define LPDDR4__DENALI_PHY_19_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_19 +#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0 + +#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_20 +#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0 + +#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_21 +#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0 + +#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_22 +#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0 + +#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_23 +#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0 + +#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_24 +#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0 + +#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_25 +#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0 + +#define LPDDR4__DENALI_PHY_26_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0 + +#define LPDDR4__DENALI_PHY_27_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_28_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_29_READ_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_29 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0 + +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_30_READ_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0 + +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_31_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_32_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0 + +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_MASK 0x03FFFF00U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_WIDTH 18U +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0 + +#define LPDDR4__DENALI_PHY_33_READ_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 + +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0 + +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0 + +#define LPDDR4__DENALI_PHY_34_READ_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0 + +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_35_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0 + +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_35 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 + +#define LPDDR4__DENALI_PHY_36_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_36 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0 + +#define LPDDR4__DENALI_PHY_37_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_37 +#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0 + +#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_38 +#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0 + +#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_39 +#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0 + +#define LPDDR4__DENALI_PHY_40_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_40 +#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0 + +#define LPDDR4__DENALI_PHY_41_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_41 +#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0 + +#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_41 +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0 + +#define LPDDR4__DENALI_PHY_42_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_43_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0 + +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0 + +#define LPDDR4__DENALI_PHY_44_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_44 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0 + +#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_44 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_44 +#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0 + +#define LPDDR4__DENALI_PHY_45_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_45 +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_46_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_47_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_49_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_50_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_50 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_50 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_51_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_WIDTH 21U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_51 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_52_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_53_READ_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_53 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_54_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_55_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_56_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0 + +#define LPDDR4__DENALI_PHY_57_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_58_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_58 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_58 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_59_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_59 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_60_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_60 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0 + +#define LPDDR4__DENALI_PHY_61_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_61 +#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_62_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_62 +#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_63_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_63 +#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_64_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_64 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_65_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_65 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_65 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0 + +#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_65 +#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0 + +#define LPDDR4__DENALI_PHY_66_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0 + +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0 + +#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0 + +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0 + +#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0 + +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0 + +#define LPDDR4__DENALI_PHY_69_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_69 +#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0 + +#define LPDDR4__DENALI_PHY_70_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_70 +#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0 + +#define LPDDR4__DENALI_PHY_71_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_71 +#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0 + +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_71 +#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0 + +#define LPDDR4__DENALI_PHY_72_READ_MASK 0x071F07FFU +#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x071F07FFU +#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_72 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0 + +#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_72 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_72 +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_74_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_75_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0 + +#define LPDDR4__DENALI_PHY_76_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0 + +#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0 + +#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0 + +#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0 + +#define LPDDR4__DENALI_PHY_77_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0 + +#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0 + +#define LPDDR4__DENALI_PHY_78_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0 + +#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_79_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0 + +#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0 + +#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0 + +#define LPDDR4__DENALI_PHY_80_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0 + +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0 + +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0 + +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0 + +#define LPDDR4__DENALI_PHY_81_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0 + +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0 + +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0 + +#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_82_READ_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_82 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_82 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 7U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_82 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_83_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_84_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_85_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_86_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_87_READ_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0 + +#define LPDDR4__DENALI_PHY_88_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_89_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0 + +#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_90_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0 + +#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0 + +#define LPDDR4__DENALI_PHY_91_READ_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_92_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_WIDTH 2U +#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0 + +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOSET 0U +#define LPDDR4__PHY_WDQLVL_IE_ON_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_WDQLVL_IE_ON_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0 + +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_93_READ_MASK 0x000F1F1FU +#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x000F1F1FU +#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_94_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_95_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0 + +#define LPDDR4__DENALI_PHY_96_READ_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_97_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0 + +#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0 + +#define LPDDR4__DENALI_PHY_98_READ_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0 + +#define LPDDR4__DENALI_PHY_99_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0 + +#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_100_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0 + +#define LPDDR4__DENALI_PHY_101_READ_MASK 0x7F7F0703U +#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x7F7F0703U +#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0 + +#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0 + +#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH 7U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0 + +#define LPDDR4__DENALI_PHY_102_READ_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_103_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_104_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_105_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_106_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_106 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_106 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_107_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_108_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_108 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_108 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_109_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_110_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0 + +#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_111_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_111 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_111 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_112_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_113_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_114_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_114 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_114 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_115_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_115 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_115 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_116_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_118_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0 + +#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_121_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0 + +#define LPDDR4__DENALI_PHY_122_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0 + +#define LPDDR4__DENALI_PHY_123_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0 + +#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0 + +#define LPDDR4__DENALI_PHY_124_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_124 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_125_READ_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0 + +#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0 + +#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h new file mode 100644 index 000000000..d60bb6afe --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h @@ -0,0 +1,2036 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_ + +#define LPDDR4__DENALI_PHY_256_READ_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_WIDTH 7U +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_257_READ_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1 + +#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_262_READ_MASK 0x030F0F1FU +#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x030F0F1FU +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_263_READ_MASK 0x01FF031FU +#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x01FF031FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1 + +#define LPDDR4__DENALI_PHY_264_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1 + +#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__FLD LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1 + +#define LPDDR4__DENALI_PHY_265_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1 + +#define LPDDR4__DENALI_PHY_266_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1 + +#define LPDDR4__DENALI_PHY_267_READ_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_WIDTH 9U +#define LPDDR4__PHY_DQ_IDLE_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_DQ_IDLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1 + +#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOSET 0U +#define LPDDR4__PHY_PDA_MODE_EN_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_PDA_MODE_EN_1__FLD LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1 + +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1 + +#define LPDDR4__DENALI_PHY_268_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1 + +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1 + +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_269_READ_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1 + +#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1 + +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_270_READ_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1 + +#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_270 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1 + +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_271_READ_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOSET 0U +#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_271 +#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_271__PHY_LPDDR_1 + +#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_271 +#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1 + +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_272_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_272 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1 + +#define LPDDR4__DENALI_PHY_273_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_273 +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1 + +#define LPDDR4__DENALI_PHY_274_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_274 +#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1 + +#define LPDDR4__DENALI_PHY_275_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_275 +#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1 + +#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_276 +#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1 + +#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_277 +#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1 + +#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_278 +#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1 + +#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_279 +#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1 + +#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_280 +#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1 + +#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_281 +#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1 + +#define LPDDR4__DENALI_PHY_282_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1 + +#define LPDDR4__DENALI_PHY_283_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1 + +#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_284_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_285_READ_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1 + +#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_285 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1 + +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_286_READ_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1 + +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_287_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_288_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1 + +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_MASK 0x03FFFF00U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_WIDTH 18U +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1 + +#define LPDDR4__DENALI_PHY_289_READ_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1 + +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1 + +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1 + +#define LPDDR4__DENALI_PHY_290_READ_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1 + +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_291_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1 + +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_291 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1 + +#define LPDDR4__DENALI_PHY_292_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_292 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1 + +#define LPDDR4__DENALI_PHY_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_293 +#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1 + +#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_294 +#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1 + +#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_295 +#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1 + +#define LPDDR4__DENALI_PHY_296_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_296 +#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1 + +#define LPDDR4__DENALI_PHY_297_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_297 +#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1 + +#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_297 +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1 + +#define LPDDR4__DENALI_PHY_298_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_299_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1 + +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1 + +#define LPDDR4__DENALI_PHY_300_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_300 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1 + +#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_300 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1 + +#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_300 +#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1 + +#define LPDDR4__DENALI_PHY_301_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_301 +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1 + +#define LPDDR4__DENALI_PHY_302_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1 + +#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_303_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1 + +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_305_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1 + +#define LPDDR4__DENALI_PHY_306_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_306 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_306 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_307_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_WIDTH 21U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_307 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_308_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_309_READ_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_309 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_310_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_311_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_312_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1 + +#define LPDDR4__DENALI_PHY_313_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_314_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_314 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_314 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_315_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_315 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_316_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_316 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1 + +#define LPDDR4__DENALI_PHY_317_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_317 +#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1 + +#define LPDDR4__DENALI_PHY_318_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_318 +#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1 + +#define LPDDR4__DENALI_PHY_319_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_319 +#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1 + +#define LPDDR4__DENALI_PHY_320_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_320 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_321_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_321 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_321 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1 + +#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_321 +#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1 + +#define LPDDR4__DENALI_PHY_322_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1 + +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1 + +#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1 + +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1 + +#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1 + +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1 + +#define LPDDR4__DENALI_PHY_325_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_325 +#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1 + +#define LPDDR4__DENALI_PHY_326_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_326 +#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1 + +#define LPDDR4__DENALI_PHY_327_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_327 +#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1 + +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_327 +#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1 + +#define LPDDR4__DENALI_PHY_328_READ_MASK 0x071F07FFU +#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x071F07FFU +#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_328 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1 + +#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_328 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1 + +#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_328 +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1 + +#define LPDDR4__DENALI_PHY_330_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_331_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1 + +#define LPDDR4__DENALI_PHY_332_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1 + +#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1 + +#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1 + +#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1 + +#define LPDDR4__DENALI_PHY_333_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1 + +#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1 + +#define LPDDR4__DENALI_PHY_334_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1 + +#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_335_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1 + +#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1 + +#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1 + +#define LPDDR4__DENALI_PHY_336_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1 + +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1 + +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1 + +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1 + +#define LPDDR4__DENALI_PHY_337_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1 + +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1 + +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1 + +#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_338_READ_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_338 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_338 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 7U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_338 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_339_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_340_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_341_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_342_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_343_READ_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1 + +#define LPDDR4__DENALI_PHY_344_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_345_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1 + +#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_346_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1 + +#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1 + +#define LPDDR4__DENALI_PHY_347_READ_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1 + +#define LPDDR4__DENALI_PHY_348_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_WIDTH 2U +#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1 + +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOSET 0U +#define LPDDR4__PHY_WDQLVL_IE_ON_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_WDQLVL_IE_ON_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1 + +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_349_READ_MASK 0x000F1F1FU +#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x000F1F1FU +#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1 + +#define LPDDR4__DENALI_PHY_350_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1 + +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1 + +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1 + +#define LPDDR4__DENALI_PHY_351_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1 + +#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1 + +#define LPDDR4__DENALI_PHY_352_READ_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_353_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1 + +#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1 + +#define LPDDR4__DENALI_PHY_354_READ_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1 + +#define LPDDR4__DENALI_PHY_355_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1 + +#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_356_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1 + +#define LPDDR4__DENALI_PHY_357_READ_MASK 0x7F7F0703U +#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x7F7F0703U +#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1 + +#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1 + +#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH 7U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1 + +#define LPDDR4__DENALI_PHY_358_READ_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_359_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1 + +#define LPDDR4__DENALI_PHY_360_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1 + +#define LPDDR4__DENALI_PHY_361_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_362_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_362 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_362 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_363_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_364_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_364 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_364 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_365_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_366_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1 + +#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_367_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_367 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_367 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_368_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_369_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_370_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_370 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_370 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_371_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_371 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_371 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_372_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_374_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1 + +#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_377_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1 + +#define LPDDR4__DENALI_PHY_378_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1 + +#define LPDDR4__DENALI_PHY_379_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1 + +#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1 + +#define LPDDR4__DENALI_PHY_380_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_380 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_381_READ_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1 + +#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1 + +#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h new file mode 100644 index 000000000..3df803e9e --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h @@ -0,0 +1,6436 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ +#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ + +#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U +#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U +#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U +#define LPDDR4__DENALI_CTL_0__START_WOSET 0U +#define LPDDR4__START__REG DENALI_CTL_0 +#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START + +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U +#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0 +#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS + +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U +#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0 +#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID + +#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1 +#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0 + +#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2 +#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1 + +#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U +#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG + +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U +#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG + +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U +#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG + +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3 +#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U +#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5 +#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES + +#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U +#define LPDDR4__TINIT_F0__REG DENALI_CTL_7 +#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0 + +#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U +#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8 +#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0 + +#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U +#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9 +#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0 + +#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U +#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10 +#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0 + +#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U +#define LPDDR4__TINIT_F1__REG DENALI_CTL_11 +#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1 + +#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U +#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12 +#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1 + +#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U +#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13 +#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1 + +#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U +#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14 +#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1 + +#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U +#define LPDDR4__TINIT_F2__REG DENALI_CTL_15 +#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2 + +#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U +#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16 +#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2 + +#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U +#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17 +#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2 + +#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U +#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18 +#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2 + +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18 +#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_CTL_19_READ_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U +#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19 +#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_WIDTH 2U +#define LPDDR4__DFI_FREQ_RATIO_F0__REG DENALI_CTL_19 +#define LPDDR4__DFI_FREQ_RATIO_F0__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0 + +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_WIDTH 2U +#define LPDDR4__DFI_FREQ_RATIO_F1__REG DENALI_CTL_19 +#define LPDDR4__DFI_FREQ_RATIO_F1__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1 + +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_WIDTH 2U +#define LPDDR4__DFI_FREQ_RATIO_F2__REG DENALI_CTL_19 +#define LPDDR4__DFI_FREQ_RATIO_F2__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2 + +#define LPDDR4__DENALI_CTL_20_READ_MASK 0x01030101U +#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x01030101U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_SHIFT 0U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOSET 0U +#define LPDDR4__DFI_CMD_RATIO__REG DENALI_CTL_20 +#define LPDDR4__DFI_CMD_RATIO__FLD LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO + +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOSET 0U +#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_20 +#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_20__NO_MRW_INIT + +#define LPDDR4__DENALI_CTL_20__ODT_VALUE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_20__ODT_VALUE_SHIFT 16U +#define LPDDR4__DENALI_CTL_20__ODT_VALUE_WIDTH 2U +#define LPDDR4__ODT_VALUE__REG DENALI_CTL_20 +#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_20__ODT_VALUE + +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 24U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20 +#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE + +#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F013FU +#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F013FU +#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_SHIFT 0U +#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_WIDTH 6U +#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_21 +#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR + +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_SHIFT 8U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_21 +#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0 + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1 + +#define LPDDR4__DENALI_CTL_22_READ_MASK 0x0303031FU +#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x0303031FU +#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_22 +#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2 + +#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U +#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23 +#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON + +#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U +#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24 +#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE + +#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_25__TDLL_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_25__TDLL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_25__TDLL_F0_WIDTH 16U +#define LPDDR4__TDLL_F0__REG DENALI_CTL_25 +#define LPDDR4__TDLL_F0__FLD LPDDR4__DENALI_CTL_25__TDLL_F0 + +#define LPDDR4__DENALI_CTL_25__TDLL_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_25__TDLL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_25__TDLL_F1_WIDTH 16U +#define LPDDR4__TDLL_F1__REG DENALI_CTL_25 +#define LPDDR4__TDLL_F1__FLD LPDDR4__DENALI_CTL_25__TDLL_F1 + +#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_26__TDLL_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_26__TDLL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_26__TDLL_F2_WIDTH 16U +#define LPDDR4__TDLL_F2__REG DENALI_CTL_26 +#define LPDDR4__TDLL_F2__FLD LPDDR4__DENALI_CTL_26__TDLL_F2 + +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOSET 0U +#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__REG DENALI_CTL_26 +#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__FLD LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS + +#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_WIDTH 2U +#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__REG DENALI_CTL_26 +#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS + +#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_SHIFT 0U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WIDTH 1U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOCLR 0U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOSET 0U +#define LPDDR4__DQS_OSC_TST__REG DENALI_CTL_27 +#define LPDDR4__DQS_OSC_TST__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_TST + +#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_SHIFT 8U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_WIDTH 24U +#define LPDDR4__DQS_OSC_MPC_CMD__REG DENALI_CTL_27 +#define LPDDR4__DQS_OSC_MPC_CMD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD + +#define LPDDR4__DENALI_CTL_28_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_SHIFT 0U +#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_WIDTH 8U +#define LPDDR4__MRR_LSB_REG__REG DENALI_CTL_28 +#define LPDDR4__MRR_LSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_LSB_REG + +#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_SHIFT 8U +#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_WIDTH 8U +#define LPDDR4__MRR_MSB_REG__REG DENALI_CTL_28 +#define LPDDR4__MRR_MSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_MSB_REG + +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOSET 0U +#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_28 +#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE + +#define LPDDR4__DENALI_CTL_29_READ_MASK 0x000F7FFFU +#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0x000F7FFFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_SHIFT 0U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_WIDTH 15U +#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_29 +#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD + +#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_SHIFT 16U +#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_WIDTH 4U +#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_29 +#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES + +#define LPDDR4__DENALI_CTL_30_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_WIDTH 32U +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_30 +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_WIDTH 32U +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_31 +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_WIDTH 32U +#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_32 +#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT + +#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 32U +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_33 +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD + +#define LPDDR4__DENALI_CTL_34_READ_MASK 0xFF00FFFFU +#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0xFF00FFFFU +#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_WIDTH 16U +#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_34 +#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT + +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_SHIFT 16U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WIDTH 1U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOCLR 0U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOSET 0U +#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_34 +#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST + +#define LPDDR4__DENALI_CTL_34__TOSCO_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_34__TOSCO_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_34__TOSCO_F0_WIDTH 8U +#define LPDDR4__TOSCO_F0__REG DENALI_CTL_34 +#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_34__TOSCO_F0 + +#define LPDDR4__DENALI_CTL_35_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_35__TOSCO_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_35__TOSCO_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_35__TOSCO_F1_WIDTH 8U +#define LPDDR4__TOSCO_F1__REG DENALI_CTL_35 +#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_35__TOSCO_F1 + +#define LPDDR4__DENALI_CTL_35__TOSCO_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_35__TOSCO_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_35__TOSCO_F2_WIDTH 8U +#define LPDDR4__TOSCO_F2__REG DENALI_CTL_35 +#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_35__TOSCO_F2 + +#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_35 +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0 + +#define LPDDR4__DENALI_CTL_36_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_36 +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0 + +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_36 +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1 + +#define LPDDR4__DENALI_CTL_37_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_37 +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1 + +#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_WIDTH 4U +#define LPDDR4__DQS_OSC_STATUS__REG DENALI_CTL_37 +#define LPDDR4__DQS_OSC_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS + +#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOSET 0U +#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__REG DENALI_CTL_37 +#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS + +#define LPDDR4__DENALI_CTL_38_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_38 +#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0 + +#define LPDDR4__DENALI_CTL_38__WRLAT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_38__WRLAT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_38__WRLAT_F0_WIDTH 7U +#define LPDDR4__WRLAT_F0__REG DENALI_CTL_38 +#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_38__WRLAT_F0 + +#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_WIDTH 6U +#define LPDDR4__ADDITIVE_LAT_F0__REG DENALI_CTL_38 +#define LPDDR4__ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0 + +#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_WIDTH 4U +#define LPDDR4__CA_PARITY_LAT_F0__REG DENALI_CTL_38 +#define LPDDR4__CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0 + +#define LPDDR4__DENALI_CTL_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_WIDTH 8U +#define LPDDR4__TMOD_PAR_F0__REG DENALI_CTL_39 +#define LPDDR4__TMOD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_F0 + +#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_WIDTH 8U +#define LPDDR4__TMRD_PAR_F0__REG DENALI_CTL_39 +#define LPDDR4__TMRD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_F0 + +#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_WIDTH 8U +#define LPDDR4__TMOD_PAR_MAX_PL_F0__REG DENALI_CTL_39 +#define LPDDR4__TMOD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0 + +#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_WIDTH 8U +#define LPDDR4__TMRD_PAR_MAX_PL_F0__REG DENALI_CTL_39 +#define LPDDR4__TMRD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0 + +#define LPDDR4__DENALI_CTL_40_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_40 +#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1 + +#define LPDDR4__DENALI_CTL_40__WRLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_40__WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_40__WRLAT_F1_WIDTH 7U +#define LPDDR4__WRLAT_F1__REG DENALI_CTL_40 +#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_40__WRLAT_F1 + +#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_WIDTH 6U +#define LPDDR4__ADDITIVE_LAT_F1__REG DENALI_CTL_40 +#define LPDDR4__ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1 + +#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_WIDTH 4U +#define LPDDR4__CA_PARITY_LAT_F1__REG DENALI_CTL_40 +#define LPDDR4__CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1 + +#define LPDDR4__DENALI_CTL_41_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_WIDTH 8U +#define LPDDR4__TMOD_PAR_F1__REG DENALI_CTL_41 +#define LPDDR4__TMOD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_F1 + +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_WIDTH 8U +#define LPDDR4__TMRD_PAR_F1__REG DENALI_CTL_41 +#define LPDDR4__TMRD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_F1 + +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_WIDTH 8U +#define LPDDR4__TMOD_PAR_MAX_PL_F1__REG DENALI_CTL_41 +#define LPDDR4__TMOD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1 + +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_WIDTH 8U +#define LPDDR4__TMRD_PAR_MAX_PL_F1__REG DENALI_CTL_41 +#define LPDDR4__TMRD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1 + +#define LPDDR4__DENALI_CTL_42_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_42 +#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2 + +#define LPDDR4__DENALI_CTL_42__WRLAT_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_42__WRLAT_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_42__WRLAT_F2_WIDTH 7U +#define LPDDR4__WRLAT_F2__REG DENALI_CTL_42 +#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_42__WRLAT_F2 + +#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_WIDTH 6U +#define LPDDR4__ADDITIVE_LAT_F2__REG DENALI_CTL_42 +#define LPDDR4__ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2 + +#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_WIDTH 4U +#define LPDDR4__CA_PARITY_LAT_F2__REG DENALI_CTL_42 +#define LPDDR4__CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2 + +#define LPDDR4__DENALI_CTL_43_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_WIDTH 8U +#define LPDDR4__TMOD_PAR_F2__REG DENALI_CTL_43 +#define LPDDR4__TMOD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_F2 + +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_WIDTH 8U +#define LPDDR4__TMRD_PAR_F2__REG DENALI_CTL_43 +#define LPDDR4__TMRD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_F2 + +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_WIDTH 8U +#define LPDDR4__TMOD_PAR_MAX_PL_F2__REG DENALI_CTL_43 +#define LPDDR4__TMOD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2 + +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_WIDTH 8U +#define LPDDR4__TMRD_PAR_MAX_PL_F2__REG DENALI_CTL_43 +#define LPDDR4__TMRD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2 + +#define LPDDR4__DENALI_CTL_44_READ_MASK 0xFF1F1F07U +#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0xFF1F1F07U +#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_WIDTH 3U +#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_44 +#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL + +#define LPDDR4__DENALI_CTL_44__TCCD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_44__TCCD_SHIFT 8U +#define LPDDR4__DENALI_CTL_44__TCCD_WIDTH 5U +#define LPDDR4__TCCD__REG DENALI_CTL_44 +#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_44__TCCD + +#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_WIDTH 5U +#define LPDDR4__TCCD_L_F0__REG DENALI_CTL_44 +#define LPDDR4__TCCD_L_F0__FLD LPDDR4__DENALI_CTL_44__TCCD_L_F0 + +#define LPDDR4__DENALI_CTL_44__TRRD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_44__TRRD_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_44__TRRD_F0_WIDTH 8U +#define LPDDR4__TRRD_F0__REG DENALI_CTL_44 +#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_44__TRRD_F0 + +#define LPDDR4__DENALI_CTL_45_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_WIDTH 8U +#define LPDDR4__TRRD_L_F0__REG DENALI_CTL_45 +#define LPDDR4__TRRD_L_F0__FLD LPDDR4__DENALI_CTL_45__TRRD_L_F0 + +#define LPDDR4__DENALI_CTL_45__TRC_F0_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_45__TRC_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_45__TRC_F0_WIDTH 9U +#define LPDDR4__TRC_F0__REG DENALI_CTL_45 +#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_45__TRC_F0 + +#define LPDDR4__DENALI_CTL_46_READ_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_WIDTH 9U +#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_46 +#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_46__TRAS_MIN_F0 + +#define LPDDR4__DENALI_CTL_46__TWTR_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_46__TWTR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_46__TWTR_F0_WIDTH 6U +#define LPDDR4__TWTR_F0__REG DENALI_CTL_46 +#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_F0 + +#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_WIDTH 6U +#define LPDDR4__TWTR_L_F0__REG DENALI_CTL_46 +#define LPDDR4__TWTR_L_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_L_F0 + +#define LPDDR4__DENALI_CTL_47_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_47__TRP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_47__TRP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_47__TRP_F0_WIDTH 8U +#define LPDDR4__TRP_F0__REG DENALI_CTL_47 +#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_47__TRP_F0 + +#define LPDDR4__DENALI_CTL_47__TFAW_F0_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_47__TFAW_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_47__TFAW_F0_WIDTH 9U +#define LPDDR4__TFAW_F0__REG DENALI_CTL_47 +#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_47__TFAW_F0 + +#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_WIDTH 5U +#define LPDDR4__TCCD_L_F1__REG DENALI_CTL_47 +#define LPDDR4__TCCD_L_F1__FLD LPDDR4__DENALI_CTL_47__TCCD_L_F1 + +#define LPDDR4__DENALI_CTL_48_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_48__TRRD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_48__TRRD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_48__TRRD_F1_WIDTH 8U +#define LPDDR4__TRRD_F1__REG DENALI_CTL_48 +#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_F1 + +#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_WIDTH 8U +#define LPDDR4__TRRD_L_F1__REG DENALI_CTL_48 +#define LPDDR4__TRRD_L_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_L_F1 + +#define LPDDR4__DENALI_CTL_48__TRC_F1_MASK 0x01FF0000U +#define LPDDR4__DENALI_CTL_48__TRC_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_48__TRC_F1_WIDTH 9U +#define LPDDR4__TRC_F1__REG DENALI_CTL_48 +#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_48__TRC_F1 + +#define LPDDR4__DENALI_CTL_49_READ_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_WIDTH 9U +#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_49 +#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_49__TRAS_MIN_F1 + +#define LPDDR4__DENALI_CTL_49__TWTR_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_49__TWTR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_49__TWTR_F1_WIDTH 6U +#define LPDDR4__TWTR_F1__REG DENALI_CTL_49 +#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_F1 + +#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_WIDTH 6U +#define LPDDR4__TWTR_L_F1__REG DENALI_CTL_49 +#define LPDDR4__TWTR_L_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_L_F1 + +#define LPDDR4__DENALI_CTL_50_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_50__TRP_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_50__TRP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_50__TRP_F1_WIDTH 8U +#define LPDDR4__TRP_F1__REG DENALI_CTL_50 +#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_50__TRP_F1 + +#define LPDDR4__DENALI_CTL_50__TFAW_F1_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_50__TFAW_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_50__TFAW_F1_WIDTH 9U +#define LPDDR4__TFAW_F1__REG DENALI_CTL_50 +#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_50__TFAW_F1 + +#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_WIDTH 5U +#define LPDDR4__TCCD_L_F2__REG DENALI_CTL_50 +#define LPDDR4__TCCD_L_F2__FLD LPDDR4__DENALI_CTL_50__TCCD_L_F2 + +#define LPDDR4__DENALI_CTL_51_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_51__TRRD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_51__TRRD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_51__TRRD_F2_WIDTH 8U +#define LPDDR4__TRRD_F2__REG DENALI_CTL_51 +#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_F2 + +#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_WIDTH 8U +#define LPDDR4__TRRD_L_F2__REG DENALI_CTL_51 +#define LPDDR4__TRRD_L_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_L_F2 + +#define LPDDR4__DENALI_CTL_51__TRC_F2_MASK 0x01FF0000U +#define LPDDR4__DENALI_CTL_51__TRC_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_51__TRC_F2_WIDTH 9U +#define LPDDR4__TRC_F2__REG DENALI_CTL_51 +#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_51__TRC_F2 + +#define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_WIDTH 9U +#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_52 +#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_52__TRAS_MIN_F2 + +#define LPDDR4__DENALI_CTL_52__TWTR_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_52__TWTR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_52__TWTR_F2_WIDTH 6U +#define LPDDR4__TWTR_F2__REG DENALI_CTL_52 +#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_F2 + +#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_WIDTH 6U +#define LPDDR4__TWTR_L_F2__REG DENALI_CTL_52 +#define LPDDR4__TWTR_L_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_L_F2 + +#define LPDDR4__DENALI_CTL_53_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_53__TRP_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_53__TRP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_53__TRP_F2_WIDTH 8U +#define LPDDR4__TRP_F2__REG DENALI_CTL_53 +#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_53__TRP_F2 + +#define LPDDR4__DENALI_CTL_53__TFAW_F2_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_53__TFAW_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_53__TFAW_F2_WIDTH 9U +#define LPDDR4__TFAW_F2__REG DENALI_CTL_53 +#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_53__TFAW_F2 + +#define LPDDR4__DENALI_CTL_53__TRTP_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_53__TRTP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_53__TRTP_F0_WIDTH 8U +#define LPDDR4__TRTP_F0__REG DENALI_CTL_53 +#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_53__TRTP_F0 + +#define LPDDR4__DENALI_CTL_54_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_WIDTH 8U +#define LPDDR4__TRTP_AP_F0__REG DENALI_CTL_54 +#define LPDDR4__TRTP_AP_F0__FLD LPDDR4__DENALI_CTL_54__TRTP_AP_F0 + +#define LPDDR4__DENALI_CTL_54__TMRD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_54__TMRD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_54__TMRD_F0_WIDTH 8U +#define LPDDR4__TMRD_F0__REG DENALI_CTL_54 +#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_54__TMRD_F0 + +#define LPDDR4__DENALI_CTL_54__TMOD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_54__TMOD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_54__TMOD_F0_WIDTH 8U +#define LPDDR4__TMOD_F0__REG DENALI_CTL_54 +#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_54__TMOD_F0 + +#define LPDDR4__DENALI_CTL_55_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_WIDTH 20U +#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_55 +#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_55__TRAS_MAX_F0 + +#define LPDDR4__DENALI_CTL_55__TCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_55__TCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_55__TCKE_F0_WIDTH 5U +#define LPDDR4__TCKE_F0__REG DENALI_CTL_55 +#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_55__TCKE_F0 + +#define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_56__TCKESR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_56__TCKESR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_56__TCKESR_F0_WIDTH 8U +#define LPDDR4__TCKESR_F0__REG DENALI_CTL_56 +#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_56__TCKESR_F0 + +#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_WIDTH 6U +#define LPDDR4__TCCDMW_F0__REG DENALI_CTL_56 +#define LPDDR4__TCCDMW_F0__FLD LPDDR4__DENALI_CTL_56__TCCDMW_F0 + +#define LPDDR4__DENALI_CTL_56__TRTP_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_56__TRTP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_56__TRTP_F1_WIDTH 8U +#define LPDDR4__TRTP_F1__REG DENALI_CTL_56 +#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_F1 + +#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_WIDTH 8U +#define LPDDR4__TRTP_AP_F1__REG DENALI_CTL_56 +#define LPDDR4__TRTP_AP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_AP_F1 + +#define LPDDR4__DENALI_CTL_57_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_57__TMRD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_57__TMRD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_57__TMRD_F1_WIDTH 8U +#define LPDDR4__TMRD_F1__REG DENALI_CTL_57 +#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_57__TMRD_F1 + +#define LPDDR4__DENALI_CTL_57__TMOD_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_57__TMOD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_57__TMOD_F1_WIDTH 8U +#define LPDDR4__TMOD_F1__REG DENALI_CTL_57 +#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_57__TMOD_F1 + +#define LPDDR4__DENALI_CTL_58_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_WIDTH 20U +#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_58 +#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_58__TRAS_MAX_F1 + +#define LPDDR4__DENALI_CTL_58__TCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_58__TCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_58__TCKE_F1_WIDTH 5U +#define LPDDR4__TCKE_F1__REG DENALI_CTL_58 +#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_58__TCKE_F1 + +#define LPDDR4__DENALI_CTL_59_READ_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_59__TCKESR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_59__TCKESR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_59__TCKESR_F1_WIDTH 8U +#define LPDDR4__TCKESR_F1__REG DENALI_CTL_59 +#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_59__TCKESR_F1 + +#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_WIDTH 6U +#define LPDDR4__TCCDMW_F1__REG DENALI_CTL_59 +#define LPDDR4__TCCDMW_F1__FLD LPDDR4__DENALI_CTL_59__TCCDMW_F1 + +#define LPDDR4__DENALI_CTL_59__TRTP_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_59__TRTP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_59__TRTP_F2_WIDTH 8U +#define LPDDR4__TRTP_F2__REG DENALI_CTL_59 +#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_F2 + +#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_WIDTH 8U +#define LPDDR4__TRTP_AP_F2__REG DENALI_CTL_59 +#define LPDDR4__TRTP_AP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_AP_F2 + +#define LPDDR4__DENALI_CTL_60_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_60__TMRD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_60__TMRD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_60__TMRD_F2_WIDTH 8U +#define LPDDR4__TMRD_F2__REG DENALI_CTL_60 +#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_60__TMRD_F2 + +#define LPDDR4__DENALI_CTL_60__TMOD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_60__TMOD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_60__TMOD_F2_WIDTH 8U +#define LPDDR4__TMOD_F2__REG DENALI_CTL_60 +#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_60__TMOD_F2 + +#define LPDDR4__DENALI_CTL_61_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_WIDTH 20U +#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_61 +#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_61__TRAS_MAX_F2 + +#define LPDDR4__DENALI_CTL_61__TCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_61__TCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_61__TCKE_F2_WIDTH 5U +#define LPDDR4__TCKE_F2__REG DENALI_CTL_61 +#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_61__TCKE_F2 + +#define LPDDR4__DENALI_CTL_62_READ_MASK 0x07073FFFU +#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x07073FFFU +#define LPDDR4__DENALI_CTL_62__TCKESR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_62__TCKESR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_62__TCKESR_F2_WIDTH 8U +#define LPDDR4__TCKESR_F2__REG DENALI_CTL_62 +#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_62__TCKESR_F2 + +#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_WIDTH 6U +#define LPDDR4__TCCDMW_F2__REG DENALI_CTL_62 +#define LPDDR4__TCCDMW_F2__FLD LPDDR4__DENALI_CTL_62__TCCDMW_F2 + +#define LPDDR4__DENALI_CTL_62__TPPD_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_62__TPPD_SHIFT 16U +#define LPDDR4__DENALI_CTL_62__TPPD_WIDTH 3U +#define LPDDR4__TPPD__REG DENALI_CTL_62 +#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_62__TPPD + +#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_SHIFT 24U +#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_WIDTH 3U +#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_62 +#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_62__MC_RESERVED0 + +#define LPDDR4__DENALI_CTL_63_READ_MASK 0xFFFF0107U +#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0xFFFF0107U +#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_SHIFT 0U +#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_WIDTH 3U +#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_63 +#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_63__MC_RESERVED1 + +#define LPDDR4__DENALI_CTL_63__WRITEINTERP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_63__WRITEINTERP_SHIFT 8U +#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WIDTH 1U +#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOCLR 0U +#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOSET 0U +#define LPDDR4__WRITEINTERP__REG DENALI_CTL_63 +#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_63__WRITEINTERP + +#define LPDDR4__DENALI_CTL_63__TRCD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_63__TRCD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_63__TRCD_F0_WIDTH 8U +#define LPDDR4__TRCD_F0__REG DENALI_CTL_63 +#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_63__TRCD_F0 + +#define LPDDR4__DENALI_CTL_63__TWR_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_63__TWR_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_63__TWR_F0_WIDTH 8U +#define LPDDR4__TWR_F0__REG DENALI_CTL_63 +#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_63__TWR_F0 + +#define LPDDR4__DENALI_CTL_64_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_64__TRCD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_64__TRCD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_64__TRCD_F1_WIDTH 8U +#define LPDDR4__TRCD_F1__REG DENALI_CTL_64 +#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_64__TRCD_F1 + +#define LPDDR4__DENALI_CTL_64__TWR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_64__TWR_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_64__TWR_F1_WIDTH 8U +#define LPDDR4__TWR_F1__REG DENALI_CTL_64 +#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_64__TWR_F1 + +#define LPDDR4__DENALI_CTL_64__TRCD_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_64__TRCD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_64__TRCD_F2_WIDTH 8U +#define LPDDR4__TRCD_F2__REG DENALI_CTL_64 +#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_64__TRCD_F2 + +#define LPDDR4__DENALI_CTL_64__TWR_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_64__TWR_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_64__TWR_F2_WIDTH 8U +#define LPDDR4__TWR_F2__REG DENALI_CTL_64 +#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_64__TWR_F2 + +#define LPDDR4__DENALI_CTL_65_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_CTL_65__TMRR_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_65__TMRR_SHIFT 0U +#define LPDDR4__DENALI_CTL_65__TMRR_WIDTH 4U +#define LPDDR4__TMRR__REG DENALI_CTL_65 +#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_65__TMRR + +#define LPDDR4__DENALI_CTL_65__AP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_65__AP_SHIFT 8U +#define LPDDR4__DENALI_CTL_65__AP_WIDTH 1U +#define LPDDR4__DENALI_CTL_65__AP_WOCLR 0U +#define LPDDR4__DENALI_CTL_65__AP_WOSET 0U +#define LPDDR4__AP__REG DENALI_CTL_65 +#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_65__AP + +#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WIDTH 1U +#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOCLR 0U +#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOSET 0U +#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_65 +#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_65__CONCURRENTAP + +#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_SHIFT 24U +#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WIDTH 1U +#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOCLR 0U +#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOSET 0U +#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_65 +#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT + +#define LPDDR4__DENALI_CTL_66_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_CTL_66__TDAL_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_66__TDAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_66__TDAL_F0_WIDTH 8U +#define LPDDR4__TDAL_F0__REG DENALI_CTL_66 +#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_66__TDAL_F0 + +#define LPDDR4__DENALI_CTL_66__TDAL_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_66__TDAL_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_66__TDAL_F1_WIDTH 8U +#define LPDDR4__TDAL_F1__REG DENALI_CTL_66 +#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_66__TDAL_F1 + +#define LPDDR4__DENALI_CTL_66__TDAL_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_66__TDAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_66__TDAL_F2_WIDTH 8U +#define LPDDR4__TDAL_F2__REG DENALI_CTL_66 +#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_66__TDAL_F2 + +#define LPDDR4__DENALI_CTL_66__BSTLEN_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_66__BSTLEN_SHIFT 24U +#define LPDDR4__DENALI_CTL_66__BSTLEN_WIDTH 6U +#define LPDDR4__BSTLEN__REG DENALI_CTL_66 +#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_66__BSTLEN + +#define LPDDR4__DENALI_CTL_67_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_WIDTH 8U +#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_67 +#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_0 + +#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_WIDTH 8U +#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_67 +#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F1_0 + +#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_WIDTH 8U +#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_67 +#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F2_0 + +#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_WIDTH 8U +#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_67 +#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_1 + +#define LPDDR4__DENALI_CTL_68_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_WIDTH 8U +#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_68 +#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F1_1 + +#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_WIDTH 8U +#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_68 +#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F2_1 + +#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_68 +#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE + +#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_SHIFT 24U +#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_WIDTH 2U +#define LPDDR4__ADDRESS_MIRRORING__REG DENALI_CTL_68 +#define LPDDR4__ADDRESS_MIRRORING__FLD LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING + +#define LPDDR4__DENALI_CTL_69_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOSET 0U +#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_69 +#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN + +#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_SHIFT 8U +#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WIDTH 1U +#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOCLR 0U +#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOSET 0U +#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_69 +#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_69__MC_RESERVED2 + +#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_SHIFT 16U +#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WIDTH 1U +#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOCLR 0U +#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOSET 0U +#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_69 +#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_69__NO_MEMORY_DM + +#define LPDDR4__DENALI_CTL_70_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_SHIFT 0U +#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_WIDTH 26U +#define LPDDR4__CA_PARITY_ERROR_INJECT__REG DENALI_CTL_70 +#define LPDDR4__CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT + +#define LPDDR4__DENALI_CTL_71_READ_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_SHIFT 0U +#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOSET 0U +#define LPDDR4__CA_PARITY_ERROR__REG DENALI_CTL_71 +#define LPDDR4__CA_PARITY_ERROR__FLD LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR + +#define LPDDR4__DENALI_CTL_71__AREFRESH_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_71__AREFRESH_SHIFT 8U +#define LPDDR4__DENALI_CTL_71__AREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__AREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__AREFRESH_WOSET 0U +#define LPDDR4__AREFRESH__REG DENALI_CTL_71 +#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_71__AREFRESH + +#define LPDDR4__DENALI_CTL_71__AREF_STATUS_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_71__AREF_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOSET 0U +#define LPDDR4__AREF_STATUS__REG DENALI_CTL_71 +#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_71__AREF_STATUS + +#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOSET 0U +#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_71 +#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_71__TREF_ENABLE + +#define LPDDR4__DENALI_CTL_72_READ_MASK 0x03FF3F07U +#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0x03FF3F07U +#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_WIDTH 3U +#define LPDDR4__TRFC_OPT_THRESHOLD__REG DENALI_CTL_72 +#define LPDDR4__TRFC_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD + +#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_72 +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH + +#define LPDDR4__DENALI_CTL_72__TRFC_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_72__TRFC_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_72__TRFC_F0_WIDTH 10U +#define LPDDR4__TRFC_F0__REG DENALI_CTL_72 +#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_72__TRFC_F0 + +#define LPDDR4__DENALI_CTL_73_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_73__TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_73__TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_73__TREF_F0_WIDTH 20U +#define LPDDR4__TREF_F0__REG DENALI_CTL_73 +#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_73__TREF_F0 + +#define LPDDR4__DENALI_CTL_74_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_74__TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_74__TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_74__TRFC_F1_WIDTH 10U +#define LPDDR4__TRFC_F1__REG DENALI_CTL_74 +#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_74__TRFC_F1 + +#define LPDDR4__DENALI_CTL_75_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_75__TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_75__TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_75__TREF_F1_WIDTH 20U +#define LPDDR4__TREF_F1__REG DENALI_CTL_75 +#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_75__TREF_F1 + +#define LPDDR4__DENALI_CTL_76_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_76__TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_76__TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_76__TRFC_F2_WIDTH 10U +#define LPDDR4__TRFC_F2__REG DENALI_CTL_76 +#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_76__TRFC_F2 + +#define LPDDR4__DENALI_CTL_77_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_77__TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_77__TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_77__TREF_F2_WIDTH 20U +#define LPDDR4__TREF_F2__REG DENALI_CTL_77 +#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_77__TREF_F2 + +#define LPDDR4__DENALI_CTL_78_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_WIDTH 20U +#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_78 +#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_78__TREF_INTERVAL + +#define LPDDR4__DENALI_CTL_79_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_WIDTH 10U +#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_79 +#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_79__TRFC_PB_F0 + +#define LPDDR4__DENALI_CTL_80_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_WIDTH 20U +#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_80 +#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_80__TREFI_PB_F0 + +#define LPDDR4__DENALI_CTL_81_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_WIDTH 10U +#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_81 +#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_81__TRFC_PB_F1 + +#define LPDDR4__DENALI_CTL_82_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_WIDTH 20U +#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_82 +#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_82__TREFI_PB_F1 + +#define LPDDR4__DENALI_CTL_83_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_WIDTH 10U +#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_83 +#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_83__TRFC_PB_F2 + +#define LPDDR4__DENALI_CTL_84_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_WIDTH 20U +#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_84 +#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_84__TREFI_PB_F2 + +#define LPDDR4__DENALI_CTL_84__PBR_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_84__PBR_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_84__PBR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_84__PBR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_84__PBR_EN_WOSET 0U +#define LPDDR4__PBR_EN__REG DENALI_CTL_84 +#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_84__PBR_EN + +#define LPDDR4__DENALI_CTL_85_READ_MASK 0x0FFFFF01U +#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x0FFFFF01U +#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_SHIFT 0U +#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WIDTH 1U +#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOCLR 0U +#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOSET 0U +#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_85 +#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER + +#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_WIDTH 16U +#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_85 +#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT + +#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_SHIFT 24U +#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_WIDTH 4U +#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_85 +#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY + +#define LPDDR4__DENALI_CTL_86_READ_MASK 0x001F1F01U +#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0x001F1F01U +#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOSET 0U +#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_86 +#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN + +#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_86 +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD + +#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_86 +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD + +#define LPDDR4__DENALI_CTL_87_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_87__TPDEX_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_87__TPDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_87__TPDEX_F0_WIDTH 16U +#define LPDDR4__TPDEX_F0__REG DENALI_CTL_87 +#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_87__TPDEX_F0 + +#define LPDDR4__DENALI_CTL_87__TPDEX_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_87__TPDEX_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_87__TPDEX_F1_WIDTH 16U +#define LPDDR4__TPDEX_F1__REG DENALI_CTL_87 +#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_87__TPDEX_F1 + +#define LPDDR4__DENALI_CTL_88_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_88__TPDEX_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_88__TPDEX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_88__TPDEX_F2_WIDTH 16U +#define LPDDR4__TPDEX_F2__REG DENALI_CTL_88 +#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_88__TPDEX_F2 + +#define LPDDR4__DENALI_CTL_89_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_WIDTH 32U +#define LPDDR4__CTL_UNUSED_REG_0__REG DENALI_CTL_89 +#define LPDDR4__CTL_UNUSED_REG_0__FLD LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0 + +#define LPDDR4__DENALI_CTL_90_READ_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_CTL_90__TMRRI_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_90__TMRRI_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_90__TMRRI_F0_WIDTH 8U +#define LPDDR4__TMRRI_F0__REG DENALI_CTL_90 +#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_90__TMRRI_F0 + +#define LPDDR4__DENALI_CTL_90__TMRRI_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_90__TMRRI_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_90__TMRRI_F1_WIDTH 8U +#define LPDDR4__TMRRI_F1__REG DENALI_CTL_90 +#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_90__TMRRI_F1 + +#define LPDDR4__DENALI_CTL_90__TMRRI_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_90__TMRRI_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_90__TMRRI_F2_WIDTH 8U +#define LPDDR4__TMRRI_F2__REG DENALI_CTL_90 +#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_90__TMRRI_F2 + +#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_WIDTH 5U +#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_90 +#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_90__TCKELCS_F0 + +#define LPDDR4__DENALI_CTL_91_READ_MASK 0x1F0F1F1FU +#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0x1F0F1F1FU +#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_WIDTH 5U +#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_91 +#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKEHCS_F0 + +#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_WIDTH 5U +#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_91 +#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_91__TMRWCKEL_F0 + +#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_WIDTH 4U +#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_91 +#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_91__TZQCKE_F0 + +#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_WIDTH 5U +#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_91 +#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_91__TCKELCS_F1 + +#define LPDDR4__DENALI_CTL_92_READ_MASK 0x1F0F1F1FU +#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x1F0F1F1FU +#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_WIDTH 5U +#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_92 +#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKEHCS_F1 + +#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_WIDTH 5U +#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_92 +#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_92__TMRWCKEL_F1 + +#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_WIDTH 4U +#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_92 +#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_92__TZQCKE_F1 + +#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_WIDTH 5U +#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_92 +#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_92__TCKELCS_F2 + +#define LPDDR4__DENALI_CTL_93_READ_MASK 0x1F0F1F1FU +#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0x1F0F1F1FU +#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_WIDTH 5U +#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_93 +#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKEHCS_F2 + +#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_WIDTH 5U +#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_93 +#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_93__TMRWCKEL_F2 + +#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_WIDTH 4U +#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_93 +#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_93__TZQCKE_F2 + +#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_WIDTH 5U +#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_93 +#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_93__TCSCKE_F0 + +#define LPDDR4__DENALI_CTL_94_READ_MASK 0x1F011F01U +#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0x1F011F01U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_94 +#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0 + +#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_WIDTH 5U +#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_94 +#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F1 + +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_94 +#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1 + +#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_WIDTH 5U +#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_94 +#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F2 + +#define LPDDR4__DENALI_CTL_95_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_95 +#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2 + +#define LPDDR4__DENALI_CTL_95__TXSR_F0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_95__TXSR_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_95__TXSR_F0_WIDTH 16U +#define LPDDR4__TXSR_F0__REG DENALI_CTL_95 +#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_95__TXSR_F0 + +#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96__TXSNR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_96__TXSNR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_96__TXSNR_F0_WIDTH 16U +#define LPDDR4__TXSNR_F0__REG DENALI_CTL_96 +#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_96__TXSNR_F0 + +#define LPDDR4__DENALI_CTL_96__TXSR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_96__TXSR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_96__TXSR_F1_WIDTH 16U +#define LPDDR4__TXSR_F1__REG DENALI_CTL_96 +#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_96__TXSR_F1 + +#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97__TXSNR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_97__TXSNR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_97__TXSNR_F1_WIDTH 16U +#define LPDDR4__TXSNR_F1__REG DENALI_CTL_97 +#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_97__TXSNR_F1 + +#define LPDDR4__DENALI_CTL_97__TXSR_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_97__TXSR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_97__TXSR_F2_WIDTH 16U +#define LPDDR4__TXSR_F2__REG DENALI_CTL_97 +#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_97__TXSR_F2 + +#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98__TXSNR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_98__TXSNR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_98__TXSNR_F2_WIDTH 16U +#define LPDDR4__TXSNR_F2__REG DENALI_CTL_98 +#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_98__TXSNR_F2 + +#define LPDDR4__DENALI_CTL_98__TXPR_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_98__TXPR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_98__TXPR_F0_WIDTH 16U +#define LPDDR4__TXPR_F0__REG DENALI_CTL_98 +#define LPDDR4__TXPR_F0__FLD LPDDR4__DENALI_CTL_98__TXPR_F0 + +#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99__TXPR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_99__TXPR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_99__TXPR_F1_WIDTH 16U +#define LPDDR4__TXPR_F1__REG DENALI_CTL_99 +#define LPDDR4__TXPR_F1__FLD LPDDR4__DENALI_CTL_99__TXPR_F1 + +#define LPDDR4__DENALI_CTL_99__TXPR_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_99__TXPR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_99__TXPR_F2_WIDTH 16U +#define LPDDR4__TXPR_F2__REG DENALI_CTL_99 +#define LPDDR4__TXPR_F2__FLD LPDDR4__DENALI_CTL_99__TXPR_F2 + +#define LPDDR4__DENALI_CTL_100_READ_MASK 0x1F1F07FFU +#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0x1F1F07FFU +#define LPDDR4__DENALI_CTL_100__TSR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_100__TSR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_100__TSR_F0_WIDTH 8U +#define LPDDR4__TSR_F0__REG DENALI_CTL_100 +#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_100__TSR_F0 + +#define LPDDR4__DENALI_CTL_100__TESCKE_F0_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_100__TESCKE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_100__TESCKE_F0_WIDTH 3U +#define LPDDR4__TESCKE_F0__REG DENALI_CTL_100 +#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_100__TESCKE_F0 + +#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_WIDTH 5U +#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_100 +#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_100__TCSCKEH_F0 + +#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_WIDTH 5U +#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_100 +#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_100__TCKELCMD_F0 + +#define LPDDR4__DENALI_CTL_101_READ_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_WIDTH 5U +#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_101 +#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKEHCMD_F0 + +#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_WIDTH 5U +#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_101 +#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_101__TCKCKEL_F0 + +#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_WIDTH 5U +#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_101 +#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_101__TCKELPD_F0 + +#define LPDDR4__DENALI_CTL_101__TSR_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_101__TSR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_101__TSR_F1_WIDTH 8U +#define LPDDR4__TSR_F1__REG DENALI_CTL_101 +#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_101__TSR_F1 + +#define LPDDR4__DENALI_CTL_102_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_102__TESCKE_F1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_102__TESCKE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_102__TESCKE_F1_WIDTH 3U +#define LPDDR4__TESCKE_F1__REG DENALI_CTL_102 +#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_102__TESCKE_F1 + +#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_WIDTH 5U +#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_102 +#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_102__TCSCKEH_F1 + +#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_WIDTH 5U +#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_102 +#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKELCMD_F1 + +#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_WIDTH 5U +#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_102 +#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKEHCMD_F1 + +#define LPDDR4__DENALI_CTL_103_READ_MASK 0x07FF1F1FU +#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0x07FF1F1FU +#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_WIDTH 5U +#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_103 +#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_103__TCKCKEL_F1 + +#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_WIDTH 5U +#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_103 +#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELPD_F1 + +#define LPDDR4__DENALI_CTL_103__TSR_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_103__TSR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_103__TSR_F2_WIDTH 8U +#define LPDDR4__TSR_F2__REG DENALI_CTL_103 +#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_103__TSR_F2 + +#define LPDDR4__DENALI_CTL_103__TESCKE_F2_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_103__TESCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_103__TESCKE_F2_WIDTH 3U +#define LPDDR4__TESCKE_F2__REG DENALI_CTL_103 +#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_103__TESCKE_F2 + +#define LPDDR4__DENALI_CTL_104_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_WIDTH 5U +#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_104 +#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_104__TCSCKEH_F2 + +#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_WIDTH 5U +#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_104 +#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKELCMD_F2 + +#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_WIDTH 5U +#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_104 +#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKEHCMD_F2 + +#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_WIDTH 5U +#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_104 +#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_104__TCKCKEL_F2 + +#define LPDDR4__DENALI_CTL_105_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_WIDTH 5U +#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_105 +#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_105__TCKELPD_F2 + +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_WIDTH 5U +#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_105 +#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F0 + +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_WIDTH 5U +#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_105 +#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F1 + +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_WIDTH 5U +#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_105 +#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F2 + +#define LPDDR4__DENALI_CTL_106_READ_MASK 0x07010101U +#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0x07010101U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_106 +#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_SHIFT 8U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOSET 0U +#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__REG DENALI_CTL_106 +#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH + +#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_SHIFT 16U +#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOSET 0U +#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_106 +#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH + +#define LPDDR4__DENALI_CTL_106__CKE_DELAY_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_106__CKE_DELAY_SHIFT 24U +#define LPDDR4__DENALI_CTL_106__CKE_DELAY_WIDTH 3U +#define LPDDR4__CKE_DELAY__REG DENALI_CTL_106 +#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_106__CKE_DELAY + +#define LPDDR4__DENALI_CTL_107_READ_MASK 0x00017F00U +#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x00017F00U +#define LPDDR4__DENALI_CTL_107__DFS_CMD_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_107__DFS_CMD_SHIFT 0U +#define LPDDR4__DENALI_CTL_107__DFS_CMD_WIDTH 5U +#define LPDDR4__DFS_CMD__REG DENALI_CTL_107 +#define LPDDR4__DFS_CMD__FLD LPDDR4__DENALI_CTL_107__DFS_CMD + +#define LPDDR4__DENALI_CTL_107__DFS_STATUS_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_107__DFS_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_107__DFS_STATUS_WIDTH 7U +#define LPDDR4__DFS_STATUS__REG DENALI_CTL_107 +#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_107__DFS_STATUS + +#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOSET 0U +#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_107 +#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_107__DFS_ZQ_EN + +#define LPDDR4__DENALI_CTL_108_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_108 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_108 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_109_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_109 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_SHIFT 16U +#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_WIDTH 3U +#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_109 +#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG + +#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_SHIFT 24U +#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_WIDTH 3U +#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_109 +#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_109__MC_RESERVED3 + +#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFF07U +#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFF07U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_SHIFT 0U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_WIDTH 3U +#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_110 +#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED4 + +#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_SHIFT 8U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_WIDTH 8U +#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_110 +#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED5 + +#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_SHIFT 16U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_WIDTH 8U +#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_110 +#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED6 + +#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_SHIFT 24U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_WIDTH 8U +#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_110 +#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED7 + +#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_111 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_111 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_112 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_112 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_113 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_114_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_114 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_114 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_115_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_116 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_116 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_117 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_117 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_118_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_119 +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0 + +#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_120 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_121_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_121 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_122_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_122 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_123_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_123 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_124_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_124 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_125_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_125 +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0 + +#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_126 +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1 + +#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_127 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_128_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_128 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_129_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_129 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_130_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_130 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_131_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_131 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_132_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_132 +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1 + +#define LPDDR4__DENALI_CTL_133_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_133 +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2 + +#define LPDDR4__DENALI_CTL_134_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_134 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_135_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_135 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_136_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_136 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_137_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_137 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_138 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_139_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_139 +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2 + +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_SHIFT 24U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WIDTH 1U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOCLR 0U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOSET 0U +#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_139 +#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF + +#define LPDDR4__DENALI_CTL_140_READ_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_140 +#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_140 +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1 + +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_140 +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE + +#define LPDDR4__DENALI_CTL_141_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_141 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_142_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_142 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_143_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_143 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_144_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_144 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_145_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_145 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_146_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_146 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_147_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_147 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_148_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_148 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_149 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_SHIFT 24U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOSET 0U +#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_149 +#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_149__PPR_CONTROL + +#define LPDDR4__DENALI_CTL_150_READ_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_SHIFT 0U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_WIDTH 3U +#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_150 +#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND + +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_SHIFT 8U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_WIDTH 8U +#define LPDDR4__PPR_COMMAND_MRW_REGNUM__REG DENALI_CTL_150 +#define LPDDR4__PPR_COMMAND_MRW_REGNUM__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM + +#define LPDDR4__DENALI_CTL_151_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_SHIFT 0U +#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_WIDTH 17U +#define LPDDR4__PPR_COMMAND_MRW_DATA__REG DENALI_CTL_151 +#define LPDDR4__PPR_COMMAND_MRW_DATA__FLD LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA + +#define LPDDR4__DENALI_CTL_152_READ_MASK 0x0F01FFFFU +#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0x0F01FFFFU +#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_WIDTH 17U +#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_152 +#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS + +#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_SHIFT 24U +#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_WIDTH 4U +#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_152 +#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS + +#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WIDTH 1U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOCLR 0U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOSET 0U +#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_153 +#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS + +#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_WIDTH 32U +#define LPDDR4__PPR_DATA_0__REG DENALI_CTL_154 +#define LPDDR4__PPR_DATA_0__FLD LPDDR4__DENALI_CTL_154__PPR_DATA_0 + +#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_WIDTH 32U +#define LPDDR4__PPR_DATA_1__REG DENALI_CTL_155 +#define LPDDR4__PPR_DATA_1__FLD LPDDR4__DENALI_CTL_155__PPR_DATA_1 + +#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFF0103U +#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFF0103U +#define LPDDR4__DENALI_CTL_156__PPR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_156__PPR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_156__PPR_STATUS_WIDTH 2U +#define LPDDR4__PPR_STATUS__REG DENALI_CTL_156 +#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_156__PPR_STATUS + +#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_SHIFT 8U +#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOSET 0U +#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_156 +#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL + +#define LPDDR4__DENALI_CTL_156__CKSRE_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_156__CKSRE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_156__CKSRE_F0_WIDTH 8U +#define LPDDR4__CKSRE_F0__REG DENALI_CTL_156 +#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_156__CKSRE_F0 + +#define LPDDR4__DENALI_CTL_156__CKSRX_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_156__CKSRX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_156__CKSRX_F0_WIDTH 8U +#define LPDDR4__CKSRX_F0__REG DENALI_CTL_156 +#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_156__CKSRX_F0 + +#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157__CKSRE_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_157__CKSRE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_157__CKSRE_F1_WIDTH 8U +#define LPDDR4__CKSRE_F1__REG DENALI_CTL_157 +#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_157__CKSRE_F1 + +#define LPDDR4__DENALI_CTL_157__CKSRX_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_157__CKSRX_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_157__CKSRX_F1_WIDTH 8U +#define LPDDR4__CKSRX_F1__REG DENALI_CTL_157 +#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_157__CKSRX_F1 + +#define LPDDR4__DENALI_CTL_157__CKSRE_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_157__CKSRE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_157__CKSRE_F2_WIDTH 8U +#define LPDDR4__CKSRE_F2__REG DENALI_CTL_157 +#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_157__CKSRE_F2 + +#define LPDDR4__DENALI_CTL_157__CKSRX_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_157__CKSRX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_157__CKSRX_F2_WIDTH 8U +#define LPDDR4__CKSRX_F2__REG DENALI_CTL_157 +#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_157__CKSRX_F2 + +#define LPDDR4__DENALI_CTL_158_READ_MASK 0x0F0F0003U +#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x0F0F0003U +#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_WIDTH 2U +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_158 +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE + +#define LPDDR4__DENALI_CTL_158__LP_CMD_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_158__LP_CMD_SHIFT 8U +#define LPDDR4__DENALI_CTL_158__LP_CMD_WIDTH 7U +#define LPDDR4__LP_CMD__REG DENALI_CTL_158 +#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_158__LP_CMD + +#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_IDLE_WAKEUP_F0__REG DENALI_CTL_158 +#define LPDDR4__LPI_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_158 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_159_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_159 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_159 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_159 +#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_159 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_160_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_160 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_160 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_160 +#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_IDLE_WAKEUP_F1__REG DENALI_CTL_160 +#define LPDDR4__LPI_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_161_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_161 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_161 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_161 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_161 +#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_162_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_162 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_162 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_162 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_162 +#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_IDLE_WAKEUP_F2__REG DENALI_CTL_163 +#define LPDDR4__LPI_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_163 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_163 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_163 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_164_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_164 +#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_164 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_164 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_164 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_165_READ_MASK 0x00013F0FU +#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x00013F0FU +#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_165 +#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_WIDTH 6U +#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_165 +#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN + +#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOSET 0U +#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_165 +#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN + +#define LPDDR4__DENALI_CTL_166_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_WIDTH 12U +#define LPDDR4__LPI_TIMER_COUNT__REG DENALI_CTL_166 +#define LPDDR4__LPI_TIMER_COUNT__FLD LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT + +#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_SHIFT 16U +#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_WIDTH 12U +#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_166 +#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT + +#define LPDDR4__DENALI_CTL_167_READ_MASK 0x0F0F7F07U +#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x0F0F7F07U +#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_WIDTH 3U +#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_167 +#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_167__TDFI_LP_RESP + +#define LPDDR4__DENALI_CTL_167__LP_STATE_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_167__LP_STATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_167__LP_STATE_WIDTH 7U +#define LPDDR4__LP_STATE__REG DENALI_CTL_167 +#define LPDDR4__LP_STATE__FLD LPDDR4__DENALI_CTL_167__LP_STATE + +#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_167 +#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN + +#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_167 +#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN + +#define LPDDR4__DENALI_CTL_168_READ_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_WIDTH 3U +#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_168 +#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN + +#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_168 +#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE + +#define LPDDR4__DENALI_CTL_169_READ_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_169 +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE + +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_169 +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE + +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_169 +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE + +#define LPDDR4__DENALI_CTL_170_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_170 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_170 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_171 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_171 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_172 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_173_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_173 +#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN + +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_173 +#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN + +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_173 +#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN + +#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOSET 0U +#define LPDDR4__LPC_SR_EXIT_CMD_EN__REG DENALI_CTL_173 +#define LPDDR4__LPC_SR_EXIT_CMD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN + +#define LPDDR4__DENALI_CTL_174_READ_MASK 0x0101FF01U +#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0x0101FF01U +#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOSET 0U +#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_174 +#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN + +#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_SHIFT 8U +#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_WIDTH 9U +#define LPDDR4__PWRDN_SHIFT_DELAY__REG DENALI_CTL_174 +#define LPDDR4__PWRDN_SHIFT_DELAY__FLD LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY + +#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOSET 0U +#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_174 +#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_174__DFS_ENABLE + +#define LPDDR4__DENALI_CTL_175_READ_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_SHIFT 0U +#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_WIDTH 3U +#define LPDDR4__DFS_DLL_OFF__REG DENALI_CTL_175 +#define LPDDR4__DFS_DLL_OFF__FLD LPDDR4__DENALI_CTL_175__DFS_DLL_OFF + +#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOSET 0U +#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_175 +#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN + +#define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U +#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_176 +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR + +#define LPDDR4__DENALI_CTL_177_READ_MASK 0x03FFFF0FU +#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0x03FFFF0FU +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_WIDTH 4U +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_177 +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK + +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_177 +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT + +#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_SHIFT 24U +#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_WIDTH 2U +#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_177 +#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY + +#define LPDDR4__DENALI_CTL_178_READ_MASK 0x00000303U +#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0x00000303U +#define LPDDR4__DENALI_CTL_178__INIT_FREQ_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_178__INIT_FREQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_178__INIT_FREQ_WIDTH 2U +#define LPDDR4__INIT_FREQ__REG DENALI_CTL_178 +#define LPDDR4__INIT_FREQ__FLD LPDDR4__DENALI_CTL_178__INIT_FREQ + +#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_SHIFT 8U +#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_WIDTH 2U +#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_178 +#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ + +#define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_179 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0 + +#define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_180 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1 + +#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_181 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2 + +#define LPDDR4__DENALI_CTL_182_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_WIDTH 24U +#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_182 +#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_CTL_183_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_WIDTH 24U +#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_183 +#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_CTL_184_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_WIDTH 24U +#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_184 +#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_CTL_185_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_WIDTH 24U +#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_185 +#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_CTL_186_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_WIDTH 24U +#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_186 +#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_CTL_187_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_WIDTH 24U +#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_187 +#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_CTL_188_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_WIDTH 27U +#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_188 +#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_188__WRITE_MODEREG + +#define LPDDR4__DENALI_CTL_189_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_189__MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_189__MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_189__MRW_STATUS_WIDTH 8U +#define LPDDR4__MRW_STATUS__REG DENALI_CTL_189 +#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_189__MRW_STATUS + +#define LPDDR4__DENALI_CTL_189__READ_MODEREG_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_189__READ_MODEREG_SHIFT 8U +#define LPDDR4__DENALI_CTL_189__READ_MODEREG_WIDTH 17U +#define LPDDR4__READ_MODEREG__REG DENALI_CTL_189 +#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_189__READ_MODEREG + +#define LPDDR4__DENALI_CTL_190_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_SHIFT 0U +#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_WIDTH 24U +#define LPDDR4__PERIPHERAL_MRR_DATA__REG DENALI_CTL_190 +#define LPDDR4__PERIPHERAL_MRR_DATA__FLD LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA + +#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_WIDTH 8U +#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_190 +#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0 + +#define LPDDR4__DENALI_CTL_191_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_WIDTH 8U +#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_191 +#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1 + +#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_SHIFT 8U +#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WIDTH 1U +#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOCLR 0U +#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOSET 0U +#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_191 +#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG + +#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_SHIFT 16U +#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_WIDTH 2U +#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_191 +#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC + +#define LPDDR4__DENALI_CTL_192_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_192 +#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0 + +#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_192 +#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0 + +#define LPDDR4__DENALI_CTL_193_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_193__TFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_193__TFC_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_193__TFC_F0_WIDTH 10U +#define LPDDR4__TFC_F0__REG DENALI_CTL_193 +#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_193__TFC_F0 + +#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_WIDTH 5U +#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_193 +#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPE_F0 + +#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_WIDTH 5U +#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_193 +#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPX_F0 + +#define LPDDR4__DENALI_CTL_194_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_WIDTH 20U +#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_194 +#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_194__TVREF_LONG_F0 + +#define LPDDR4__DENALI_CTL_195_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_195 +#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1 + +#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_195 +#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1 + +#define LPDDR4__DENALI_CTL_196_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_196__TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_196__TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_196__TFC_F1_WIDTH 10U +#define LPDDR4__TFC_F1__REG DENALI_CTL_196 +#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_196__TFC_F1 + +#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_WIDTH 5U +#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_196 +#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPE_F1 + +#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_WIDTH 5U +#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_196 +#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPX_F1 + +#define LPDDR4__DENALI_CTL_197_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_WIDTH 20U +#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_197 +#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_197__TVREF_LONG_F1 + +#define LPDDR4__DENALI_CTL_198_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_198 +#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2 + +#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_198 +#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2 + +#define LPDDR4__DENALI_CTL_199_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_199__TFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_199__TFC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_199__TFC_F2_WIDTH 10U +#define LPDDR4__TFC_F2__REG DENALI_CTL_199 +#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_199__TFC_F2 + +#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_WIDTH 5U +#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_199 +#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPE_F2 + +#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_WIDTH 5U +#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_199 +#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPX_F2 + +#define LPDDR4__DENALI_CTL_200_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_WIDTH 20U +#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_200 +#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_200__TVREF_LONG_F2 + +#define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_201 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_201 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_202 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_202 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_203 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_203 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_204_READ_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_SHIFT 0U +#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WIDTH 1U +#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOCLR 0U +#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOSET 0U +#define LPDDR4__MR4_DLL_RST__REG DENALI_CTL_204 +#define LPDDR4__MR4_DLL_RST__FLD LPDDR4__DENALI_CTL_204__MR4_DLL_RST + +#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR0_DATA_F0_0__REG DENALI_CTL_204 +#define LPDDR4__MR0_DATA_F0_0__FLD LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_205_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_205 +#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_206_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_206 +#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_207_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR0_DATA_F1_0__REG DENALI_CTL_207 +#define LPDDR4__MR0_DATA_F1_0__FLD LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_208_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_208 +#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_209_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_209 +#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_210_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR0_DATA_F2_0__REG DENALI_CTL_210 +#define LPDDR4__MR0_DATA_F2_0__FLD LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_211 +#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_212_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_212 +#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_213_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR0_DATA_F0_1__REG DENALI_CTL_213 +#define LPDDR4__MR0_DATA_F0_1__FLD LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_214_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_214 +#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_215 +#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_216_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR0_DATA_F1_1__REG DENALI_CTL_216 +#define LPDDR4__MR0_DATA_F1_1__FLD LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_217_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_217 +#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_218_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_218 +#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_219_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR0_DATA_F2_1__REG DENALI_CTL_219 +#define LPDDR4__MR0_DATA_F2_1__FLD LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_220_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_220 +#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_221_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_221 +#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_222_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_WIDTH 17U +#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_222 +#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_CTL_223_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_WIDTH 17U +#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_223 +#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_CTL_224_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_224 +#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_225_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_225 +#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_226_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_226 +#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_227_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_227 +#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_228_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_228 +#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_229_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_229 +#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_230_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_230 +#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_231_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_231 +#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_232_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_232 +#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_233_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_233 +#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_234_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_234 +#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_235_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_235 +#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_236_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR5_DATA_F0_0__REG DENALI_CTL_236 +#define LPDDR4__MR5_DATA_F0_0__FLD LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_237_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR5_DATA_F1_0__REG DENALI_CTL_237 +#define LPDDR4__MR5_DATA_F1_0__FLD LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_238_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR5_DATA_F2_0__REG DENALI_CTL_238 +#define LPDDR4__MR5_DATA_F2_0__FLD LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_239_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR5_DATA_F0_1__REG DENALI_CTL_239 +#define LPDDR4__MR5_DATA_F0_1__FLD LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_240_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR5_DATA_F1_1__REG DENALI_CTL_240 +#define LPDDR4__MR5_DATA_F1_1__FLD LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_241_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR5_DATA_F2_1__REG DENALI_CTL_241 +#define LPDDR4__MR5_DATA_F2_1__FLD LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR6_DATA_F0_0__REG DENALI_CTL_242 +#define LPDDR4__MR6_DATA_F0_0__FLD LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_243_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR6_DATA_F1_0__REG DENALI_CTL_243 +#define LPDDR4__MR6_DATA_F1_0__FLD LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_244_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR6_DATA_F2_0__REG DENALI_CTL_244 +#define LPDDR4__MR6_DATA_F2_0__FLD LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_245_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR6_DATA_F0_1__REG DENALI_CTL_245 +#define LPDDR4__MR6_DATA_F0_1__FLD LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_246_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR6_DATA_F1_1__REG DENALI_CTL_246 +#define LPDDR4__MR6_DATA_F1_1__FLD LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_247_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR6_DATA_F2_1__REG DENALI_CTL_247 +#define LPDDR4__MR6_DATA_F2_1__FLD LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_WIDTH 8U +#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_247 +#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_247__MR8_DATA_0 + +#define LPDDR4__DENALI_CTL_248_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_WIDTH 8U +#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_248 +#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_248__MR8_DATA_1 + +#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR10_DATA_F0_0__REG DENALI_CTL_248 +#define LPDDR4__MR10_DATA_F0_0__FLD LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_249_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR10_DATA_F1_0__REG DENALI_CTL_249 +#define LPDDR4__MR10_DATA_F1_0__FLD LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_250_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR10_DATA_F2_0__REG DENALI_CTL_250 +#define LPDDR4__MR10_DATA_F2_0__FLD LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_251_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR10_DATA_F0_1__REG DENALI_CTL_251 +#define LPDDR4__MR10_DATA_F0_1__FLD LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_252_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR10_DATA_F1_1__REG DENALI_CTL_252 +#define LPDDR4__MR10_DATA_F1_1__FLD LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_253_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR10_DATA_F2_1__REG DENALI_CTL_253 +#define LPDDR4__MR10_DATA_F2_1__FLD LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_253 +#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_254 +#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_254 +#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_254 +#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_254 +#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_255_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_255 +#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_255 +#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_256_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_256 +#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_257_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_257 +#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_258_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_258 +#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_259_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_259 +#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_260 +#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_261_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_WIDTH 17U +#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_261 +#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_261__MR13_DATA_0 + +#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_WIDTH 17U +#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_262 +#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_262__MR13_DATA_1 + +#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_263 +#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_264 +#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_265 +#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_266_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_266 +#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_267_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_267 +#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_268_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_268 +#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_WIDTH 8U +#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_268 +#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_268__MR16_DATA_0 + +#define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_WIDTH 8U +#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_269 +#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR16_DATA_1 + +#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_WIDTH 8U +#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_269 +#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_0 + +#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_WIDTH 8U +#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_269 +#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_1 + +#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_WIDTH 8U +#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_269 +#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR20_DATA_0 + +#define LPDDR4__DENALI_CTL_270_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_WIDTH 8U +#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_270 +#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_270__MR20_DATA_1 + +#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_270 +#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_271_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_271 +#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_272_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_272 +#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_273_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_273 +#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_274_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_274 +#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_275_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_275 +#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_276_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_276__MR23_DATA_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_276__MR23_DATA_SHIFT 0U +#define LPDDR4__DENALI_CTL_276__MR23_DATA_WIDTH 17U +#define LPDDR4__MR23_DATA__REG DENALI_CTL_276 +#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_276__MR23_DATA + +#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_276 +#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0 + +#define LPDDR4__DENALI_CTL_277_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_277 +#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1 + +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_277 +#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2 + +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_SHIFT 16U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOSET 0U +#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__REG DENALI_CTL_277 +#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE + +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_SHIFT 24U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOSET 0U +#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__REG DENALI_CTL_277 +#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE + +#define LPDDR4__DENALI_CTL_278_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_SHIFT 0U +#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOSET 0U +#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_278 +#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW + +#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_SHIFT 8U +#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOSET 0U +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_278 +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP + +#define LPDDR4__DENALI_CTL_278__FSP_STATUS_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_278__FSP_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOSET 0U +#define LPDDR4__FSP_STATUS__REG DENALI_CTL_278 +#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_278__FSP_STATUS + +#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_SHIFT 24U +#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOSET 0U +#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_278 +#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT + +#define LPDDR4__DENALI_CTL_279_READ_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_SHIFT 0U +#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOSET 0U +#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_279 +#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT + +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_SHIFT 8U +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOSET 0U +#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_279 +#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID + +#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_SHIFT 16U +#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOSET 0U +#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_279 +#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID + +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_SHIFT 24U +#define LPDDR4__DENALI_CTL_279__FSP0_FRC_WIDTH 2U +#define LPDDR4__FSP0_FRC__REG DENALI_CTL_279 +#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC + +#define LPDDR4__DENALI_CTL_280_READ_MASK 0x3F030003U +#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x3F030003U +#define LPDDR4__DENALI_CTL_280__FSP1_FRC_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_280__FSP1_FRC_SHIFT 0U +#define LPDDR4__DENALI_CTL_280__FSP1_FRC_WIDTH 2U +#define LPDDR4__FSP1_FRC__REG DENALI_CTL_280 +#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_280__FSP1_FRC + +#define LPDDR4__DENALI_CTL_280__BIST_GO_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_280__BIST_GO_SHIFT 8U +#define LPDDR4__DENALI_CTL_280__BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_CTL_280__BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_CTL_280__BIST_GO_WOSET 0U +#define LPDDR4__BIST_GO__REG DENALI_CTL_280 +#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_280__BIST_GO + +#define LPDDR4__DENALI_CTL_280__BIST_RESULT_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_280__BIST_RESULT_SHIFT 16U +#define LPDDR4__DENALI_CTL_280__BIST_RESULT_WIDTH 2U +#define LPDDR4__BIST_RESULT__REG DENALI_CTL_280 +#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_280__BIST_RESULT + +#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_SHIFT 24U +#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_WIDTH 6U +#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_280 +#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_280__ADDR_SPACE + +#define LPDDR4__DENALI_CTL_281_READ_MASK 0x00000101U +#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_SHIFT 0U +#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_281 +#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK + +#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_SHIFT 8U +#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_281 +#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK + +#define LPDDR4__DENALI_CTL_282_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_282 +#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_CTL_283_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOSET 0U +#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_283 +#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_CTL_284_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_WIDTH 32U +#define LPDDR4__BIST_DATA_MASK__REG DENALI_CTL_284 +#define LPDDR4__BIST_DATA_MASK__FLD LPDDR4__DENALI_CTL_284__BIST_DATA_MASK + +#define LPDDR4__DENALI_CTL_285_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_WIDTH 3U +#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_285 +#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_285__BIST_TEST_MODE + +#define LPDDR4__DENALI_CTL_286_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_286 +#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0 + +#define LPDDR4__DENALI_CTL_287_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_287 +#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1 + +#define LPDDR4__DENALI_CTL_288_READ_MASK 0x000FFF01U +#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x000FFF01U +#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_SHIFT 0U +#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOSET 0U +#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_288 +#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_288__BIST_RET_STATE + +#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_SHIFT 8U +#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_288 +#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_288__BIST_ERR_STOP + +#define LPDDR4__DENALI_CTL_289_READ_MASK 0x1F000FFFU +#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x1F000FFFU +#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_289 +#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT + +#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOSET 0U +#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_289 +#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT + +#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_SHIFT 24U +#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_289 +#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK + +#define LPDDR4__DENALI_CTL_290_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_290 +#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_290 +#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_WIDTH 5U +#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_290 +#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT + +#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_WIDTH 5U +#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_290 +#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT + +#define LPDDR4__DENALI_CTL_291_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_WIDTH 4U +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_291 +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI + +#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_WIDTH 3U +#define LPDDR4__ZQCS_OPT_THRESHOLD__REG DENALI_CTL_291 +#define LPDDR4__ZQCS_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD + +#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_291 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_292_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_292 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_292 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_293 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_293 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_294_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_294 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_294 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_295_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_295_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_295 +#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_295 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_296_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_296_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_296 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_296 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_297 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_297 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_298_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_298 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_298 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_299 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_299 +#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_300_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_300 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_300 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_301_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_301 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_301 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_302 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_302 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_303 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_303 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_304 +#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_304 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_305_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_SHIFT 0U +#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_WIDTH 8U +#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_305 +#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG + +#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_WIDTH 12U +#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_305 +#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_305__ZQINIT_F0 + +#define LPDDR4__DENALI_CTL_306_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_306__ZQCL_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_306__ZQCL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_306__ZQCL_F0_WIDTH 12U +#define LPDDR4__ZQCL_F0__REG DENALI_CTL_306 +#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_306__ZQCL_F0 + +#define LPDDR4__DENALI_CTL_306__ZQCS_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_306__ZQCS_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_306__ZQCS_F0_WIDTH 12U +#define LPDDR4__ZQCS_F0__REG DENALI_CTL_306 +#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_306__ZQCS_F0 + +#define LPDDR4__DENALI_CTL_307_READ_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_WIDTH 12U +#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_307 +#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_307__TZQCAL_F0 + +#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_WIDTH 7U +#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_307 +#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_307__TZQLAT_F0 + +#define LPDDR4__DENALI_CTL_308_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_WIDTH 12U +#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_308 +#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_308__ZQINIT_F1 + +#define LPDDR4__DENALI_CTL_308__ZQCL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_308__ZQCL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_308__ZQCL_F1_WIDTH 12U +#define LPDDR4__ZQCL_F1__REG DENALI_CTL_308 +#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_308__ZQCL_F1 + +#define LPDDR4__DENALI_CTL_309_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_309__ZQCS_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_309__ZQCS_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_309__ZQCS_F1_WIDTH 12U +#define LPDDR4__ZQCS_F1__REG DENALI_CTL_309 +#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_309__ZQCS_F1 + +#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_WIDTH 12U +#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_309 +#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_309__TZQCAL_F1 + +#define LPDDR4__DENALI_CTL_310_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_WIDTH 7U +#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_310 +#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_310__TZQLAT_F1 + +#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_WIDTH 12U +#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_310 +#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_310__ZQINIT_F2 + +#define LPDDR4__DENALI_CTL_311_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_311__ZQCL_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_311__ZQCL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_311__ZQCL_F2_WIDTH 12U +#define LPDDR4__ZQCL_F2__REG DENALI_CTL_311 +#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_311__ZQCL_F2 + +#define LPDDR4__DENALI_CTL_311__ZQCS_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_311__ZQCS_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_311__ZQCS_F2_WIDTH 12U +#define LPDDR4__ZQCS_F2__REG DENALI_CTL_311 +#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_311__ZQCS_F2 + +#define LPDDR4__DENALI_CTL_312_READ_MASK 0x037F0FFFU +#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0x037F0FFFU +#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_WIDTH 12U +#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_312 +#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_312__TZQCAL_F2 + +#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_WIDTH 7U +#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_312 +#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_312__TZQLAT_F2 + +#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 24U +#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_312 +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP + +#define LPDDR4__DENALI_CTL_313_READ_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_WIDTH 4U +#define LPDDR4__ZQ_REQ__REG DENALI_CTL_313 +#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ + +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_SHIFT 8U +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_313 +#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING + +#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_WIDTH 12U +#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_313 +#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_313__ZQRESET_F0 + +#define LPDDR4__DENALI_CTL_314_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_WIDTH 12U +#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_314 +#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F1 + +#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_WIDTH 12U +#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_314 +#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F2 + +#define LPDDR4__DENALI_CTL_315_READ_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOSET 0U +#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_315 +#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_315__NO_ZQ_INIT + +#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOSET 0U +#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_315 +#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_315__ZQCS_ROTATE + +#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_315 +#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_315 +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_CTL_316_READ_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_316 +#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_316 +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_WIDTH 2U +#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_316 +#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_0 + +#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_WIDTH 2U +#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_316 +#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_1 + +#define LPDDR4__DENALI_CTL_317_READ_MASK 0x0F0F0707U +#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x0F0F0707U +#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_WIDTH 3U +#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_317 +#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_0 + +#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_WIDTH 3U +#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_317 +#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_1 + +#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_WIDTH 4U +#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_317 +#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_0 + +#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_WIDTH 4U +#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_317 +#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_1 + +#define LPDDR4__DENALI_CTL_318_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_318 +#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0 + +#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_318 +#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0 + +#define LPDDR4__DENALI_CTL_319_READ_MASK 0x00FFFF03U +#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x00FFFF03U +#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_WIDTH 2U +#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_319 +#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_319__ROW_START_VAL_0 + +#define LPDDR4__DENALI_CTL_319__CS_MSK_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_319__CS_MSK_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_319__CS_MSK_0_WIDTH 16U +#define LPDDR4__CS_MSK_0__REG DENALI_CTL_319 +#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_319__CS_MSK_0 + +#define LPDDR4__DENALI_CTL_320_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_320 +#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1 + +#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_320 +#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1 + +#define LPDDR4__DENALI_CTL_321_READ_MASK 0x03FFFF03U +#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x03FFFF03U +#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_WIDTH 2U +#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_321 +#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_321__ROW_START_VAL_1 + +#define LPDDR4__DENALI_CTL_321__CS_MSK_1_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_321__CS_MSK_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_321__CS_MSK_1_WIDTH 16U +#define LPDDR4__CS_MSK_1__REG DENALI_CTL_321 +#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_321__CS_MSK_1 + +#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_SHIFT 24U +#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_WIDTH 2U +#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_321 +#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2 + +#define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F011F01U +#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F011F01U +#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOSET 0U +#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_322 +#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN + +#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_SHIFT 8U +#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_WIDTH 5U +#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_322 +#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED8 + +#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_SHIFT 16U +#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WIDTH 1U +#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOCLR 0U +#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOSET 0U +#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_322 +#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED9 + +#define LPDDR4__DENALI_CTL_322__APREBIT_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_322__APREBIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_322__APREBIT_WIDTH 5U +#define LPDDR4__APREBIT__REG DENALI_CTL_322 +#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_322__APREBIT + +#define LPDDR4__DENALI_CTL_323_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_323__AGE_COUNT_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_323__AGE_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_323__AGE_COUNT_WIDTH 8U +#define LPDDR4__AGE_COUNT__REG DENALI_CTL_323 +#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__AGE_COUNT + +#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_SHIFT 8U +#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_WIDTH 8U +#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_323 +#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT + +#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOSET 0U +#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_323 +#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_323__ADDR_CMP_EN + +#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_SHIFT 24U +#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WIDTH 1U +#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOCLR 0U +#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOSET 0U +#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_323 +#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS + +#define LPDDR4__DENALI_CTL_324_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOSET 0U +#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_324 +#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN + +#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOSET 0U +#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_324 +#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_324__PLACEMENT_EN + +#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOSET 0U +#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_324 +#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_324__PRIORITY_EN + +#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOSET 0U +#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_324 +#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_324__RW_SAME_EN + +#define LPDDR4__DENALI_CTL_325_READ_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOSET 0U +#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_325 +#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN + +#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOSET 0U +#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_325 +#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_325__CS_SAME_EN + +#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOSET 0U +#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_325 +#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN + +#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 24U +#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_325 +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT + +#define LPDDR4__DENALI_CTL_326_READ_MASK 0x0301011FU +#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x0301011FU +#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_326 +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE + +#define LPDDR4__DENALI_CTL_326__SWAP_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_326__SWAP_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_326__SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOSET 0U +#define LPDDR4__SWAP_EN__REG DENALI_CTL_326 +#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_326__SWAP_EN + +#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_SHIFT 16U +#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOSET 0U +#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_326 +#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE + +#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_SHIFT 24U +#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_WIDTH 2U +#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_326 +#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD + +#define LPDDR4__DENALI_CTL_327_READ_MASK 0x07010F03U +#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x07010F03U +#define LPDDR4__DENALI_CTL_327__CS_MAP_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_327__CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_CTL_327__CS_MAP_WIDTH 2U +#define LPDDR4__CS_MAP__REG DENALI_CTL_327 +#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_327__CS_MAP + +#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_WIDTH 4U +#define LPDDR4__BURST_ON_FLY_BIT__REG DENALI_CTL_327 +#define LPDDR4__BURST_ON_FLY_BIT__FLD LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT + +#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_SHIFT 16U +#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOSET 0U +#define LPDDR4__MEM_DP_REDUCTION__REG DENALI_CTL_327 +#define LPDDR4__MEM_DP_REDUCTION__FLD LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION + +#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_327 +#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0 + +#define LPDDR4__DENALI_CTL_328_READ_MASK 0x03030307U +#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x03030307U +#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_328 +#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1 + +#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_SHIFT 8U +#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_WIDTH 2U +#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_328 +#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_WIDTH 2U +#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_328 +#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_SHIFT 24U +#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_WIDTH 2U +#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_328 +#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_329_READ_MASK 0x03011F03U +#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x03011F03U +#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_WIDTH 2U +#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_329 +#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_SHIFT 8U +#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_WIDTH 5U +#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_329 +#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_329__Q_FULLNESS + +#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_SHIFT 16U +#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WIDTH 1U +#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOCLR 0U +#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOSET 0U +#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_329 +#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT + +#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_SHIFT 24U +#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_WIDTH 2U +#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_329 +#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_329__WR_ORDER_REQ + +#define LPDDR4__DENALI_CTL_330_READ_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_SHIFT 0U +#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOSET 0U +#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_330 +#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY + +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_SHIFT 8U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOSET 0U +#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_330 +#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ + +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_330 +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOSET 0U +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_330 +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE + +#define LPDDR4__DENALI_CTL_331_READ_MASK 0x01030303U +#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x01030303U +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_331 +#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0 + +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_331 +#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1 + +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_331 +#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2 + +#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_331 +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_CTL_332_READ_MASK 0x00070101U +#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0x00070101U +#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOSET 0U +#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_332 +#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_332__WR_DBI_EN + +#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOSET 0U +#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_332 +#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_332__RD_DBI_EN + +#define LPDDR4__DENALI_CTL_332__DFI_ERROR_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_332__DFI_ERROR_SHIFT 16U +#define LPDDR4__DENALI_CTL_332__DFI_ERROR_WIDTH 3U +#define LPDDR4__DFI_ERROR__REG DENALI_CTL_332 +#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_332__DFI_ERROR + +#define LPDDR4__DENALI_CTL_333_READ_MASK 0x00010FFFU +#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0x00010FFFU +#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_WIDTH 12U +#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_333 +#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO + +#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOSET 0U +#define LPDDR4__BG_ROTATE_EN__REG DENALI_CTL_333 +#define LPDDR4__BG_ROTATE_EN__FLD LPDDR4__DENALI_CTL_333__BG_ROTATE_EN + +#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_SHIFT 24U +#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WIDTH 1U +#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOCLR 0U +#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOSET 0U +#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_333 +#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_333__MC_RESERVED10 + +#define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_SHIFT 0U +#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_WIDTH 32U +#define LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL_334 +#define LPDDR4__INT_STATUS_MASTER__FLD LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER + +#define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_SHIFT 0U +#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_WIDTH 32U +#define LPDDR4__INT_MASK_MASTER__REG DENALI_CTL_335 +#define LPDDR4__INT_MASK_MASTER__FLD LPDDR4__DENALI_CTL_335__INT_MASK_MASTER + +#define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_WIDTH 32U +#define LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL_336 +#define LPDDR4__INT_STATUS_TIMEOUT__FLD LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT + +#define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_SHIFT 0U +#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_WIDTH 16U +#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_337 +#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_337__MC_RESERVED11 + +#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_SHIFT 16U +#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_WIDTH 16U +#define LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL_337 +#define LPDDR4__INT_STATUS_LOWPOWER__FLD LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER + +#define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_SHIFT 0U +#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_WIDTH 16U +#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_338 +#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED12 + +#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_SHIFT 16U +#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_WIDTH 16U +#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_338 +#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED13 + +#define LPDDR4__DENALI_CTL_339_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_SHIFT 0U +#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_WIDTH 32U +#define LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL_339 +#define LPDDR4__INT_STATUS_TRAINING__FLD LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING + +#define LPDDR4__DENALI_CTL_340_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_SHIFT 0U +#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_WIDTH 32U +#define LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL_340 +#define LPDDR4__INT_STATUS_USERIF__FLD LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF + +#define LPDDR4__DENALI_CTL_341_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_341_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_SHIFT 0U +#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_WIDTH 16U +#define LPDDR4__INT_STATUS_MISC__REG DENALI_CTL_341 +#define LPDDR4__INT_STATUS_MISC__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_MISC + +#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_SHIFT 16U +#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_WIDTH 8U +#define LPDDR4__INT_STATUS_BIST__REG DENALI_CTL_341 +#define LPDDR4__INT_STATUS_BIST__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_BIST + +#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_SHIFT 24U +#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_WIDTH 8U +#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_341 +#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_341__MC_RESERVED14 + +#define LPDDR4__DENALI_CTL_342_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_WIDTH 8U +#define LPDDR4__INT_STATUS_DFI__REG DENALI_CTL_342 +#define LPDDR4__INT_STATUS_DFI__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_DFI + +#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_SHIFT 8U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_WIDTH 8U +#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_342 +#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED15 + +#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_WIDTH 8U +#define LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL_342 +#define LPDDR4__INT_STATUS_FREQ__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ + +#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_WIDTH 8U +#define LPDDR4__INT_STATUS_INIT__REG DENALI_CTL_342 +#define LPDDR4__INT_STATUS_INIT__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_INIT + +#define LPDDR4__DENALI_CTL_343_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_WIDTH 8U +#define LPDDR4__INT_STATUS_MODE__REG DENALI_CTL_343 +#define LPDDR4__INT_STATUS_MODE__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_MODE + +#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_WIDTH 8U +#define LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL_343 +#define LPDDR4__INT_STATUS_PARITY__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY + +#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_WIDTH 32U +#define LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL_344 +#define LPDDR4__INT_ACK_TIMEOUT__FLD LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT + +#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_SHIFT 0U +#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_WIDTH 16U +#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_345 +#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_345__MC_RESERVED16 + +#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_SHIFT 16U +#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_WIDTH 16U +#define LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL_345 +#define LPDDR4__INT_ACK_LOWPOWER__FLD LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER + +#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_SHIFT 0U +#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_WIDTH 16U +#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_346 +#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED17 + +#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_SHIFT 16U +#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_WIDTH 16U +#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_346 +#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED18 + +#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_SHIFT 0U +#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_WIDTH 32U +#define LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL_347 +#define LPDDR4__INT_ACK_TRAINING__FLD LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING + +#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_SHIFT 0U +#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_WIDTH 32U +#define LPDDR4__INT_ACK_USERIF__REG DENALI_CTL_348 +#define LPDDR4__INT_ACK_USERIF__FLD LPDDR4__DENALI_CTL_348__INT_ACK_USERIF + +#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_SHIFT 0U +#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_WIDTH 16U +#define LPDDR4__INT_ACK_MISC__REG DENALI_CTL_349 +#define LPDDR4__INT_ACK_MISC__FLD LPDDR4__DENALI_CTL_349__INT_ACK_MISC + +#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_SHIFT 16U +#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_WIDTH 8U +#define LPDDR4__INT_ACK_BIST__REG DENALI_CTL_349 +#define LPDDR4__INT_ACK_BIST__FLD LPDDR4__DENALI_CTL_349__INT_ACK_BIST + +#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_SHIFT 24U +#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_WIDTH 8U +#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_349 +#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_349__MC_RESERVED19 + +#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_WIDTH 8U +#define LPDDR4__INT_ACK_DFI__REG DENALI_CTL_350 +#define LPDDR4__INT_ACK_DFI__FLD LPDDR4__DENALI_CTL_350__INT_ACK_DFI + +#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_SHIFT 8U +#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_WIDTH 8U +#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_350 +#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_350__MC_RESERVED20 + +#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_WIDTH 8U +#define LPDDR4__INT_ACK_FREQ__REG DENALI_CTL_350 +#define LPDDR4__INT_ACK_FREQ__FLD LPDDR4__DENALI_CTL_350__INT_ACK_FREQ + +#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_WIDTH 8U +#define LPDDR4__INT_ACK_INIT__REG DENALI_CTL_350 +#define LPDDR4__INT_ACK_INIT__FLD LPDDR4__DENALI_CTL_350__INT_ACK_INIT + +#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_WIDTH 8U +#define LPDDR4__INT_ACK_MODE__REG DENALI_CTL_351 +#define LPDDR4__INT_ACK_MODE__FLD LPDDR4__DENALI_CTL_351__INT_ACK_MODE + +#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_WIDTH 8U +#define LPDDR4__INT_ACK_PARITY__REG DENALI_CTL_351 +#define LPDDR4__INT_ACK_PARITY__FLD LPDDR4__DENALI_CTL_351__INT_ACK_PARITY + +#define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_WIDTH 32U +#define LPDDR4__INT_MASK_TIMEOUT__REG DENALI_CTL_352 +#define LPDDR4__INT_MASK_TIMEOUT__FLD LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT + +#define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_SHIFT 0U +#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_WIDTH 16U +#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_353 +#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_353__MC_RESERVED21 + +#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_SHIFT 16U +#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_WIDTH 16U +#define LPDDR4__INT_MASK_LOWPOWER__REG DENALI_CTL_353 +#define LPDDR4__INT_MASK_LOWPOWER__FLD LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER + +#define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_SHIFT 0U +#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_WIDTH 16U +#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_354 +#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED22 + +#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_SHIFT 16U +#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_WIDTH 16U +#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_354 +#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED23 + +#define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_SHIFT 0U +#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_WIDTH 32U +#define LPDDR4__INT_MASK_TRAINING__REG DENALI_CTL_355 +#define LPDDR4__INT_MASK_TRAINING__FLD LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING + +#define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_SHIFT 0U +#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_WIDTH 32U +#define LPDDR4__INT_MASK_USERIF__REG DENALI_CTL_356 +#define LPDDR4__INT_MASK_USERIF__FLD LPDDR4__DENALI_CTL_356__INT_MASK_USERIF + +#define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_SHIFT 0U +#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_WIDTH 16U +#define LPDDR4__INT_MASK_MISC__REG DENALI_CTL_357 +#define LPDDR4__INT_MASK_MISC__FLD LPDDR4__DENALI_CTL_357__INT_MASK_MISC + +#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_SHIFT 16U +#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_WIDTH 8U +#define LPDDR4__INT_MASK_BIST__REG DENALI_CTL_357 +#define LPDDR4__INT_MASK_BIST__FLD LPDDR4__DENALI_CTL_357__INT_MASK_BIST + +#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_SHIFT 24U +#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_WIDTH 8U +#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_357 +#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_357__MC_RESERVED24 + +#define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_WIDTH 8U +#define LPDDR4__INT_MASK_DFI__REG DENALI_CTL_358 +#define LPDDR4__INT_MASK_DFI__FLD LPDDR4__DENALI_CTL_358__INT_MASK_DFI + +#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_SHIFT 8U +#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_WIDTH 8U +#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_358 +#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_358__MC_RESERVED25 + +#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_WIDTH 8U +#define LPDDR4__INT_MASK_FREQ__REG DENALI_CTL_358 +#define LPDDR4__INT_MASK_FREQ__FLD LPDDR4__DENALI_CTL_358__INT_MASK_FREQ + +#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_WIDTH 8U +#define LPDDR4__INT_MASK_INIT__REG DENALI_CTL_358 +#define LPDDR4__INT_MASK_INIT__FLD LPDDR4__DENALI_CTL_358__INT_MASK_INIT + +#define LPDDR4__DENALI_CTL_359_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_WIDTH 8U +#define LPDDR4__INT_MASK_MODE__REG DENALI_CTL_359 +#define LPDDR4__INT_MASK_MODE__FLD LPDDR4__DENALI_CTL_359__INT_MASK_MODE + +#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_WIDTH 8U +#define LPDDR4__INT_MASK_PARITY__REG DENALI_CTL_359 +#define LPDDR4__INT_MASK_PARITY__FLD LPDDR4__DENALI_CTL_359__INT_MASK_PARITY + +#define LPDDR4__DENALI_CTL_360_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_WIDTH 32U +#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_360 +#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0 + +#define LPDDR4__DENALI_CTL_361_READ_MASK 0x7F07FF01U +#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x7F07FF01U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WIDTH 1U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOCLR 0U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOSET 0U +#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_361 +#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1 + +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_MASK 0x0007FF00U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_WIDTH 11U +#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_361 +#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH + +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_SHIFT 24U +#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_WIDTH 7U +#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_361 +#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE + +#define LPDDR4__DENALI_CTL_362_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U +#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_362 +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID + +#define LPDDR4__DENALI_CTL_363_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_363 +#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_CTL_364_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_364 +#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_CTL_365_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_365 +#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_CTL_366_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_366 +#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_CTL_367_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_367 +#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_CTL_368_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WIDTH 1U +#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOCLR 0U +#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOSET 0U +#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_368 +#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_CTL_369_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_WIDTH 32U +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_369 +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0 + +#define LPDDR4__DENALI_CTL_370_READ_MASK 0xFF033F01U +#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFF033F01U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WIDTH 1U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOCLR 0U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOSET 0U +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_370 +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1 + +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_WIDTH 6U +#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_370 +#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID + +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_SHIFT 16U +#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_WIDTH 2U +#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_370 +#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE + +#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_370 +#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0 + +#define LPDDR4__DENALI_CTL_371_READ_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_WIDTH 4U +#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_371 +#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F0 + +#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_WIDTH 4U +#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_371 +#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_RD_F0 + +#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_371 +#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1 + +#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_WIDTH 4U +#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_371 +#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F1 + +#define LPDDR4__DENALI_CTL_372_READ_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_WIDTH 4U +#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_372 +#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F1 + +#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_372 +#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2 + +#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_WIDTH 4U +#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_372 +#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_WR_F2 + +#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_WIDTH 4U +#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_372 +#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F2 + +#define LPDDR4__DENALI_CTL_373_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOSET 0U +#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_373 +#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F0 + +#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOSET 0U +#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_373 +#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F1 + +#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOSET 0U +#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_373 +#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F2 + +#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U +#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U +#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U +#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_373 +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD + +#define LPDDR4__DENALI_CTL_374_READ_MASK 0x033F3F3FU +#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0x033F3F3FU +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_374 +#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_374 +#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_374 +#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_SHIFT 24U +#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_374 +#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0 + +#define LPDDR4__DENALI_CTL_375_READ_MASK 0x3F030303U +#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0x3F030303U +#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_375 +#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0 + +#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_375 +#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1 + +#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_375 +#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1 + +#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_375 +#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_376_READ_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_376 +#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_376 +#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_376 +#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0 + +#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_376 +#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1 + +#define LPDDR4__DENALI_CTL_377_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_377 +#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2 + +#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_377 +#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_377 +#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_377 +#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_378_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_378 +#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_378 +#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_378 +#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_378 +#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_379_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_379 +#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_379 +#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_379 +#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_379 +#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_380_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_380 +#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_380 +#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0 + +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_380 +#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1 + +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_380 +#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2 + +#define LPDDR4__DENALI_CTL_381_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_SHIFT 0U +#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_381 +#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_SHIFT 8U +#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_381 +#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_SHIFT 16U +#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_381 +#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_381 +#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_CTL_382_READ_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_382 +#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0 + +#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_382 +#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_382 +#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1 + +#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_382 +#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_CTL_383_READ_MASK 0x07010107U +#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0x07010107U +#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_383 +#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2 + +#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_383 +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE + +#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_383 +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE + +#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_SHIFT 24U +#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_383 +#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY + +#define LPDDR4__DENALI_CTL_384_READ_MASK 0xFF010307U +#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFF010307U +#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_SHIFT 0U +#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_384 +#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY + +#define LPDDR4__DENALI_CTL_384__CKE_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_384__CKE_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_384__CKE_STATUS_WIDTH 2U +#define LPDDR4__CKE_STATUS__REG DENALI_CTL_384 +#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_384__CKE_STATUS + +#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_SHIFT 16U +#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOSET 0U +#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_384 +#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_384__MEM_RST_VALID + +#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_384 +#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0 + +#define LPDDR4__DENALI_CTL_385_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_385 +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_CTL_386_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_386 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_387_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_387 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_388_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_388 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_389_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_389 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_390_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_390 +#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0 + +#define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_391 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_392 +#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_392 +#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_392 +#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0 + +#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_WIDTH 8U +#define LPDDR4__TDFI_RDDATA_EN_F0__REG DENALI_CTL_392 +#define LPDDR4__TDFI_RDDATA_EN_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0 + +#define LPDDR4__DENALI_CTL_393_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_393 +#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0 + +#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_PHY_WRLAT_F0__REG DENALI_CTL_393 +#define LPDDR4__TDFI_PHY_WRLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0 + +#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_393 +#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1 + +#define LPDDR4__DENALI_CTL_394_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_394 +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_395 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_396_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_396 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_397_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_397 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_398 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_399_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_399 +#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1 + +#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_400 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_401 +#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_401 +#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_401 +#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1 + +#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_WIDTH 8U +#define LPDDR4__TDFI_RDDATA_EN_F1__REG DENALI_CTL_401 +#define LPDDR4__TDFI_RDDATA_EN_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1 + +#define LPDDR4__DENALI_CTL_402_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_402 +#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1 + +#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_PHY_WRLAT_F1__REG DENALI_CTL_402 +#define LPDDR4__TDFI_PHY_WRLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1 + +#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_402 +#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2 + +#define LPDDR4__DENALI_CTL_403_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_403 +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_CTL_404_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_404 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_405_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_405 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_406 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_407 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_408_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_408 +#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2 + +#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_409 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_CTL_410_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_410 +#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_410 +#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_410 +#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2 + +#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_WIDTH 8U +#define LPDDR4__TDFI_RDDATA_EN_F2__REG DENALI_CTL_410 +#define LPDDR4__TDFI_RDDATA_EN_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2 + +#define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_411 +#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2 + +#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_PHY_WRLAT_F2__REG DENALI_CTL_411 +#define LPDDR4__TDFI_PHY_WRLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2 + +#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_SHIFT 16U +#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_411 +#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_411__DLL_RST_DELAY + +#define LPDDR4__DENALI_CTL_412_READ_MASK 0x00037FFFU +#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x00037FFFU +#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_SHIFT 0U +#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_412 +#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_WIDTH 7U +#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_412 +#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_WIDTH 2U +#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_412 +#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_413_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_SHIFT 0U +#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_WIDTH 16U +#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_413 +#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413 +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413 +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE + +#define LPDDR4__DENALI_CTL_414_READ_MASK 0x0701FF07U +#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x0701FF07U +#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_SHIFT 0U +#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_WIDTH 3U +#define LPDDR4__TDFI_PARIN_LAT__REG DENALI_CTL_414 +#define LPDDR4__TDFI_PARIN_LAT__FLD LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT + +#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_SHIFT 8U +#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_WIDTH 8U +#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_414 +#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY + +#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U +#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U +#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U +#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_414 +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE + +#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_SHIFT 24U +#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_WIDTH 3U +#define LPDDR4__STRATEGY_2TICK_COUNT__REG DENALI_CTL_414 +#define LPDDR4__STRATEGY_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT + +#define LPDDR4__DENALI_CTL_415_READ_MASK 0x07070707U +#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0x07070707U +#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_WIDTH 3U +#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__REG DENALI_CTL_415 +#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT + +#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_SHIFT 8U +#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_WIDTH 3U +#define LPDDR4__PRE_2TICK_COUNT__REG DENALI_CTL_415 +#define LPDDR4__PRE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT + +#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_SHIFT 16U +#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_WIDTH 3U +#define LPDDR4__STRATEGY_4TICK_COUNT__REG DENALI_CTL_415 +#define LPDDR4__STRATEGY_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT + +#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_SHIFT 24U +#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_WIDTH 3U +#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__REG DENALI_CTL_415 +#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT + +#define LPDDR4__DENALI_CTL_416_READ_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_WIDTH 3U +#define LPDDR4__PRE_4TICK_COUNT__REG DENALI_CTL_416 +#define LPDDR4__PRE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT + +#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__REG DENALI_CTL_416 +#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__REG DENALI_CTL_416 +#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__REG DENALI_CTL_416 +#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_417_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__REG DENALI_CTL_417 +#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__ODT_TICK_PLUS_ADJ__REG DENALI_CTL_417 +#define LPDDR4__ODT_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__ODT_TICK_MINUS_ADJ__REG DENALI_CTL_417 +#define LPDDR4__ODT_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TRAS_TICK_PLUS_ADJ__REG DENALI_CTL_417 +#define LPDDR4__TRAS_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_418_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TRAS_TICK_MINUS_ADJ__REG DENALI_CTL_418 +#define LPDDR4__TRAS_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TRP_TICK_PLUS_ADJ__REG DENALI_CTL_418 +#define LPDDR4__TRP_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TRP_TICK_MINUS_ADJ__REG DENALI_CTL_418 +#define LPDDR4__TRP_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TWR_TICK_PLUS_ADJ__REG DENALI_CTL_418 +#define LPDDR4__TWR_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_419_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TWR_TICK_MINUS_ADJ__REG DENALI_CTL_419 +#define LPDDR4__TWR_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__REG DENALI_CTL_419 +#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__REG DENALI_CTL_419 +#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TRFC_TICK_PLUS_ADJ__REG DENALI_CTL_419 +#define LPDDR4__TRFC_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_420_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TRFC_TICK_MINUS_ADJ__REG DENALI_CTL_420 +#define LPDDR4__TRFC_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__RL_TICK_PLUS_ADJ__REG DENALI_CTL_420 +#define LPDDR4__RL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__RL_TICK_MINUS_ADJ__REG DENALI_CTL_420 +#define LPDDR4__RL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__WL_TICK_PLUS_ADJ__REG DENALI_CTL_420 +#define LPDDR4__WL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_421_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__WL_TICK_MINUS_ADJ__REG DENALI_CTL_421 +#define LPDDR4__WL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_421__NWR_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_421__NWR_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_421__NWR_F0_WIDTH 8U +#define LPDDR4__NWR_F0__REG DENALI_CTL_421 +#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_421__NWR_F0 + +#define LPDDR4__DENALI_CTL_421__NWR_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_421__NWR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_421__NWR_F1_WIDTH 8U +#define LPDDR4__NWR_F1__REG DENALI_CTL_421 +#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_421__NWR_F1 + +#define LPDDR4__DENALI_CTL_421__NWR_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_421__NWR_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_421__NWR_F2_WIDTH 8U +#define LPDDR4__NWR_F2__REG DENALI_CTL_421 +#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_421__NWR_F2 + +#define LPDDR4__DENALI_CTL_422_READ_MASK 0x007F7F7FU +#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x007F7F7FU +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_WIDTH 7U +#define LPDDR4__TDFI_CTRLMSG_RESP_F0__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CTRLMSG_RESP_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0 + +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_WIDTH 7U +#define LPDDR4__TDFI_CTRLMSG_RESP_F1__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CTRLMSG_RESP_F1__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1 + +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_WIDTH 7U +#define LPDDR4__TDFI_CTRLMSG_RESP_F2__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CTRLMSG_RESP_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2 + +#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h new file mode 100644 index 000000000..dcfd7d9e8 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h @@ -0,0 +1,1838 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_ +#define REG_LPDDR4_PHY_CORE_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280 +#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1281_READ_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_SHIFT 8U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN + +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT 16U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX + +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281 +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_2__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP0_SHIFT_2__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_2__REG DENALI_PHY_1284 +#define LPDDR4__PHY_SW_GRP1_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_2__REG DENALI_PHY_1284 +#define LPDDR4__PHY_SW_GRP2_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_2__REG DENALI_PHY_1284 +#define LPDDR4__PHY_SW_GRP3_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_3__REG DENALI_PHY_1284 +#define LPDDR4__PHY_SW_GRP0_SHIFT_3__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_3__REG DENALI_PHY_1285 +#define LPDDR4__PHY_SW_GRP1_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_3__REG DENALI_PHY_1285 +#define LPDDR4__PHY_SW_GRP2_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_3__REG DENALI_PHY_1285 +#define LPDDR4__PHY_SW_GRP3_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1286 +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY + +#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1286 +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT + +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1286 +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE + +#define LPDDR4__DENALI_PHY_1287_READ_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1287_WRITE_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1287 +#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET 0U +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1287 +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE + +#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_WIDTH 11U +#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1287 +#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START + +#define LPDDR4__DENALI_PHY_1288_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1288 +#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY + +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOSET 0U +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1288 +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE + +#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1288 +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT + +#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1289 +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR + +#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1290 +#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0 + +#define LPDDR4__DENALI_PHY_1291_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1291 +#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1 + +#define LPDDR4__DENALI_PHY_1292_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1292 +#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2 + +#define LPDDR4__DENALI_PHY_1293_READ_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOSET 0U +#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE + +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT 8U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH 9U +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET + +#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1293 +#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE + +#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x0007FF03U +#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x0007FF03U +#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_WIDTH 2U +#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1294 +#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP + +#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_SHIFT 8U +#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_WIDTH 11U +#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1294 +#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR + +#define LPDDR4__DENALI_PHY_1295_READ_MASK 0x070F07FFU +#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0x070F07FFU +#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1295 +#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK + +#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1295 +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1295 +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE + +#define LPDDR4__DENALI_PHY_1296_READ_MASK 0x01010300U +#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0x01010300U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOSET 0U +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1296 +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS + +#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_WIDTH 2U +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1296 +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE + +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_SHIFT 16U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOSET 0U +#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1296 +#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR + +#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOSET 0U +#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1296 +#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE + +#define LPDDR4__DENALI_PHY_1297_READ_MASK 0x0F010001U +#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0x0F010001U +#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOSET 0U +#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1297 +#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS + +#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 8U +#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET 0U +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1297 +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES + +#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE + +#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1297 +#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_1298_READ_MASK 0x010F0F0FU +#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0x010F0F0FU +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298 +#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1 + +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_2__REG DENALI_PHY_1298 +#define LPDDR4__PHY_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2 + +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_3__REG DENALI_PHY_1298 +#define LPDDR4__PHY_SW_TXIO_CTRL_3__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3 + +#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 24U +#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1298 +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL + +#define LPDDR4__DENALI_PHY_1299_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2 + +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3 + +#define LPDDR4__DENALI_PHY_1300_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1300 +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL + +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1300 +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1300 +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_WIDTH 16U +#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1301 +#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL + +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1301 +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1301 +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1302_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1302 +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1303_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_WIDTH 32U +#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1303 +#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS + +#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_WIDTH 16U +#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1304 +#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT + +#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1305 +#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1306 +#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0 + +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1306 +#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1 + +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_2__REG DENALI_PHY_1306 +#define LPDDR4__PHY_SET_DFI_INPUT_2__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2 + +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_3__REG DENALI_PHY_1306 +#define LPDDR4__PHY_SET_DFI_INPUT_3__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3 + +#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0 + +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0 + +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0 + +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0 + +#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1308 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1 + +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1308 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1 + +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1308 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1 + +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1308 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1 + +#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__REG DENALI_PHY_1309 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2 + +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__REG DENALI_PHY_1309 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2 + +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__REG DENALI_PHY_1309 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2 + +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__REG DENALI_PHY_1309 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2 + +#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__REG DENALI_PHY_1310 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3 + +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__REG DENALI_PHY_1310 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3 + +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__REG DENALI_PHY_1310 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3 + +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_WIDTH 2U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__REG DENALI_PHY_1310 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3 + +#define LPDDR4__DENALI_PHY_1311_READ_MASK 0xFFFF1FFFU +#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0xFFFF1FFFU +#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1311 +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1311 +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE + +#define LPDDR4__DENALI_PHY_1312_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOSET 0U +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1312 +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK + +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_SHIFT 8U +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_WIDTH 8U +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1312 +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL + +#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1312 +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS + +#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1313 +#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0 + +#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1314 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0 + +#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_WIDTH 12U +#define LPDDR4__PHY_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315 +#define LPDDR4__PHY_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0 + +#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_WIDTH 12U +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315 +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0 + +#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1316 +#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1 + +#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1317 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1 + +#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_WIDTH 12U +#define LPDDR4__PHY_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318 +#define LPDDR4__PHY_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1 + +#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_WIDTH 12U +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318 +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1 + +#define LPDDR4__DENALI_PHY_1319_READ_MASK 0xFF0F0101U +#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0xFF0F0101U +#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOSET 0U +#define LPDDR4__PHY_PLL_REFOUT_SEL__REG DENALI_PHY_1319 +#define LPDDR4__PHY_PLL_REFOUT_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL + +#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT 8U +#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1319 +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_WIDTH 4U +#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1319 +#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT + +#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_WIDTH 8U +#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1319 +#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP + +#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x0003FF01U +#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x0003FF01U +#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOSET 0U +#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1320 +#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN + +#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 8U +#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1320 +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG + +#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_WIDTH 17U +#define LPDDR4__PHY_DS_EXIT_CTRL__REG DENALI_PHY_1321 +#define LPDDR4__PHY_DS_EXIT_CTRL__FLD LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL + +#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_SHIFT 24U +#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WIDTH 1U +#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOCLR 0U +#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOSET 0U +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1321 +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY + +#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1322 +#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM + +#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1323 +#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM + +#define LPDDR4__DENALI_PHY_1324_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1324 +#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM + +#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1325 +#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM + +#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1326 +#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM + +#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ERR_TERM__REG DENALI_PHY_1327 +#define LPDDR4__PHY_PAD_ERR_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM + +#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1328 +#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM + +#define LPDDR4__DENALI_PHY_1329_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1329_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1329 +#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM + +#define LPDDR4__DENALI_PHY_1330_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1330_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1330 +#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM + +#define LPDDR4__DENALI_PHY_1331_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1331_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1331 +#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM + +#define LPDDR4__DENALI_PHY_1332_READ_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1332_WRITE_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_WIDTH 10U +#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1332 +#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL + +#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U +#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1332 +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL + +#define LPDDR4__DENALI_PHY_1333_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1333_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_WIDTH 13U +#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1333 +#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0 + +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOSET 0U +#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1333 +#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1333 +#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0 + +#define LPDDR4__DENALI_PHY_1334_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1334_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1334 +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0 + +#define LPDDR4__DENALI_PHY_1335_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1335_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1335 +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1335 +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1336_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1336 +#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_1337_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1337 +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0 + +#define LPDDR4__DENALI_PHY_1338_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1338_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1338 +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0 + +#define LPDDR4__DENALI_PHY_1339_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1339_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0 + +#define LPDDR4__DENALI_PHY_1340_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1340_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1340 +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0 + +#define LPDDR4__DENALI_PHY_1341_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1341_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1341 +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0 + +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_WIDTH 7U +#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1341 +#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0 + +#define LPDDR4__DENALI_PHY_1342_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1342_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOSET 0U +#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0 + +#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1343 +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0 + +#define LPDDR4__DENALI_PHY_1344_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1344_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_WIDTH 32U +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1344 +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0 + +#define LPDDR4__DENALI_PHY_1345_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1345_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_WIDTH 8U +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1345 +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0 + +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1345 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1346_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1346_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0 + +#define LPDDR4__DENALI_PHY_1347_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1347_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0 + +#define LPDDR4__DENALI_PHY_1348_READ_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1348_WRITE_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0 + +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1349_READ_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1349_WRITE_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1349 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1349 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1349 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1349 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1350_READ_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1350_WRITE_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1350 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1350 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1350 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1350 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1351_READ_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1351_WRITE_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1351 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1351 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1351 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1352_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1352_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_WIDTH 16U +#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1352 +#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL + +#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1352 +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_SHIFT 24U +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1352 +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR + +#define LPDDR4__DENALI_PHY_1353_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1353_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_WIDTH 2U +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_WIDTH 4U +#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_WIDTH 9U +#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1354_READ_MASK 0x00000F7FU +#define LPDDR4__DENALI_PHY_1354_WRITE_MASK 0x00000F7FU +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_SHIFT 0U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_WIDTH 7U +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1354 +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START + +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_SHIFT 8U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_WIDTH 4U +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1354 +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK + +#define LPDDR4__DENALI_PHY_1355_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1355_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1355 +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1356_READ_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1356_WRITE_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1356 +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1356 +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1356 +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1357_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1357_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1357 +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1357 +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1357 +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1358_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1358_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1358 +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE + +#define LPDDR4__DENALI_PHY_1359_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1359 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL + +#define LPDDR4__DENALI_PHY_1360_READ_MASK 0x03071FFFU +#define LPDDR4__DENALI_PHY_1360_WRITE_MASK 0x03071FFFU +#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U +#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1360 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH + +#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_SHIFT 8U +#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_WIDTH 5U +#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1360 +#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP + +#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_WIDTH 3U +#define LPDDR4__PHY_ADR_DISABLE__REG DENALI_PHY_1360 +#define LPDDR4__PHY_ADR_DISABLE__FLD LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE + +#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1360 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 + +#define LPDDR4__DENALI_PHY_1361_READ_MASK 0x00030303U +#define LPDDR4__DENALI_PHY_1361_WRITE_MASK 0x00030303U +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1361 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 + +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__REG DENALI_PHY_1361 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2 + +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__REG DENALI_PHY_1361 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3 + +#define LPDDR4__DENALI_PHY_1362_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1362_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_WIDTH 32U +#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1362 +#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE + +#define LPDDR4__DENALI_PHY_1363_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1363_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_WIDTH 26U +#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1363 +#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE + +#define LPDDR4__DENALI_PHY_1364_READ_MASK 0x00FF073FU +#define LPDDR4__DENALI_PHY_1364_WRITE_MASK 0x00FF073FU +#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_WIDTH 6U +#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1364 +#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK + +#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_SHIFT 8U +#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_WIDTH 3U +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1364 +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG + +#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT 16U +#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1364 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC + +#define LPDDR4__DENALI_PHY_1365_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_1365_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_WIDTH 16U +#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__REG DENALI_PHY_1365 +#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__FLD LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN + +#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_WIDTH 3U +#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1365 +#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN + +#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_WIDTH 3U +#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1365 +#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS + +#define LPDDR4__DENALI_PHY_1366_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1366 +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1367_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1367_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1367 +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1368_READ_MASK 0x030FFF03U +#define LPDDR4__DENALI_PHY_1368_WRITE_MASK 0x030FFF03U +#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_WIDTH 2U +#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1368 +#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN + +#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_WIDTH 12U +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1368 +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_WIDTH 2U +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1368 +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1369_READ_MASK 0x0F1F0101U +#define LPDDR4__DENALI_PHY_1369_WRITE_MASK 0x0F1F0101U +#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOSET 0U +#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1369 +#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK + +#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOSET 0U +#define LPDDR4__PHY_ERR_IE__REG DENALI_PHY_1369 +#define LPDDR4__PHY_ERR_IE__FLD LPDDR4__DENALI_PHY_1369__PHY_ERR_IE + +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH 5U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1369 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_WIDTH 4U +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1369 +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1370_READ_MASK 0x000707FFU +#define LPDDR4__DENALI_PHY_1370_WRITE_MASK 0x000707FFU +#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1370 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS + +#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_WIDTH 3U +#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1370 +#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS + +#define LPDDR4__DENALI_PHY_1371_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1371_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1371 +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_1372_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1372_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_SHIFT 0U +#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_WIDTH 16U +#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1372 +#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG + +#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_WIDTH 3U +#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__REG DENALI_PHY_1372 +#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL + +#define LPDDR4__DENALI_PHY_1373_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1373_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1373 +#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1374_READ_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1374_WRITE_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1374 +#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1374 +#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1375_READ_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1375_WRITE_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_SHIFT 0U +#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1375 +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC + +#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1375 +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_WIDTH 4U +#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1375 +#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP + +#define LPDDR4__DENALI_PHY_1376_READ_MASK 0x010103FFU +#define LPDDR4__DENALI_PHY_1376_WRITE_MASK 0x010103FFU +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_WIDTH 10U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1376 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN + +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1376 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN + +#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET 0U +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1376 +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE + +#define LPDDR4__DENALI_PHY_1377_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1377_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1377 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1377 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1378_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1378_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1378 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1378 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1379_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1379_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1379 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1379 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1380_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1380_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1380 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1380 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1381_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1381_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__REG DENALI_PHY_1381 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__REG DENALI_PHY_1381 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1382_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1382_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__REG DENALI_PHY_1382 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__REG DENALI_PHY_1382 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1383_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1383_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__REG DENALI_PHY_1383 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1384_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1384_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__REG DENALI_PHY_1384 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1385_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1385_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__REG DENALI_PHY_1385 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1386_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1386_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__REG DENALI_PHY_1386 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1387_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1387_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1387 +#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE + +#define LPDDR4__DENALI_PHY_1388_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1388_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1388 +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1389_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1389_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_WIDTH 31U +#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1389 +#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE + +#define LPDDR4__DENALI_PHY_1390_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1390_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1390 +#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE + +#define LPDDR4__DENALI_PHY_1391_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1391_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1391 +#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE + +#define LPDDR4__DENALI_PHY_1392_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1392_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1392 +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2 + +#define LPDDR4__DENALI_PHY_1393_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1393_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1393 +#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE + +#define LPDDR4__DENALI_PHY_1394_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1394_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_WIDTH 19U +#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1394 +#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1395_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1395_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ERR_DRIVE__REG DENALI_PHY_1395 +#define LPDDR4__PHY_PAD_ERR_DRIVE__FLD LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE + +#define LPDDR4__DENALI_PHY_1396_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1396_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_ERR_DRIVE2__REG DENALI_PHY_1396 +#define LPDDR4__PHY_PAD_ERR_DRIVE2__FLD LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2 + +#define LPDDR4__DENALI_PHY_1397_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1397_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1397 +#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE + +#define LPDDR4__DENALI_PHY_1398_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1398_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1398 +#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2 + +#define LPDDR4__DENALI_PHY_1399_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1399_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1399 +#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE + +#define LPDDR4__DENALI_PHY_1400_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1400_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1400 +#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2 + +#define LPDDR4__DENALI_PHY_1401_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1401_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1401 +#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE + +#define LPDDR4__DENALI_PHY_1402_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1402_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1402 +#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2 + +#define LPDDR4__DENALI_PHY_1403_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1403_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1403 +#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE + +#define LPDDR4__DENALI_PHY_1404_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1404_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1404 +#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2 + +#define LPDDR4__DENALI_PHY_1405_READ_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1405_WRITE_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1405 +#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH 16U +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1405 +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0 + +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_WIDTH 7U +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1405 +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0 + +#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h new file mode 100644 index 000000000..9aa281af2 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h @@ -0,0 +1,5784 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_PI_MACROS_H_ +#define REG_LPDDR4_PI_MACROS_H_ + +#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U +#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U +#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U +#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U +#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U +#define LPDDR4__PI_START__REG DENALI_PI_0 +#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START + +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U +#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0 +#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS + +#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U +#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1 +#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0 + +#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U +#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2 +#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1 + +#define LPDDR4__DENALI_PI_3_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U +#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U +#define LPDDR4__PI_ID__REG DENALI_PI_3 +#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID + +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK 0x00010000U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT 16U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH 1U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR 0U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET 0U +#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3 +#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI + +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT 24U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH 1U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR 0U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET 0U +#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3 +#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ + +#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET 0U +#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4 +#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN + +#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK 0x00000300U +#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT 8U +#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH 2U +#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4 +#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD + +#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT 16U +#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH 16U +#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4 +#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP + +#define LPDDR4__DENALI_PI_5_READ_MASK 0x030100FFU +#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x030100FFU +#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT 0U +#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH 8U +#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5 +#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0 + +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT 8U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5 +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ + +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK 0x00010000U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT 16U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET 0U +#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5 +#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION + +#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK 0x03000000U +#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT 24U +#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5 +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_6_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00000001U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 0U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6 +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R + +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x00000100U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 8U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6 +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R + +#define LPDDR4__DENALI_PI_7_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_7_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7 +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX + +#define LPDDR4__DENALI_PI_8_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_8_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8 +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP + +#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9 +#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP + +#define LPDDR4__DENALI_PI_10_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_10_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10 +#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX + +#define LPDDR4__DENALI_PI_11_READ_MASK 0x0000011FU +#define LPDDR4__DENALI_PI_11_WRITE_MASK 0x0000011FU +#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT 0U +#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH 5U +#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11 +#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ + +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET 0U +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11 +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY + +#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U +#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12 +#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP + +#define LPDDR4__DENALI_PI_13_READ_MASK 0x01030101U +#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x01030101U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00000001U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 0U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U +#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13 +#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N + +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 8U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U +#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13 +#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1 + +#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH 2U +#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13 +#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP + +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK 0x01000000U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT 24U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET 0U +#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13 +#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL + +#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F03U +#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F03U +#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK 0x00000003U +#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH 2U +#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14 +#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK + +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U +#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14 +#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE + +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14 +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN + +#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U +#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U +#define LPDDR4__PI_TMRR__REG DENALI_PI_14 +#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR + +#define LPDDR4__DENALI_PI_15_READ_MASK 0x0101070FU +#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x0101070FU +#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT 0U +#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH 4U +#define LPDDR4__PI_TMPRR__REG DENALI_PI_15 +#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR + +#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK 0x00000700U +#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH 3U +#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15 +#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN + +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00010000U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 16U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15 +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY + +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x01000000U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 24U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U +#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15 +#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2 + +#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U +#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16 +#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL + +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U +#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16 +#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS + +#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U +#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17 +#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U +#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U +#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE + +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17 +#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0 + +#define LPDDR4__DENALI_PI_18_READ_MASK 0x03030301U +#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03030301U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1 + +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 8U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18 +#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0 + +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_18 +#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1 + +#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_18 +#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0 + +#define LPDDR4__DENALI_PI_19_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_SHIFT 0U +#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_WIDTH 3U +#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_19 +#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE + +#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_MASK 0x00000100U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_SHIFT 8U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WIDTH 1U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOCLR 0U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOSET 0U +#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_19 +#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_START + +#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOSET 0U +#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_19 +#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT + +#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_SHIFT 24U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_19 +#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0 + +#define LPDDR4__DENALI_PI_20_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0 + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0 + +#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_SHIFT 16U +#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_20 +#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0 + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_SHIFT 24U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1 + +#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1 + +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_21 +#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_MASK 0x01000000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_SHIFT 24U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START + +#define LPDDR4__DENALI_PI_22_READ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_MASK 0x00000001U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_SHIFT 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR + +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_SHIFT 8U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD + +#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOSET 0U +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_22 +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ + +#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_22 +#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN + +#define LPDDR4__DENALI_PI_23_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_23 +#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN + +#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_23 +#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN + +#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_MASK 0x00010000U +#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_SHIFT 16U +#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOSET 0U +#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_23 +#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY + +#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOSET 0U +#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_23 +#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_23__PI_WRLVL_REQ + +#define LPDDR4__DENALI_PI_24_READ_MASK 0x3F3F0103U +#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x3F3F0103U +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_MASK 0x00000003U +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_SHIFT 0U +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_WIDTH 2U +#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_24 +#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW + +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_MASK 0x00000100U +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SHIFT 8U +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOSET 0U +#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_24 +#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS + +#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_SHIFT 16U +#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_WIDTH 6U +#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_24 +#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_24__PI_WLDQSEN + +#define LPDDR4__DENALI_PI_24__PI_WLMRD_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_24__PI_WLMRD_SHIFT 24U +#define LPDDR4__DENALI_PI_24__PI_WLMRD_WIDTH 6U +#define LPDDR4__PI_WLMRD__REG DENALI_PI_24 +#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_24__PI_WLMRD + +#define LPDDR4__DENALI_PI_25_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_25 +#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL + +#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_25 +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_SHIFT 24U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_25 +#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_26_READ_MASK 0x01030103U +#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x01030103U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_MASK 0x00000003U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_WIDTH 2U +#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_26 +#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_MASK 0x00000100U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_SHIFT 8U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_26 +#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE + +#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_WIDTH 2U +#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_26 +#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP + +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_26 +#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_27_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_27 +#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_27 +#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN + +#define LPDDR4__DENALI_PI_28_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_28_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_28 +#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP + +#define LPDDR4__DENALI_PI_29_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_29_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_29 +#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX + +#define LPDDR4__DENALI_PI_30_READ_MASK 0x030F0F1FU +#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x030F0F1FU +#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_30 +#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_SHIFT 8U +#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_WIDTH 4U +#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_30 +#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_30__PI_TODTH_WR + +#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_SHIFT 16U +#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_WIDTH 4U +#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_30 +#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_30__PI_TODTH_RD + +#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_MASK 0x03000000U +#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_SHIFT 24U +#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_WIDTH 2U +#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_30 +#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_30__PI_ODT_VALUE + +#define LPDDR4__DENALI_PI_31_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_31_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_MASK 0x00000003U +#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_SHIFT 0U +#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_WIDTH 2U +#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_31 +#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING + +#define LPDDR4__DENALI_PI_32_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_32_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_SHIFT 0U +#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_WIDTH 26U +#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_32 +#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT + +#define LPDDR4__DENALI_PI_33_READ_MASK 0x00000F07U +#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x00000F07U +#define LPDDR4__DENALI_PI_33__PI_RESERVED3_MASK 0x00000007U +#define LPDDR4__DENALI_PI_33__PI_RESERVED3_SHIFT 0U +#define LPDDR4__DENALI_PI_33__PI_RESERVED3_WIDTH 3U +#define LPDDR4__PI_RESERVED3__REG DENALI_PI_33 +#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_33__PI_RESERVED3 + +#define LPDDR4__DENALI_PI_33__PI_RESERVED4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_33__PI_RESERVED4_SHIFT 8U +#define LPDDR4__DENALI_PI_33__PI_RESERVED4_WIDTH 4U +#define LPDDR4__PI_RESERVED4__REG DENALI_PI_33 +#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_33__PI_RESERVED4 + +#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_33 +#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_REQ + +#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_33 +#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ + +#define LPDDR4__DENALI_PI_34_READ_MASK 0x00000103U +#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00000103U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_MASK 0x00000003U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_SHIFT 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_WIDTH 2U +#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW + +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00000100U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 8U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 1U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOCLR 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOSET 0U +#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS + +#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35 +#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0 + +#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36 +#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1 + +#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37 +#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2 + +#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38 +#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3 + +#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39 +#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4 + +#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40 +#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5 + +#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41 +#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6 + +#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42 +#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7 + +#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U +#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE + +#define LPDDR4__DENALI_PI_45_READ_MASK 0x00030301U +#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x00030301U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE + +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000300U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 2U +#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP + +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP + +#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U +#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46 +#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR + +#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47 +#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP + +#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF03U +#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF03U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x00000003U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 2U +#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48 +#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48 +#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN + +#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49 +#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX + +#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50 +#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50 +#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL + +#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL + +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START + +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM + +#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52 +#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52 +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM + +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52 +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52 +#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE + +#define LPDDR4__DENALI_PI_53_READ_MASK 0x0300FFFFU +#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x0300FFFFU +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53 +#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN + +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 8U +#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53 +#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT + +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U +#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53 +#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ + +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_MASK 0x03000000U +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_SHIFT 24U +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_WIDTH 2U +#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_53 +#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW + +#define LPDDR4__DENALI_PI_54_READ_MASK 0x030F0101U +#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x030F0101U +#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_SHIFT 0U +#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WIDTH 1U +#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOCLR 0U +#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOSET 0U +#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_54 +#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_54__PI_CALVL_CS + +#define LPDDR4__DENALI_PI_54__PI_RESERVED5_MASK 0x00000100U +#define LPDDR4__DENALI_PI_54__PI_RESERVED5_SHIFT 8U +#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WIDTH 1U +#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOCLR 0U +#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOSET 0U +#define LPDDR4__PI_RESERVED5__REG DENALI_PI_54 +#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_54__PI_RESERVED5 + +#define LPDDR4__DENALI_PI_54__PI_RESERVED6_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_54__PI_RESERVED6_SHIFT 16U +#define LPDDR4__DENALI_PI_54__PI_RESERVED6_WIDTH 4U +#define LPDDR4__PI_RESERVED6__REG DENALI_PI_54 +#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_54__PI_RESERVED6 + +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x03000000U +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U +#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54 +#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN + +#define LPDDR4__DENALI_PI_55_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_MASK 0x00000001U +#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_SHIFT 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC + +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U +#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE + +#define LPDDR4__DENALI_PI_56_READ_MASK 0x0000FF03U +#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x0000FF03U +#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_MASK 0x00000003U +#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_WIDTH 2U +#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_56 +#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP + +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56 +#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN + +#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57 +#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP + +#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58 +#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX + +#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U +#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK + +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL + +#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U +#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60 +#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL + +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U +#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60 +#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD + +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U +#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60 +#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH + +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U +#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60 +#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT + +#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U +#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61 +#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN + +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61 +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61 +#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN + +#define LPDDR4__DENALI_PI_62_READ_MASK 0x017F1FFFU +#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x017F1FFFU +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 0U +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 8U +#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62 +#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH + +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62 +#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 16U +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U +#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62 +#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF + +#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_62 +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE + +#define LPDDR4__DENALI_PI_63_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_63_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63 +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START + +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63 +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE + +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63 +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL + +#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 24U +#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_63 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN + +#define LPDDR4__DENALI_PI_64_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_64__PI_VREF_CS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_64__PI_VREF_CS_SHIFT 0U +#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WIDTH 1U +#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOCLR 0U +#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOSET 0U +#define LPDDR4__PI_VREF_CS__REG DENALI_PI_64 +#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_64__PI_VREF_CS + +#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOSET 0U +#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_64 +#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN + +#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_64 +#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64 +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE + +#define LPDDR4__DENALI_PI_65_READ_MASK 0x030701FFU +#define LPDDR4__DENALI_PI_65_WRITE_MASK 0x030701FFU +#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT 0U +#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH 8U +#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_65 +#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT + +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_65 +#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN + +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_MASK 0x00070000U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_WIDTH 3U +#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_65 +#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM + +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_MASK 0x03000000U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_SHIFT 24U +#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_WIDTH 2U +#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_65 +#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_66_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_MASK 0x00000300U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_SHIFT 8U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_WIDTH 2U +#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 24U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_67_READ_MASK 0x01030001U +#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x01030001U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x00000001U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_SHIFT 8U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOSET 0U +#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_MASK 0x00030000U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_SHIFT 16U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_WIDTH 2U +#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SHIFT 24U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOSET 0U +#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS + +#define LPDDR4__DENALI_PI_68_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68 +#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN + +#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69 +#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP + +#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70 +#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX + +#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL + +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_72_READ_MASK 0x00030301U +#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x00030301U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_SHIFT 0U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_72 +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72 +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT 16U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH 2U +#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_72 +#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE + +#define LPDDR4__DENALI_PI_73_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_73_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH 32U +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_73 +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0 + +#define LPDDR4__DENALI_PI_74_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH 1U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOCLR 0U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOSET 0U +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_74 +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1 + +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_74 +#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN + +#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_MASK 0x00010000U +#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_SHIFT 16U +#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WIDTH 1U +#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOCLR 0U +#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOSET 0U +#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_74 +#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM + +#define LPDDR4__DENALI_PI_75_READ_MASK 0x010003FFU +#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x010003FFU +#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_SHIFT 0U +#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_75 +#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW + +#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_MASK 0x00010000U +#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT 16U +#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH 1U +#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR 0U +#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_75 +#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START + +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_SHIFT 24U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WIDTH 1U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOCLR 0U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOSET 0U +#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_75 +#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE + +#define LPDDR4__DENALI_PI_76_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_76 +#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN + +#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_76 +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN + +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_76 +#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN + +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT 24U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH 1U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR 0U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOSET 0U +#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_76 +#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN + +#define LPDDR4__DENALI_PI_77_READ_MASK 0x1F070303U +#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x1F070303U +#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_MASK 0x00000003U +#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_WIDTH 2U +#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_77 +#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK + +#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_MASK 0x00000300U +#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_SHIFT 8U +#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_WIDTH 2U +#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_77 +#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_77__PI_BANK_DIFF + +#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_MASK 0x00070000U +#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_SHIFT 16U +#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_WIDTH 3U +#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_77 +#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_77__PI_ROW_DIFF + +#define LPDDR4__DENALI_PI_77__PI_TCCD_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_77__PI_TCCD_SHIFT 24U +#define LPDDR4__DENALI_PI_77__PI_TCCD_WIDTH 5U +#define LPDDR4__PI_TCCD__REG DENALI_PI_77 +#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_77__PI_TCCD + +#define LPDDR4__DENALI_PI_78_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_78__PI_RESERVED7_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_78__PI_RESERVED7_SHIFT 0U +#define LPDDR4__DENALI_PI_78__PI_RESERVED7_WIDTH 4U +#define LPDDR4__PI_RESERVED7__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_78__PI_RESERVED7 + +#define LPDDR4__DENALI_PI_78__PI_RESERVED8_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_78__PI_RESERVED8_SHIFT 8U +#define LPDDR4__DENALI_PI_78__PI_RESERVED8_WIDTH 4U +#define LPDDR4__PI_RESERVED8__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_78__PI_RESERVED8 + +#define LPDDR4__DENALI_PI_78__PI_RESERVED9_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_78__PI_RESERVED9_SHIFT 16U +#define LPDDR4__DENALI_PI_78__PI_RESERVED9_WIDTH 4U +#define LPDDR4__PI_RESERVED9__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_78__PI_RESERVED9 + +#define LPDDR4__DENALI_PI_78__PI_RESERVED10_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_78__PI_RESERVED10_SHIFT 24U +#define LPDDR4__DENALI_PI_78__PI_RESERVED10_WIDTH 4U +#define LPDDR4__PI_RESERVED10__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_78__PI_RESERVED10 + +#define LPDDR4__DENALI_PI_79_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_79__PI_RESERVED11_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_79__PI_RESERVED11_SHIFT 0U +#define LPDDR4__DENALI_PI_79__PI_RESERVED11_WIDTH 4U +#define LPDDR4__PI_RESERVED11__REG DENALI_PI_79 +#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_79__PI_RESERVED11 + +#define LPDDR4__DENALI_PI_79__PI_RESERVED12_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_79__PI_RESERVED12_SHIFT 8U +#define LPDDR4__DENALI_PI_79__PI_RESERVED12_WIDTH 4U +#define LPDDR4__PI_RESERVED12__REG DENALI_PI_79 +#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_79__PI_RESERVED12 + +#define LPDDR4__DENALI_PI_79__PI_RESERVED13_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_79__PI_RESERVED13_SHIFT 16U +#define LPDDR4__DENALI_PI_79__PI_RESERVED13_WIDTH 4U +#define LPDDR4__PI_RESERVED13__REG DENALI_PI_79 +#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_79__PI_RESERVED13 + +#define LPDDR4__DENALI_PI_79__PI_RESERVED14_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_79__PI_RESERVED14_SHIFT 24U +#define LPDDR4__DENALI_PI_79__PI_RESERVED14_WIDTH 4U +#define LPDDR4__PI_RESERVED14__REG DENALI_PI_79 +#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_79__PI_RESERVED14 + +#define LPDDR4__DENALI_PI_80_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_80_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_80__PI_RESERVED15_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_80__PI_RESERVED15_SHIFT 0U +#define LPDDR4__DENALI_PI_80__PI_RESERVED15_WIDTH 4U +#define LPDDR4__PI_RESERVED15__REG DENALI_PI_80 +#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_80__PI_RESERVED15 + +#define LPDDR4__DENALI_PI_80__PI_RESERVED16_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_80__PI_RESERVED16_SHIFT 8U +#define LPDDR4__DENALI_PI_80__PI_RESERVED16_WIDTH 4U +#define LPDDR4__PI_RESERVED16__REG DENALI_PI_80 +#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_80__PI_RESERVED16 + +#define LPDDR4__DENALI_PI_80__PI_RESERVED17_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_80__PI_RESERVED17_SHIFT 16U +#define LPDDR4__DENALI_PI_80__PI_RESERVED17_WIDTH 4U +#define LPDDR4__PI_RESERVED17__REG DENALI_PI_80 +#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_80__PI_RESERVED17 + +#define LPDDR4__DENALI_PI_80__PI_RESERVED18_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_80__PI_RESERVED18_SHIFT 24U +#define LPDDR4__DENALI_PI_80__PI_RESERVED18_WIDTH 4U +#define LPDDR4__PI_RESERVED18__REG DENALI_PI_80 +#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_80__PI_RESERVED18 + +#define LPDDR4__DENALI_PI_81_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_81__PI_RESERVED19_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_81__PI_RESERVED19_SHIFT 0U +#define LPDDR4__DENALI_PI_81__PI_RESERVED19_WIDTH 4U +#define LPDDR4__PI_RESERVED19__REG DENALI_PI_81 +#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_81__PI_RESERVED19 + +#define LPDDR4__DENALI_PI_81__PI_RESERVED20_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_81__PI_RESERVED20_SHIFT 8U +#define LPDDR4__DENALI_PI_81__PI_RESERVED20_WIDTH 4U +#define LPDDR4__PI_RESERVED20__REG DENALI_PI_81 +#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_81__PI_RESERVED20 + +#define LPDDR4__DENALI_PI_81__PI_RESERVED21_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_81__PI_RESERVED21_SHIFT 16U +#define LPDDR4__DENALI_PI_81__PI_RESERVED21_WIDTH 4U +#define LPDDR4__PI_RESERVED21__REG DENALI_PI_81 +#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_81__PI_RESERVED21 + +#define LPDDR4__DENALI_PI_81__PI_RESERVED22_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_81__PI_RESERVED22_SHIFT 24U +#define LPDDR4__DENALI_PI_81__PI_RESERVED22_WIDTH 4U +#define LPDDR4__PI_RESERVED22__REG DENALI_PI_81 +#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_81__PI_RESERVED22 + +#define LPDDR4__DENALI_PI_82_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_82_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_82__PI_RESERVED23_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_82__PI_RESERVED23_SHIFT 0U +#define LPDDR4__DENALI_PI_82__PI_RESERVED23_WIDTH 4U +#define LPDDR4__PI_RESERVED23__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_82__PI_RESERVED23 + +#define LPDDR4__DENALI_PI_82__PI_RESERVED24_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_82__PI_RESERVED24_SHIFT 8U +#define LPDDR4__DENALI_PI_82__PI_RESERVED24_WIDTH 4U +#define LPDDR4__PI_RESERVED24__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_82__PI_RESERVED24 + +#define LPDDR4__DENALI_PI_82__PI_RESERVED25_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_82__PI_RESERVED25_SHIFT 16U +#define LPDDR4__DENALI_PI_82__PI_RESERVED25_WIDTH 4U +#define LPDDR4__PI_RESERVED25__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_82__PI_RESERVED25 + +#define LPDDR4__DENALI_PI_82__PI_RESERVED26_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_82__PI_RESERVED26_SHIFT 24U +#define LPDDR4__DENALI_PI_82__PI_RESERVED26_WIDTH 4U +#define LPDDR4__PI_RESERVED26__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_82__PI_RESERVED26 + +#define LPDDR4__DENALI_PI_83_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_83_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_WIDTH 30U +#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_83 +#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_83__PI_INT_STATUS + +#define LPDDR4__DENALI_PI_84__PI_INT_ACK_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_PI_84__PI_INT_ACK_SHIFT 0U +#define LPDDR4__DENALI_PI_84__PI_INT_ACK_WIDTH 29U +#define LPDDR4__PI_INT_ACK__REG DENALI_PI_84 +#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_84__PI_INT_ACK + +#define LPDDR4__DENALI_PI_85_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_85_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_85__PI_INT_MASK_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_85__PI_INT_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_85__PI_INT_MASK_WIDTH 30U +#define LPDDR4__PI_INT_MASK__REG DENALI_PI_85 +#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_85__PI_INT_MASK + +#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_86 +#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_87 +#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_88 +#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_89 +#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90 +#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F3F01U +#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F3F01U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 1U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOCLR 0U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOSET 0U +#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91 +#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 6U +#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91 +#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN + +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91 +#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK + +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U +#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91 +#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN + +#define LPDDR4__DENALI_PI_92_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_SHIFT 0U +#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_WIDTH 5U +#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_92 +#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX + +#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_SHIFT 8U +#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_WIDTH 5U +#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_92 +#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_92__PI_ACT_N_MUX + +#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_SHIFT 16U +#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_WIDTH 5U +#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_92 +#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_0 + +#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_SHIFT 24U +#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_WIDTH 5U +#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_92 +#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_1 + +#define LPDDR4__DENALI_PI_93_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_SHIFT 0U +#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_WIDTH 5U +#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_93 +#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_RAS_N_MUX + +#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_SHIFT 8U +#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_WIDTH 5U +#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_93 +#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_CAS_N_MUX + +#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_SHIFT 16U +#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_WIDTH 5U +#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_93 +#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_WE_N_MUX + +#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_WIDTH 5U +#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_93 +#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_93__PI_BANK_MUX_0 + +#define LPDDR4__DENALI_PI_94_READ_MASK 0x0101011FU +#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x0101011FU +#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_WIDTH 5U +#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_94 +#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_94__PI_BANK_MUX_1 + +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOSET 0U +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_94 +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN + +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00010000U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 16U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 1U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOCLR 0U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOSET 0U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_94 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0 + +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 24U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 1U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOCLR 0U +#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOSET 0U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_94 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1 + +#define LPDDR4__DENALI_PI_95_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_95 +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_SHIFT 8U +#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_WIDTH 16U +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_95 +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U +#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_95 +#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_PI_96_READ_MASK 0x01030107U +#define LPDDR4__DENALI_PI_96_WRITE_MASK 0x01030107U +#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_MASK 0x00000007U +#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_SHIFT 0U +#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_WIDTH 3U +#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_96 +#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT + +#define LPDDR4__DENALI_PI_96__PI_BIST_GO_MASK 0x00000100U +#define LPDDR4__DENALI_PI_96__PI_BIST_GO_SHIFT 8U +#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOSET 0U +#define LPDDR4__PI_BIST_GO__REG DENALI_PI_96 +#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_96__PI_BIST_GO + +#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_MASK 0x00030000U +#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_SHIFT 16U +#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_WIDTH 2U +#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_96 +#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_96__PI_BIST_RESULT + +#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_SHIFT 24U +#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WIDTH 1U +#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOCLR 0U +#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOSET 0U +#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_96 +#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE + +#define LPDDR4__DENALI_PI_97_READ_MASK 0x000101FFU +#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x000101FFU +#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_SHIFT 0U +#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_WIDTH 8U +#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_97 +#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_97__PI_ADDR_SPACE + +#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_MASK 0x00000100U +#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_SHIFT 8U +#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_97 +#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK + +#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_MASK 0x00010000U +#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_SHIFT 16U +#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_97 +#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK + +#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_98 +#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_PI_99_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_99_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WIDTH 1U +#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOCLR 0U +#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOSET 0U +#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_99 +#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_SHIFT 8U +#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_WIDTH 8U +#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_99 +#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN + +#define LPDDR4__DENALI_PI_100_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_100_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_WIDTH 32U +#define LPDDR4__PI_BIST_DATA_MASK__REG DENALI_PI_100 +#define LPDDR4__PI_BIST_DATA_MASK__FLD LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK + +#define LPDDR4__DENALI_PI_101_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_101_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_101 +#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT + +#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_SHIFT 16U +#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_101 +#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP + +#define LPDDR4__DENALI_PI_102_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_102_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_102 +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0 + +#define LPDDR4__DENALI_PI_103_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_103_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_103 +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1 + +#define LPDDR4__DENALI_PI_104_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_104_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_104 +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0 + +#define LPDDR4__DENALI_PI_105_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_105_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_105 +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1 + +#define LPDDR4__DENALI_PI_106_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_106_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_106 +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0 + +#define LPDDR4__DENALI_PI_107_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_107_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_107 +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1 + +#define LPDDR4__DENALI_PI_108_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_108_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_SHIFT 0U +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_108 +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0 + +#define LPDDR4__DENALI_PI_109_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_109_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_SHIFT 0U +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_109 +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1 + +#define LPDDR4__DENALI_PI_110_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_110_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_SHIFT 0U +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_110 +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0 + +#define LPDDR4__DENALI_PI_111_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_111_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_SHIFT 0U +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_111 +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1 + +#define LPDDR4__DENALI_PI_112_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_112_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_SHIFT 0U +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_112 +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0 + +#define LPDDR4__DENALI_PI_113_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_113_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_SHIFT 0U +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_113 +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1 + +#define LPDDR4__DENALI_PI_114_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_114_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_SHIFT 0U +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_114 +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0 + +#define LPDDR4__DENALI_PI_115_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_115_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_SHIFT 0U +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_115 +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1 + +#define LPDDR4__DENALI_PI_116_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_116_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_SHIFT 0U +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_116 +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0 + +#define LPDDR4__DENALI_PI_117_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_117_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_SHIFT 0U +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_117 +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1 + +#define LPDDR4__DENALI_PI_118_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_118_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_SHIFT 0U +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_118 +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0 + +#define LPDDR4__DENALI_PI_119_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PI_119_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_SHIFT 0U +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_119 +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1 + +#define LPDDR4__DENALI_PI_120_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_120_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_SHIFT 0U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0 + +#define LPDDR4__DENALI_PI_121_READ_MASK 0x03030703U +#define LPDDR4__DENALI_PI_121_WRITE_MASK 0x03030703U +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_SHIFT 0U +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_121 +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1 + +#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_MASK 0x00000700U +#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_SHIFT 8U +#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_WIDTH 3U +#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_121 +#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_MODE + +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_SHIFT 16U +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_121 +#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE + +#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_MASK 0x03000000U +#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_SHIFT 24U +#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_121 +#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE + +#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_122 +#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0 + +#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_123 +#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1 + +#define LPDDR4__DENALI_PI_124_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_124_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_WIDTH 6U +#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_124 +#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM + +#define LPDDR4__DENALI_PI_125_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_125 +#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0 + +#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_126 +#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1 + +#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_SHIFT 0U +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_127 +#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2 + +#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_SHIFT 0U +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_128 +#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3 + +#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_SHIFT 0U +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_129 +#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4 + +#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_SHIFT 0U +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_130 +#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5 + +#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_SHIFT 0U +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_131 +#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6 + +#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_SHIFT 0U +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_132 +#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7 + +#define LPDDR4__DENALI_PI_133_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_SHIFT 0U +#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_WIDTH 4U +#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_133 +#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_133__PI_COL_DIFF + +#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOSET 0U +#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_133 +#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN + +#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_MASK 0x00010000U +#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_SHIFT 16U +#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WIDTH 1U +#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOCLR 0U +#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOSET 0U +#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_133 +#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_133__PI_CRC_CALC + +#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOSET 0U +#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_133 +#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN + +#define LPDDR4__DENALI_PI_134_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT 0U +#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134 +#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134 +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x00010000U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 16U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134 +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH + +#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOSET 0U +#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_134 +#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ + +#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 0U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT + +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 8U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT + +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 16U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT + +#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_PI_136_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_136_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_WIDTH 32U +#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_136 +#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_136__PI_TRST_PWRON + +#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_WIDTH 32U +#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_137 +#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE + +#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_MASK 0x00000001U +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_SHIFT 0U +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WIDTH 1U +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOCLR 0U +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOSET 0U +#define LPDDR4__PI_DLL_RST__REG DENALI_PI_138 +#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST + +#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOSET 0U +#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_138 +#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN + +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_SHIFT 16U +#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_138 +#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY + +#define LPDDR4__DENALI_PI_139_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_139_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_SHIFT 0U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_139 +#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_PI_140_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_WIDTH 26U +#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_140 +#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG + +#define LPDDR4__DENALI_PI_141_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_WIDTH 8U +#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_141 +#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_141__PI_MRW_STATUS + +#define LPDDR4__DENALI_PI_141__PI_RESERVED27_MASK 0x00000100U +#define LPDDR4__DENALI_PI_141__PI_RESERVED27_SHIFT 8U +#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WIDTH 1U +#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOCLR 0U +#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOSET 0U +#define LPDDR4__PI_RESERVED27__REG DENALI_PI_141 +#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_141__PI_RESERVED27 + +#define LPDDR4__DENALI_PI_142_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U +#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142 +#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG + +#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143 +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0 + +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U +#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143 +#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT + +#define LPDDR4__DENALI_PI_144_READ_MASK 0x01010003U +#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x01010003U +#define LPDDR4__DENALI_PI_144__PI_RESERVED28_MASK 0x00000003U +#define LPDDR4__DENALI_PI_144__PI_RESERVED28_SHIFT 0U +#define LPDDR4__DENALI_PI_144__PI_RESERVED28_WIDTH 2U +#define LPDDR4__PI_RESERVED28__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_144__PI_RESERVED28 + +#define LPDDR4__DENALI_PI_144__PI_RESERVED29_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_144__PI_RESERVED29_SHIFT 8U +#define LPDDR4__DENALI_PI_144__PI_RESERVED29_WIDTH 4U +#define LPDDR4__PI_RESERVED29__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_144__PI_RESERVED29 + +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144 +#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING + +#define LPDDR4__DENALI_PI_144__PI_RESERVED30_MASK 0x01000000U +#define LPDDR4__DENALI_PI_144__PI_RESERVED30_SHIFT 24U +#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WIDTH 1U +#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOCLR 0U +#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOSET 0U +#define LPDDR4__PI_RESERVED30__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_144__PI_RESERVED30 + +#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_145__PI_RESERVED31_MASK 0x00000007U +#define LPDDR4__DENALI_PI_145__PI_RESERVED31_SHIFT 0U +#define LPDDR4__DENALI_PI_145__PI_RESERVED31_WIDTH 3U +#define LPDDR4__PI_RESERVED31__REG DENALI_PI_145 +#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_145__PI_RESERVED31 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U +#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0 + +#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U +#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2 + +#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U +#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3 + +#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U +#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U +#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4 + +#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U +#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6 + +#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U +#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7 + +#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U +#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151 +#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7 + +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U +#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152 +#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE + +#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U +#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153 +#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK + +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U +#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153 +#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS + +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U +#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153 +#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM + +#define LPDDR4__DENALI_PI_153__PI_RESERVED32_MASK 0x01000000U +#define LPDDR4__DENALI_PI_153__PI_RESERVED32_SHIFT 24U +#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WIDTH 1U +#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOCLR 0U +#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOSET 0U +#define LPDDR4__PI_RESERVED32__REG DENALI_PI_153 +#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_153__PI_RESERVED32 + +#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U +#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154 +#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_154__PI_RESERVED33_MASK 0x00000100U +#define LPDDR4__DENALI_PI_154__PI_RESERVED33_SHIFT 8U +#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOSET 0U +#define LPDDR4__PI_RESERVED33__REG DENALI_PI_154 +#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_154__PI_RESERVED33 + +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U +#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154 +#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN + +#define LPDDR4__DENALI_PI_154__PI_RESERVED34_MASK 0x01000000U +#define LPDDR4__DENALI_PI_154__PI_RESERVED34_SHIFT 24U +#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOSET 0U +#define LPDDR4__PI_RESERVED34__REG DENALI_PI_154 +#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_154__PI_RESERVED34 + +#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x00000001U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U +#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED36_MASK 0x00000100U +#define LPDDR4__DENALI_PI_155__PI_RESERVED36_SHIFT 8U +#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOSET 0U +#define LPDDR4__PI_RESERVED36__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_155__PI_RESERVED36 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED37_MASK 0x00010000U +#define LPDDR4__DENALI_PI_155__PI_RESERVED37_SHIFT 16U +#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOSET 0U +#define LPDDR4__PI_RESERVED37__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_155__PI_RESERVED37 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED38_MASK 0x01000000U +#define LPDDR4__DENALI_PI_155__PI_RESERVED38_SHIFT 24U +#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOSET 0U +#define LPDDR4__PI_RESERVED38__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_155__PI_RESERVED38 + +#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x00000001U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U +#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED40_MASK 0x00000100U +#define LPDDR4__DENALI_PI_156__PI_RESERVED40_SHIFT 8U +#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOSET 0U +#define LPDDR4__PI_RESERVED40__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_156__PI_RESERVED40 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED41_MASK 0x00010000U +#define LPDDR4__DENALI_PI_156__PI_RESERVED41_SHIFT 16U +#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOSET 0U +#define LPDDR4__PI_RESERVED41__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_156__PI_RESERVED41 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED42_MASK 0x01000000U +#define LPDDR4__DENALI_PI_156__PI_RESERVED42_SHIFT 24U +#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOSET 0U +#define LPDDR4__PI_RESERVED42__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_156__PI_RESERVED42 + +#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x00000001U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U +#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED44_MASK 0x00000100U +#define LPDDR4__DENALI_PI_157__PI_RESERVED44_SHIFT 8U +#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOSET 0U +#define LPDDR4__PI_RESERVED44__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_157__PI_RESERVED44 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED45_MASK 0x00010000U +#define LPDDR4__DENALI_PI_157__PI_RESERVED45_SHIFT 16U +#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOSET 0U +#define LPDDR4__PI_RESERVED45__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_157__PI_RESERVED45 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED46_MASK 0x01000000U +#define LPDDR4__DENALI_PI_157__PI_RESERVED46_SHIFT 24U +#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOSET 0U +#define LPDDR4__PI_RESERVED46__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_157__PI_RESERVED46 + +#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x00000001U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U +#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED48_MASK 0x00000100U +#define LPDDR4__DENALI_PI_158__PI_RESERVED48_SHIFT 8U +#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOSET 0U +#define LPDDR4__PI_RESERVED48__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_158__PI_RESERVED48 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED49_MASK 0x00010000U +#define LPDDR4__DENALI_PI_158__PI_RESERVED49_SHIFT 16U +#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOSET 0U +#define LPDDR4__PI_RESERVED49__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_158__PI_RESERVED49 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED50_MASK 0x01000000U +#define LPDDR4__DENALI_PI_158__PI_RESERVED50_SHIFT 24U +#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOSET 0U +#define LPDDR4__PI_RESERVED50__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_158__PI_RESERVED50 + +#define LPDDR4__DENALI_PI_159_READ_MASK 0x00FF0101U +#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x00FF0101U +#define LPDDR4__DENALI_PI_159__PI_RESERVED51_MASK 0x00000001U +#define LPDDR4__DENALI_PI_159__PI_RESERVED51_SHIFT 0U +#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WIDTH 1U +#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOCLR 0U +#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOSET 0U +#define LPDDR4__PI_RESERVED51__REG DENALI_PI_159 +#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_159__PI_RESERVED51 + +#define LPDDR4__DENALI_PI_159__PI_RESERVED52_MASK 0x00000100U +#define LPDDR4__DENALI_PI_159__PI_RESERVED52_SHIFT 8U +#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WIDTH 1U +#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOCLR 0U +#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOSET 0U +#define LPDDR4__PI_RESERVED52__REG DENALI_PI_159 +#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_159__PI_RESERVED52 + +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 16U +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159 +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND + +#define LPDDR4__DENALI_PI_160_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_SHIFT 0U +#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_WIDTH 9U +#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_160 +#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_160__PI_TREFBW_THR + +#define LPDDR4__DENALI_PI_161_READ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U +#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_161 +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY + +#define LPDDR4__DENALI_PI_162_READ_MASK 0x01031F01U +#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01031F01U +#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_162 +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PI_162__PI_RESERVED53_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_162__PI_RESERVED53_SHIFT 8U +#define LPDDR4__DENALI_PI_162__PI_RESERVED53_WIDTH 5U +#define LPDDR4__PI_RESERVED53__REG DENALI_PI_162 +#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_162__PI_RESERVED53 + +#define LPDDR4__DENALI_PI_162__PI_CATR_MASK 0x00030000U +#define LPDDR4__DENALI_PI_162__PI_CATR_SHIFT 16U +#define LPDDR4__DENALI_PI_162__PI_CATR_WIDTH 2U +#define LPDDR4__PI_CATR__REG DENALI_PI_162 +#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_162__PI_CATR + +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 24U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U +#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162 +#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ + +#define LPDDR4__DENALI_PI_163_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_163_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_SHIFT 0U +#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_163 +#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE + +#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_MASK 0x00000100U +#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_SHIFT 8U +#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WIDTH 1U +#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOCLR 0U +#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOSET 0U +#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_163 +#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC + +#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOSET 0U +#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_163 +#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ + +#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U +#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_SHIFT 24U +#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WIDTH 1U +#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOCLR 0U +#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOSET 0U +#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_163 +#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START + +#define LPDDR4__DENALI_PI_164_READ_MASK 0x00FFFF07U +#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x00FFFF07U +#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK 0x00000007U +#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT 0U +#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH 3U +#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_164 +#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY + +#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_WIDTH 16U +#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_164 +#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_164__PI_TVREF_F0 + +#define LPDDR4__DENALI_PI_165_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_165_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_WIDTH 16U +#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_165 +#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F1 + +#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_WIDTH 16U +#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_165 +#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F2 + +#define LPDDR4__DENALI_PI_166_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_WIDTH 8U +#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_166 +#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F0 + +#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_WIDTH 8U +#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_166 +#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F1 + +#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_WIDTH 8U +#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_166 +#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F2 + +#define LPDDR4__DENALI_PI_167_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_167 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0 + +#define LPDDR4__DENALI_PI_168_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_168 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1 + +#define LPDDR4__DENALI_PI_169_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_169 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2 + +#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_169 +#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_169__PI_ZQINIT_F0 + +#define LPDDR4__DENALI_PI_170_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_170 +#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F1 + +#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_170 +#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F2 + +#define LPDDR4__DENALI_PI_171_READ_MASK 0xFF0F3F7FU +#define LPDDR4__DENALI_PI_171_WRITE_MASK 0xFF0F3F7FU +#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_WIDTH 7U +#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_171 +#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_171__PI_WRLAT_F0 + +#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_WIDTH 6U +#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_171 +#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0 + +#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_WIDTH 4U +#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_171 +#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0 + +#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH 8U +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_171 +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0 + +#define LPDDR4__DENALI_PI_172_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_172 +#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0 + +#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_WIDTH 7U +#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_172 +#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_172__PI_WRLAT_F1 + +#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_WIDTH 6U +#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_172 +#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1 + +#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_WIDTH 4U +#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_172 +#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1 + +#define LPDDR4__DENALI_PI_173_READ_MASK 0x3F7F7FFFU +#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x3F7F7FFFU +#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH 8U +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_173 +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1 + +#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_173 +#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1 + +#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_WIDTH 7U +#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_173 +#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_173__PI_WRLAT_F2 + +#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_WIDTH 6U +#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_173 +#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2 + +#define LPDDR4__DENALI_PI_174_READ_MASK 0x007FFF0FU +#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x007FFF0FU +#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_WIDTH 4U +#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_174 +#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2 + +#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH 8U +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_174 +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2 + +#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_174 +#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2 + +#define LPDDR4__DENALI_PI_175_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_WIDTH 10U +#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_175 +#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_175__PI_TRFC_F0 + +#define LPDDR4__DENALI_PI_176_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_176__PI_TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_176__PI_TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_176__PI_TREF_F0_WIDTH 20U +#define LPDDR4__PI_TREF_F0__REG DENALI_PI_176 +#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TREF_F0 + +#define LPDDR4__DENALI_PI_177_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_WIDTH 10U +#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_177 +#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_177__PI_TRFC_F1 + +#define LPDDR4__DENALI_PI_178_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_178__PI_TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_178__PI_TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_178__PI_TREF_F1_WIDTH 20U +#define LPDDR4__PI_TREF_F1__REG DENALI_PI_178 +#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_178__PI_TREF_F1 + +#define LPDDR4__DENALI_PI_179_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_WIDTH 10U +#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_179 +#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_179__PI_TRFC_F2 + +#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_180__PI_TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_180__PI_TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_180__PI_TREF_F2_WIDTH 20U +#define LPDDR4__PI_TREF_F2__REG DENALI_PI_180 +#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_180__PI_TREF_F2 + +#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_180 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_181 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_181 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_181 +#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0 + +#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_181 +#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1 + +#define LPDDR4__DENALI_PI_182_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_182 +#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2 + +#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_182 +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0 + +#define LPDDR4__DENALI_PI_183_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_183 +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1 + +#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_183 +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2 + +#define LPDDR4__DENALI_PI_184_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_184 +#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0 + +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOSET 0U +#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_184 +#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F0 + +#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_184 +#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1 + +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOSET 0U +#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_184 +#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F1 + +#define LPDDR4__DENALI_PI_185_READ_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_185 +#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2 + +#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOSET 0U +#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_185 +#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_ODT_EN_F2 + +#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_WIDTH 4U +#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_185 +#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_185__PI_ODTLON_F0 + +#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_185 +#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0 + +#define LPDDR4__DENALI_PI_186_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_WIDTH 4U +#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_186 +#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F1 + +#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_186 +#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1 + +#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_WIDTH 4U +#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_186 +#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F2 + +#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_186 +#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2 + +#define LPDDR4__DENALI_PI_187_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_187 +#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0 + +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_187 +#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1 + +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_187 +#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2 + +#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_187 +#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0 + +#define LPDDR4__DENALI_PI_188_READ_MASK 0x03033F3FU +#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03033F3FU +#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_188 +#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1 + +#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_188 +#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2 + +#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_188 +#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0 + +#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_188 +#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0 + +#define LPDDR4__DENALI_PI_189_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_189 +#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1 + +#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_189 +#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1 + +#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_189 +#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2 + +#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_189 +#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2 + +#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_WIDTH 8U +#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_190 +#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0 + +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_WIDTH 8U +#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_190 +#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1 + +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_WIDTH 8U +#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_190 +#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2 + +#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_190 +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0 + +#define LPDDR4__DENALI_PI_191_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_191 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0 + +#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_191 +#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0 + +#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_191 +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0 + +#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_191 +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1 + +#define LPDDR4__DENALI_PI_192_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_192 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1 + +#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_192 +#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1 + +#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_192 +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1 + +#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_192 +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2 + +#define LPDDR4__DENALI_PI_193_READ_MASK 0xFF030303U +#define LPDDR4__DENALI_PI_193_WRITE_MASK 0xFF030303U +#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_193 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2 + +#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_193 +#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2 + +#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_193 +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2 + +#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_193 +#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_194_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_194_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_194 +#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_194 +#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_194 +#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_194 +#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_195_READ_MASK 0x070707FFU +#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x070707FFU +#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_195 +#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000700U +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_195 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_MASK 0x00070000U +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_195 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_MASK 0x07000000U +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_195 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_196 +#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0 + +#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_196 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0 + +#define LPDDR4__DENALI_PI_197_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_197 +#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1 + +#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_197 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1 + +#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_198 +#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2 + +#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_198 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2 + +#define LPDDR4__DENALI_PI_199_READ_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2 + +#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_WIDTH 5U +#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_199 +#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_199__PI_TMRZ_F0 + +#define LPDDR4__DENALI_PI_200_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_WIDTH 14U +#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_200 +#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_200__PI_TCAENT_F0 + +#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_WIDTH 5U +#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_200 +#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_200__PI_TMRZ_F1 + +#define LPDDR4__DENALI_PI_201_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_201_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_WIDTH 14U +#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_201 +#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_201__PI_TCAENT_F1 + +#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_WIDTH 5U +#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_201 +#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_201__PI_TMRZ_F2 + +#define LPDDR4__DENALI_PI_202_READ_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_202_WRITE_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_WIDTH 14U +#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_202 +#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_202__PI_TCAENT_F2 + +#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_202 +#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0 + +#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_202 +#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0 + +#define LPDDR4__DENALI_PI_203_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_203_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_203 +#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0 + +#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_203 +#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0 + +#define LPDDR4__DENALI_PI_204_READ_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_204 +#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1 + +#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_204 +#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1 + +#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_204 +#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1 + +#define LPDDR4__DENALI_PI_205_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_205 +#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1 + +#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_205 +#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2 + +#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_205 +#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2 + +#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_206 +#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2 + +#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_206 +#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2 + +#define LPDDR4__DENALI_PI_207_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_207 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_207 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_207 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_207 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_208_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_208 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_208 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_208 +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_208 +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_209_READ_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_209_WRITE_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_209 +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_209 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0 + +#define LPDDR4__DENALI_PI_209__PI_TXP_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_209__PI_TXP_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_209__PI_TXP_F0_WIDTH 5U +#define LPDDR4__PI_TXP_F0__REG DENALI_PI_209 +#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_209__PI_TXP_F0 + +#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_209 +#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0 + +#define LPDDR4__DENALI_PI_210_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_210_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_210 +#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_210__PI_TCKELCK_F0 + +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_210 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1 + +#define LPDDR4__DENALI_PI_210__PI_TXP_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_210__PI_TXP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_210__PI_TXP_F1_WIDTH 5U +#define LPDDR4__PI_TXP_F1__REG DENALI_PI_210 +#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_210__PI_TXP_F1 + +#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_210 +#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1 + +#define LPDDR4__DENALI_PI_211_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_211_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_211 +#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_211__PI_TCKELCK_F1 + +#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_211 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2 + +#define LPDDR4__DENALI_PI_211__PI_TXP_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_211__PI_TXP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_211__PI_TXP_F2_WIDTH 5U +#define LPDDR4__PI_TXP_F2__REG DENALI_PI_211 +#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_211__PI_TXP_F2 + +#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_211 +#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2 + +#define LPDDR4__DENALI_PI_212_READ_MASK 0xFFFFFF1FU +#define LPDDR4__DENALI_PI_212_WRITE_MASK 0xFFFFFF1FU +#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_212 +#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_212__PI_TCKELCK_F2 + +#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_212 +#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_PI_213_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_213 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_PI_214_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_214 +#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_PI_215_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_215 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_PI_216_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_216 +#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_PI_217_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_217_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_217 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_217 +#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0 + +#define LPDDR4__DENALI_PI_218_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_218_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_218__PI_TFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_218__PI_TFC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_218__PI_TFC_F0_WIDTH 10U +#define LPDDR4__PI_TFC_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_218__PI_TFC_F0 + +#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_218 +#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1 + +#define LPDDR4__DENALI_PI_219_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_219_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_219__PI_TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_219__PI_TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_219__PI_TFC_F1_WIDTH 10U +#define LPDDR4__PI_TFC_F1__REG DENALI_PI_219 +#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_219__PI_TFC_F1 + +#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_219 +#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2 + +#define LPDDR4__DENALI_PI_220_READ_MASK 0x030303FFU +#define LPDDR4__DENALI_PI_220_WRITE_MASK 0x030303FFU +#define LPDDR4__DENALI_PI_220__PI_TFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_220__PI_TFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_220__PI_TFC_F2_WIDTH 10U +#define LPDDR4__PI_TFC_F2__REG DENALI_PI_220 +#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_220__PI_TFC_F2 + +#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_WIDTH 2U +#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_220 +#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F0 + +#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_WIDTH 2U +#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_220 +#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F1 + +#define LPDDR4__DENALI_PI_221_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_221_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_WIDTH 2U +#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_221 +#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_221__PI_VREF_EN_F2 + +#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_221 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0 + +#define LPDDR4__DENALI_PI_222_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_222 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0 + +#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_222 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_222 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_223_READ_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_223_WRITE_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_223 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_223 +#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0 + +#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_223 +#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0 + +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_WIDTH 5U +#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_223 +#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0 + +#define LPDDR4__DENALI_PI_224_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_224_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_224 +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_224 +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1 + +#define LPDDR4__DENALI_PI_225_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_225_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_225 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1 + +#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_225 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_225 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_226_READ_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_226 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_226 +#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1 + +#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_226 +#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1 + +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_WIDTH 5U +#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_226 +#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1 + +#define LPDDR4__DENALI_PI_227_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_227_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_227 +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_227 +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_227 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2 + +#define LPDDR4__DENALI_PI_228_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_228_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2 + +#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_228 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_228 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_229_READ_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_229 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_229 +#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2 + +#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_229 +#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2 + +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_WIDTH 5U +#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_229 +#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2 + +#define LPDDR4__DENALI_PI_230_READ_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PI_230_WRITE_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_230 +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_230 +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_230 +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0 + +#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_230 +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1 + +#define LPDDR4__DENALI_PI_231_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PI_231_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_231 +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2 + +#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_WIDTH 8U +#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_231 +#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRTP_F0 + +#define LPDDR4__DENALI_PI_231__PI_TRP_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_231__PI_TRP_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_231__PI_TRP_F0_WIDTH 8U +#define LPDDR4__PI_TRP_F0__REG DENALI_PI_231 +#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRP_F0 + +#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_WIDTH 8U +#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_231 +#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_231__PI_TRCD_F0 + +#define LPDDR4__DENALI_PI_232_READ_MASK 0x00FF3F1FU +#define LPDDR4__DENALI_PI_232_WRITE_MASK 0x00FF3F1FU +#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_WIDTH 5U +#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_232 +#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_232__PI_TCCD_L_F0 + +#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_WIDTH 6U +#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_232 +#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWTR_F0 + +#define LPDDR4__DENALI_PI_232__PI_TWR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_232__PI_TWR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_232__PI_TWR_F0_WIDTH 8U +#define LPDDR4__PI_TWR_F0__REG DENALI_PI_232 +#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWR_F0 + +#define LPDDR4__DENALI_PI_233_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_WIDTH 20U +#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_233 +#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0 + +#define LPDDR4__DENALI_PI_234_READ_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_234_WRITE_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_WIDTH 9U +#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_234 +#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0 + +#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_234 +#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_234 +#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_234__PI_TCCDMW_F0 + +#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_235__PI_TSR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_235__PI_TSR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_235__PI_TSR_F0_WIDTH 8U +#define LPDDR4__PI_TSR_F0__REG DENALI_PI_235 +#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TSR_F0 + +#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_WIDTH 8U +#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_235 +#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRD_F0 + +#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_WIDTH 8U +#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_235 +#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRW_F0 + +#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_WIDTH 8U +#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_235 +#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMOD_F0 + +#define LPDDR4__DENALI_PI_236_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_236_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_WIDTH 8U +#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_236 +#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0 + +#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_WIDTH 8U +#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_236 +#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0 + +#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_WIDTH 8U +#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_236 +#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRTP_F1 + +#define LPDDR4__DENALI_PI_236__PI_TRP_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_236__PI_TRP_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_236__PI_TRP_F1_WIDTH 8U +#define LPDDR4__PI_TRP_F1__REG DENALI_PI_236 +#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRP_F1 + +#define LPDDR4__DENALI_PI_237_READ_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_WIDTH 8U +#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_237 +#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_237__PI_TRCD_F1 + +#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_WIDTH 5U +#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_237 +#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_237__PI_TCCD_L_F1 + +#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_WIDTH 6U +#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_237 +#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWTR_F1 + +#define LPDDR4__DENALI_PI_237__PI_TWR_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_237__PI_TWR_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_237__PI_TWR_F1_WIDTH 8U +#define LPDDR4__PI_TWR_F1__REG DENALI_PI_237 +#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWR_F1 + +#define LPDDR4__DENALI_PI_238_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_WIDTH 20U +#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_238 +#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1 + +#define LPDDR4__DENALI_PI_239_READ_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_WIDTH 9U +#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_239 +#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1 + +#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_239 +#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_239 +#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_239__PI_TCCDMW_F1 + +#define LPDDR4__DENALI_PI_240_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_240_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_240__PI_TSR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_240__PI_TSR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_240__PI_TSR_F1_WIDTH 8U +#define LPDDR4__PI_TSR_F1__REG DENALI_PI_240 +#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_240__PI_TSR_F1 + +#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_WIDTH 8U +#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_240 +#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRD_F1 + +#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_WIDTH 8U +#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_240 +#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRW_F1 + +#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_WIDTH 8U +#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_240 +#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMOD_F1 + +#define LPDDR4__DENALI_PI_241_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_241_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_WIDTH 8U +#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_241 +#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1 + +#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_WIDTH 8U +#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_241 +#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1 + +#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_WIDTH 8U +#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_241 +#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRTP_F2 + +#define LPDDR4__DENALI_PI_241__PI_TRP_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_241__PI_TRP_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_241__PI_TRP_F2_WIDTH 8U +#define LPDDR4__PI_TRP_F2__REG DENALI_PI_241 +#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRP_F2 + +#define LPDDR4__DENALI_PI_242_READ_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_242_WRITE_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_WIDTH 8U +#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_242 +#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_242__PI_TRCD_F2 + +#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_WIDTH 5U +#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_242 +#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_242__PI_TCCD_L_F2 + +#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_WIDTH 6U +#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_242 +#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWTR_F2 + +#define LPDDR4__DENALI_PI_242__PI_TWR_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_242__PI_TWR_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_242__PI_TWR_F2_WIDTH 8U +#define LPDDR4__PI_TWR_F2__REG DENALI_PI_242 +#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWR_F2 + +#define LPDDR4__DENALI_PI_243_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_WIDTH 20U +#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_243 +#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2 + +#define LPDDR4__DENALI_PI_244_READ_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_WIDTH 9U +#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_244 +#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2 + +#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_244 +#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_244 +#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_244__PI_TCCDMW_F2 + +#define LPDDR4__DENALI_PI_245_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_245_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_245__PI_TSR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_245__PI_TSR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_245__PI_TSR_F2_WIDTH 8U +#define LPDDR4__PI_TSR_F2__REG DENALI_PI_245 +#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_245__PI_TSR_F2 + +#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_WIDTH 8U +#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_245 +#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRD_F2 + +#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_WIDTH 8U +#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_245 +#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRW_F2 + +#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_WIDTH 8U +#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_245 +#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMOD_F2 + +#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_WIDTH 8U +#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_246 +#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2 + +#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_WIDTH 8U +#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_246 +#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2 + +#define LPDDR4__DENALI_PI_247_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_247 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_PI_248_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_248_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_248 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_PI_249_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_249 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_PI_250_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_250_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_250 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_PI_251_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_251 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_PI_252_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_252_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_252 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_PI_253_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_253_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_WIDTH 16U +#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_253 +#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F0 + +#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_WIDTH 16U +#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_253 +#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F1 + +#define LPDDR4__DENALI_PI_254_READ_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_WIDTH 16U +#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_254 +#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_254__PI_TXSR_F2 + +#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_254 +#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F0 + +#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_254 +#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F1 + +#define LPDDR4__DENALI_PI_255_READ_MASK 0x00FFFF3FU +#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x00FFFF3FU +#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_255 +#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_255__PI_TEXCKE_F2 + +#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_WIDTH 16U +#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_255 +#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_255__PI_TDLL_F0 + +#define LPDDR4__DENALI_PI_256_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_256_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_WIDTH 16U +#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_256 +#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F1 + +#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_WIDTH 16U +#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_256 +#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F2 + +#define LPDDR4__DENALI_PI_257_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_257_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_WIDTH 8U +#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_257 +#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F0 + +#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_WIDTH 8U +#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_257 +#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F0 + +#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_WIDTH 8U +#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_257 +#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F1 + +#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_WIDTH 8U +#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_257 +#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F1 + +#define LPDDR4__DENALI_PI_258_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_WIDTH 8U +#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_258 +#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRX_F2 + +#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_WIDTH 8U +#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_258 +#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRE_F2 + +#define LPDDR4__DENALI_PI_259_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_259_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_WIDTH 24U +#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_259 +#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_259__PI_TINIT_F0 + +#define LPDDR4__DENALI_PI_260_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_260_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_WIDTH 24U +#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_260 +#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_260__PI_TINIT3_F0 + +#define LPDDR4__DENALI_PI_261_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_261_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_WIDTH 24U +#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_261 +#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_261__PI_TINIT4_F0 + +#define LPDDR4__DENALI_PI_262_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_262_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_WIDTH 24U +#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_262 +#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_262__PI_TINIT5_F0 + +#define LPDDR4__DENALI_PI_263_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_263_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_WIDTH 16U +#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_263 +#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_263__PI_TXSNR_F0 + +#define LPDDR4__DENALI_PI_264_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_264_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_WIDTH 24U +#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_264 +#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_264__PI_TINIT_F1 + +#define LPDDR4__DENALI_PI_265_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_265_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_WIDTH 24U +#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_265 +#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_265__PI_TINIT3_F1 + +#define LPDDR4__DENALI_PI_266_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_WIDTH 24U +#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_266 +#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_266__PI_TINIT4_F1 + +#define LPDDR4__DENALI_PI_267_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_WIDTH 24U +#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_267 +#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_267__PI_TINIT5_F1 + +#define LPDDR4__DENALI_PI_268_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_WIDTH 16U +#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_268 +#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_268__PI_TXSNR_F1 + +#define LPDDR4__DENALI_PI_269_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_269_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_WIDTH 24U +#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_269 +#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_269__PI_TINIT_F2 + +#define LPDDR4__DENALI_PI_270_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_WIDTH 24U +#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_270 +#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_270__PI_TINIT3_F2 + +#define LPDDR4__DENALI_PI_271_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_WIDTH 24U +#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_271 +#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_271__PI_TINIT4_F2 + +#define LPDDR4__DENALI_PI_272_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_WIDTH 24U +#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_272 +#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_272__PI_TINIT5_F2 + +#define LPDDR4__DENALI_PI_273_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_273_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_WIDTH 16U +#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_273 +#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_273__PI_TXSNR_F2 + +#define LPDDR4__DENALI_PI_273__PI_RESERVED54_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_273__PI_RESERVED54_SHIFT 16U +#define LPDDR4__DENALI_PI_273__PI_RESERVED54_WIDTH 12U +#define LPDDR4__PI_RESERVED54__REG DENALI_PI_273 +#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_273__PI_RESERVED54 + +#define LPDDR4__DENALI_PI_274_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_274_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_274__PI_RESERVED55_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_274__PI_RESERVED55_SHIFT 0U +#define LPDDR4__DENALI_PI_274__PI_RESERVED55_WIDTH 12U +#define LPDDR4__PI_RESERVED55__REG DENALI_PI_274 +#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_274__PI_RESERVED55 + +#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_274 +#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_274__PI_TZQCAL_F0 + +#define LPDDR4__DENALI_PI_275_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_275_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_275 +#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_275__PI_TZQLAT_F0 + +#define LPDDR4__DENALI_PI_275__PI_RESERVED56_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_275__PI_RESERVED56_SHIFT 8U +#define LPDDR4__DENALI_PI_275__PI_RESERVED56_WIDTH 12U +#define LPDDR4__PI_RESERVED56__REG DENALI_PI_275 +#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_275__PI_RESERVED56 + +#define LPDDR4__DENALI_PI_276_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_276_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_276__PI_RESERVED57_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_276__PI_RESERVED57_SHIFT 0U +#define LPDDR4__DENALI_PI_276__PI_RESERVED57_WIDTH 12U +#define LPDDR4__PI_RESERVED57__REG DENALI_PI_276 +#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_276__PI_RESERVED57 + +#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_276 +#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_276__PI_TZQCAL_F1 + +#define LPDDR4__DENALI_PI_277_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_277_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_277 +#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_277__PI_TZQLAT_F1 + +#define LPDDR4__DENALI_PI_277__PI_RESERVED58_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_277__PI_RESERVED58_SHIFT 8U +#define LPDDR4__DENALI_PI_277__PI_RESERVED58_WIDTH 12U +#define LPDDR4__PI_RESERVED58__REG DENALI_PI_277 +#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_277__PI_RESERVED58 + +#define LPDDR4__DENALI_PI_278_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_278_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_278__PI_RESERVED59_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_278__PI_RESERVED59_SHIFT 0U +#define LPDDR4__DENALI_PI_278__PI_RESERVED59_WIDTH 12U +#define LPDDR4__PI_RESERVED59__REG DENALI_PI_278 +#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_278__PI_RESERVED59 + +#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_278 +#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_278__PI_TZQCAL_F2 + +#define LPDDR4__DENALI_PI_279_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_279_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_279 +#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_279__PI_TZQLAT_F2 + +#define LPDDR4__DENALI_PI_279__PI_RESERVED60_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_279__PI_RESERVED60_SHIFT 8U +#define LPDDR4__DENALI_PI_279__PI_RESERVED60_WIDTH 12U +#define LPDDR4__PI_RESERVED60__REG DENALI_PI_279 +#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_279__PI_RESERVED60 + +#define LPDDR4__DENALI_PI_280_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_280_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_280__PI_RESERVED61_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_280__PI_RESERVED61_SHIFT 0U +#define LPDDR4__DENALI_PI_280__PI_RESERVED61_WIDTH 12U +#define LPDDR4__PI_RESERVED61__REG DENALI_PI_280 +#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_280__PI_RESERVED61 + +#define LPDDR4__DENALI_PI_280__PI_RESERVED62_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_280__PI_RESERVED62_SHIFT 16U +#define LPDDR4__DENALI_PI_280__PI_RESERVED62_WIDTH 12U +#define LPDDR4__PI_RESERVED62__REG DENALI_PI_280 +#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_280__PI_RESERVED62 + +#define LPDDR4__DENALI_PI_281_READ_MASK 0x030F0F0FU +#define LPDDR4__DENALI_PI_281_WRITE_MASK 0x030F0F0FU +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_281 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0 + +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_281 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1 + +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_281 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2 + +#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_281 +#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0 + +#define LPDDR4__DENALI_PI_282_READ_MASK 0x07070303U +#define LPDDR4__DENALI_PI_282_WRITE_MASK 0x07070303U +#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_282 +#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1 + +#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_282 +#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2 + +#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_MASK 0x00070000U +#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_SHIFT 16U +#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_WIDTH 3U +#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_282 +#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0 + +#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_MASK 0x07000000U +#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_SHIFT 24U +#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_WIDTH 3U +#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_282 +#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1 + +#define LPDDR4__DENALI_PI_283_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_283_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_SHIFT 0U +#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_WIDTH 2U +#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_283 +#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0 + +#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_SHIFT 8U +#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_WIDTH 2U +#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_283 +#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0 + +#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_SHIFT 16U +#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_WIDTH 2U +#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_283 +#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1 + +#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_SHIFT 24U +#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_WIDTH 2U +#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_283 +#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1 + +#define LPDDR4__DENALI_PI_284_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_284_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_284 +#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0 + +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_SHIFT 8U +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_284 +#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1 + +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_284 +#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0 + +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_284 +#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1 + +#define LPDDR4__DENALI_PI_285_READ_MASK 0x3F3F0303U +#define LPDDR4__DENALI_PI_285_WRITE_MASK 0x3F3F0303U +#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_SHIFT 0U +#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_WIDTH 2U +#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_285 +#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0 + +#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_SHIFT 8U +#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_WIDTH 2U +#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_285 +#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1 + +#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_285 +#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0 + +#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1 + +#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFF3F3FU +#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFF3F3FU +#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_286 +#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0 + +#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_SHIFT 8U +#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1 + +#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_286 +#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR13_DATA_0 + +#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_286 +#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR15_DATA_0 + +#define LPDDR4__DENALI_PI_287_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_287_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_287 +#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR16_DATA_0 + +#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_287 +#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR17_DATA_0 + +#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_287 +#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR20_DATA_0 + +#define LPDDR4__DENALI_PI_288_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_WIDTH 17U +#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_288 +#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR32_DATA_0 + +#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_288 +#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR40_DATA_0 + +#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_289 +#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR13_DATA_1 + +#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_SHIFT 8U +#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_289 +#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR15_DATA_1 + +#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_289 +#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR16_DATA_1 + +#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_289 +#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR17_DATA_1 + +#define LPDDR4__DENALI_PI_290_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_290_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_290 +#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR20_DATA_1 + +#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_MASK 0x01FFFF00U +#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_SHIFT 8U +#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_WIDTH 17U +#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_290 +#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR32_DATA_1 + +#define LPDDR4__DENALI_PI_291_READ_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_PI_291_WRITE_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_291 +#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_291__PI_MR40_DATA_1 + +#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_SHIFT 8U +#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_WIDTH 5U +#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_291 +#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_0 + +#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_SHIFT 16U +#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_WIDTH 5U +#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_291 +#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_1 + +#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_WIDTH 5U +#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_291 +#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CS_MUX_0 + +#define LPDDR4__DENALI_PI_292_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_292_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_WIDTH 5U +#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_292 +#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_CS_MUX_1 + +#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_SHIFT 8U +#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_WIDTH 5U +#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_292 +#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_0 + +#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_SHIFT 16U +#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_WIDTH 5U +#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_292 +#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_1 + +#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_WIDTH 5U +#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_292 +#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0 + +#define LPDDR4__DENALI_PI_293_READ_MASK 0x01FFFF1FU +#define LPDDR4__DENALI_PI_293_WRITE_MASK 0x01FFFF1FU +#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_WIDTH 5U +#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_293 +#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1 + +#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_WIDTH 17U +#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_293 +#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_PI_294_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_PI_294_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_WIDTH 17U +#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_294 +#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_WIDTH 2U +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_294 +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_PI_295_READ_MASK 0x00030303U +#define LPDDR4__DENALI_PI_295_WRITE_MASK 0x00030303U +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 2U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_295 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_SHIFT 8U +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_WIDTH 2U +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_295 +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 2U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_295 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_296 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0 + +#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 16U +#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_296 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1 + +#define LPDDR4__DENALI_PI_297_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_297_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_297 +#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0 + +#define LPDDR4__DENALI_PI_298_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_298_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_298 +#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0 + +#define LPDDR4__DENALI_PI_299_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_299 +#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0 + +#define LPDDR4__DENALI_PI_300_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_300_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_300 +#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0 + +#define LPDDR4__DENALI_PI_301_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_301_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_301 +#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0 + +#define LPDDR4__DENALI_PI_302_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_302_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_302 +#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0 + +#define LPDDR4__DENALI_PI_303_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_303_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_303 +#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0 + +#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_303 +#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0 + +#define LPDDR4__DENALI_PI_304_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_304_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_304 +#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0 + +#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_304 +#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0 + +#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_304 +#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0 + +#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_304 +#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0 + +#define LPDDR4__DENALI_PI_305_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_305_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_305 +#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0 + +#define LPDDR4__DENALI_PI_306_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_306_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_306 +#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0 + +#define LPDDR4__DENALI_PI_307_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_307_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_307 +#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0 + +#define LPDDR4__DENALI_PI_308_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_308_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_308 +#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0 + +#define LPDDR4__DENALI_PI_309_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_309_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_309 +#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0 + +#define LPDDR4__DENALI_PI_310_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_310_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_310 +#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0 + +#define LPDDR4__DENALI_PI_311_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_311_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_311 +#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0 + +#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_311 +#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0 + +#define LPDDR4__DENALI_PI_312_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_312_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_312 +#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0 + +#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_SHIFT 8U +#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_312 +#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0 + +#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_312 +#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0 + +#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_312 +#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0 + +#define LPDDR4__DENALI_PI_313_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_313_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_313 +#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0 + +#define LPDDR4__DENALI_PI_314_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_314_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_314 +#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0 + +#define LPDDR4__DENALI_PI_315_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_315_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_315 +#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0 + +#define LPDDR4__DENALI_PI_316_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_316_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_316 +#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0 + +#define LPDDR4__DENALI_PI_317_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_317_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_317 +#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0 + +#define LPDDR4__DENALI_PI_318_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_318_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_318 +#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0 + +#define LPDDR4__DENALI_PI_319_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_319_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_319 +#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0 + +#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_319 +#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0 + +#define LPDDR4__DENALI_PI_320_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_320_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_320 +#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0 + +#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_320 +#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0 + +#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_320 +#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0 + +#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_320 +#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0 + +#define LPDDR4__DENALI_PI_321_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_321_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_321 +#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1 + +#define LPDDR4__DENALI_PI_322_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_322_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_322 +#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1 + +#define LPDDR4__DENALI_PI_323_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_323_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_323 +#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1 + +#define LPDDR4__DENALI_PI_324_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_324_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_324 +#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1 + +#define LPDDR4__DENALI_PI_325_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_325_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_325 +#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1 + +#define LPDDR4__DENALI_PI_326_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_326_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_326 +#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1 + +#define LPDDR4__DENALI_PI_327_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_327_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_327 +#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1 + +#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_327 +#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1 + +#define LPDDR4__DENALI_PI_328_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_328_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_328 +#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1 + +#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_328 +#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1 + +#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_328 +#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1 + +#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_328 +#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1 + +#define LPDDR4__DENALI_PI_329_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_329_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_329 +#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1 + +#define LPDDR4__DENALI_PI_330_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_330_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_330 +#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1 + +#define LPDDR4__DENALI_PI_331_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_331_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_331 +#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1 + +#define LPDDR4__DENALI_PI_332_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_332_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_332 +#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1 + +#define LPDDR4__DENALI_PI_333_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_333_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_333 +#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1 + +#define LPDDR4__DENALI_PI_334_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_334_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_334 +#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1 + +#define LPDDR4__DENALI_PI_335_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_335_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_335 +#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1 + +#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_335 +#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1 + +#define LPDDR4__DENALI_PI_336_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_336_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_336 +#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1 + +#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_336 +#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1 + +#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_336 +#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1 + +#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_336 +#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1 + +#define LPDDR4__DENALI_PI_337_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_337_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_337 +#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1 + +#define LPDDR4__DENALI_PI_338_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_338_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_338 +#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1 + +#define LPDDR4__DENALI_PI_339_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_339_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_339 +#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1 + +#define LPDDR4__DENALI_PI_340_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_340_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_340 +#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1 + +#define LPDDR4__DENALI_PI_341_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_341_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_341 +#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1 + +#define LPDDR4__DENALI_PI_342_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_342_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_342 +#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1 + +#define LPDDR4__DENALI_PI_343_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_343_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_343 +#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1 + +#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_343 +#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1 + +#define LPDDR4__DENALI_PI_344_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_344_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_344 +#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1 + +#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_344 +#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1 + +#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_344 +#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1 + +#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_344 +#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1 + +#endif /* REG_LPDDR4_PI_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h new file mode 100644 index 000000000..f14ca245e --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_32BIT_IF_H +#define LPDDR4_32BIT_IF_H + +#include + +#define LPDDR4_INTR_MAX_CS (2U) + +#define LPDDR4_INTR_CTL_REG_COUNT (459U) + +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (300U) + +#define LPDDR4_INTR_PHY_REG_COUNT (1423U) + +typedef enum { + LPDDR4_INTR_RESET_DONE = 0U, + LPDDR4_INTR_BUS_ACCESS_ERROR = 1U, + LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR = 2U, + LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR = 3U, + LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR = 4U, + LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR = 5U, + LPDDR4_INTR_ECC_SCRUB_DONE = 6U, + LPDDR4_INTR_ECC_SCRUB_ERROR = 7U, + LPDDR4_INTR_PORT_COMMAND_ERROR = 8U, + LPDDR4_INTR_MC_INIT_DONE = 9U, + LPDDR4_INTR_LP_DONE = 10U, + LPDDR4_INTR_BIST_DONE = 11U, + LPDDR4_INTR_WRAP_ERROR = 12U, + LPDDR4_INTR_INVALID_BURST_ERROR = 13U, + LPDDR4_INTR_RDLVL_ERROR = 14U, + LPDDR4_INTR_RDLVL_GATE_ERROR = 15U, + LPDDR4_INTR_WRLVL_ERROR = 16U, + LPDDR4_INTR_CA_TRAINING_ERROR = 17U, + LPDDR4_INTR_DFI_UPDATE_ERROR = 18U, + LPDDR4_INTR_MRR_ERROR = 19U, + LPDDR4_INTR_PHY_MASTER_ERROR = 20U, + LPDDR4_INTR_WRLVL_REQ = 21U, + LPDDR4_INTR_RDLVL_REQ = 22U, + LPDDR4_INTR_RDLVL_GATE_REQ = 23U, + LPDDR4_INTR_CA_TRAINING_REQ = 24U, + LPDDR4_INTR_LEVELING_DONE = 25U, + LPDDR4_INTR_PHY_ERROR = 26U, + LPDDR4_INTR_MR_READ_DONE = 27U, + LPDDR4_INTR_TEMP_CHANGE = 28U, + LPDDR4_INTR_TEMP_ALERT = 29U, + LPDDR4_INTR_SW_DQS_COMPLETE = 30U, + LPDDR4_INTR_DQS_OSC_BV_UPDATED = 31U, + LPDDR4_INTR_DQS_OSC_OVERFLOW = 32U, + LPDDR4_INTR_DQS_OSC_VAR_OUT = 33U, + LPDDR4_INTR_MR_WRITE_DONE = 34U, + LPDDR4_INTR_INHIBIT_DRAM_DONE = 35U, + LPDDR4_INTR_DFI_INIT_STATE = 36U, + LPDDR4_INTR_DLL_RESYNC_DONE = 37U, + LPDDR4_INTR_TDFI_TO = 38U, + LPDDR4_INTR_DFS_DONE = 39U, + LPDDR4_INTR_DFS_STATUS = 40U, + LPDDR4_INTR_REFRESH_STATUS = 41U, + LPDDR4_INTR_ZQ_STATUS = 42U, + LPDDR4_INTR_SW_REQ_MODE = 43U, + LPDDR4_INTR_LOR_BITS = 44U +} lpddr4_intr_ctlinterrupt; + +typedef enum { + LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U, + LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT = 1U, + LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 2U, + LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 3U, + LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 4U, + LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 5U, + LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 6U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 7U, + LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 8U, + LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 9U, + LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U, + LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 11U, + LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 12U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 13U, + LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 14U, + LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 15U, + LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U, + LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U +} lpddr4_intr_phyindepinterrupt; + +#endif /* LPDDR4_32BIT_IF_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h new file mode 100644 index 000000000..7fee54f00 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_32BIT_OBJ_IF_H +#define LPDDR4_32BIT_OBJ_IF_H + +#include "lpddr4_32bit_if.h" + +#endif /* LPDDR4_32BIT_OBJ_IF_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h new file mode 100644 index 000000000..69b2a47ab --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_32BIT_STRUCTS_IF_H +#define LPDDR4_32BIT_STRUCTS_IF_H + +#include +#include "lpddr4_32bit_if.h" + +#endif /* LPDDR4_32BIT_STRUCTS_IF_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h new file mode 100644 index 000000000..58ba340e7 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h @@ -0,0 +1,824 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031 +#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032 +#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0 + +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0 + +#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036 +#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0 + +#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0 + +#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0 + +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041 +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0 + +#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042 +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0 + +#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043 +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0 + +#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044 +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0 + +#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045 +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0 + +#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046 +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0 + +#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047 +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0 + +#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048 +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0 + +#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049 +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0 + +#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050 +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0 + +#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051 +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0 + +#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052 +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0 + +#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U +#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053 +#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0 + +#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0 + +#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U +#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0 + +#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0 + +#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U +#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0 + +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0 + +#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061 +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_WIDTH 9U +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061 +#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U +#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U +#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH 9U +#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1062 +#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOSET 0U +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_1062 +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOSET 0U +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_1062 +#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOSET 0U +#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063 +#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1068 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1069 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1070 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1074 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1074 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074 +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1075 +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1075 +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h new file mode 100644 index 000000000..411360843 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h @@ -0,0 +1,1545 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_CTL_REGS_H_ +#define REG_LPDDR4_CTL_REGS_H_ + +#include "lpddr4_ddr_controller_macros.h" +#include "lpddr4_pi_macros.h" +#include "lpddr4_data_slice_0_macros.h" +#include "lpddr4_data_slice_1_macros.h" +#include "lpddr4_data_slice_2_macros.h" +#include "lpddr4_data_slice_3_macros.h" +#include "lpddr4_address_slice_0_macros.h" +#include "lpddr4_phy_core_macros.h" + +typedef struct __attribute__((packed)) lpddr4_ctlregs_s { + volatile u32 DENALI_CTL_0; + volatile u32 DENALI_CTL_1; + volatile u32 DENALI_CTL_2; + volatile u32 DENALI_CTL_3; + volatile u32 DENALI_CTL_4; + volatile u32 DENALI_CTL_5; + volatile u32 DENALI_CTL_6; + volatile u32 DENALI_CTL_7; + volatile u32 DENALI_CTL_8; + volatile u32 DENALI_CTL_9; + volatile u32 DENALI_CTL_10; + volatile u32 DENALI_CTL_11; + volatile u32 DENALI_CTL_12; + volatile u32 DENALI_CTL_13; + volatile u32 DENALI_CTL_14; + volatile u32 DENALI_CTL_15; + volatile u32 DENALI_CTL_16; + volatile u32 DENALI_CTL_17; + volatile u32 DENALI_CTL_18; + volatile u32 DENALI_CTL_19; + volatile u32 DENALI_CTL_20; + volatile u32 DENALI_CTL_21; + volatile u32 DENALI_CTL_22; + volatile u32 DENALI_CTL_23; + volatile u32 DENALI_CTL_24; + volatile u32 DENALI_CTL_25; + volatile u32 DENALI_CTL_26; + volatile u32 DENALI_CTL_27; + volatile u32 DENALI_CTL_28; + volatile u32 DENALI_CTL_29; + volatile u32 DENALI_CTL_30; + volatile u32 DENALI_CTL_31; + volatile u32 DENALI_CTL_32; + volatile u32 DENALI_CTL_33; + volatile u32 DENALI_CTL_34; + volatile u32 DENALI_CTL_35; + volatile u32 DENALI_CTL_36; + volatile u32 DENALI_CTL_37; + volatile u32 DENALI_CTL_38; + volatile u32 DENALI_CTL_39; + volatile u32 DENALI_CTL_40; + volatile u32 DENALI_CTL_41; + volatile u32 DENALI_CTL_42; + volatile u32 DENALI_CTL_43; + volatile u32 DENALI_CTL_44; + volatile u32 DENALI_CTL_45; + volatile u32 DENALI_CTL_46; + volatile u32 DENALI_CTL_47; + volatile u32 DENALI_CTL_48; + volatile u32 DENALI_CTL_49; + volatile u32 DENALI_CTL_50; + volatile u32 DENALI_CTL_51; + volatile u32 DENALI_CTL_52; + volatile u32 DENALI_CTL_53; + volatile u32 DENALI_CTL_54; + volatile u32 DENALI_CTL_55; + volatile u32 DENALI_CTL_56; + volatile u32 DENALI_CTL_57; + volatile u32 DENALI_CTL_58; + volatile u32 DENALI_CTL_59; + volatile u32 DENALI_CTL_60; + volatile u32 DENALI_CTL_61; + volatile u32 DENALI_CTL_62; + volatile u32 DENALI_CTL_63; + volatile u32 DENALI_CTL_64; + volatile u32 DENALI_CTL_65; + volatile u32 DENALI_CTL_66; + volatile u32 DENALI_CTL_67; + volatile u32 DENALI_CTL_68; + volatile u32 DENALI_CTL_69; + volatile u32 DENALI_CTL_70; + volatile u32 DENALI_CTL_71; + volatile u32 DENALI_CTL_72; + volatile u32 DENALI_CTL_73; + volatile u32 DENALI_CTL_74; + volatile u32 DENALI_CTL_75; + volatile u32 DENALI_CTL_76; + volatile u32 DENALI_CTL_77; + volatile u32 DENALI_CTL_78; + volatile u32 DENALI_CTL_79; + volatile u32 DENALI_CTL_80; + volatile u32 DENALI_CTL_81; + volatile u32 DENALI_CTL_82; + volatile u32 DENALI_CTL_83; + volatile u32 DENALI_CTL_84; + volatile u32 DENALI_CTL_85; + volatile u32 DENALI_CTL_86; + volatile u32 DENALI_CTL_87; + volatile u32 DENALI_CTL_88; + volatile u32 DENALI_CTL_89; + volatile u32 DENALI_CTL_90; + volatile u32 DENALI_CTL_91; + volatile u32 DENALI_CTL_92; + volatile u32 DENALI_CTL_93; + volatile u32 DENALI_CTL_94; + volatile u32 DENALI_CTL_95; + volatile u32 DENALI_CTL_96; + volatile u32 DENALI_CTL_97; + volatile u32 DENALI_CTL_98; + volatile u32 DENALI_CTL_99; + volatile u32 DENALI_CTL_100; + volatile u32 DENALI_CTL_101; + volatile u32 DENALI_CTL_102; + volatile u32 DENALI_CTL_103; + volatile u32 DENALI_CTL_104; + volatile u32 DENALI_CTL_105; + volatile u32 DENALI_CTL_106; + volatile u32 DENALI_CTL_107; + volatile u32 DENALI_CTL_108; + volatile u32 DENALI_CTL_109; + volatile u32 DENALI_CTL_110; + volatile u32 DENALI_CTL_111; + volatile u32 DENALI_CTL_112; + volatile u32 DENALI_CTL_113; + volatile u32 DENALI_CTL_114; + volatile u32 DENALI_CTL_115; + volatile u32 DENALI_CTL_116; + volatile u32 DENALI_CTL_117; + volatile u32 DENALI_CTL_118; + volatile u32 DENALI_CTL_119; + volatile u32 DENALI_CTL_120; + volatile u32 DENALI_CTL_121; + volatile u32 DENALI_CTL_122; + volatile u32 DENALI_CTL_123; + volatile u32 DENALI_CTL_124; + volatile u32 DENALI_CTL_125; + volatile u32 DENALI_CTL_126; + volatile u32 DENALI_CTL_127; + volatile u32 DENALI_CTL_128; + volatile u32 DENALI_CTL_129; + volatile u32 DENALI_CTL_130; + volatile u32 DENALI_CTL_131; + volatile u32 DENALI_CTL_132; + volatile u32 DENALI_CTL_133; + volatile u32 DENALI_CTL_134; + volatile u32 DENALI_CTL_135; + volatile u32 DENALI_CTL_136; + volatile u32 DENALI_CTL_137; + volatile u32 DENALI_CTL_138; + volatile u32 DENALI_CTL_139; + volatile u32 DENALI_CTL_140; + volatile u32 DENALI_CTL_141; + volatile u32 DENALI_CTL_142; + volatile u32 DENALI_CTL_143; + volatile u32 DENALI_CTL_144; + volatile u32 DENALI_CTL_145; + volatile u32 DENALI_CTL_146; + volatile u32 DENALI_CTL_147; + volatile u32 DENALI_CTL_148; + volatile u32 DENALI_CTL_149; + volatile u32 DENALI_CTL_150; + volatile u32 DENALI_CTL_151; + volatile u32 DENALI_CTL_152; + volatile u32 DENALI_CTL_153; + volatile u32 DENALI_CTL_154; + volatile u32 DENALI_CTL_155; + volatile u32 DENALI_CTL_156; + volatile u32 DENALI_CTL_157; + volatile u32 DENALI_CTL_158; + volatile u32 DENALI_CTL_159; + volatile u32 DENALI_CTL_160; + volatile u32 DENALI_CTL_161; + volatile u32 DENALI_CTL_162; + volatile u32 DENALI_CTL_163; + volatile u32 DENALI_CTL_164; + volatile u32 DENALI_CTL_165; + volatile u32 DENALI_CTL_166; + volatile u32 DENALI_CTL_167; + volatile u32 DENALI_CTL_168; + volatile u32 DENALI_CTL_169; + volatile u32 DENALI_CTL_170; + volatile u32 DENALI_CTL_171; + volatile u32 DENALI_CTL_172; + volatile u32 DENALI_CTL_173; + volatile u32 DENALI_CTL_174; + volatile u32 DENALI_CTL_175; + volatile u32 DENALI_CTL_176; + volatile u32 DENALI_CTL_177; + volatile u32 DENALI_CTL_178; + volatile u32 DENALI_CTL_179; + volatile u32 DENALI_CTL_180; + volatile u32 DENALI_CTL_181; + volatile u32 DENALI_CTL_182; + volatile u32 DENALI_CTL_183; + volatile u32 DENALI_CTL_184; + volatile u32 DENALI_CTL_185; + volatile u32 DENALI_CTL_186; + volatile u32 DENALI_CTL_187; + volatile u32 DENALI_CTL_188; + volatile u32 DENALI_CTL_189; + volatile u32 DENALI_CTL_190; + volatile u32 DENALI_CTL_191; + volatile u32 DENALI_CTL_192; + volatile u32 DENALI_CTL_193; + volatile u32 DENALI_CTL_194; + volatile u32 DENALI_CTL_195; + volatile u32 DENALI_CTL_196; + volatile u32 DENALI_CTL_197; + volatile u32 DENALI_CTL_198; + volatile u32 DENALI_CTL_199; + volatile u32 DENALI_CTL_200; + volatile u32 DENALI_CTL_201; + volatile u32 DENALI_CTL_202; + volatile u32 DENALI_CTL_203; + volatile u32 DENALI_CTL_204; + volatile u32 DENALI_CTL_205; + volatile u32 DENALI_CTL_206; + volatile u32 DENALI_CTL_207; + volatile u32 DENALI_CTL_208; + volatile u32 DENALI_CTL_209; + volatile u32 DENALI_CTL_210; + volatile u32 DENALI_CTL_211; + volatile u32 DENALI_CTL_212; + volatile u32 DENALI_CTL_213; + volatile u32 DENALI_CTL_214; + volatile u32 DENALI_CTL_215; + volatile u32 DENALI_CTL_216; + volatile u32 DENALI_CTL_217; + volatile u32 DENALI_CTL_218; + volatile u32 DENALI_CTL_219; + volatile u32 DENALI_CTL_220; + volatile u32 DENALI_CTL_221; + volatile u32 DENALI_CTL_222; + volatile u32 DENALI_CTL_223; + volatile u32 DENALI_CTL_224; + volatile u32 DENALI_CTL_225; + volatile u32 DENALI_CTL_226; + volatile u32 DENALI_CTL_227; + volatile u32 DENALI_CTL_228; + volatile u32 DENALI_CTL_229; + volatile u32 DENALI_CTL_230; + volatile u32 DENALI_CTL_231; + volatile u32 DENALI_CTL_232; + volatile u32 DENALI_CTL_233; + volatile u32 DENALI_CTL_234; + volatile u32 DENALI_CTL_235; + volatile u32 DENALI_CTL_236; + volatile u32 DENALI_CTL_237; + volatile u32 DENALI_CTL_238; + volatile u32 DENALI_CTL_239; + volatile u32 DENALI_CTL_240; + volatile u32 DENALI_CTL_241; + volatile u32 DENALI_CTL_242; + volatile u32 DENALI_CTL_243; + volatile u32 DENALI_CTL_244; + volatile u32 DENALI_CTL_245; + volatile u32 DENALI_CTL_246; + volatile u32 DENALI_CTL_247; + volatile u32 DENALI_CTL_248; + volatile u32 DENALI_CTL_249; + volatile u32 DENALI_CTL_250; + volatile u32 DENALI_CTL_251; + volatile u32 DENALI_CTL_252; + volatile u32 DENALI_CTL_253; + volatile u32 DENALI_CTL_254; + volatile u32 DENALI_CTL_255; + volatile u32 DENALI_CTL_256; + volatile u32 DENALI_CTL_257; + volatile u32 DENALI_CTL_258; + volatile u32 DENALI_CTL_259; + volatile u32 DENALI_CTL_260; + volatile u32 DENALI_CTL_261; + volatile u32 DENALI_CTL_262; + volatile u32 DENALI_CTL_263; + volatile u32 DENALI_CTL_264; + volatile u32 DENALI_CTL_265; + volatile u32 DENALI_CTL_266; + volatile u32 DENALI_CTL_267; + volatile u32 DENALI_CTL_268; + volatile u32 DENALI_CTL_269; + volatile u32 DENALI_CTL_270; + volatile u32 DENALI_CTL_271; + volatile u32 DENALI_CTL_272; + volatile u32 DENALI_CTL_273; + volatile u32 DENALI_CTL_274; + volatile u32 DENALI_CTL_275; + volatile u32 DENALI_CTL_276; + volatile u32 DENALI_CTL_277; + volatile u32 DENALI_CTL_278; + volatile u32 DENALI_CTL_279; + volatile u32 DENALI_CTL_280; + volatile u32 DENALI_CTL_281; + volatile u32 DENALI_CTL_282; + volatile u32 DENALI_CTL_283; + volatile u32 DENALI_CTL_284; + volatile u32 DENALI_CTL_285; + volatile u32 DENALI_CTL_286; + volatile u32 DENALI_CTL_287; + volatile u32 DENALI_CTL_288; + volatile u32 DENALI_CTL_289; + volatile u32 DENALI_CTL_290; + volatile u32 DENALI_CTL_291; + volatile u32 DENALI_CTL_292; + volatile u32 DENALI_CTL_293; + volatile u32 DENALI_CTL_294; + volatile u32 DENALI_CTL_295; + volatile u32 DENALI_CTL_296; + volatile u32 DENALI_CTL_297; + volatile u32 DENALI_CTL_298; + volatile u32 DENALI_CTL_299; + volatile u32 DENALI_CTL_300; + volatile u32 DENALI_CTL_301; + volatile u32 DENALI_CTL_302; + volatile u32 DENALI_CTL_303; + volatile u32 DENALI_CTL_304; + volatile u32 DENALI_CTL_305; + volatile u32 DENALI_CTL_306; + volatile u32 DENALI_CTL_307; + volatile u32 DENALI_CTL_308; + volatile u32 DENALI_CTL_309; + volatile u32 DENALI_CTL_310; + volatile u32 DENALI_CTL_311; + volatile u32 DENALI_CTL_312; + volatile u32 DENALI_CTL_313; + volatile u32 DENALI_CTL_314; + volatile u32 DENALI_CTL_315; + volatile u32 DENALI_CTL_316; + volatile u32 DENALI_CTL_317; + volatile u32 DENALI_CTL_318; + volatile u32 DENALI_CTL_319; + volatile u32 DENALI_CTL_320; + volatile u32 DENALI_CTL_321; + volatile u32 DENALI_CTL_322; + volatile u32 DENALI_CTL_323; + volatile u32 DENALI_CTL_324; + volatile u32 DENALI_CTL_325; + volatile u32 DENALI_CTL_326; + volatile u32 DENALI_CTL_327; + volatile u32 DENALI_CTL_328; + volatile u32 DENALI_CTL_329; + volatile u32 DENALI_CTL_330; + volatile u32 DENALI_CTL_331; + volatile u32 DENALI_CTL_332; + volatile u32 DENALI_CTL_333; + volatile u32 DENALI_CTL_334; + volatile u32 DENALI_CTL_335; + volatile u32 DENALI_CTL_336; + volatile u32 DENALI_CTL_337; + volatile u32 DENALI_CTL_338; + volatile u32 DENALI_CTL_339; + volatile u32 DENALI_CTL_340; + volatile u32 DENALI_CTL_341; + volatile u32 DENALI_CTL_342; + volatile u32 DENALI_CTL_343; + volatile u32 DENALI_CTL_344; + volatile u32 DENALI_CTL_345; + volatile u32 DENALI_CTL_346; + volatile u32 DENALI_CTL_347; + volatile u32 DENALI_CTL_348; + volatile u32 DENALI_CTL_349; + volatile u32 DENALI_CTL_350; + volatile u32 DENALI_CTL_351; + volatile u32 DENALI_CTL_352; + volatile u32 DENALI_CTL_353; + volatile u32 DENALI_CTL_354; + volatile u32 DENALI_CTL_355; + volatile u32 DENALI_CTL_356; + volatile u32 DENALI_CTL_357; + volatile u32 DENALI_CTL_358; + volatile u32 DENALI_CTL_359; + volatile u32 DENALI_CTL_360; + volatile u32 DENALI_CTL_361; + volatile u32 DENALI_CTL_362; + volatile u32 DENALI_CTL_363; + volatile u32 DENALI_CTL_364; + volatile u32 DENALI_CTL_365; + volatile u32 DENALI_CTL_366; + volatile u32 DENALI_CTL_367; + volatile u32 DENALI_CTL_368; + volatile u32 DENALI_CTL_369; + volatile u32 DENALI_CTL_370; + volatile u32 DENALI_CTL_371; + volatile u32 DENALI_CTL_372; + volatile u32 DENALI_CTL_373; + volatile u32 DENALI_CTL_374; + volatile u32 DENALI_CTL_375; + volatile u32 DENALI_CTL_376; + volatile u32 DENALI_CTL_377; + volatile u32 DENALI_CTL_378; + volatile u32 DENALI_CTL_379; + volatile u32 DENALI_CTL_380; + volatile u32 DENALI_CTL_381; + volatile u32 DENALI_CTL_382; + volatile u32 DENALI_CTL_383; + volatile u32 DENALI_CTL_384; + volatile u32 DENALI_CTL_385; + volatile u32 DENALI_CTL_386; + volatile u32 DENALI_CTL_387; + volatile u32 DENALI_CTL_388; + volatile u32 DENALI_CTL_389; + volatile u32 DENALI_CTL_390; + volatile u32 DENALI_CTL_391; + volatile u32 DENALI_CTL_392; + volatile u32 DENALI_CTL_393; + volatile u32 DENALI_CTL_394; + volatile u32 DENALI_CTL_395; + volatile u32 DENALI_CTL_396; + volatile u32 DENALI_CTL_397; + volatile u32 DENALI_CTL_398; + volatile u32 DENALI_CTL_399; + volatile u32 DENALI_CTL_400; + volatile u32 DENALI_CTL_401; + volatile u32 DENALI_CTL_402; + volatile u32 DENALI_CTL_403; + volatile u32 DENALI_CTL_404; + volatile u32 DENALI_CTL_405; + volatile u32 DENALI_CTL_406; + volatile u32 DENALI_CTL_407; + volatile u32 DENALI_CTL_408; + volatile u32 DENALI_CTL_409; + volatile u32 DENALI_CTL_410; + volatile u32 DENALI_CTL_411; + volatile u32 DENALI_CTL_412; + volatile u32 DENALI_CTL_413; + volatile u32 DENALI_CTL_414; + volatile u32 DENALI_CTL_415; + volatile u32 DENALI_CTL_416; + volatile u32 DENALI_CTL_417; + volatile u32 DENALI_CTL_418; + volatile u32 DENALI_CTL_419; + volatile u32 DENALI_CTL_420; + volatile u32 DENALI_CTL_421; + volatile u32 DENALI_CTL_422; + volatile u32 DENALI_CTL_423; + volatile u32 DENALI_CTL_424; + volatile u32 DENALI_CTL_425; + volatile u32 DENALI_CTL_426; + volatile u32 DENALI_CTL_427; + volatile u32 DENALI_CTL_428; + volatile u32 DENALI_CTL_429; + volatile u32 DENALI_CTL_430; + volatile u32 DENALI_CTL_431; + volatile u32 DENALI_CTL_432; + volatile u32 DENALI_CTL_433; + volatile u32 DENALI_CTL_434; + volatile u32 DENALI_CTL_435; + volatile u32 DENALI_CTL_436; + volatile u32 DENALI_CTL_437; + volatile u32 DENALI_CTL_438; + volatile u32 DENALI_CTL_439; + volatile u32 DENALI_CTL_440; + volatile u32 DENALI_CTL_441; + volatile u32 DENALI_CTL_442; + volatile u32 DENALI_CTL_443; + volatile u32 DENALI_CTL_444; + volatile u32 DENALI_CTL_445; + volatile u32 DENALI_CTL_446; + volatile u32 DENALI_CTL_447; + volatile u32 DENALI_CTL_448; + volatile u32 DENALI_CTL_449; + volatile u32 DENALI_CTL_450; + volatile u32 DENALI_CTL_451; + volatile u32 DENALI_CTL_452; + volatile u32 DENALI_CTL_453; + volatile u32 DENALI_CTL_454; + volatile u32 DENALI_CTL_455; + volatile u32 DENALI_CTL_456; + volatile u32 DENALI_CTL_457; + volatile u32 DENALI_CTL_458; + volatile char pad__0[0x18D4U]; + volatile u32 DENALI_PI_0; + volatile u32 DENALI_PI_1; + volatile u32 DENALI_PI_2; + volatile u32 DENALI_PI_3; + volatile u32 DENALI_PI_4; + volatile u32 DENALI_PI_5; + volatile u32 DENALI_PI_6; + volatile u32 DENALI_PI_7; + volatile u32 DENALI_PI_8; + volatile u32 DENALI_PI_9; + volatile u32 DENALI_PI_10; + volatile u32 DENALI_PI_11; + volatile u32 DENALI_PI_12; + volatile u32 DENALI_PI_13; + volatile u32 DENALI_PI_14; + volatile u32 DENALI_PI_15; + volatile u32 DENALI_PI_16; + volatile u32 DENALI_PI_17; + volatile u32 DENALI_PI_18; + volatile u32 DENALI_PI_19; + volatile u32 DENALI_PI_20; + volatile u32 DENALI_PI_21; + volatile u32 DENALI_PI_22; + volatile u32 DENALI_PI_23; + volatile u32 DENALI_PI_24; + volatile u32 DENALI_PI_25; + volatile u32 DENALI_PI_26; + volatile u32 DENALI_PI_27; + volatile u32 DENALI_PI_28; + volatile u32 DENALI_PI_29; + volatile u32 DENALI_PI_30; + volatile u32 DENALI_PI_31; + volatile u32 DENALI_PI_32; + volatile u32 DENALI_PI_33; + volatile u32 DENALI_PI_34; + volatile u32 DENALI_PI_35; + volatile u32 DENALI_PI_36; + volatile u32 DENALI_PI_37; + volatile u32 DENALI_PI_38; + volatile u32 DENALI_PI_39; + volatile u32 DENALI_PI_40; + volatile u32 DENALI_PI_41; + volatile u32 DENALI_PI_42; + volatile u32 DENALI_PI_43; + volatile u32 DENALI_PI_44; + volatile u32 DENALI_PI_45; + volatile u32 DENALI_PI_46; + volatile u32 DENALI_PI_47; + volatile u32 DENALI_PI_48; + volatile u32 DENALI_PI_49; + volatile u32 DENALI_PI_50; + volatile u32 DENALI_PI_51; + volatile u32 DENALI_PI_52; + volatile u32 DENALI_PI_53; + volatile u32 DENALI_PI_54; + volatile u32 DENALI_PI_55; + volatile u32 DENALI_PI_56; + volatile u32 DENALI_PI_57; + volatile u32 DENALI_PI_58; + volatile u32 DENALI_PI_59; + volatile u32 DENALI_PI_60; + volatile u32 DENALI_PI_61; + volatile u32 DENALI_PI_62; + volatile u32 DENALI_PI_63; + volatile u32 DENALI_PI_64; + volatile u32 DENALI_PI_65; + volatile u32 DENALI_PI_66; + volatile u32 DENALI_PI_67; + volatile u32 DENALI_PI_68; + volatile u32 DENALI_PI_69; + volatile u32 DENALI_PI_70; + volatile u32 DENALI_PI_71; + volatile u32 DENALI_PI_72; + volatile u32 DENALI_PI_73; + volatile u32 DENALI_PI_74; + volatile u32 DENALI_PI_75; + volatile u32 DENALI_PI_76; + volatile u32 DENALI_PI_77; + volatile u32 DENALI_PI_78; + volatile u32 DENALI_PI_79; + volatile u32 DENALI_PI_80; + volatile u32 DENALI_PI_81; + volatile u32 DENALI_PI_82; + volatile u32 DENALI_PI_83; + volatile u32 DENALI_PI_84; + volatile u32 DENALI_PI_85; + volatile u32 DENALI_PI_86; + volatile u32 DENALI_PI_87; + volatile u32 DENALI_PI_88; + volatile u32 DENALI_PI_89; + volatile u32 DENALI_PI_90; + volatile u32 DENALI_PI_91; + volatile u32 DENALI_PI_92; + volatile u32 DENALI_PI_93; + volatile u32 DENALI_PI_94; + volatile u32 DENALI_PI_95; + volatile u32 DENALI_PI_96; + volatile u32 DENALI_PI_97; + volatile u32 DENALI_PI_98; + volatile u32 DENALI_PI_99; + volatile u32 DENALI_PI_100; + volatile u32 DENALI_PI_101; + volatile u32 DENALI_PI_102; + volatile u32 DENALI_PI_103; + volatile u32 DENALI_PI_104; + volatile u32 DENALI_PI_105; + volatile u32 DENALI_PI_106; + volatile u32 DENALI_PI_107; + volatile u32 DENALI_PI_108; + volatile u32 DENALI_PI_109; + volatile u32 DENALI_PI_110; + volatile u32 DENALI_PI_111; + volatile u32 DENALI_PI_112; + volatile u32 DENALI_PI_113; + volatile u32 DENALI_PI_114; + volatile u32 DENALI_PI_115; + volatile u32 DENALI_PI_116; + volatile u32 DENALI_PI_117; + volatile u32 DENALI_PI_118; + volatile u32 DENALI_PI_119; + volatile u32 DENALI_PI_120; + volatile u32 DENALI_PI_121; + volatile u32 DENALI_PI_122; + volatile u32 DENALI_PI_123; + volatile u32 DENALI_PI_124; + volatile u32 DENALI_PI_125; + volatile u32 DENALI_PI_126; + volatile u32 DENALI_PI_127; + volatile u32 DENALI_PI_128; + volatile u32 DENALI_PI_129; + volatile u32 DENALI_PI_130; + volatile u32 DENALI_PI_131; + volatile u32 DENALI_PI_132; + volatile u32 DENALI_PI_133; + volatile u32 DENALI_PI_134; + volatile u32 DENALI_PI_135; + volatile u32 DENALI_PI_136; + volatile u32 DENALI_PI_137; + volatile u32 DENALI_PI_138; + volatile u32 DENALI_PI_139; + volatile u32 DENALI_PI_140; + volatile u32 DENALI_PI_141; + volatile u32 DENALI_PI_142; + volatile u32 DENALI_PI_143; + volatile u32 DENALI_PI_144; + volatile u32 DENALI_PI_145; + volatile u32 DENALI_PI_146; + volatile u32 DENALI_PI_147; + volatile u32 DENALI_PI_148; + volatile u32 DENALI_PI_149; + volatile u32 DENALI_PI_150; + volatile u32 DENALI_PI_151; + volatile u32 DENALI_PI_152; + volatile u32 DENALI_PI_153; + volatile u32 DENALI_PI_154; + volatile u32 DENALI_PI_155; + volatile u32 DENALI_PI_156; + volatile u32 DENALI_PI_157; + volatile u32 DENALI_PI_158; + volatile u32 DENALI_PI_159; + volatile u32 DENALI_PI_160; + volatile u32 DENALI_PI_161; + volatile u32 DENALI_PI_162; + volatile u32 DENALI_PI_163; + volatile u32 DENALI_PI_164; + volatile u32 DENALI_PI_165; + volatile u32 DENALI_PI_166; + volatile u32 DENALI_PI_167; + volatile u32 DENALI_PI_168; + volatile u32 DENALI_PI_169; + volatile u32 DENALI_PI_170; + volatile u32 DENALI_PI_171; + volatile u32 DENALI_PI_172; + volatile u32 DENALI_PI_173; + volatile u32 DENALI_PI_174; + volatile u32 DENALI_PI_175; + volatile u32 DENALI_PI_176; + volatile u32 DENALI_PI_177; + volatile u32 DENALI_PI_178; + volatile u32 DENALI_PI_179; + volatile u32 DENALI_PI_180; + volatile u32 DENALI_PI_181; + volatile u32 DENALI_PI_182; + volatile u32 DENALI_PI_183; + volatile u32 DENALI_PI_184; + volatile u32 DENALI_PI_185; + volatile u32 DENALI_PI_186; + volatile u32 DENALI_PI_187; + volatile u32 DENALI_PI_188; + volatile u32 DENALI_PI_189; + volatile u32 DENALI_PI_190; + volatile u32 DENALI_PI_191; + volatile u32 DENALI_PI_192; + volatile u32 DENALI_PI_193; + volatile u32 DENALI_PI_194; + volatile u32 DENALI_PI_195; + volatile u32 DENALI_PI_196; + volatile u32 DENALI_PI_197; + volatile u32 DENALI_PI_198; + volatile u32 DENALI_PI_199; + volatile u32 DENALI_PI_200; + volatile u32 DENALI_PI_201; + volatile u32 DENALI_PI_202; + volatile u32 DENALI_PI_203; + volatile u32 DENALI_PI_204; + volatile u32 DENALI_PI_205; + volatile u32 DENALI_PI_206; + volatile u32 DENALI_PI_207; + volatile u32 DENALI_PI_208; + volatile u32 DENALI_PI_209; + volatile u32 DENALI_PI_210; + volatile u32 DENALI_PI_211; + volatile u32 DENALI_PI_212; + volatile u32 DENALI_PI_213; + volatile u32 DENALI_PI_214; + volatile u32 DENALI_PI_215; + volatile u32 DENALI_PI_216; + volatile u32 DENALI_PI_217; + volatile u32 DENALI_PI_218; + volatile u32 DENALI_PI_219; + volatile u32 DENALI_PI_220; + volatile u32 DENALI_PI_221; + volatile u32 DENALI_PI_222; + volatile u32 DENALI_PI_223; + volatile u32 DENALI_PI_224; + volatile u32 DENALI_PI_225; + volatile u32 DENALI_PI_226; + volatile u32 DENALI_PI_227; + volatile u32 DENALI_PI_228; + volatile u32 DENALI_PI_229; + volatile u32 DENALI_PI_230; + volatile u32 DENALI_PI_231; + volatile u32 DENALI_PI_232; + volatile u32 DENALI_PI_233; + volatile u32 DENALI_PI_234; + volatile u32 DENALI_PI_235; + volatile u32 DENALI_PI_236; + volatile u32 DENALI_PI_237; + volatile u32 DENALI_PI_238; + volatile u32 DENALI_PI_239; + volatile u32 DENALI_PI_240; + volatile u32 DENALI_PI_241; + volatile u32 DENALI_PI_242; + volatile u32 DENALI_PI_243; + volatile u32 DENALI_PI_244; + volatile u32 DENALI_PI_245; + volatile u32 DENALI_PI_246; + volatile u32 DENALI_PI_247; + volatile u32 DENALI_PI_248; + volatile u32 DENALI_PI_249; + volatile u32 DENALI_PI_250; + volatile u32 DENALI_PI_251; + volatile u32 DENALI_PI_252; + volatile u32 DENALI_PI_253; + volatile u32 DENALI_PI_254; + volatile u32 DENALI_PI_255; + volatile u32 DENALI_PI_256; + volatile u32 DENALI_PI_257; + volatile u32 DENALI_PI_258; + volatile u32 DENALI_PI_259; + volatile u32 DENALI_PI_260; + volatile u32 DENALI_PI_261; + volatile u32 DENALI_PI_262; + volatile u32 DENALI_PI_263; + volatile u32 DENALI_PI_264; + volatile u32 DENALI_PI_265; + volatile u32 DENALI_PI_266; + volatile u32 DENALI_PI_267; + volatile u32 DENALI_PI_268; + volatile u32 DENALI_PI_269; + volatile u32 DENALI_PI_270; + volatile u32 DENALI_PI_271; + volatile u32 DENALI_PI_272; + volatile u32 DENALI_PI_273; + volatile u32 DENALI_PI_274; + volatile u32 DENALI_PI_275; + volatile u32 DENALI_PI_276; + volatile u32 DENALI_PI_277; + volatile u32 DENALI_PI_278; + volatile u32 DENALI_PI_279; + volatile u32 DENALI_PI_280; + volatile u32 DENALI_PI_281; + volatile u32 DENALI_PI_282; + volatile u32 DENALI_PI_283; + volatile u32 DENALI_PI_284; + volatile u32 DENALI_PI_285; + volatile u32 DENALI_PI_286; + volatile u32 DENALI_PI_287; + volatile u32 DENALI_PI_288; + volatile u32 DENALI_PI_289; + volatile u32 DENALI_PI_290; + volatile u32 DENALI_PI_291; + volatile u32 DENALI_PI_292; + volatile u32 DENALI_PI_293; + volatile u32 DENALI_PI_294; + volatile u32 DENALI_PI_295; + volatile u32 DENALI_PI_296; + volatile u32 DENALI_PI_297; + volatile u32 DENALI_PI_298; + volatile u32 DENALI_PI_299; + volatile char pad__1[0x1B50U]; + volatile u32 DENALI_PHY_0; + volatile u32 DENALI_PHY_1; + volatile u32 DENALI_PHY_2; + volatile u32 DENALI_PHY_3; + volatile u32 DENALI_PHY_4; + volatile u32 DENALI_PHY_5; + volatile u32 DENALI_PHY_6; + volatile u32 DENALI_PHY_7; + volatile u32 DENALI_PHY_8; + volatile u32 DENALI_PHY_9; + volatile u32 DENALI_PHY_10; + volatile u32 DENALI_PHY_11; + volatile u32 DENALI_PHY_12; + volatile u32 DENALI_PHY_13; + volatile u32 DENALI_PHY_14; + volatile u32 DENALI_PHY_15; + volatile u32 DENALI_PHY_16; + volatile u32 DENALI_PHY_17; + volatile u32 DENALI_PHY_18; + volatile u32 DENALI_PHY_19; + volatile u32 DENALI_PHY_20; + volatile u32 DENALI_PHY_21; + volatile u32 DENALI_PHY_22; + volatile u32 DENALI_PHY_23; + volatile u32 DENALI_PHY_24; + volatile u32 DENALI_PHY_25; + volatile u32 DENALI_PHY_26; + volatile u32 DENALI_PHY_27; + volatile u32 DENALI_PHY_28; + volatile u32 DENALI_PHY_29; + volatile u32 DENALI_PHY_30; + volatile u32 DENALI_PHY_31; + volatile u32 DENALI_PHY_32; + volatile u32 DENALI_PHY_33; + volatile u32 DENALI_PHY_34; + volatile u32 DENALI_PHY_35; + volatile u32 DENALI_PHY_36; + volatile u32 DENALI_PHY_37; + volatile u32 DENALI_PHY_38; + volatile u32 DENALI_PHY_39; + volatile u32 DENALI_PHY_40; + volatile u32 DENALI_PHY_41; + volatile u32 DENALI_PHY_42; + volatile u32 DENALI_PHY_43; + volatile u32 DENALI_PHY_44; + volatile u32 DENALI_PHY_45; + volatile u32 DENALI_PHY_46; + volatile u32 DENALI_PHY_47; + volatile u32 DENALI_PHY_48; + volatile u32 DENALI_PHY_49; + volatile u32 DENALI_PHY_50; + volatile u32 DENALI_PHY_51; + volatile u32 DENALI_PHY_52; + volatile u32 DENALI_PHY_53; + volatile u32 DENALI_PHY_54; + volatile u32 DENALI_PHY_55; + volatile u32 DENALI_PHY_56; + volatile u32 DENALI_PHY_57; + volatile u32 DENALI_PHY_58; + volatile u32 DENALI_PHY_59; + volatile u32 DENALI_PHY_60; + volatile u32 DENALI_PHY_61; + volatile u32 DENALI_PHY_62; + volatile u32 DENALI_PHY_63; + volatile u32 DENALI_PHY_64; + volatile u32 DENALI_PHY_65; + volatile u32 DENALI_PHY_66; + volatile u32 DENALI_PHY_67; + volatile u32 DENALI_PHY_68; + volatile u32 DENALI_PHY_69; + volatile u32 DENALI_PHY_70; + volatile u32 DENALI_PHY_71; + volatile u32 DENALI_PHY_72; + volatile u32 DENALI_PHY_73; + volatile u32 DENALI_PHY_74; + volatile u32 DENALI_PHY_75; + volatile u32 DENALI_PHY_76; + volatile u32 DENALI_PHY_77; + volatile u32 DENALI_PHY_78; + volatile u32 DENALI_PHY_79; + volatile u32 DENALI_PHY_80; + volatile u32 DENALI_PHY_81; + volatile u32 DENALI_PHY_82; + volatile u32 DENALI_PHY_83; + volatile u32 DENALI_PHY_84; + volatile u32 DENALI_PHY_85; + volatile u32 DENALI_PHY_86; + volatile u32 DENALI_PHY_87; + volatile u32 DENALI_PHY_88; + volatile u32 DENALI_PHY_89; + volatile u32 DENALI_PHY_90; + volatile u32 DENALI_PHY_91; + volatile u32 DENALI_PHY_92; + volatile u32 DENALI_PHY_93; + volatile u32 DENALI_PHY_94; + volatile u32 DENALI_PHY_95; + volatile u32 DENALI_PHY_96; + volatile u32 DENALI_PHY_97; + volatile u32 DENALI_PHY_98; + volatile u32 DENALI_PHY_99; + volatile u32 DENALI_PHY_100; + volatile u32 DENALI_PHY_101; + volatile u32 DENALI_PHY_102; + volatile u32 DENALI_PHY_103; + volatile u32 DENALI_PHY_104; + volatile u32 DENALI_PHY_105; + volatile u32 DENALI_PHY_106; + volatile u32 DENALI_PHY_107; + volatile u32 DENALI_PHY_108; + volatile u32 DENALI_PHY_109; + volatile u32 DENALI_PHY_110; + volatile u32 DENALI_PHY_111; + volatile u32 DENALI_PHY_112; + volatile u32 DENALI_PHY_113; + volatile u32 DENALI_PHY_114; + volatile u32 DENALI_PHY_115; + volatile u32 DENALI_PHY_116; + volatile u32 DENALI_PHY_117; + volatile u32 DENALI_PHY_118; + volatile u32 DENALI_PHY_119; + volatile u32 DENALI_PHY_120; + volatile u32 DENALI_PHY_121; + volatile u32 DENALI_PHY_122; + volatile u32 DENALI_PHY_123; + volatile u32 DENALI_PHY_124; + volatile u32 DENALI_PHY_125; + volatile u32 DENALI_PHY_126; + volatile u32 DENALI_PHY_127; + volatile u32 DENALI_PHY_128; + volatile u32 DENALI_PHY_129; + volatile u32 DENALI_PHY_130; + volatile u32 DENALI_PHY_131; + volatile u32 DENALI_PHY_132; + volatile u32 DENALI_PHY_133; + volatile u32 DENALI_PHY_134; + volatile u32 DENALI_PHY_135; + volatile u32 DENALI_PHY_136; + volatile u32 DENALI_PHY_137; + volatile u32 DENALI_PHY_138; + volatile u32 DENALI_PHY_139; + volatile char pad__2[0x1D0U]; + volatile u32 DENALI_PHY_256; + volatile u32 DENALI_PHY_257; + volatile u32 DENALI_PHY_258; + volatile u32 DENALI_PHY_259; + volatile u32 DENALI_PHY_260; + volatile u32 DENALI_PHY_261; + volatile u32 DENALI_PHY_262; + volatile u32 DENALI_PHY_263; + volatile u32 DENALI_PHY_264; + volatile u32 DENALI_PHY_265; + volatile u32 DENALI_PHY_266; + volatile u32 DENALI_PHY_267; + volatile u32 DENALI_PHY_268; + volatile u32 DENALI_PHY_269; + volatile u32 DENALI_PHY_270; + volatile u32 DENALI_PHY_271; + volatile u32 DENALI_PHY_272; + volatile u32 DENALI_PHY_273; + volatile u32 DENALI_PHY_274; + volatile u32 DENALI_PHY_275; + volatile u32 DENALI_PHY_276; + volatile u32 DENALI_PHY_277; + volatile u32 DENALI_PHY_278; + volatile u32 DENALI_PHY_279; + volatile u32 DENALI_PHY_280; + volatile u32 DENALI_PHY_281; + volatile u32 DENALI_PHY_282; + volatile u32 DENALI_PHY_283; + volatile u32 DENALI_PHY_284; + volatile u32 DENALI_PHY_285; + volatile u32 DENALI_PHY_286; + volatile u32 DENALI_PHY_287; + volatile u32 DENALI_PHY_288; + volatile u32 DENALI_PHY_289; + volatile u32 DENALI_PHY_290; + volatile u32 DENALI_PHY_291; + volatile u32 DENALI_PHY_292; + volatile u32 DENALI_PHY_293; + volatile u32 DENALI_PHY_294; + volatile u32 DENALI_PHY_295; + volatile u32 DENALI_PHY_296; + volatile u32 DENALI_PHY_297; + volatile u32 DENALI_PHY_298; + volatile u32 DENALI_PHY_299; + volatile u32 DENALI_PHY_300; + volatile u32 DENALI_PHY_301; + volatile u32 DENALI_PHY_302; + volatile u32 DENALI_PHY_303; + volatile u32 DENALI_PHY_304; + volatile u32 DENALI_PHY_305; + volatile u32 DENALI_PHY_306; + volatile u32 DENALI_PHY_307; + volatile u32 DENALI_PHY_308; + volatile u32 DENALI_PHY_309; + volatile u32 DENALI_PHY_310; + volatile u32 DENALI_PHY_311; + volatile u32 DENALI_PHY_312; + volatile u32 DENALI_PHY_313; + volatile u32 DENALI_PHY_314; + volatile u32 DENALI_PHY_315; + volatile u32 DENALI_PHY_316; + volatile u32 DENALI_PHY_317; + volatile u32 DENALI_PHY_318; + volatile u32 DENALI_PHY_319; + volatile u32 DENALI_PHY_320; + volatile u32 DENALI_PHY_321; + volatile u32 DENALI_PHY_322; + volatile u32 DENALI_PHY_323; + volatile u32 DENALI_PHY_324; + volatile u32 DENALI_PHY_325; + volatile u32 DENALI_PHY_326; + volatile u32 DENALI_PHY_327; + volatile u32 DENALI_PHY_328; + volatile u32 DENALI_PHY_329; + volatile u32 DENALI_PHY_330; + volatile u32 DENALI_PHY_331; + volatile u32 DENALI_PHY_332; + volatile u32 DENALI_PHY_333; + volatile u32 DENALI_PHY_334; + volatile u32 DENALI_PHY_335; + volatile u32 DENALI_PHY_336; + volatile u32 DENALI_PHY_337; + volatile u32 DENALI_PHY_338; + volatile u32 DENALI_PHY_339; + volatile u32 DENALI_PHY_340; + volatile u32 DENALI_PHY_341; + volatile u32 DENALI_PHY_342; + volatile u32 DENALI_PHY_343; + volatile u32 DENALI_PHY_344; + volatile u32 DENALI_PHY_345; + volatile u32 DENALI_PHY_346; + volatile u32 DENALI_PHY_347; + volatile u32 DENALI_PHY_348; + volatile u32 DENALI_PHY_349; + volatile u32 DENALI_PHY_350; + volatile u32 DENALI_PHY_351; + volatile u32 DENALI_PHY_352; + volatile u32 DENALI_PHY_353; + volatile u32 DENALI_PHY_354; + volatile u32 DENALI_PHY_355; + volatile u32 DENALI_PHY_356; + volatile u32 DENALI_PHY_357; + volatile u32 DENALI_PHY_358; + volatile u32 DENALI_PHY_359; + volatile u32 DENALI_PHY_360; + volatile u32 DENALI_PHY_361; + volatile u32 DENALI_PHY_362; + volatile u32 DENALI_PHY_363; + volatile u32 DENALI_PHY_364; + volatile u32 DENALI_PHY_365; + volatile u32 DENALI_PHY_366; + volatile u32 DENALI_PHY_367; + volatile u32 DENALI_PHY_368; + volatile u32 DENALI_PHY_369; + volatile u32 DENALI_PHY_370; + volatile u32 DENALI_PHY_371; + volatile u32 DENALI_PHY_372; + volatile u32 DENALI_PHY_373; + volatile u32 DENALI_PHY_374; + volatile u32 DENALI_PHY_375; + volatile u32 DENALI_PHY_376; + volatile u32 DENALI_PHY_377; + volatile u32 DENALI_PHY_378; + volatile u32 DENALI_PHY_379; + volatile u32 DENALI_PHY_380; + volatile u32 DENALI_PHY_381; + volatile u32 DENALI_PHY_382; + volatile u32 DENALI_PHY_383; + volatile u32 DENALI_PHY_384; + volatile u32 DENALI_PHY_385; + volatile u32 DENALI_PHY_386; + volatile u32 DENALI_PHY_387; + volatile u32 DENALI_PHY_388; + volatile u32 DENALI_PHY_389; + volatile u32 DENALI_PHY_390; + volatile u32 DENALI_PHY_391; + volatile u32 DENALI_PHY_392; + volatile u32 DENALI_PHY_393; + volatile u32 DENALI_PHY_394; + volatile u32 DENALI_PHY_395; + volatile char pad__3[0x1D0U]; + volatile u32 DENALI_PHY_512; + volatile u32 DENALI_PHY_513; + volatile u32 DENALI_PHY_514; + volatile u32 DENALI_PHY_515; + volatile u32 DENALI_PHY_516; + volatile u32 DENALI_PHY_517; + volatile u32 DENALI_PHY_518; + volatile u32 DENALI_PHY_519; + volatile u32 DENALI_PHY_520; + volatile u32 DENALI_PHY_521; + volatile u32 DENALI_PHY_522; + volatile u32 DENALI_PHY_523; + volatile u32 DENALI_PHY_524; + volatile u32 DENALI_PHY_525; + volatile u32 DENALI_PHY_526; + volatile u32 DENALI_PHY_527; + volatile u32 DENALI_PHY_528; + volatile u32 DENALI_PHY_529; + volatile u32 DENALI_PHY_530; + volatile u32 DENALI_PHY_531; + volatile u32 DENALI_PHY_532; + volatile u32 DENALI_PHY_533; + volatile u32 DENALI_PHY_534; + volatile u32 DENALI_PHY_535; + volatile u32 DENALI_PHY_536; + volatile u32 DENALI_PHY_537; + volatile u32 DENALI_PHY_538; + volatile u32 DENALI_PHY_539; + volatile u32 DENALI_PHY_540; + volatile u32 DENALI_PHY_541; + volatile u32 DENALI_PHY_542; + volatile u32 DENALI_PHY_543; + volatile u32 DENALI_PHY_544; + volatile u32 DENALI_PHY_545; + volatile u32 DENALI_PHY_546; + volatile u32 DENALI_PHY_547; + volatile u32 DENALI_PHY_548; + volatile u32 DENALI_PHY_549; + volatile u32 DENALI_PHY_550; + volatile u32 DENALI_PHY_551; + volatile u32 DENALI_PHY_552; + volatile u32 DENALI_PHY_553; + volatile u32 DENALI_PHY_554; + volatile u32 DENALI_PHY_555; + volatile u32 DENALI_PHY_556; + volatile u32 DENALI_PHY_557; + volatile u32 DENALI_PHY_558; + volatile u32 DENALI_PHY_559; + volatile u32 DENALI_PHY_560; + volatile u32 DENALI_PHY_561; + volatile u32 DENALI_PHY_562; + volatile u32 DENALI_PHY_563; + volatile u32 DENALI_PHY_564; + volatile u32 DENALI_PHY_565; + volatile u32 DENALI_PHY_566; + volatile u32 DENALI_PHY_567; + volatile u32 DENALI_PHY_568; + volatile u32 DENALI_PHY_569; + volatile u32 DENALI_PHY_570; + volatile u32 DENALI_PHY_571; + volatile u32 DENALI_PHY_572; + volatile u32 DENALI_PHY_573; + volatile u32 DENALI_PHY_574; + volatile u32 DENALI_PHY_575; + volatile u32 DENALI_PHY_576; + volatile u32 DENALI_PHY_577; + volatile u32 DENALI_PHY_578; + volatile u32 DENALI_PHY_579; + volatile u32 DENALI_PHY_580; + volatile u32 DENALI_PHY_581; + volatile u32 DENALI_PHY_582; + volatile u32 DENALI_PHY_583; + volatile u32 DENALI_PHY_584; + volatile u32 DENALI_PHY_585; + volatile u32 DENALI_PHY_586; + volatile u32 DENALI_PHY_587; + volatile u32 DENALI_PHY_588; + volatile u32 DENALI_PHY_589; + volatile u32 DENALI_PHY_590; + volatile u32 DENALI_PHY_591; + volatile u32 DENALI_PHY_592; + volatile u32 DENALI_PHY_593; + volatile u32 DENALI_PHY_594; + volatile u32 DENALI_PHY_595; + volatile u32 DENALI_PHY_596; + volatile u32 DENALI_PHY_597; + volatile u32 DENALI_PHY_598; + volatile u32 DENALI_PHY_599; + volatile u32 DENALI_PHY_600; + volatile u32 DENALI_PHY_601; + volatile u32 DENALI_PHY_602; + volatile u32 DENALI_PHY_603; + volatile u32 DENALI_PHY_604; + volatile u32 DENALI_PHY_605; + volatile u32 DENALI_PHY_606; + volatile u32 DENALI_PHY_607; + volatile u32 DENALI_PHY_608; + volatile u32 DENALI_PHY_609; + volatile u32 DENALI_PHY_610; + volatile u32 DENALI_PHY_611; + volatile u32 DENALI_PHY_612; + volatile u32 DENALI_PHY_613; + volatile u32 DENALI_PHY_614; + volatile u32 DENALI_PHY_615; + volatile u32 DENALI_PHY_616; + volatile u32 DENALI_PHY_617; + volatile u32 DENALI_PHY_618; + volatile u32 DENALI_PHY_619; + volatile u32 DENALI_PHY_620; + volatile u32 DENALI_PHY_621; + volatile u32 DENALI_PHY_622; + volatile u32 DENALI_PHY_623; + volatile u32 DENALI_PHY_624; + volatile u32 DENALI_PHY_625; + volatile u32 DENALI_PHY_626; + volatile u32 DENALI_PHY_627; + volatile u32 DENALI_PHY_628; + volatile u32 DENALI_PHY_629; + volatile u32 DENALI_PHY_630; + volatile u32 DENALI_PHY_631; + volatile u32 DENALI_PHY_632; + volatile u32 DENALI_PHY_633; + volatile u32 DENALI_PHY_634; + volatile u32 DENALI_PHY_635; + volatile u32 DENALI_PHY_636; + volatile u32 DENALI_PHY_637; + volatile u32 DENALI_PHY_638; + volatile u32 DENALI_PHY_639; + volatile u32 DENALI_PHY_640; + volatile u32 DENALI_PHY_641; + volatile u32 DENALI_PHY_642; + volatile u32 DENALI_PHY_643; + volatile u32 DENALI_PHY_644; + volatile u32 DENALI_PHY_645; + volatile u32 DENALI_PHY_646; + volatile u32 DENALI_PHY_647; + volatile u32 DENALI_PHY_648; + volatile u32 DENALI_PHY_649; + volatile u32 DENALI_PHY_650; + volatile u32 DENALI_PHY_651; + volatile char pad__4[0x1D0U]; + volatile u32 DENALI_PHY_768; + volatile u32 DENALI_PHY_769; + volatile u32 DENALI_PHY_770; + volatile u32 DENALI_PHY_771; + volatile u32 DENALI_PHY_772; + volatile u32 DENALI_PHY_773; + volatile u32 DENALI_PHY_774; + volatile u32 DENALI_PHY_775; + volatile u32 DENALI_PHY_776; + volatile u32 DENALI_PHY_777; + volatile u32 DENALI_PHY_778; + volatile u32 DENALI_PHY_779; + volatile u32 DENALI_PHY_780; + volatile u32 DENALI_PHY_781; + volatile u32 DENALI_PHY_782; + volatile u32 DENALI_PHY_783; + volatile u32 DENALI_PHY_784; + volatile u32 DENALI_PHY_785; + volatile u32 DENALI_PHY_786; + volatile u32 DENALI_PHY_787; + volatile u32 DENALI_PHY_788; + volatile u32 DENALI_PHY_789; + volatile u32 DENALI_PHY_790; + volatile u32 DENALI_PHY_791; + volatile u32 DENALI_PHY_792; + volatile u32 DENALI_PHY_793; + volatile u32 DENALI_PHY_794; + volatile u32 DENALI_PHY_795; + volatile u32 DENALI_PHY_796; + volatile u32 DENALI_PHY_797; + volatile u32 DENALI_PHY_798; + volatile u32 DENALI_PHY_799; + volatile u32 DENALI_PHY_800; + volatile u32 DENALI_PHY_801; + volatile u32 DENALI_PHY_802; + volatile u32 DENALI_PHY_803; + volatile u32 DENALI_PHY_804; + volatile u32 DENALI_PHY_805; + volatile u32 DENALI_PHY_806; + volatile u32 DENALI_PHY_807; + volatile u32 DENALI_PHY_808; + volatile u32 DENALI_PHY_809; + volatile u32 DENALI_PHY_810; + volatile u32 DENALI_PHY_811; + volatile u32 DENALI_PHY_812; + volatile u32 DENALI_PHY_813; + volatile u32 DENALI_PHY_814; + volatile u32 DENALI_PHY_815; + volatile u32 DENALI_PHY_816; + volatile u32 DENALI_PHY_817; + volatile u32 DENALI_PHY_818; + volatile u32 DENALI_PHY_819; + volatile u32 DENALI_PHY_820; + volatile u32 DENALI_PHY_821; + volatile u32 DENALI_PHY_822; + volatile u32 DENALI_PHY_823; + volatile u32 DENALI_PHY_824; + volatile u32 DENALI_PHY_825; + volatile u32 DENALI_PHY_826; + volatile u32 DENALI_PHY_827; + volatile u32 DENALI_PHY_828; + volatile u32 DENALI_PHY_829; + volatile u32 DENALI_PHY_830; + volatile u32 DENALI_PHY_831; + volatile u32 DENALI_PHY_832; + volatile u32 DENALI_PHY_833; + volatile u32 DENALI_PHY_834; + volatile u32 DENALI_PHY_835; + volatile u32 DENALI_PHY_836; + volatile u32 DENALI_PHY_837; + volatile u32 DENALI_PHY_838; + volatile u32 DENALI_PHY_839; + volatile u32 DENALI_PHY_840; + volatile u32 DENALI_PHY_841; + volatile u32 DENALI_PHY_842; + volatile u32 DENALI_PHY_843; + volatile u32 DENALI_PHY_844; + volatile u32 DENALI_PHY_845; + volatile u32 DENALI_PHY_846; + volatile u32 DENALI_PHY_847; + volatile u32 DENALI_PHY_848; + volatile u32 DENALI_PHY_849; + volatile u32 DENALI_PHY_850; + volatile u32 DENALI_PHY_851; + volatile u32 DENALI_PHY_852; + volatile u32 DENALI_PHY_853; + volatile u32 DENALI_PHY_854; + volatile u32 DENALI_PHY_855; + volatile u32 DENALI_PHY_856; + volatile u32 DENALI_PHY_857; + volatile u32 DENALI_PHY_858; + volatile u32 DENALI_PHY_859; + volatile u32 DENALI_PHY_860; + volatile u32 DENALI_PHY_861; + volatile u32 DENALI_PHY_862; + volatile u32 DENALI_PHY_863; + volatile u32 DENALI_PHY_864; + volatile u32 DENALI_PHY_865; + volatile u32 DENALI_PHY_866; + volatile u32 DENALI_PHY_867; + volatile u32 DENALI_PHY_868; + volatile u32 DENALI_PHY_869; + volatile u32 DENALI_PHY_870; + volatile u32 DENALI_PHY_871; + volatile u32 DENALI_PHY_872; + volatile u32 DENALI_PHY_873; + volatile u32 DENALI_PHY_874; + volatile u32 DENALI_PHY_875; + volatile u32 DENALI_PHY_876; + volatile u32 DENALI_PHY_877; + volatile u32 DENALI_PHY_878; + volatile u32 DENALI_PHY_879; + volatile u32 DENALI_PHY_880; + volatile u32 DENALI_PHY_881; + volatile u32 DENALI_PHY_882; + volatile u32 DENALI_PHY_883; + volatile u32 DENALI_PHY_884; + volatile u32 DENALI_PHY_885; + volatile u32 DENALI_PHY_886; + volatile u32 DENALI_PHY_887; + volatile u32 DENALI_PHY_888; + volatile u32 DENALI_PHY_889; + volatile u32 DENALI_PHY_890; + volatile u32 DENALI_PHY_891; + volatile u32 DENALI_PHY_892; + volatile u32 DENALI_PHY_893; + volatile u32 DENALI_PHY_894; + volatile u32 DENALI_PHY_895; + volatile u32 DENALI_PHY_896; + volatile u32 DENALI_PHY_897; + volatile u32 DENALI_PHY_898; + volatile u32 DENALI_PHY_899; + volatile u32 DENALI_PHY_900; + volatile u32 DENALI_PHY_901; + volatile u32 DENALI_PHY_902; + volatile u32 DENALI_PHY_903; + volatile u32 DENALI_PHY_904; + volatile u32 DENALI_PHY_905; + volatile u32 DENALI_PHY_906; + volatile u32 DENALI_PHY_907; + volatile char pad__5[0x1D0U]; + volatile u32 DENALI_PHY_1024; + volatile u32 DENALI_PHY_1025; + volatile u32 DENALI_PHY_1026; + volatile u32 DENALI_PHY_1027; + volatile u32 DENALI_PHY_1028; + volatile u32 DENALI_PHY_1029; + volatile u32 DENALI_PHY_1030; + volatile u32 DENALI_PHY_1031; + volatile u32 DENALI_PHY_1032; + volatile u32 DENALI_PHY_1033; + volatile u32 DENALI_PHY_1034; + volatile u32 DENALI_PHY_1035; + volatile u32 DENALI_PHY_1036; + volatile u32 DENALI_PHY_1037; + volatile u32 DENALI_PHY_1038; + volatile u32 DENALI_PHY_1039; + volatile u32 DENALI_PHY_1040; + volatile u32 DENALI_PHY_1041; + volatile u32 DENALI_PHY_1042; + volatile u32 DENALI_PHY_1043; + volatile u32 DENALI_PHY_1044; + volatile u32 DENALI_PHY_1045; + volatile u32 DENALI_PHY_1046; + volatile u32 DENALI_PHY_1047; + volatile u32 DENALI_PHY_1048; + volatile u32 DENALI_PHY_1049; + volatile u32 DENALI_PHY_1050; + volatile u32 DENALI_PHY_1051; + volatile u32 DENALI_PHY_1052; + volatile u32 DENALI_PHY_1053; + volatile u32 DENALI_PHY_1054; + volatile u32 DENALI_PHY_1055; + volatile u32 DENALI_PHY_1056; + volatile u32 DENALI_PHY_1057; + volatile u32 DENALI_PHY_1058; + volatile u32 DENALI_PHY_1059; + volatile u32 DENALI_PHY_1060; + volatile u32 DENALI_PHY_1061; + volatile u32 DENALI_PHY_1062; + volatile u32 DENALI_PHY_1063; + volatile u32 DENALI_PHY_1064; + volatile u32 DENALI_PHY_1065; + volatile u32 DENALI_PHY_1066; + volatile u32 DENALI_PHY_1067; + volatile u32 DENALI_PHY_1068; + volatile u32 DENALI_PHY_1069; + volatile u32 DENALI_PHY_1070; + volatile u32 DENALI_PHY_1071; + volatile u32 DENALI_PHY_1072; + volatile u32 DENALI_PHY_1073; + volatile u32 DENALI_PHY_1074; + volatile u32 DENALI_PHY_1075; + volatile char pad__6[0x330U]; + volatile u32 DENALI_PHY_1280; + volatile u32 DENALI_PHY_1281; + volatile u32 DENALI_PHY_1282; + volatile u32 DENALI_PHY_1283; + volatile u32 DENALI_PHY_1284; + volatile u32 DENALI_PHY_1285; + volatile u32 DENALI_PHY_1286; + volatile u32 DENALI_PHY_1287; + volatile u32 DENALI_PHY_1288; + volatile u32 DENALI_PHY_1289; + volatile u32 DENALI_PHY_1290; + volatile u32 DENALI_PHY_1291; + volatile u32 DENALI_PHY_1292; + volatile u32 DENALI_PHY_1293; + volatile u32 DENALI_PHY_1294; + volatile u32 DENALI_PHY_1295; + volatile u32 DENALI_PHY_1296; + volatile u32 DENALI_PHY_1297; + volatile u32 DENALI_PHY_1298; + volatile u32 DENALI_PHY_1299; + volatile u32 DENALI_PHY_1300; + volatile u32 DENALI_PHY_1301; + volatile u32 DENALI_PHY_1302; + volatile u32 DENALI_PHY_1303; + volatile u32 DENALI_PHY_1304; + volatile u32 DENALI_PHY_1305; + volatile u32 DENALI_PHY_1306; + volatile u32 DENALI_PHY_1307; + volatile u32 DENALI_PHY_1308; + volatile u32 DENALI_PHY_1309; + volatile u32 DENALI_PHY_1310; + volatile u32 DENALI_PHY_1311; + volatile u32 DENALI_PHY_1312; + volatile u32 DENALI_PHY_1313; + volatile u32 DENALI_PHY_1314; + volatile u32 DENALI_PHY_1315; + volatile u32 DENALI_PHY_1316; + volatile u32 DENALI_PHY_1317; + volatile u32 DENALI_PHY_1318; + volatile u32 DENALI_PHY_1319; + volatile u32 DENALI_PHY_1320; + volatile u32 DENALI_PHY_1321; + volatile u32 DENALI_PHY_1322; + volatile u32 DENALI_PHY_1323; + volatile u32 DENALI_PHY_1324; + volatile u32 DENALI_PHY_1325; + volatile u32 DENALI_PHY_1326; + volatile u32 DENALI_PHY_1327; + volatile u32 DENALI_PHY_1328; + volatile u32 DENALI_PHY_1329; + volatile u32 DENALI_PHY_1330; + volatile u32 DENALI_PHY_1331; + volatile u32 DENALI_PHY_1332; + volatile u32 DENALI_PHY_1333; + volatile u32 DENALI_PHY_1334; + volatile u32 DENALI_PHY_1335; + volatile u32 DENALI_PHY_1336; + volatile u32 DENALI_PHY_1337; + volatile u32 DENALI_PHY_1338; + volatile u32 DENALI_PHY_1339; + volatile u32 DENALI_PHY_1340; + volatile u32 DENALI_PHY_1341; + volatile u32 DENALI_PHY_1342; + volatile u32 DENALI_PHY_1343; + volatile u32 DENALI_PHY_1344; + volatile u32 DENALI_PHY_1345; + volatile u32 DENALI_PHY_1346; + volatile u32 DENALI_PHY_1347; + volatile u32 DENALI_PHY_1348; + volatile u32 DENALI_PHY_1349; + volatile u32 DENALI_PHY_1350; + volatile u32 DENALI_PHY_1351; + volatile u32 DENALI_PHY_1352; + volatile u32 DENALI_PHY_1353; + volatile u32 DENALI_PHY_1354; + volatile u32 DENALI_PHY_1355; + volatile u32 DENALI_PHY_1356; + volatile u32 DENALI_PHY_1357; + volatile u32 DENALI_PHY_1358; + volatile u32 DENALI_PHY_1359; + volatile u32 DENALI_PHY_1360; + volatile u32 DENALI_PHY_1361; + volatile u32 DENALI_PHY_1362; + volatile u32 DENALI_PHY_1363; + volatile u32 DENALI_PHY_1364; + volatile u32 DENALI_PHY_1365; + volatile u32 DENALI_PHY_1366; + volatile u32 DENALI_PHY_1367; + volatile u32 DENALI_PHY_1368; + volatile u32 DENALI_PHY_1369; + volatile u32 DENALI_PHY_1370; + volatile u32 DENALI_PHY_1371; + volatile u32 DENALI_PHY_1372; + volatile u32 DENALI_PHY_1373; + volatile u32 DENALI_PHY_1374; + volatile u32 DENALI_PHY_1375; + volatile u32 DENALI_PHY_1376; + volatile u32 DENALI_PHY_1377; + volatile u32 DENALI_PHY_1378; + volatile u32 DENALI_PHY_1379; + volatile u32 DENALI_PHY_1380; + volatile u32 DENALI_PHY_1381; + volatile u32 DENALI_PHY_1382; + volatile u32 DENALI_PHY_1383; + volatile u32 DENALI_PHY_1384; + volatile u32 DENALI_PHY_1385; + volatile u32 DENALI_PHY_1386; + volatile u32 DENALI_PHY_1387; + volatile u32 DENALI_PHY_1388; + volatile u32 DENALI_PHY_1389; + volatile u32 DENALI_PHY_1390; + volatile u32 DENALI_PHY_1391; + volatile u32 DENALI_PHY_1392; + volatile u32 DENALI_PHY_1393; + volatile u32 DENALI_PHY_1394; + volatile u32 DENALI_PHY_1395; + volatile u32 DENALI_PHY_1396; + volatile u32 DENALI_PHY_1397; + volatile u32 DENALI_PHY_1398; + volatile u32 DENALI_PHY_1399; + volatile u32 DENALI_PHY_1400; + volatile u32 DENALI_PHY_1401; + volatile u32 DENALI_PHY_1402; + volatile u32 DENALI_PHY_1403; + volatile u32 DENALI_PHY_1404; + volatile u32 DENALI_PHY_1405; + volatile u32 DENALI_PHY_1406; + volatile u32 DENALI_PHY_1407; + volatile u32 DENALI_PHY_1408; + volatile u32 DENALI_PHY_1409; + volatile u32 DENALI_PHY_1410; + volatile u32 DENALI_PHY_1411; + volatile u32 DENALI_PHY_1412; + volatile u32 DENALI_PHY_1413; + volatile u32 DENALI_PHY_1414; + volatile u32 DENALI_PHY_1415; + volatile u32 DENALI_PHY_1416; + volatile u32 DENALI_PHY_1417; + volatile u32 DENALI_PHY_1418; + volatile u32 DENALI_PHY_1419; + volatile u32 DENALI_PHY_1420; + volatile u32 DENALI_PHY_1421; + volatile u32 DENALI_PHY_1422; +} lpddr4_ctlregs; + +#endif /* REG_LPDDR4_CTL_REGS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h new file mode 100644 index 000000000..71122946b --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_RW_MASKS_H_ +#define LPDDR4_RW_MASKS_H_ + +#include + +extern u32 g_lpddr4_ddr_controller_rw_mask[459]; +extern u32 g_lpddr4_pi_rw_mask[300]; +extern u32 g_lpddr4_data_slice_0_rw_mask[140]; +extern u32 g_lpddr4_data_slice_1_rw_mask[140]; +extern u32 g_lpddr4_data_slice_2_rw_mask[140]; +extern u32 g_lpddr4_data_slice_3_rw_mask[140]; +extern u32 g_lpddr4_address_slice_0_rw_mask[52]; +extern u32 g_lpddr4_phy_core_rw_mask[143]; + +#endif /* LPDDR4_RW_MASKS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h new file mode 100644 index 000000000..ad45dd98d --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h @@ -0,0 +1,2372 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_0_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0 + +#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0 + +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0 + +#define LPDDR4__DENALI_PHY_6_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__FLD LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_7_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_8_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0 + +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0 + +#define LPDDR4__DENALI_PHY_9_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0 + +#define LPDDR4__DENALI_PHY_10_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0 + +#define LPDDR4__DENALI_PHY_11_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0 + +#define LPDDR4__DENALI_PHY_12_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0 + +#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0 + +#define LPDDR4__DENALI_PHY_13_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0 + +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_13 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_14_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET 0U +#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_14__PHY_LPDDR_0 + +#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0 + +#define LPDDR4__DENALI_PHY_15_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_15 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0 + +#define LPDDR4__DENALI_PHY_16_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_16 +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0 + +#define LPDDR4__DENALI_PHY_17_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_17 +#define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0 + +#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_17 +#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0 + +#define LPDDR4__DENALI_PHY_18_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_18 +#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0 + +#define LPDDR4__DENALI_PHY_19_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_19 +#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0 + +#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_20 +#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0 + +#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_21 +#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0 + +#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_22 +#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0 + +#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_23 +#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0 + +#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_24 +#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0 + +#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_25 +#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0 + +#define LPDDR4__DENALI_PHY_26_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_28_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_28 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0 + +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_WRLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0 + +#define LPDDR4__DENALI_PHY_29_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0 + +#define LPDDR4__DENALI_PHY_30_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0 + +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_31_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0 + +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_32_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0 + +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 + +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0 + +#define LPDDR4__DENALI_PHY_33_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0 + +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0 + +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_34_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_34 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 + +#define LPDDR4__DENALI_PHY_35_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0 + +#define LPDDR4__DENALI_PHY_36_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_36 +#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0 + +#define LPDDR4__DENALI_PHY_37_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_37 +#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0 + +#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_38 +#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0 + +#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_39 +#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0 + +#define LPDDR4__DENALI_PHY_40_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_40 +#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0 + +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_40 +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0 + +#define LPDDR4__DENALI_PHY_41_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_41 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_41 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_42_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0 + +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0 + +#define LPDDR4__DENALI_PHY_43_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0 + +#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_43 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0 + +#define LPDDR4__DENALI_PHY_44_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_44 +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_45_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_45 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_45 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_46_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_49_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_50_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_50 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_51_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_52_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_52 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0 + +#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_52 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_53_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_54_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_55_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_56_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0 + +#define LPDDR4__DENALI_PHY_57_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_58_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__REG DENALI_PHY_58 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0 + +#define LPDDR4__DENALI_PHY_59_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_59 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_59 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_60_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_60 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_61_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_61 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0 + +#define LPDDR4__DENALI_PHY_62_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_62 +#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_63_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_63 +#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_64_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_64 +#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_65_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_65 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_66_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0 + +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_0__REG DENALI_PHY_66 +#define LPDDR4__SC_PHY_RX_CAL_START_0__FLD LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0 + +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__FLD LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0 + +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0 + +#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0 + +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0 + +#define LPDDR4__DENALI_PHY_69_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69 +#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0 + +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69 +#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0 + +#define LPDDR4__DENALI_PHY_70_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70 +#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0 + +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70 +#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0 + +#define LPDDR4__DENALI_PHY_71_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71 +#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0 + +#define LPDDR4__DENALI_PHY_72_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72 +#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0 + +#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0 + +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0 + +#define LPDDR4__DENALI_PHY_74_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_RX_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0 + +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_75_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_DISABLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0 + +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0 + +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0 + +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0 + +#define LPDDR4__DENALI_PHY_76_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__FLD LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0 + +#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0 + +#define LPDDR4__DENALI_PHY_77_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0 + +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0 + +#define LPDDR4__DENALI_PHY_78_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0 + +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0 + +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0 + +#define LPDDR4__DENALI_PHY_79_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0 + +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0 + +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0 + +#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_80_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_81_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__FLD LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0 + +#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_82_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_82 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_82 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_83_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_83 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_84_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_85_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0 + +#define LPDDR4__DENALI_PHY_86_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0 + +#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0 + +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0 + +#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0 + +#define LPDDR4__DENALI_PHY_87_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0 + +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0 + +#define LPDDR4__DENALI_PHY_88_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0 + +#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_89_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0 + +#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0 + +#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0 + +#define LPDDR4__DENALI_PHY_90_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0 + +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0 + +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0 + +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0 + +#define LPDDR4__DENALI_PHY_91_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0 + +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0 + +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0 + +#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_92_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_93_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_94_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_95_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_96_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_97_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_99_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0 + +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_100_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0 + +#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0 + +#define LPDDR4__DENALI_PHY_101_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0 + +#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_102_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0 + +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_103_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_104_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_105_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0 + +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_106_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_106 +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0 + +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_106 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0 + +#define LPDDR4__DENALI_PHY_107_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0 + +#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_108_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_108 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0 + +#define LPDDR4__DENALI_PHY_109_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_RDLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_110_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0 + +#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0 + +#define LPDDR4__DENALI_PHY_111_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__REG DENALI_PHY_111 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_111 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_112_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_113_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0 + +#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0 + +#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_114_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_114 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_115_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_115 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_116_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_118_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_121_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0 + +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_122_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_123_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_124_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_124 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_125_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_126_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_126_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_126 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_127_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_127_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_127 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_127 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_128_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_128_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_128 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_128 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_129_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_129_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_129 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_129 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_130_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_130_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_130 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_130 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_131_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_131_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0 + +#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_132_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_132_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_132 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_132 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0 + +#define LPDDR4__DENALI_PHY_133_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_133_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0 + +#define LPDDR4__DENALI_PHY_134_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_134_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0 + +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0 + +#define LPDDR4__DENALI_PHY_135_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_135_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_135 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_136_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_136_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_137_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_137 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_138_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_138_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__REG DENALI_PHY_138 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__REG DENALI_PHY_138 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_138 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0 + +#define LPDDR4__DENALI_PHY_139_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_139_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_139 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0 + +#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_139 +#define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0 + +#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_139 +#define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0 + +#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h new file mode 100644 index 000000000..5385e1e87 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h @@ -0,0 +1,2372 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_ + +#define LPDDR4__DENALI_PHY_256_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1 + +#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1 + +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1 + +#define LPDDR4__DENALI_PHY_262_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__FLD LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_263_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_264_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1 + +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1 + +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1 + +#define LPDDR4__DENALI_PHY_265_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1 + +#define LPDDR4__DENALI_PHY_266_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1 + +#define LPDDR4__DENALI_PHY_267_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1 + +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1 + +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1 + +#define LPDDR4__DENALI_PHY_268_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1 + +#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1 + +#define LPDDR4__DENALI_PHY_269_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1 + +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_269 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1 + +#define LPDDR4__DENALI_PHY_270_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET 0U +#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_270__PHY_LPDDR_1 + +#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1 + +#define LPDDR4__DENALI_PHY_271_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_271 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1 + +#define LPDDR4__DENALI_PHY_272_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_272 +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1 + +#define LPDDR4__DENALI_PHY_273_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_273 +#define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1 + +#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_273 +#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1 + +#define LPDDR4__DENALI_PHY_274_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_274 +#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1 + +#define LPDDR4__DENALI_PHY_275_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_275 +#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1 + +#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_276 +#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1 + +#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_277 +#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1 + +#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_278 +#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1 + +#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_279 +#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1 + +#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_280 +#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1 + +#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_281 +#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1 + +#define LPDDR4__DENALI_PHY_282_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1 + +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_282__PHY_SW_FIFO_PTR_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_MASTER_DLY_LOCK_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_SHIFT_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_284_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1 + +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_284 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1 + +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1 + +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_WRLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1 + +#define LPDDR4__DENALI_PHY_285_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1 + +#define LPDDR4__DENALI_PHY_286_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1 + +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_287_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1 + +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_288_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1 + +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1 + +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1 + +#define LPDDR4__DENALI_PHY_289_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1 + +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1 + +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_290_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PERIODIC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_290 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1 + +#define LPDDR4__DENALI_PHY_291_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1 + +#define LPDDR4__DENALI_PHY_292_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_292 +#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1 + +#define LPDDR4__DENALI_PHY_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_293 +#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1 + +#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_294 +#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1 + +#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_295 +#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1 + +#define LPDDR4__DENALI_PHY_296_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_296 +#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1 + +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_296 +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1 + +#define LPDDR4__DENALI_PHY_297_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_297 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_297 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_298_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1 + +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1 + +#define LPDDR4__DENALI_PHY_299_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1 + +#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_299 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1 + +#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1 + +#define LPDDR4__DENALI_PHY_300_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_300 +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1 + +#define LPDDR4__DENALI_PHY_301_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_301 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1 + +#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_301 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_302_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_302__PHY_MEAS_DLY_STEP_VALUE_1 + +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1 + +#define LPDDR4__DENALI_PHY_305_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_306_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_306 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_307_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_308_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_308 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1 + +#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_308 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_309_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_310_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_311_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_312_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1 + +#define LPDDR4__DENALI_PHY_313_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_314_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__REG DENALI_PHY_314 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1 + +#define LPDDR4__DENALI_PHY_315_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_315 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_315 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_316_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_316 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_317_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_317 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1 + +#define LPDDR4__DENALI_PHY_318_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_318 +#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1 + +#define LPDDR4__DENALI_PHY_319_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_319 +#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1 + +#define LPDDR4__DENALI_PHY_320_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_320 +#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1 + +#define LPDDR4__DENALI_PHY_321_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_321 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_322_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1 + +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_1__REG DENALI_PHY_322 +#define LPDDR4__SC_PHY_RX_CAL_START_1__FLD LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1 + +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1 + +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__FLD LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1 + +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1 + +#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1 + +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1 + +#define LPDDR4__DENALI_PHY_325_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325 +#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1 + +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325 +#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1 + +#define LPDDR4__DENALI_PHY_326_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326 +#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1 + +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326 +#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1 + +#define LPDDR4__DENALI_PHY_327_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327 +#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1 + +#define LPDDR4__DENALI_PHY_328_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328 +#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1 + +#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1 + +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1 + +#define LPDDR4__DENALI_PHY_330_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_RX_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1 + +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_331_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_DISABLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1 + +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1 + +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1 + +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1 + +#define LPDDR4__DENALI_PHY_332_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__FLD LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1 + +#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1 + +#define LPDDR4__DENALI_PHY_333_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1 + +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_SAMPLE_WAIT_1 + +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1 + +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1 + +#define LPDDR4__DENALI_PHY_334_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1 + +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1 + +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1 + +#define LPDDR4__DENALI_PHY_335_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1 + +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1 + +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1 + +#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_336_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_RDPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1 + +#define LPDDR4__DENALI_PHY_337_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__FLD LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1 + +#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1 + +#define LPDDR4__DENALI_PHY_338_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_338 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1 + +#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_338 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1 + +#define LPDDR4__DENALI_PHY_339_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1 + +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1 + +#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__REG DENALI_PHY_339 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1 + +#define LPDDR4__DENALI_PHY_340_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_341_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1 + +#define LPDDR4__DENALI_PHY_342_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1 + +#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1 + +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1 + +#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1 + +#define LPDDR4__DENALI_PHY_343_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1 + +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1 + +#define LPDDR4__DENALI_PHY_344_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1 + +#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_345_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1 + +#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1 + +#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1 + +#define LPDDR4__DENALI_PHY_346_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1 + +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1 + +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1 + +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1 + +#define LPDDR4__DENALI_PHY_347_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1 + +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1 + +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1 + +#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_348_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_349_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_350_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_351_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_352_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_353_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_354_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_355_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1 + +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_356_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1 + +#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1 + +#define LPDDR4__DENALI_PHY_357_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1 + +#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_358_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1 + +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1 + +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_359_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1 + +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1 + +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1 + +#define LPDDR4__DENALI_PHY_360_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1 + +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1 + +#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_361_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1 + +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_362_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_362 +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1 + +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_362 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1 + +#define LPDDR4__DENALI_PHY_363_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_QTR_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1 + +#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_364_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_364 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1 + +#define LPDDR4__DENALI_PHY_365_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_RDLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_365__PHY_SW_RDLVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_366_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1 + +#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1 + +#define LPDDR4__DENALI_PHY_367_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__REG DENALI_PHY_367 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_367 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_368_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WDQLVL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_369_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1 + +#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1 + +#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_370_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_370 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1 + +#define LPDDR4__DENALI_PHY_371_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_371 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1 + +#define LPDDR4__DENALI_PHY_372_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_374_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_377_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1 + +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_378_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_379_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_380_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_380 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_381_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_382_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_382_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_382 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_383_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_383_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_383 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_383 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_384_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_384_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_384 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_384 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_385_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_385_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_385 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_385 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_386_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_386_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_386 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_386 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_387_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_387_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1 + +#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_388_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_388_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_388 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_388 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1 + +#define LPDDR4__DENALI_PHY_389_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_389_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1 + +#define LPDDR4__DENALI_PHY_390_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_390_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1 + +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1 + +#define LPDDR4__DENALI_PHY_391_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_391_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_391 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_392_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_392_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ0_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ1_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_393_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ4_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ5_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_393 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_394_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_394_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__REG DENALI_PHY_394 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__REG DENALI_PHY_394 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DM_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_394 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1 + +#define LPDDR4__DENALI_PHY_395_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_395_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_395 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1 + +#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_395 +#define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1 + +#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_395 +#define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1 + +#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h new file mode 100644 index 000000000..f6edad4ea --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h @@ -0,0 +1,2372 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_2_MACROS_H_ + +#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_512 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_512 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2 + +#define LPDDR4__DENALI_PHY_513_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__REG DENALI_PHY_513 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2 + +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2 + +#define LPDDR4__DENALI_PHY_514_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2 + +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2 + +#define LPDDR4__DENALI_PHY_515_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2 + +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2 + +#define LPDDR4__DENALI_PHY_518_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__FLD LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2 + +#define LPDDR4__DENALI_PHY_519_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2 + +#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2 + +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2 + +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2 + +#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_521 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2 + +#define LPDDR4__DENALI_PHY_522_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_522 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2 + +#define LPDDR4__DENALI_PHY_523_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_523 +#define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2 + +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_523 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2 + +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_523 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2 + +#define LPDDR4__DENALI_PHY_524_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2 + +#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2 + +#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2 + +#define LPDDR4__DENALI_PHY_525_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_525 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__REG DENALI_PHY_525 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2 + +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_525 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2 + +#define LPDDR4__DENALI_PHY_526_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET 0U +#define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_526__PHY_LPDDR_2 + +#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2 + +#define LPDDR4__DENALI_PHY_527_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__REG DENALI_PHY_527 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_527 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2 + +#define LPDDR4__DENALI_PHY_528_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_528 +#define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2 + +#define LPDDR4__DENALI_PHY_529_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_529 +#define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2 + +#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_529 +#define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2 + +#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_530 +#define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2 + +#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_531 +#define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2 + +#define LPDDR4__DENALI_PHY_532_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_532 +#define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2 + +#define LPDDR4__DENALI_PHY_533_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_533 +#define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2 + +#define LPDDR4__DENALI_PHY_534_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_534 +#define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2 + +#define LPDDR4__DENALI_PHY_535_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_535 +#define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2 + +#define LPDDR4__DENALI_PHY_536_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_536 +#define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2 + +#define LPDDR4__DENALI_PHY_537_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_537 +#define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2 + +#define LPDDR4__DENALI_PHY_538_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2 + +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2 + +#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_540_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2 + +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_540 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2 + +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2 + +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_WRLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2 + +#define LPDDR4__DENALI_PHY_541_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2 + +#define LPDDR4__DENALI_PHY_542_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_GTLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2 + +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_543_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2 + +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_544_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2 + +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2 + +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2 + +#define LPDDR4__DENALI_PHY_545_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2 + +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2 + +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_546_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__REG DENALI_PHY_546 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_546 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_546 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2 + +#define LPDDR4__DENALI_PHY_547_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_547 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2 + +#define LPDDR4__DENALI_PHY_548_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_548 +#define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2 + +#define LPDDR4__DENALI_PHY_549_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_549 +#define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2 + +#define LPDDR4__DENALI_PHY_550_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_550 +#define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2 + +#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_551 +#define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2 + +#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_552 +#define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2 + +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_552 +#define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2 + +#define LPDDR4__DENALI_PHY_553_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__REG DENALI_PHY_553 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_553 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_554_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__REG DENALI_PHY_554 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2 + +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_554 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2 + +#define LPDDR4__DENALI_PHY_555_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_555_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__REG DENALI_PHY_555 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2 + +#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_555 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2 + +#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_555 +#define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2 + +#define LPDDR4__DENALI_PHY_556_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_556_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_556 +#define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2 + +#define LPDDR4__DENALI_PHY_557_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_557_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_557 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2 + +#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_557 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2 + +#define LPDDR4__DENALI_PHY_558_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_558_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2 + +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_559_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_559_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_560_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2 + +#define LPDDR4__DENALI_PHY_561_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_561_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_561 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_561 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_562_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_562_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_562 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_563_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_563_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_564_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_564_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_564 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2 + +#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_564 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_565_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_565_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_565 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_566_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_566_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_566 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_567_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_567_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__REG DENALI_PHY_567 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_567 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_568_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_568_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_568 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2 + +#define LPDDR4__DENALI_PHY_569_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_569_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_569 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_570_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_570_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__REG DENALI_PHY_570 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2 + +#define LPDDR4__DENALI_PHY_571_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_571_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__REG DENALI_PHY_571 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_571 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_572_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_572_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_572 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_573_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_573 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2 + +#define LPDDR4__DENALI_PHY_574_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_574_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_574 +#define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2 + +#define LPDDR4__DENALI_PHY_575_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_575_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_575 +#define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2 + +#define LPDDR4__DENALI_PHY_576_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_576_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_576 +#define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2 + +#define LPDDR4__DENALI_PHY_577_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_577 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_578_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_578_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__REG DENALI_PHY_578 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_578 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2 + +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_2__REG DENALI_PHY_578 +#define LPDDR4__SC_PHY_RX_CAL_START_2__FLD LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2 + +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__REG DENALI_PHY_578 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2 + +#define LPDDR4__DENALI_PHY_579_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_579_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2 + +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__FLD LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2 + +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2 + +#define LPDDR4__DENALI_PHY_580_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_580_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580 +#define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2 + +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580 +#define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2 + +#define LPDDR4__DENALI_PHY_581_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_581_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581 +#define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2 + +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581 +#define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2 + +#define LPDDR4__DENALI_PHY_582_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_582_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582 +#define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2 + +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582 +#define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2 + +#define LPDDR4__DENALI_PHY_583_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583 +#define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2 + +#define LPDDR4__DENALI_PHY_584_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584 +#define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2 + +#define LPDDR4__DENALI_PHY_585_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_585_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585 +#define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2 + +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585 +#define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2 + +#define LPDDR4__DENALI_PHY_586_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_586_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_2__REG DENALI_PHY_586 +#define LPDDR4__PHY_RX_CAL_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2 + +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__REG DENALI_PHY_586 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2 + +#define LPDDR4__DENALI_PHY_587_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_587_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_DISABLE_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2 + +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2 + +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2 + +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2 + +#define LPDDR4__DENALI_PHY_588_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_588_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__FLD LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2 + +#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2 + +#define LPDDR4__DENALI_PHY_589_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_589_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2 + +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2 + +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2 + +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2 + +#define LPDDR4__DENALI_PHY_590_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_590_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2 + +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2 + +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2 + +#define LPDDR4__DENALI_PHY_591_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_591_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2 + +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2 + +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2 + +#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2 + +#define LPDDR4__DENALI_PHY_592_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_592_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2 + +#define LPDDR4__DENALI_PHY_593_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_593_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__FLD LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2 + +#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2 + +#define LPDDR4__DENALI_PHY_594_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_594_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__REG DENALI_PHY_594 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2 + +#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__REG DENALI_PHY_594 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2 + +#define LPDDR4__DENALI_PHY_595_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_595_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__REG DENALI_PHY_595 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2 + +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__REG DENALI_PHY_595 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2 + +#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__REG DENALI_PHY_595 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2 + +#define LPDDR4__DENALI_PHY_596_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_596_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_597_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_597_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2 + +#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2 + +#define LPDDR4__DENALI_PHY_598_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_598_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2 + +#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2 + +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2 + +#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2 + +#define LPDDR4__DENALI_PHY_599_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_599_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_599 +#define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2 + +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_599 +#define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2 + +#define LPDDR4__DENALI_PHY_600_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_600_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2 + +#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2 + +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2 + +#define LPDDR4__DENALI_PHY_601_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_601_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2 + +#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2 + +#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2 + +#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2 + +#define LPDDR4__DENALI_PHY_602_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_602_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2 + +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2 + +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2 + +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2 + +#define LPDDR4__DENALI_PHY_603_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_603_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2 + +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2 + +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2 + +#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_604_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_604_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2 + +#define LPDDR4__DENALI_PHY_605_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_605_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_605 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_605 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_606_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_606_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_607_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_607_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_608_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_608_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_608 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_608 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_609_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_609_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_610_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_610_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2 + +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2 + +#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2 + +#define LPDDR4__DENALI_PHY_611_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_611_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2 + +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2 + +#define LPDDR4__DENALI_PHY_612_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_612_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_612 +#define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2 + +#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_612 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2 + +#define LPDDR4__DENALI_PHY_613_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_613_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2 + +#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2 + +#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2 + +#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2 + +#define LPDDR4__DENALI_PHY_614_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_614_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2 + +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2 + +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2 + +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2 + +#define LPDDR4__DENALI_PHY_615_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_615_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2 + +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2 + +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2 + +#define LPDDR4__DENALI_PHY_616_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_616_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2 + +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2 + +#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2 + +#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_617_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_617_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2 + +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_618_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_618_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_618 +#define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2 + +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_618 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2 + +#define LPDDR4__DENALI_PHY_619_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_619_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2 + +#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_620_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_620_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_620 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2 + +#define LPDDR4__DENALI_PHY_621_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_621_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_RDLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2 + +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2 + +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2 + +#define LPDDR4__DENALI_PHY_622_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_622_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2 + +#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2 + +#define LPDDR4__DENALI_PHY_623_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_623_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__REG DENALI_PHY_623 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_623 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_624_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_624_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_625_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_625_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2 + +#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2 + +#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2 + +#define LPDDR4__DENALI_PHY_626_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_626_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_626 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2 + +#define LPDDR4__DENALI_PHY_627_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_627_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_627 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2 + +#define LPDDR4__DENALI_PHY_628_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_628_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__REG DENALI_PHY_628 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_628 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_629_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_629_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__REG DENALI_PHY_629 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_629 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_630_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_630_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__REG DENALI_PHY_630 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_630 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_631_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_631_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__REG DENALI_PHY_631 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_631 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_632_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_632_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__REG DENALI_PHY_632 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_632 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_633_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_633_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__REG DENALI_PHY_633 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__FLD LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2 + +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_634_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_634_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__REG DENALI_PHY_634 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_635_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_635_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__REG DENALI_PHY_635 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_636_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_636_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__REG DENALI_PHY_636 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_637_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_637_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__REG DENALI_PHY_637 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_638_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_638_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__REG DENALI_PHY_638 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_639_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_639_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__REG DENALI_PHY_639 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_639 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_640_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_640_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__REG DENALI_PHY_640 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_640 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_641_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_641_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__REG DENALI_PHY_641 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_641 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_642_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_642_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__REG DENALI_PHY_642 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_642 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_643_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_643_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2 + +#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2 + +#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_644_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_644_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__REG DENALI_PHY_644 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_644 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2 + +#define LPDDR4__DENALI_PHY_645_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_645_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2 + +#define LPDDR4__DENALI_PHY_646_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_646_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2 + +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2 + +#define LPDDR4__DENALI_PHY_647_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_647_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_647 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_648_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_648_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_649_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_649 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_650_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_650_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__REG DENALI_PHY_650 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__REG DENALI_PHY_650 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_650 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2 + +#define LPDDR4__DENALI_PHY_651_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_651_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_651 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2 + +#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_651 +#define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2 + +#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_651 +#define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2 + +#endif /* REG_LPDDR4_DATA_SLICE_2_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h new file mode 100644 index 000000000..73e5f71df --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h @@ -0,0 +1,2372 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_3_MACROS_H_ + +#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_768 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_768 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3 + +#define LPDDR4__DENALI_PHY_769_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__REG DENALI_PHY_769 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3 + +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3 + +#define LPDDR4__DENALI_PHY_770_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3 + +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3 + +#define LPDDR4__DENALI_PHY_771_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3 + +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3 + +#define LPDDR4__DENALI_PHY_774_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__FLD LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3 + +#define LPDDR4__DENALI_PHY_775_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3 + +#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3 + +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3 + +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3 + +#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_777 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3 + +#define LPDDR4__DENALI_PHY_778_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_778 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3 + +#define LPDDR4__DENALI_PHY_779_READ_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x0101FF7FU +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_779 +#define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3 + +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_779 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3 + +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_779 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3 + +#define LPDDR4__DENALI_PHY_780_READ_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x007F3F01U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3 + +#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3 + +#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3 + +#define LPDDR4__DENALI_PHY_781_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_781 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__REG DENALI_PHY_781 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3 + +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_781 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3 + +#define LPDDR4__DENALI_PHY_782_READ_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x070101FFU +#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET 0U +#define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_782__PHY_LPDDR_3 + +#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3 + +#define LPDDR4__DENALI_PHY_783_READ_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x000301FFU +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__REG DENALI_PHY_783 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_783 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3 + +#define LPDDR4__DENALI_PHY_784_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_784 +#define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3 + +#define LPDDR4__DENALI_PHY_785_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_785 +#define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3 + +#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_785 +#define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3 + +#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_786 +#define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3 + +#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_787 +#define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3 + +#define LPDDR4__DENALI_PHY_788_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_788 +#define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3 + +#define LPDDR4__DENALI_PHY_789_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_789 +#define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3 + +#define LPDDR4__DENALI_PHY_790_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_790 +#define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3 + +#define LPDDR4__DENALI_PHY_791_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_791 +#define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3 + +#define LPDDR4__DENALI_PHY_792_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_792 +#define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3 + +#define LPDDR4__DENALI_PHY_793_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_793 +#define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3 + +#define LPDDR4__DENALI_PHY_794_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3 + +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_794__PHY_SW_FIFO_PTR_RST_DISABLE_3 + +#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_MASTER_DLY_LOCK_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_SHIFT_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_796_READ_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0xFF030001U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3 + +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_796 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3 + +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3 + +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH 8U +#define LPDDR4__PHY_WRLVL_PER_START_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_WRLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3 + +#define LPDDR4__DENALI_PHY_797_READ_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x00FF0F3FU +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3 + +#define LPDDR4__DENALI_PHY_798_READ_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x0F3F03FFU +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_PER_START_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_GTLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3 + +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_799_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3 + +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_800_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3 + +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3 + +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3 + +#define LPDDR4__DENALI_PHY_801_READ_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x0F07FF07U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3 + +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3 + +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_802_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__REG DENALI_PHY_802 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_802 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PERIODIC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_802 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3 + +#define LPDDR4__DENALI_PHY_803_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_803 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3 + +#define LPDDR4__DENALI_PHY_804_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_804 +#define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3 + +#define LPDDR4__DENALI_PHY_805_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_805 +#define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3 + +#define LPDDR4__DENALI_PHY_806_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_806 +#define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3 + +#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_807 +#define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3 + +#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_808 +#define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3 + +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_808 +#define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3 + +#define LPDDR4__DENALI_PHY_809_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__REG DENALI_PHY_809 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_809 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_810_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__REG DENALI_PHY_810 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3 + +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_810 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3 + +#define LPDDR4__DENALI_PHY_811_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_811_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__REG DENALI_PHY_811 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3 + +#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_811 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3 + +#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_811 +#define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3 + +#define LPDDR4__DENALI_PHY_812_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_812_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_812 +#define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3 + +#define LPDDR4__DENALI_PHY_813_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_813_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__REG DENALI_PHY_813 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3 + +#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_813 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3 + +#define LPDDR4__DENALI_PHY_814_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_814_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__FLD LPDDR4__DENALI_PHY_814__PHY_MEAS_DLY_STEP_VALUE_3 + +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_815_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_815_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_816_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3 + +#define LPDDR4__DENALI_PHY_817_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_817_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_817 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_817 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_818_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_818_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH 17U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_818 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_819_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_819_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_820_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_820_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_820 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3 + +#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_820 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_821_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_821_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_821 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_822_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_822_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_822 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_823_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_823_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__REG DENALI_PHY_823 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_823 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_824_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_824_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_824 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3 + +#define LPDDR4__DENALI_PHY_825_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_825_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_825 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_826_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_826_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__REG DENALI_PHY_826 +#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3 + +#define LPDDR4__DENALI_PHY_827_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_827_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__REG DENALI_PHY_827 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_827 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_828_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_828_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_828 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_829_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_829 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3 + +#define LPDDR4__DENALI_PHY_830_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_830_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_830 +#define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3 + +#define LPDDR4__DENALI_PHY_831_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_831_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_831 +#define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3 + +#define LPDDR4__DENALI_PHY_832_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_832_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_832 +#define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3 + +#define LPDDR4__DENALI_PHY_833_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_833 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_834_READ_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_834_WRITE_MASK 0x010001FFU +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__REG DENALI_PHY_834 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_834 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3 + +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET 0U +#define LPDDR4__SC_PHY_RX_CAL_START_3__REG DENALI_PHY_834 +#define LPDDR4__SC_PHY_RX_CAL_START_3__FLD LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3 + +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET 0U +#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__REG DENALI_PHY_834 +#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3 + +#define LPDDR4__DENALI_PHY_835_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_835_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3 + +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3_WOSET 0U +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__FLD LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3 + +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3 + +#define LPDDR4__DENALI_PHY_836_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_836_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836 +#define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3 + +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836 +#define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3 + +#define LPDDR4__DENALI_PHY_837_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_837_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837 +#define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3 + +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837 +#define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3 + +#define LPDDR4__DENALI_PHY_838_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_838_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838 +#define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3 + +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838 +#define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3 + +#define LPDDR4__DENALI_PHY_839_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839 +#define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3 + +#define LPDDR4__DENALI_PHY_840_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840 +#define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3 + +#define LPDDR4__DENALI_PHY_841_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_841_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841 +#define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3 + +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841 +#define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3 + +#define LPDDR4__DENALI_PHY_842_READ_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_842_WRITE_MASK 0x01FF07FFU +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH 11U +#define LPDDR4__PHY_RX_CAL_OBS_3__REG DENALI_PHY_842 +#define LPDDR4__PHY_RX_CAL_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3 + +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__REG DENALI_PHY_842 +#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3 + +#define LPDDR4__DENALI_PHY_843_READ_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_843_WRITE_MASK 0x017F7F01U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RX_CAL_DISABLE_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_DISABLE_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3 + +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3 + +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH 7U +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3 + +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET 0U +#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3 + +#define LPDDR4__DENALI_PHY_844_READ_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_844_WRITE_MASK 0x07FF0FFFU +#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH 12U +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__FLD LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3 + +#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3 + +#define LPDDR4__DENALI_PHY_845_READ_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_845_WRITE_MASK 0x03FFFF1FU +#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3 + +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_SAMPLE_WAIT_3 + +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3 + +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3 + +#define LPDDR4__DENALI_PHY_846_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_846_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3 + +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3 + +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3 + +#define LPDDR4__DENALI_PHY_847_READ_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_847_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3 + +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3 + +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3 + +#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3 + +#define LPDDR4__DENALI_PHY_848_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_848_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_RDPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3 + +#define LPDDR4__DENALI_PHY_849_READ_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_849_WRITE_MASK 0x3FFF07FFU +#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__FLD LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3 + +#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3 + +#define LPDDR4__DENALI_PHY_850_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_850_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_WIDTH 14U +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__REG DENALI_PHY_850 +#define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3 + +#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3_WIDTH 14U +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__REG DENALI_PHY_850 +#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3 + +#define LPDDR4__DENALI_PHY_851_READ_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_851_WRITE_MASK 0x00001F1FU +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__REG DENALI_PHY_851 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3 + +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3_WIDTH 5U +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__REG DENALI_PHY_851 +#define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3__FLD LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3 + +#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3_WIDTH 5U +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__REG DENALI_PHY_851 +#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3 + +#define LPDDR4__DENALI_PHY_852_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_852_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3 + +#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_853_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_853_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3 + +#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3 + +#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3 + +#define LPDDR4__DENALI_PHY_854_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_854_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3 + +#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3 + +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3 + +#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3 + +#define LPDDR4__DENALI_PHY_855_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_855_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_855 +#define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3 + +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_855 +#define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3 + +#define LPDDR4__DENALI_PHY_856_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_856_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3 + +#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3 + +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3 + +#define LPDDR4__DENALI_PHY_857_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_857_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3 + +#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3 + +#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3 + +#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3 + +#define LPDDR4__DENALI_PHY_858_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_858_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3 + +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3 + +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3 + +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3 + +#define LPDDR4__DENALI_PHY_859_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_859_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3 + +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3 + +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3 + +#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_860_READ_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_860_WRITE_MASK 0x003F1F1FU +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH 6U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3 + +#define LPDDR4__DENALI_PHY_861_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_861_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_861 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_861 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_862_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_862_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_863_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_863_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_864_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_864_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_864 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_864 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_865_READ_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_865_WRITE_MASK 0x000703FFU +#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3 + +#define LPDDR4__DENALI_PHY_866_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_866_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3 + +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3 + +#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3 + +#define LPDDR4__DENALI_PHY_867_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_867_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3 + +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3 + +#define LPDDR4__DENALI_PHY_868_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_868_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_868 +#define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3 + +#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_868 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3 + +#define LPDDR4__DENALI_PHY_869_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_869_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3 + +#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3 + +#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3 + +#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3 + +#define LPDDR4__DENALI_PHY_870_READ_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_870_WRITE_MASK 0x1F1F0103U +#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3 + +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET 0U +#define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3 + +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3 + +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3 + +#define LPDDR4__DENALI_PHY_871_READ_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_871_WRITE_MASK 0x3F07FF0FU +#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3 + +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3 + +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3 + +#define LPDDR4__DENALI_PHY_872_READ_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_872_WRITE_MASK 0xFF0FFFFFU +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3 + +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3 + +#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3 + +#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_873_READ_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_873_WRITE_MASK 0x1F0F3F0FU +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3 + +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_874_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_874_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_874 +#define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3 + +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_874 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3 + +#define LPDDR4__DENALI_PHY_875_READ_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_875_WRITE_MASK 0x0F010FFFU +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_QTR_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3 + +#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_876_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_876_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_876 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3 + +#define LPDDR4__DENALI_PHY_877_READ_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_877_WRITE_MASK 0x3F0103FFU +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_DVW_MIN_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_RDLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3 + +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3_WOSET 0U +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_877__PHY_SW_RDLVL_DVW_MIN_EN_3 + +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3_WIDTH 6U +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3 + +#define LPDDR4__DENALI_PHY_878_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_878_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3 + +#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3 + +#define LPDDR4__DENALI_PHY_879_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_879_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__REG DENALI_PHY_879 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3 + +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_879 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3 + +#define LPDDR4__DENALI_PHY_880_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_880_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WDQLVL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_881_READ_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_881_WRITE_MASK 0x001F3F7FU +#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3 + +#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3_WIDTH 6U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3 + +#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3 + +#define LPDDR4__DENALI_PHY_882_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_882_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_882 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3 + +#define LPDDR4__DENALI_PHY_883_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_883_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_883 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3 + +#define LPDDR4__DENALI_PHY_884_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_884_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__REG DENALI_PHY_884 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_884 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_885_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_885_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__REG DENALI_PHY_885 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_885 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_886_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_886_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__REG DENALI_PHY_886 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_886 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_887_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_887_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__REG DENALI_PHY_887 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_887 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_888_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_888_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__REG DENALI_PHY_888 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_888 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_889_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_889_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__REG DENALI_PHY_889 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__FLD LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3 + +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_890_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_890_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__REG DENALI_PHY_890 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_891_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_891_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__REG DENALI_PHY_891 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_892_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_892_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__REG DENALI_PHY_892 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_893_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_893_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__REG DENALI_PHY_893 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_894_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_894_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__REG DENALI_PHY_894 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_895_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_895_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__REG DENALI_PHY_895 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_895 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_896_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_896_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__REG DENALI_PHY_896 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_896 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_897_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_897_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__REG DENALI_PHY_897 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_897 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_898_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_898_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__REG DENALI_PHY_898 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_898 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_899_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_899_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3 + +#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3 + +#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_900_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_900_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__REG DENALI_PHY_900 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_900 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3 + +#define LPDDR4__DENALI_PHY_901_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_901_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3 + +#define LPDDR4__DENALI_PHY_902_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_902_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3 + +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3 + +#define LPDDR4__DENALI_PHY_903_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_903_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_903 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_904_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_904_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ0_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ1_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_905_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ4_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ5_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_905 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_906_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_906_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__REG DENALI_PHY_906 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__REG DENALI_PHY_906 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DM_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_906 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3 + +#define LPDDR4__DENALI_PHY_907_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_907_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_907 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3 + +#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_907 +#define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3 + +#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_907 +#define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3 + +#endif /* REG_LPDDR4_DATA_SLICE_3_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h new file mode 100644 index 000000000..4e33d04d1 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h @@ -0,0 +1,7792 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ +#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ + +#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U +#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U +#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U +#define LPDDR4__DENALI_CTL_0__START_WOSET 0U +#define LPDDR4__START__REG DENALI_CTL_0 +#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START + +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U +#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0 +#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS + +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U +#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0 +#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID + +#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1 +#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0 + +#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2 +#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1 + +#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U +#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG + +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U +#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG + +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U +#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG + +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3 +#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U +#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5 +#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES + +#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U +#define LPDDR4__TINIT_F0__REG DENALI_CTL_7 +#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0 + +#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U +#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8 +#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0 + +#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U +#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9 +#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0 + +#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U +#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10 +#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0 + +#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U +#define LPDDR4__TINIT_F1__REG DENALI_CTL_11 +#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1 + +#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U +#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12 +#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1 + +#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U +#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13 +#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1 + +#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U +#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14 +#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1 + +#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U +#define LPDDR4__TINIT_F2__REG DENALI_CTL_15 +#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2 + +#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U +#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16 +#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2 + +#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U +#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17 +#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2 + +#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U +#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18 +#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2 + +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18 +#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_CTL_19_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U +#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19 +#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT 8U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET 0U +#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19 +#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS + +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET 0U +#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19 +#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT + +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT 24U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET 0U +#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19 +#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE + +#define LPDDR4__DENALI_CTL_20_READ_MASK 0x03013F01U +#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x03013F01U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20 +#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE + +#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT 8U +#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH 6U +#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20 +#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR + +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT 16U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20 +#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE + +#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH 2U +#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20 +#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT + +#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F1F03U +#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F1F03U +#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH 2U +#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0 + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1 + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2 + +#define LPDDR4__DENALI_CTL_22_READ_MASK 0x00030303U +#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x00030303U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2 + +#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U +#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23 +#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON + +#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U +#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24 +#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE + +#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT 0U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH 1U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR 0U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET 0U +#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25 +#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0 + +#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT 8U +#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH 24U +#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25 +#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1 + +#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT 0U +#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH 8U +#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26 +#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2 + +#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT 8U +#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH 8U +#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26 +#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3 + +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET 0U +#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26 +#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE + +#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFF0F7FFFU +#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFF0F7FFFU +#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT 0U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH 15U +#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27 +#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD + +#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT 16U +#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH 4U +#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27 +#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES + +#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH 8U +#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27 +#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0 + +#define LPDDR4__DENALI_CTL_28_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH 8U +#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28 +#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1 + +#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH 8U +#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28 +#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2 + +#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH 8U +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28 +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT 24U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH 8U +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28 +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_29_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH 8U +#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29 +#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT + +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 8U +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29 +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD + +#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH 16U +#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29 +#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT + +#define LPDDR4__DENALI_CTL_30_READ_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT 0U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH 1U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR 0U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET 0U +#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30 +#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST + +#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT 8U +#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30 +#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0 + +#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31 +#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0 + +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31 +#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0 + +#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32 +#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0 + +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32 +#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1 + +#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33 +#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1 + +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33 +#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1 + +#define LPDDR4__DENALI_CTL_34_READ_MASK 0x7F7FFFFFU +#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0x7F7FFFFFU +#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH 16U +#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34 +#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1 + +#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34 +#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0 + +#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH 7U +#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34 +#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0 + +#define LPDDR4__DENALI_CTL_35_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35 +#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1 + +#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH 7U +#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35 +#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1 + +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35 +#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2 + +#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH 7U +#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35 +#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2 + +#define LPDDR4__DENALI_CTL_36_READ_MASK 0x00FF1F07U +#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0x00FF1F07U +#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH 3U +#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36 +#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL + +#define LPDDR4__DENALI_CTL_36__TCCD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT 8U +#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH 5U +#define LPDDR4__TCCD__REG DENALI_CTL_36 +#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD + +#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH 8U +#define LPDDR4__TRRD_F0__REG DENALI_CTL_36 +#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0 + +#define LPDDR4__DENALI_CTL_37_READ_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH 9U +#define LPDDR4__TRC_F0__REG DENALI_CTL_37 +#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0 + +#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH 8U +#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37 +#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0 + +#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH 6U +#define LPDDR4__TWTR_F0__REG DENALI_CTL_37 +#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0 + +#define LPDDR4__DENALI_CTL_38_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH 8U +#define LPDDR4__TRP_F0__REG DENALI_CTL_38 +#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0 + +#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH 9U +#define LPDDR4__TFAW_F0__REG DENALI_CTL_38 +#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0 + +#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH 8U +#define LPDDR4__TRRD_F1__REG DENALI_CTL_38 +#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1 + +#define LPDDR4__DENALI_CTL_39_READ_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH 9U +#define LPDDR4__TRC_F1__REG DENALI_CTL_39 +#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1 + +#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH 8U +#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39 +#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1 + +#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH 6U +#define LPDDR4__TWTR_F1__REG DENALI_CTL_39 +#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1 + +#define LPDDR4__DENALI_CTL_40_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH 8U +#define LPDDR4__TRP_F1__REG DENALI_CTL_40 +#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1 + +#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH 9U +#define LPDDR4__TFAW_F1__REG DENALI_CTL_40 +#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1 + +#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH 8U +#define LPDDR4__TRRD_F2__REG DENALI_CTL_40 +#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2 + +#define LPDDR4__DENALI_CTL_41_READ_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0x3FFF01FFU +#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH 9U +#define LPDDR4__TRC_F2__REG DENALI_CTL_41 +#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2 + +#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH 8U +#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41 +#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2 + +#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH 6U +#define LPDDR4__TWTR_F2__REG DENALI_CTL_41 +#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2 + +#define LPDDR4__DENALI_CTL_42_READ_MASK 0x3F01FFFFU +#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x3F01FFFFU +#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH 8U +#define LPDDR4__TRP_F2__REG DENALI_CTL_42 +#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2 + +#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH 9U +#define LPDDR4__TFAW_F2__REG DENALI_CTL_42 +#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2 + +#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT 24U +#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH 6U +#define LPDDR4__TCCDMW__REG DENALI_CTL_42 +#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW + +#define LPDDR4__DENALI_CTL_43_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH 8U +#define LPDDR4__TRTP_F0__REG DENALI_CTL_43 +#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0 + +#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH 8U +#define LPDDR4__TMRD_F0__REG DENALI_CTL_43 +#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0 + +#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH 8U +#define LPDDR4__TMOD_F0__REG DENALI_CTL_43 +#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0 + +#define LPDDR4__DENALI_CTL_44_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH 17U +#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44 +#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0 + +#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH 5U +#define LPDDR4__TCKE_F0__REG DENALI_CTL_44 +#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0 + +#define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH 8U +#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45 +#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0 + +#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH 8U +#define LPDDR4__TRTP_F1__REG DENALI_CTL_45 +#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1 + +#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH 8U +#define LPDDR4__TMRD_F1__REG DENALI_CTL_45 +#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1 + +#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH 8U +#define LPDDR4__TMOD_F1__REG DENALI_CTL_45 +#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1 + +#define LPDDR4__DENALI_CTL_46_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH 17U +#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46 +#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1 + +#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH 5U +#define LPDDR4__TCKE_F1__REG DENALI_CTL_46 +#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1 + +#define LPDDR4__DENALI_CTL_47_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH 8U +#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47 +#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1 + +#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH 8U +#define LPDDR4__TRTP_F2__REG DENALI_CTL_47 +#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2 + +#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH 8U +#define LPDDR4__TMRD_F2__REG DENALI_CTL_47 +#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2 + +#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH 8U +#define LPDDR4__TMOD_F2__REG DENALI_CTL_47 +#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2 + +#define LPDDR4__DENALI_CTL_48_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH 17U +#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48 +#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2 + +#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH 5U +#define LPDDR4__TCKE_F2__REG DENALI_CTL_48 +#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2 + +#define LPDDR4__DENALI_CTL_49_READ_MASK 0x070707FFU +#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x070707FFU +#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH 8U +#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49 +#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2 + +#define LPDDR4__DENALI_CTL_49__TPPD_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT 8U +#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH 3U +#define LPDDR4__TPPD__REG DENALI_CTL_49 +#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD + +#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT 16U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH 3U +#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49 +#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4 + +#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT 24U +#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH 3U +#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49 +#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5 + +#define LPDDR4__DENALI_CTL_50_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT 0U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH 1U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR 0U +#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET 0U +#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50 +#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP + +#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH 8U +#define LPDDR4__TRCD_F0__REG DENALI_CTL_50 +#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0 + +#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH 8U +#define LPDDR4__TWR_F0__REG DENALI_CTL_50 +#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0 + +#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH 8U +#define LPDDR4__TRCD_F1__REG DENALI_CTL_50 +#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1 + +#define LPDDR4__DENALI_CTL_51_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH 8U +#define LPDDR4__TWR_F1__REG DENALI_CTL_51 +#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1 + +#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH 8U +#define LPDDR4__TRCD_F2__REG DENALI_CTL_51 +#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2 + +#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH 8U +#define LPDDR4__TWR_F2__REG DENALI_CTL_51 +#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2 + +#define LPDDR4__DENALI_CTL_51__TMRR_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT 24U +#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH 4U +#define LPDDR4__TMRR__REG DENALI_CTL_51 +#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR + +#define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F03FF1FU +#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F03FF1FU +#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT 0U +#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH 5U +#define LPDDR4__TCACKEL__REG DENALI_CTL_52 +#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL + +#define LPDDR4__DENALI_CTL_52__TCAENT_MASK 0x0003FF00U +#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT 8U +#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH 10U +#define LPDDR4__TCAENT__REG DENALI_CTL_52 +#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT + +#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT 24U +#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH 6U +#define LPDDR4__TCAMRD__REG DENALI_CTL_52 +#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD + +#define LPDDR4__DENALI_CTL_53_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT 0U +#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH 5U +#define LPDDR4__TCAEXT__REG DENALI_CTL_53 +#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT + +#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT 8U +#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH 5U +#define LPDDR4__TCACKEH__REG DENALI_CTL_53 +#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH + +#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH 5U +#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53 +#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0 + +#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH 5U +#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53 +#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1 + +#define LPDDR4__DENALI_CTL_54_READ_MASK 0x0101011FU +#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x0101011FU +#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH 5U +#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54 +#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2 + +#define LPDDR4__DENALI_CTL_54__AP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_54__AP_SHIFT 8U +#define LPDDR4__DENALI_CTL_54__AP_WIDTH 1U +#define LPDDR4__DENALI_CTL_54__AP_WOCLR 0U +#define LPDDR4__DENALI_CTL_54__AP_WOSET 0U +#define LPDDR4__AP__REG DENALI_CTL_54 +#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP + +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH 1U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR 0U +#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET 0U +#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54 +#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP + +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT 24U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH 1U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR 0U +#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET 0U +#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54 +#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT + +#define LPDDR4__DENALI_CTL_55_READ_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH 8U +#define LPDDR4__TDAL_F0__REG DENALI_CTL_55 +#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0 + +#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH 8U +#define LPDDR4__TDAL_F1__REG DENALI_CTL_55 +#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1 + +#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH 8U +#define LPDDR4__TDAL_F2__REG DENALI_CTL_55 +#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2 + +#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT 24U +#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH 5U +#define LPDDR4__BSTLEN__REG DENALI_CTL_55 +#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN + +#define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH 8U +#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0 + +#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH 8U +#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0 + +#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH 8U +#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0 + +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH 8U +#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56 +#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1 + +#define LPDDR4__DENALI_CTL_57_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH 8U +#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57 +#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1 + +#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH 8U +#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57 +#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1 + +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57 +#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE + +#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT 24U +#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH 2U +#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57 +#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6 + +#define LPDDR4__DENALI_CTL_58_READ_MASK 0x0101017FU +#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x0101017FU +#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT 0U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH 7U +#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58 +#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7 + +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET 0U +#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58 +#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN + +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT 16U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH 1U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR 0U +#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET 0U +#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58 +#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8 + +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT 24U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH 1U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR 0U +#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET 0U +#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58 +#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM + +#define LPDDR4__DENALI_CTL_59_READ_MASK 0x07010100U +#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x07010100U +#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT 0U +#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET 0U +#define LPDDR4__AREFRESH__REG DENALI_CTL_59 +#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH + +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET 0U +#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59 +#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS + +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET 0U +#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59 +#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE + +#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT 24U +#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH 3U +#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59 +#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9 + +#define LPDDR4__DENALI_CTL_60_READ_MASK 0x0003FF3FU +#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0003FF3FU +#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60 +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH + +#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH 10U +#define LPDDR4__TRFC_F0__REG DENALI_CTL_60 +#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0 + +#define LPDDR4__DENALI_CTL_61_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH 20U +#define LPDDR4__TREF_F0__REG DENALI_CTL_61 +#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0 + +#define LPDDR4__DENALI_CTL_62_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH 10U +#define LPDDR4__TRFC_F1__REG DENALI_CTL_62 +#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1 + +#define LPDDR4__DENALI_CTL_63_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH 20U +#define LPDDR4__TREF_F1__REG DENALI_CTL_63 +#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1 + +#define LPDDR4__DENALI_CTL_64_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH 10U +#define LPDDR4__TRFC_F2__REG DENALI_CTL_64 +#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2 + +#define LPDDR4__DENALI_CTL_65_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH 20U +#define LPDDR4__TREF_F2__REG DENALI_CTL_65 +#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2 + +#define LPDDR4__DENALI_CTL_66_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH 20U +#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66 +#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL + +#define LPDDR4__DENALI_CTL_67_READ_MASK 0x03FF0101U +#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x03FF0101U +#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET 0U +#define LPDDR4__PBR_EN__REG DENALI_CTL_67 +#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN + +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT 8U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH 1U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR 0U +#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET 0U +#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67 +#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER + +#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH 10U +#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67 +#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0 + +#define LPDDR4__DENALI_CTL_68_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH 16U +#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68 +#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0 + +#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH 10U +#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68 +#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1 + +#define LPDDR4__DENALI_CTL_69_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH 16U +#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69 +#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1 + +#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH 10U +#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69 +#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2 + +#define LPDDR4__DENALI_CTL_70_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH 16U +#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70 +#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2 + +#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH 16U +#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70 +#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT + +#define LPDDR4__DENALI_CTL_71_READ_MASK 0x1F1F010FU +#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x1F1F010FU +#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT 0U +#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH 4U +#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71 +#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY + +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET 0U +#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71 +#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN + +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71 +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD + +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 24U +#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71 +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD + +#define LPDDR4__DENALI_CTL_72_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH 16U +#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72 +#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0 + +#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH 16U +#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72 +#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1 + +#define LPDDR4__DENALI_CTL_73_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH 16U +#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73 +#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2 + +#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH 8U +#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73 +#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0 + +#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH 8U +#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73 +#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1 + +#define LPDDR4__DENALI_CTL_74_READ_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH 8U +#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74 +#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2 + +#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH 5U +#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74 +#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0 + +#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH 5U +#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74 +#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0 + +#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH 5U +#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74 +#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0 + +#define LPDDR4__DENALI_CTL_75_READ_MASK 0x1F010F1FU +#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x1F010F1FU +#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH 5U +#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75 +#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0 + +#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH 4U +#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75 +#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0 + +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75 +#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0 + +#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH 5U +#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75 +#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1 + +#define LPDDR4__DENALI_CTL_76_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH 5U +#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76 +#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1 + +#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH 5U +#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76 +#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1 + +#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH 5U +#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76 +#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1 + +#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH 4U +#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76 +#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1 + +#define LPDDR4__DENALI_CTL_77_READ_MASK 0x1F1F1F01U +#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x1F1F1F01U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77 +#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1 + +#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH 5U +#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77 +#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2 + +#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH 5U +#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77 +#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2 + +#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH 5U +#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77 +#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2 + +#define LPDDR4__DENALI_CTL_78_READ_MASK 0x00010F1FU +#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x00010F1FU +#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH 5U +#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78 +#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2 + +#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH 4U +#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78 +#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2 + +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78 +#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2 + +#define LPDDR4__DENALI_CTL_79_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH 16U +#define LPDDR4__TXSR_F0__REG DENALI_CTL_79 +#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0 + +#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH 16U +#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79 +#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0 + +#define LPDDR4__DENALI_CTL_80_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH 16U +#define LPDDR4__TXSR_F1__REG DENALI_CTL_80 +#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1 + +#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH 16U +#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80 +#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1 + +#define LPDDR4__DENALI_CTL_81_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH 16U +#define LPDDR4__TXSR_F2__REG DENALI_CTL_81 +#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2 + +#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH 16U +#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81 +#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2 + +#define LPDDR4__DENALI_CTL_82_READ_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH 5U +#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82 +#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0 + +#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH 5U +#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82 +#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0 + +#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH 5U +#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82 +#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0 + +#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH 8U +#define LPDDR4__TSR_F0__REG DENALI_CTL_82 +#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0 + +#define LPDDR4__DENALI_CTL_83_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH 3U +#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83 +#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0 + +#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH 5U +#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83 +#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0 + +#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH 5U +#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83 +#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0 + +#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH 5U +#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83 +#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0 + +#define LPDDR4__DENALI_CTL_84_READ_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH 5U +#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84 +#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1 + +#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH 5U +#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84 +#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1 + +#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH 5U +#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84 +#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1 + +#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH 8U +#define LPDDR4__TSR_F1__REG DENALI_CTL_84 +#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1 + +#define LPDDR4__DENALI_CTL_85_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH 3U +#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85 +#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1 + +#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH 5U +#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85 +#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1 + +#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH 5U +#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85 +#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1 + +#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH 5U +#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85 +#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1 + +#define LPDDR4__DENALI_CTL_86_READ_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0xFF1F1F1FU +#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH 5U +#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86 +#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2 + +#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH 5U +#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86 +#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2 + +#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH 5U +#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86 +#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2 + +#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH 8U +#define LPDDR4__TSR_F2__REG DENALI_CTL_86 +#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2 + +#define LPDDR4__DENALI_CTL_87_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH 3U +#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87 +#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2 + +#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH 5U +#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87 +#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2 + +#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH 5U +#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87 +#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2 + +#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH 5U +#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87 +#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2 + +#define LPDDR4__DENALI_CTL_88_READ_MASK 0x07010101U +#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x07010101U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88 +#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT 8U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH 1U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR 0U +#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET 0U +#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88 +#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10 + +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT 16U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET 0U +#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88 +#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH + +#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT 24U +#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH 3U +#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88 +#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY + +#define LPDDR4__DENALI_CTL_89_READ_MASK 0x01010300U +#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0x01010300U +#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT 0U +#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH 5U +#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89 +#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11 + +#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH 2U +#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89 +#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS + +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET 0U +#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89 +#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN + +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET 0U +#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89 +#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN + +#define LPDDR4__DENALI_CTL_90_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET 0U +#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90 +#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN + +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET 0U +#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90 +#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN + +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET 0U +#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90 +#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN + +#define LPDDR4__DENALI_CTL_91_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_92_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT 16U +#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH 3U +#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92 +#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG + +#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT 24U +#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH 3U +#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92 +#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12 + +#define LPDDR4__DENALI_CTL_93_READ_MASK 0xFFFFFF07U +#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0xFFFFFF07U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT 0U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH 3U +#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13 + +#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT 8U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH 8U +#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14 + +#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT 16U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH 8U +#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15 + +#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT 24U +#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH 8U +#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93 +#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16 + +#define LPDDR4__DENALI_CTL_94_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_95_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_100_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_101_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_102_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102 +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0 + +#define LPDDR4__DENALI_CTL_103_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_104_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_105_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_106_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_107_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_108_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108 +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0 + +#define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109 +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1 + +#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_114_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_115_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115 +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1 + +#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116 +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2 + +#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_121_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_122_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122 +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2 + +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT 24U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH 1U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR 0U +#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET 0U +#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122 +#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF + +#define LPDDR4__DENALI_CTL_123_READ_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123 +#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123 +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1 + +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123 +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE + +#define LPDDR4__DENALI_CTL_124_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_125_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_128_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET 0U +#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128 +#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL + +#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT 24U +#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH 3U +#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128 +#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND + +#define LPDDR4__DENALI_CTL_129_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT 0U +#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH 8U +#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129 +#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW + +#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT 8U +#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH 17U +#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129 +#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS + +#define LPDDR4__DENALI_CTL_130_READ_MASK 0x01030107U +#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0x01030107U +#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH 3U +#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130 +#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS + +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT 8U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH 1U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR 0U +#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET 0U +#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130 +#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS + +#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH 2U +#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130 +#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS + +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT 24U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET 0U +#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130 +#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL + +#define LPDDR4__DENALI_CTL_131_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH 2U +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131 +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE + +#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH 8U +#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131 +#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0 + +#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH 8U +#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131 +#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0 + +#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH 8U +#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131 +#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1 + +#define LPDDR4__DENALI_CTL_132_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH 8U +#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132 +#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1 + +#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH 8U +#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132 +#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2 + +#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH 8U +#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132 +#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2 + +#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT 24U +#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH 7U +#define LPDDR4__LP_CMD__REG DENALI_CTL_132 +#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD + +#define LPDDR4__DENALI_CTL_133_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_135_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135 +#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135 +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_137_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137 +#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137 +#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139_READ_MASK 0x3F0F0F0FU +#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x3F0F0F0FU +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139 +#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH 6U +#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139 +#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN + +#define LPDDR4__DENALI_CTL_140_READ_MASK 0x070FFF01U +#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x070FFF01U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET 0U +#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140 +#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN + +#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT 8U +#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH 12U +#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140 +#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT + +#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT 24U +#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH 3U +#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140 +#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP + +#define LPDDR4__DENALI_CTL_141_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH 7U +#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141 +#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0 + +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH 7U +#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141 +#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1 + +#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141 +#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN + +#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141 +#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN + +#define LPDDR4__DENALI_CTL_142_READ_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH 3U +#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142 +#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN + +#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142 +#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE + +#define LPDDR4__DENALI_CTL_143_READ_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143 +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE + +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143 +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE + +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143 +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE + +#define LPDDR4__DENALI_CTL_144_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_145_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_146_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_147_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147 +#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN + +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147 +#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN + +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147 +#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN + +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT 24U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH 1U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR 0U +#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET 0U +#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147 +#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17 + +#define LPDDR4__DENALI_CTL_148_READ_MASK 0x3F3F0101U +#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x3F3F0101U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET 0U +#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148 +#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN + +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET 0U +#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148 +#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN + +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH 6U +#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148 +#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH + +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH 6U +#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148 +#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH + +#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FF03FFU +#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FF03FFU +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT 0U +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH 8U +#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149 +#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER + +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT 8U +#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH 2U +#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149 +#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK + +#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT 16U +#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH 8U +#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149 +#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18 + +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET 0U +#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149 +#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE + +#define LPDDR4__DENALI_CTL_150_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH 10U +#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150 +#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH 16U +#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150 +#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_CTL_151_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH 10U +#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151 +#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH 16U +#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151 +#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_CTL_152_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH 10U +#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152 +#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH 16U +#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152 +#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000103U +#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000103U +#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT 0U +#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH 2U +#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153 +#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY + +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET 0U +#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153 +#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN + +#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U +#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154 +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR + +#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0 + +#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1 + +#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2 + +#define LPDDR4__DENALI_CTL_158_READ_MASK 0x00FFFF0FU +#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x00FFFF0FU +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH 4U +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158 +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK + +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158 +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT + +#define LPDDR4__DENALI_CTL_159_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH 27U +#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159 +#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG + +#define LPDDR4__DENALI_CTL_160_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH 8U +#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160 +#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS + +#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT 8U +#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH 17U +#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160 +#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG + +#define LPDDR4__DENALI_CTL_161_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH 32U +#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161 +#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0 + +#define LPDDR4__DENALI_CTL_162_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH 8U +#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162 +#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1 + +#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH 16U +#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162 +#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0 + +#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH 16U +#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163 +#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1 + +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT 16U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH 1U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR 0U +#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET 0U +#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163 +#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG + +#define LPDDR4__DENALI_CTL_164_READ_MASK 0x03FF0003U +#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x03FF0003U +#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT 0U +#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH 2U +#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164 +#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC + +#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164 +#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0 + +#define LPDDR4__DENALI_CTL_165_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165 +#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0 + +#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH 10U +#define LPDDR4__TFC_F0__REG DENALI_CTL_165 +#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0 + +#define LPDDR4__DENALI_CTL_166_READ_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH 5U +#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166 +#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0 + +#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH 5U +#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166 +#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0 + +#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH 16U +#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166 +#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0 + +#define LPDDR4__DENALI_CTL_167_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167 +#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1 + +#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167 +#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1 + +#define LPDDR4__DENALI_CTL_168_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH 10U +#define LPDDR4__TFC_F1__REG DENALI_CTL_168 +#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1 + +#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH 5U +#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168 +#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1 + +#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH 5U +#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168 +#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1 + +#define LPDDR4__DENALI_CTL_169_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH 16U +#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169 +#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1 + +#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169 +#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2 + +#define LPDDR4__DENALI_CTL_170_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170 +#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2 + +#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH 10U +#define LPDDR4__TFC_F2__REG DENALI_CTL_170 +#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2 + +#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF1F1FU +#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH 5U +#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171 +#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2 + +#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH 5U +#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171 +#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2 + +#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH 16U +#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171 +#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2 + +#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_175_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175 +#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175 +#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175 +#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175 +#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176 +#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176 +#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH 8U +#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176 +#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176 +#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_177_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177 +#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177 +#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177 +#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177 +#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178 +#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH 8U +#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178 +#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0 + +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178 +#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178 +#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179 +#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179 +#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179 +#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179 +#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH 8U +#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180 +#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0 + +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180 +#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180 +#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180 +#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH 8U +#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181 +#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0 + +#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH 8U +#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181 +#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0 + +#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH 8U +#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181 +#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0 + +#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181 +#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182 +#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182 +#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182 +#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182 +#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183 +#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183 +#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183 +#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183 +#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_184_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH 8U +#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184 +#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184 +#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184 +#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184 +#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_185_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185 +#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185 +#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185 +#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH 8U +#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185 +#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1 + +#define LPDDR4__DENALI_CTL_186_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186 +#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186 +#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186 +#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186 +#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_187_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187 +#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187 +#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH 8U +#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187 +#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1 + +#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187 +#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_188_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188 +#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188 +#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH 8U +#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188 +#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1 + +#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH 8U +#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188 +#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1 + +#define LPDDR4__DENALI_CTL_189_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH 8U +#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189 +#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1 + +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189 +#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189 +#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189 +#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_190_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT 0U +#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH 8U +#define LPDDR4__MR23_DATA__REG DENALI_CTL_190 +#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA + +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190 +#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0 + +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190 +#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1 + +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190 +#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2 + +#define LPDDR4__DENALI_CTL_191_READ_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH 2U +#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191 +#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN + +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT 8U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH 1U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR 0U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET 0U +#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191 +#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19 + +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT 16U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH 1U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR 0U +#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET 0U +#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191 +#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20 + +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT 24U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH 1U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR 0U +#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET 0U +#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191 +#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW + +#define LPDDR4__DENALI_CTL_192_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT 0U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET 0U +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192 +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP + +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET 0U +#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192 +#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS + +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT 16U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET 0U +#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192 +#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT + +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT 24U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET 0U +#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192 +#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT + +#define LPDDR4__DENALI_CTL_193_READ_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT 0U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET 0U +#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193 +#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID + +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT 8U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET 0U +#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193 +#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID + +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT 16U +#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH 2U +#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193 +#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC + +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT 24U +#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH 2U +#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193 +#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC + +#define LPDDR4__DENALI_CTL_194_READ_MASK 0x013F0300U +#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x013F0300U +#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT 0U +#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET 0U +#define LPDDR4__BIST_GO__REG DENALI_CTL_194 +#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO + +#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT 8U +#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH 2U +#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194 +#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT + +#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT 16U +#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH 6U +#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194 +#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE + +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT 24U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194 +#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK + +#define LPDDR4__DENALI_CTL_195_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT 0U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195 +#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK + +#define LPDDR4__DENALI_CTL_196_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196 +#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_CTL_197_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH 3U +#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197 +#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_CTL_198_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH 32U +#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198 +#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0 + +#define LPDDR4__DENALI_CTL_199_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH 32U +#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199 +#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1 + +#define LPDDR4__DENALI_CTL_200_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH 3U +#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200 +#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE + +#define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201 +#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0 + +#define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202 +#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1 + +#define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203 +#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2 + +#define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204 +#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3 + +#define LPDDR4__DENALI_CTL_205_READ_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET 0U +#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205 +#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT + +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET 0U +#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205 +#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE + +#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT 16U +#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205 +#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP + +#define LPDDR4__DENALI_CTL_206_READ_MASK 0x07030FFFU +#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x07030FFFU +#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206 +#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT + +#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH 2U +#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206 +#define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE + +#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT 24U +#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH 3U +#define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206 +#define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET + +#define LPDDR4__DENALI_CTL_207_READ_MASK 0x010F0101U +#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x010F0101U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET 0U +#define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207 +#define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN + +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET 0U +#define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207 +#define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN + +#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT 16U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH 4U +#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207 +#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21 + +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT 24U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH 1U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR 0U +#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET 0U +#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207 +#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22 + +#define LPDDR4__DENALI_CTL_208_READ_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_208__FWC_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_208__FWC_SHIFT 0U +#define LPDDR4__DENALI_CTL_208__FWC_WIDTH 1U +#define LPDDR4__DENALI_CTL_208__FWC_WOCLR 0U +#define LPDDR4__DENALI_CTL_208__FWC_WOSET 0U +#define LPDDR4__FWC__REG DENALI_CTL_208 +#define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC + +#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT 8U +#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH 16U +#define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208 +#define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS + +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET 0U +#define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208 +#define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN + +#define LPDDR4__DENALI_CTL_209_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT 0U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH 1U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR 0U +#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET 0U +#define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209 +#define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR + +#define LPDDR4__DENALI_CTL_210_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210 +#define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0 + +#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211 +#define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1 + +#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT 8U +#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH 8U +#define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211 +#define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND + +#define LPDDR4__DENALI_CTL_212_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH 32U +#define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212 +#define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0 + +#define LPDDR4__DENALI_CTL_213_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH 32U +#define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213 +#define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1 + +#define LPDDR4__DENALI_CTL_214_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214 +#define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0 + +#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0000FF07U +#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215 +#define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1 + +#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT 8U +#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH 8U +#define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215 +#define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND + +#define LPDDR4__DENALI_CTL_216_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH 32U +#define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216 +#define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0 + +#define LPDDR4__DENALI_CTL_217_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH 32U +#define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217 +#define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1 + +#define LPDDR4__DENALI_CTL_218_READ_MASK 0x7FFF3F3FU +#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x7FFF3F3FU +#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT 0U +#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH 6U +#define LPDDR4__ECC_U_ID__REG DENALI_CTL_218 +#define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID + +#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH 6U +#define LPDDR4__ECC_C_ID__REG DENALI_CTL_218 +#define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID + +#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK 0x7FFF0000U +#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218 +#define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0 + +#define LPDDR4__DENALI_CTL_219_READ_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219 +#define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0 + +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK 0x7FFF0000U +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219 +#define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1 + +#define LPDDR4__DENALI_CTL_220_READ_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x7FFF7FFFU +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220 +#define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1 + +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK 0x7FFF0000U +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT 16U +#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220 +#define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2 + +#define LPDDR4__DENALI_CTL_221_READ_MASK 0x00077FFFU +#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x00077FFFU +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH 15U +#define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221 +#define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2 + +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH 3U +#define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221 +#define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE + +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT 24U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH 1U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR 0U +#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET 0U +#define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221 +#define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START + +#define LPDDR4__DENALI_CTL_222_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH 1U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR 0U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET 0U +#define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222 +#define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS + +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT 8U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH 12U +#define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222 +#define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN + +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT 24U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET 0U +#define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222 +#define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE + +#define LPDDR4__DENALI_CTL_223_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH 16U +#define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223 +#define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL + +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT 16U +#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH 16U +#define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223 +#define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT + +#define LPDDR4__DENALI_CTL_224_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224 +#define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0 + +#define LPDDR4__DENALI_CTL_225_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225 +#define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1 + +#define LPDDR4__DENALI_CTL_226_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH 32U +#define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226 +#define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0 + +#define LPDDR4__DENALI_CTL_227_READ_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x1F1F1F07U +#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH 3U +#define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227 +#define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1 + +#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT 8U +#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227 +#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK + +#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227 +#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT 24U +#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227 +#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_228_READ_MASK 0x000F1F1FU +#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x000F1F1FU +#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH 5U +#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228 +#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT + +#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH 5U +#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228 +#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT + +#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT 16U +#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH 4U +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228 +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI + +#define LPDDR4__DENALI_CTL_229_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_230_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_231_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_232_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232 +#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_233_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_234_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_235_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_236_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_237_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237 +#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_238_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_239_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_240_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_241_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241 +#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT 16U +#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH 3U +#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242 +#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23 + +#define LPDDR4__DENALI_CTL_243_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243 +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0 + +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243 +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0 + +#define LPDDR4__DENALI_CTL_244_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0 + +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244 +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0 + +#define LPDDR4__DENALI_CTL_245_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245 +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0 + +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0 + +#define LPDDR4__DENALI_CTL_246_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246 +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0 + +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246 +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0 + +#define LPDDR4__DENALI_CTL_247_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247 +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1 + +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247 +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1 + +#define LPDDR4__DENALI_CTL_248_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1 + +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248 +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1 + +#define LPDDR4__DENALI_CTL_249_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249 +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1 + +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1 + +#define LPDDR4__DENALI_CTL_250_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250 +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1 + +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250 +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1 + +#define LPDDR4__DENALI_CTL_251_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251 +#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2 + +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251 +#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2 + +#define LPDDR4__DENALI_CTL_252_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2 + +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252 +#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2 + +#define LPDDR4__DENALI_CTL_253_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253 +#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2 + +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253 +#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2 + +#define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254 +#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2 + +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH 16U +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254 +#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2 + +#define LPDDR4__DENALI_CTL_255_READ_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT 0U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH 8U +#define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255 +#define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD + +#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT 8U +#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH 8U +#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255 +#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE + +#define LPDDR4__DENALI_CTL_256_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT 0U +#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH 20U +#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256 +#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG + +#define LPDDR4__DENALI_CTL_257_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH 12U +#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257 +#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0 + +#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH 12U +#define LPDDR4__ZQCL_F0__REG DENALI_CTL_257 +#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0 + +#define LPDDR4__DENALI_CTL_258_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH 12U +#define LPDDR4__ZQCS_F0__REG DENALI_CTL_258 +#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0 + +#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH 12U +#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258 +#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0 + +#define LPDDR4__DENALI_CTL_259_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH 7U +#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259 +#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0 + +#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH 12U +#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259 +#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1 + +#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH 12U +#define LPDDR4__ZQCL_F1__REG DENALI_CTL_260 +#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1 + +#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH 12U +#define LPDDR4__ZQCS_F1__REG DENALI_CTL_260 +#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1 + +#define LPDDR4__DENALI_CTL_261_READ_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH 12U +#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261 +#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1 + +#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH 7U +#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261 +#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1 + +#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH 12U +#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262 +#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2 + +#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH 12U +#define LPDDR4__ZQCL_F2__REG DENALI_CTL_262 +#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2 + +#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH 12U +#define LPDDR4__ZQCS_F2__REG DENALI_CTL_263 +#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2 + +#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH 12U +#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263 +#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2 + +#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0100037FU +#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0100037FU +#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH 7U +#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264 +#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2 + +#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 8U +#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264 +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP + +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH 4U +#define LPDDR4__ZQ_REQ__REG DENALI_CTL_264 +#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ + +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT 24U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264 +#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING + +#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH 12U +#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265 +#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0 + +#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH 12U +#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265 +#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1 + +#define LPDDR4__DENALI_CTL_266_READ_MASK 0x01010FFFU +#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x01010FFFU +#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH 12U +#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266 +#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2 + +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET 0U +#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266 +#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT + +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET 0U +#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266 +#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE + +#define LPDDR4__DENALI_CTL_267_READ_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267 +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_CTL_268_READ_MASK 0x07070303U +#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x07070303U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH 2U +#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268 +#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0 + +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH 2U +#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268 +#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1 + +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH 3U +#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268 +#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0 + +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH 3U +#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268 +#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1 + +#define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFF0F0FU +#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFF0F0FU +#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH 4U +#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269 +#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0 + +#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH 4U +#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269 +#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1 + +#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269 +#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0 + +#define LPDDR4__DENALI_CTL_270_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270 +#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0 + +#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH 3U +#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270 +#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0 + +#define LPDDR4__DENALI_CTL_271_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271 +#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1 + +#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271 +#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1 + +#define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFF0307U +#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFF0307U +#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH 3U +#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272 +#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1 + +#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT 8U +#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH 2U +#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272 +#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2 + +#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH 16U +#define LPDDR4__CS_MSK_0__REG DENALI_CTL_272 +#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0 + +#define LPDDR4__DENALI_CTL_273_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH 16U +#define LPDDR4__CS_MSK_1__REG DENALI_CTL_273 +#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1 + +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET 0U +#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273 +#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN + +#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT 24U +#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH 5U +#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273 +#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24 + +#define LPDDR4__DENALI_CTL_274_READ_MASK 0xFFFF1F01U +#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0xFFFF1F01U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT 0U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH 1U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR 0U +#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET 0U +#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274 +#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25 + +#define LPDDR4__DENALI_CTL_274__APREBIT_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH 5U +#define LPDDR4__APREBIT__REG DENALI_CTL_274 +#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT + +#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT 16U +#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH 8U +#define LPDDR4__AGE_COUNT__REG DENALI_CTL_274 +#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT + +#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT 24U +#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH 8U +#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274 +#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT + +#define LPDDR4__DENALI_CTL_275_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET 0U +#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275 +#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN + +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT 8U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET 0U +#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275 +#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS + +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET 0U +#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275 +#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN + +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET 0U +#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275 +#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN + +#define LPDDR4__DENALI_CTL_276_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET 0U +#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276 +#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN + +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET 0U +#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276 +#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN + +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET 0U +#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276 +#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN + +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET 0U +#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276 +#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN + +#define LPDDR4__DENALI_CTL_277_READ_MASK 0x011F0301U +#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x011F0301U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET 0U +#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277 +#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN + +#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 8U +#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277 +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT + +#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277 +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE + +#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET 0U +#define LPDDR4__SWAP_EN__REG DENALI_CTL_277 +#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN + +#define LPDDR4__DENALI_CTL_278_READ_MASK 0x01030301U +#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01030301U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT 0U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET 0U +#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278 +#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE + +#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT 8U +#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH 2U +#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278 +#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD + +#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH 2U +#define LPDDR4__CS_MAP__REG DENALI_CTL_278 +#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP + +#define LPDDR4__DENALI_CTL_278__REDUC_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT 24U +#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH 1U +#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR 0U +#define LPDDR4__DENALI_CTL_278__REDUC_WOSET 0U +#define LPDDR4__REDUC__REG DENALI_CTL_278 +#define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC + +#define LPDDR4__DENALI_CTL_279_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH 18U +#define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279 +#define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_280_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH 18U +#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280 +#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS + +#define LPDDR4__DENALI_CTL_281_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH 18U +#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281 +#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281 +#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282_READ_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH 2U +#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET 0U +#define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282 +#define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN + +#define LPDDR4__DENALI_CTL_283_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT 0U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET 0U +#define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283 +#define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26 + +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT 8U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET 0U +#define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283 +#define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27 + +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET 0U +#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283 +#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN + +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET 0U +#define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283 +#define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN + +#define LPDDR4__DENALI_CTL_284_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN + +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN + +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET 0U +#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN + +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U +#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 +#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN + +#define LPDDR4__DENALI_CTL_285_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET 0U +#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285 +#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN + +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET 0U +#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285 +#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT + +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET 0U +#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285 +#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN + +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285 +#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_286_READ_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286 +#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0 + +#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT 8U +#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286 +#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286 +#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT 24U +#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286 +#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_287_READ_MASK 0x0F0F070FU +#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0x0F0F070FU +#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287 +#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287 +#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1 + +#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287 +#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT 24U +#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287 +#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_288_READ_MASK 0x011F0F0FU +#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x011F0F0FU +#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288 +#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288 +#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT 16U +#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH 5U +#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288 +#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS + +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT 24U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH 1U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR 0U +#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET 0U +#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288 +#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT + +#define LPDDR4__DENALI_CTL_289_READ_MASK 0x01000103U +#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x01000103U +#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH 2U +#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289 +#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ + +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT 8U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH 1U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR 0U +#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET 0U +#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289 +#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY + +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET 0U +#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289 +#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ + +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289 +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_CTL_290_READ_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET 0U +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290 +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE + +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290 +#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0 + +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290 +#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1 + +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290 +#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2 + +#define LPDDR4__DENALI_CTL_291_READ_MASK 0x1F010101U +#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0x1F010101U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291 +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET 0U +#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291 +#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN + +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET 0U +#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291 +#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN + +#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT 24U +#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH 5U +#define LPDDR4__DFI_ERROR__REG DENALI_CTL_291 +#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR + +#define LPDDR4__DENALI_CTL_292_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH 20U +#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292 +#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO + +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT 24U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH 1U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR 0U +#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET 0U +#define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292 +#define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28 + +#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH 32U +#define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293 +#define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0 + +#define LPDDR4__DENALI_CTL_294_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH 13U +#define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294 +#define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1 + +#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH 32U +#define LPDDR4__INT_ACK_0__REG DENALI_CTL_295 +#define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0 + +#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH 12U +#define LPDDR4__INT_ACK_1__REG DENALI_CTL_296 +#define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1 + +#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH 32U +#define LPDDR4__INT_MASK_0__REG DENALI_CTL_297 +#define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0 + +#define LPDDR4__DENALI_CTL_298_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK 0x00001FFFU +#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH 13U +#define LPDDR4__INT_MASK_1__REG DENALI_CTL_298 +#define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1 + +#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH 32U +#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299 +#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0 + +#define LPDDR4__DENALI_CTL_300_READ_MASK 0x7F0FFF07U +#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0x7F0FFF07U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH 3U +#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300 +#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1 + +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH 12U +#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300 +#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH + +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT 24U +#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH 7U +#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300 +#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE + +#define LPDDR4__DENALI_CTL_301_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U +#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301 +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID + +#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302 +#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303 +#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304 +#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2 + +#define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305 +#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3 + +#define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306 +#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307 +#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308 +#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2 + +#define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309 +#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3 + +#define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310 +#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_CTL_311_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH 3U +#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311 +#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_CTL_312_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH 32U +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312 +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0 + +#define LPDDR4__DENALI_CTL_313_READ_MASK 0x03033F07U +#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x03033F07U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH 3U +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313 +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1 + +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH 6U +#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313 +#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID + +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT 16U +#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH 2U +#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313 +#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE + +#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT 24U +#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313 +#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0 + +#define LPDDR4__DENALI_CTL_314_READ_MASK 0xFF030303U +#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0xFF030303U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314 +#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0 + +#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314 +#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1 + +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314 +#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1 + +#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314 +#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0 + +#define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH 4U +#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315 +#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0 + +#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH 4U +#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315 +#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0 + +#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315 +#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1 + +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH 4U +#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315 +#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1 + +#define LPDDR4__DENALI_CTL_316_READ_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH 4U +#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316 +#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1 + +#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316 +#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2 + +#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH 4U +#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316 +#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2 + +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH 4U +#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316 +#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2 + +#define LPDDR4__DENALI_CTL_317_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET 0U +#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317 +#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0 + +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET 0U +#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317 +#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1 + +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET 0U +#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317 +#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2 + +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U +#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317 +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD + +#define LPDDR4__DENALI_CTL_318_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318 +#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318 +#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318 +#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318 +#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_319_READ_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319 +#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319 +#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319 +#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0 + +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319 +#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1 + +#define LPDDR4__DENALI_CTL_320_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320 +#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2 + +#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320 +#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320 +#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320 +#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_321_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321 +#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321 +#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321 +#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321 +#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322 +#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322 +#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322 +#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322 +#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_323_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323 +#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT 8U +#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323 +#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323 +#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0 + +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323 +#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1 + +#define LPDDR4__DENALI_CTL_324_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324 +#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2 + +#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT 8U +#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324 +#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT 16U +#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324 +#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324 +#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_CTL_325_READ_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0 + +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1 + +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325 +#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_CTL_326_READ_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326 +#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2 + +#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT 8U +#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH 3U +#define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326 +#define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE + +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT 16U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH 1U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR 0U +#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET 0U +#define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326 +#define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD + +#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT 24U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH 1U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR 0U +#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET 0U +#define LPDDR4__SWLVL_START__REG DENALI_CTL_326 +#define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START + +#define LPDDR4__DENALI_CTL_327_READ_MASK 0x01010100U +#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x01010100U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET 0U +#define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT + +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT 8U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET 0U +#define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE + +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET 0U +#define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0 + +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH 1U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR 0U +#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET 0U +#define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327 +#define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1 + +#define LPDDR4__DENALI_CTL_328_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET 0U +#define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328 +#define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2 + +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT 8U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET 0U +#define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328 +#define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3 + +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET 0U +#define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328 +#define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN + +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT 24U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET 0U +#define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328 +#define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ + +#define LPDDR4__DENALI_CTL_329_READ_MASK 0x013F3F01U +#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x013F3F01U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT 0U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET 0U +#define LPDDR4__WRLVL_CS__REG DENALI_CTL_329 +#define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS + +#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT 8U +#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH 6U +#define LPDDR4__WLDQSEN__REG DENALI_CTL_329 +#define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN + +#define LPDDR4__DENALI_CTL_329__WLMRD_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT 16U +#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH 6U +#define LPDDR4__WLMRD__REG DENALI_CTL_329 +#define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD + +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET 0U +#define LPDDR4__WRLVL_EN__REG DENALI_CTL_329 +#define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN + +#define LPDDR4__DENALI_CTL_330_READ_MASK 0x0F010101U +#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x0F010101U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330 +#define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE + +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT 8U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET 0U +#define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330 +#define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC + +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330 +#define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT 24U +#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330 +#define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK + +#define LPDDR4__DENALI_CTL_331_READ_MASK 0x07030101U +#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x07030101U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET 0U +#define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN + +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET 0U +#define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE + +#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH 2U +#define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP + +#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH 3U +#define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331 +#define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_332_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332 +#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332 +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_333_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333 +#define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333 +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334 +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334 +#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335 +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335 +#define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336 +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336 +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337 +#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337 +#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338 +#define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338 +#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_339_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339 +#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET 0U +#define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339 +#define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ + +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT 24U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET 0U +#define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339 +#define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ + +#define LPDDR4__DENALI_CTL_340_READ_MASK 0x010F0F01U +#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010F0F01U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT 0U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET 0U +#define LPDDR4__RDLVL_CS__REG DENALI_CTL_340 +#define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS + +#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH 4U +#define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340 +#define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN + +#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH 4U +#define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340 +#define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN + +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT 24U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340 +#define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE + +#define LPDDR4__DENALI_CTL_341_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_341_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341 +#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE + +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT 8U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET 0U +#define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341 +#define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC + +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341 +#define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET 0U +#define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341 +#define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC + +#define LPDDR4__DENALI_CTL_342_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342 +#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET 0U +#define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342 +#define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN + +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET 0U +#define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342 +#define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN + +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT 24U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH 1U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR 0U +#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET 0U +#define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342 +#define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29 + +#define LPDDR4__DENALI_CTL_343_READ_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET 0U +#define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE + +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET 0U +#define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE + +#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH 2U +#define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP + +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH 2U +#define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343 +#define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP + +#define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344 +#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344 +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345 +#define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345 +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346 +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346 +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347 +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347 +#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348 +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348 +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349 +#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349 +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350 +#define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350 +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_351_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_351_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351 +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351 +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352 +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352 +#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353 +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353 +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354 +#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354 +#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355 +#define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355 +#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356 +#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356 +#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357 +#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357 +#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358 +#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358 +#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_359_READ_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET 0U +#define LPDDR4__CALVL_REQ__REG DENALI_CTL_359 +#define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ + +#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT 8U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH 1U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR 0U +#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET 0U +#define LPDDR4__CALVL_CS__REG DENALI_CTL_359 +#define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS + +#define LPDDR4__DENALI_CTL_360_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH 20U +#define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360 +#define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0 + +#define LPDDR4__DENALI_CTL_361_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361 +#define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0 + +#define LPDDR4__DENALI_CTL_362_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH 20U +#define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362 +#define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1 + +#define LPDDR4__DENALI_CTL_363_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363 +#define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1 + +#define LPDDR4__DENALI_CTL_364_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH 20U +#define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364 +#define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2 + +#define LPDDR4__DENALI_CTL_365_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365 +#define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2 + +#define LPDDR4__DENALI_CTL_366_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH 20U +#define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366 +#define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3 + +#define LPDDR4__DENALI_CTL_367_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH 20U +#define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367 +#define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3 + +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT 24U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH 1U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR 0U +#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET 0U +#define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367 +#define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30 + +#define LPDDR4__DENALI_CTL_368_READ_MASK 0x0101030FU +#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x0101030FU +#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT 0U +#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH 4U +#define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368 +#define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31 + +#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH 2U +#define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368 +#define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN + +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT 16U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET 0U +#define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368 +#define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE + +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET 0U +#define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368 +#define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC + +#define LPDDR4__DENALI_CTL_369_READ_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369 +#define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET 0U +#define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369 +#define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN + +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT 16U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET 0U +#define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369 +#define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE + +#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH 2U +#define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369 +#define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP + +#define LPDDR4__DENALI_CTL_370_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370 +#define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370 +#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371 +#define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371 +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372 +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372 +#define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373 +#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373 +#define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374 +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374 +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375 +#define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375 +#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376 +#define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376 +#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_377_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377 +#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377 +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE + +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377 +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE + +#define LPDDR4__DENALI_CTL_378_READ_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x00000707U +#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT 0U +#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378 +#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY + +#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378 +#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY + +#define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH 32U +#define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379 +#define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0 + +#define LPDDR4__DENALI_CTL_380_READ_MASK 0x1FFF3F07U +#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1FFF3F07U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH 3U +#define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380 +#define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1 + +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH 6U +#define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380 +#define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID + +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK 0x1FFF0000U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT 16U +#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH 13U +#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380 +#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL + +#define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0 + +#define LPDDR4__DENALI_CTL_382_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1 + +#define LPDDR4__DENALI_CTL_383_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2 + +#define LPDDR4__DENALI_CTL_384_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH 32U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3 + +#define LPDDR4__DENALI_CTL_385_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT 0U +#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH 16U +#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385 +#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR + +#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH 2U +#define LPDDR4__CKE_STATUS__REG DENALI_CTL_385 +#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS + +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT 24U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET 0U +#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385 +#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID + +#define LPDDR4__DENALI_CTL_386_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT 0U +#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386 +#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY + +#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT 16U +#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386 +#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT 24U +#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH 7U +#define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386 +#define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT + +#define LPDDR4__DENALI_CTL_387_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH 7U +#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387 +#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH 7U +#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387 +#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0 + +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH 7U +#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387 +#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1 + +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH 7U +#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387 +#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2 + +#define LPDDR4__DENALI_CTL_388_READ_MASK 0x00FF037FU +#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x00FF037FU +#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH 7U +#define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388 +#define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN + +#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH 2U +#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388 +#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT 16U +#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH 8U +#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388 +#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_CTL_389_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389 +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_CTL_390_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_393_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_394_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394 +#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0 + +#define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_CTL_396_READ_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396 +#define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396 +#define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397 +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402 +#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1 + +#define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_CTL_404_READ_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0x00007F7FU +#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404 +#define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404 +#define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_CTL_405_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405 +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_410_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410 +#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2 + +#define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_CTL_412_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412 +#define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412 +#define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412 +#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412 +#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_CTL_413_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413 +#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413 +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413 +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE + +#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH 8U +#define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413 +#define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN + +#define LPDDR4__DENALI_CTL_414_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT 0U +#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH 10U +#define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414 +#define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW + +#define LPDDR4__DENALI_CTL_415_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH 32U +#define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415 +#define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP + +#define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH 32U +#define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416 +#define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX + +#define LPDDR4__DENALI_CTL_417_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH 8U +#define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417 +#define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN + +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK 0x0003FF00U +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT 8U +#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH 10U +#define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417 +#define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR + +#define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH 32U +#define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418 +#define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP + +#define LPDDR4__DENALI_CTL_419_READ_MASK 0x000101FFU +#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x000101FFU +#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH 8U +#define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419 +#define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK + +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET 0U +#define LPDDR4__RDLVL_EN__REG DENALI_CTL_419 +#define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN + +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET 0U +#define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419 +#define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN + +#define LPDDR4__DENALI_CTL_420_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH 32U +#define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420 +#define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX + +#define LPDDR4__DENALI_CTL_421_READ_MASK 0x00FF0707U +#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0x00FF0707U +#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH 3U +#define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421 +#define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH 3U +#define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421 +#define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH 8U +#define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421 +#define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN + +#define LPDDR4__DENALI_CTL_422_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0 + +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0 + +#define LPDDR4__DENALI_CTL_423_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423 +#define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1 + +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423 +#define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1 + +#define LPDDR4__DENALI_CTL_424_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424 +#define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2 + +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH 10U +#define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424 +#define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2 + +#define LPDDR4__DENALI_CTL_425_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_425_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH 32U +#define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425 +#define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP + +#define LPDDR4__DENALI_CTL_426_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_426_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH 32U +#define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426 +#define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX + +#define LPDDR4__DENALI_CTL_427_READ_MASK 0x070F0101U +#define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x070F0101U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH 1U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR 0U +#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET 0U +#define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427 +#define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK + +#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET 0U +#define LPDDR4__CALVL_EN__REG DENALI_CTL_427 +#define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN + +#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH 4U +#define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427 +#define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427 +#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_CTL_428_READ_MASK 0x7F7F0707U +#define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x7F7F0707U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428 +#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428 +#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH 7U +#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428 +#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0 + +#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH 7U +#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428 +#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0 + +#define LPDDR4__DENALI_CTL_429_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH 7U +#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429 +#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1 + +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH 7U +#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429 +#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1 + +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH 7U +#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429 +#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2 + +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH 7U +#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429 +#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2 + +#define LPDDR4__DENALI_CTL_430_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT 0U +#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH 8U +#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430 +#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY + +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT 8U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH 1U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR 0U +#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET 0U +#define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430 +#define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING + +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U +#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430 +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE + +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET 0U +#define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430 +#define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE + +#define LPDDR4__DENALI_CTL_431_READ_MASK 0x07070701U +#define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x07070701U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT 0U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH 1U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR 0U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET 0U +#define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32 + +#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT 8U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH 3U +#define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33 + +#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT 16U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH 3U +#define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34 + +#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT 24U +#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH 3U +#define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431 +#define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35 + +#define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F070707U +#define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F070707U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT 0U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH 3U +#define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36 + +#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT 8U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH 3U +#define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37 + +#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT 16U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH 3U +#define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38 + +#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT 24U +#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH 4U +#define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432 +#define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39 + +#define LPDDR4__DENALI_CTL_433_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_433_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT 0U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH 4U +#define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40 + +#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT 8U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH 4U +#define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41 + +#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT 16U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH 4U +#define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42 + +#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT 24U +#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH 4U +#define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433 +#define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43 + +#define LPDDR4__DENALI_CTL_434_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT 0U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH 4U +#define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44 + +#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT 8U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH 4U +#define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45 + +#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT 16U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH 4U +#define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46 + +#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT 24U +#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH 4U +#define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434 +#define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47 + +#define LPDDR4__DENALI_CTL_435_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_435_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT 0U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH 4U +#define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48 + +#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT 8U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH 4U +#define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49 + +#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT 16U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH 4U +#define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50 + +#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT 24U +#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH 4U +#define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435 +#define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51 + +#define LPDDR4__DENALI_CTL_436_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_436_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT 0U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH 4U +#define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52 + +#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT 8U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH 4U +#define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53 + +#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT 16U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH 4U +#define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54 + +#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT 24U +#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH 4U +#define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436 +#define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55 + +#define LPDDR4__DENALI_CTL_437_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_437_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT 0U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH 4U +#define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437 +#define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56 + +#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT 8U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH 4U +#define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437 +#define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57 + +#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT 16U +#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH 4U +#define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437 +#define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58 + +#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT 24U +#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH 8U +#define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437 +#define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO + +#define LPDDR4__DENALI_CTL_438_READ_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_438_WRITE_MASK 0xFFFF03FFU +#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH 8U +#define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438 +#define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK + +#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH 2U +#define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438 +#define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH 8U +#define LPDDR4__NWR_F0__REG DENALI_CTL_438 +#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0 + +#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH 8U +#define LPDDR4__NWR_F1__REG DENALI_CTL_438 +#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1 + +#define LPDDR4__DENALI_CTL_439_READ_MASK 0x001F01FFU +#define LPDDR4__DENALI_CTL_439_WRITE_MASK 0x001F01FFU +#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH 8U +#define LPDDR4__NWR_F2__REG DENALI_CTL_439 +#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2 + +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT 8U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH 1U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR 0U +#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET 0U +#define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439 +#define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59 + +#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH 5U +#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439 +#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS + +#define LPDDR4__DENALI_CTL_440_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_440_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH 32U +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440 +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0 + +#define LPDDR4__DENALI_CTL_441_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_441_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH 32U +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441 +#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1 + +#define LPDDR4__DENALI_CTL_442_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_442_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT 0U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET 0U +#define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442 +#define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE + +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442 +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442 +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442 +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_443_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_443_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET 0U +#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443 +#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_444_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_444_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 +#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 +#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U +#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 +#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN + +#define LPDDR4__DENALI_CTL_445_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_445_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH 32U +#define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445 +#define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0 + +#define LPDDR4__DENALI_CTL_446_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_446_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH 32U +#define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446 +#define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1 + +#define LPDDR4__DENALI_CTL_447_READ_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_447_WRITE_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH 3U +#define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447 +#define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2 + +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET 0U +#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447 +#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN + +#define LPDDR4__DENALI_CTL_448_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_448_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448 +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0 + +#define LPDDR4__DENALI_CTL_449_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_449_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449 +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1 + +#define LPDDR4__DENALI_CTL_450_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_450_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH 3U +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450 +#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2 + +#define LPDDR4__DENALI_CTL_451_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_451_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH 32U +#define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451 +#define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0 + +#define LPDDR4__DENALI_CTL_452_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_452_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH 32U +#define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452 +#define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1 + +#define LPDDR4__DENALI_CTL_453_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_453_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH 32U +#define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453 +#define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2 + +#define LPDDR4__DENALI_CTL_454_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_454_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH 4U +#define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454 +#define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3 + +#define LPDDR4__DENALI_CTL_455_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_455_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0 + +#define LPDDR4__DENALI_CTL_456_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_456_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1 + +#define LPDDR4__DENALI_CTL_457_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_457_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH 32U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2 + +#define LPDDR4__DENALI_CTL_458_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_458_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH 4U +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458 +#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3 + +#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h new file mode 100644 index 000000000..d8c7a5222 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h @@ -0,0 +1,2060 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_ +#define REG_LPDDR4_PHY_CORE_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280 +#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1281_READ_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_SHIFT 8U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN + +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT 16U +#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281 +#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX + +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281 +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282 +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283_READ_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1284 +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY + +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1284 +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT + +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1284 +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE + +#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1285 +#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET 0U +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1285 +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE + +#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_WIDTH 11U +#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1285 +#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START + +#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1286 +#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY + +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOSET 0U +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1286 +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE + +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1286 +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT + +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1287 +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR + +#define LPDDR4__DENALI_PHY_1288_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1288 +#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0 + +#define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1289 +#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1 + +#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1290 +#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2 + +#define LPDDR4__DENALI_PHY_1291_READ_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOSET 0U +#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1291 +#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE + +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT 8U +#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH 9U +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1291 +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET + +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1291 +#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE + +#define LPDDR4__DENALI_PHY_1292_READ_MASK 0x0007FF0FU +#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x0007FF0FU +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1292 +#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP + +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_SHIFT 8U +#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_WIDTH 11U +#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1292 +#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR + +#define LPDDR4__DENALI_PHY_1293_READ_MASK 0xFF0F07FFU +#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0xFF0F07FFU +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK + +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_WIDTH 8U +#define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1293 +#define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP + +#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x01030007U +#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x01030007U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE + +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WOSET 0U +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS + +#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_WIDTH 2U +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1294 +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE + +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_SHIFT 24U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOSET 0U +#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR + +#define LPDDR4__DENALI_PHY_1295_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOSET 0U +#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1295 +#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE + +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOSET 0U +#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1295 +#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS + +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__REG DENALI_PHY_1295 +#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT + +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1295 +#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT + +#define LPDDR4__DENALI_PHY_1296_READ_MASK 0xFF3F0103U +#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0xFF3F0103U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_WIDTH 2U +#define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT + +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT 8U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET 0U +#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ + +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_WIDTH 6U +#define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START + +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1296 +#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT + +#define LPDDR4__DENALI_PHY_1297_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD + +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_SHIFT 8U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WOSET 0U +#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT + +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_SHIFT 16U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOSET 0U +#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY + +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_SHIFT 24U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WIDTH 1U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOCLR 0U +#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOSET 0U +#define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1297 +#define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START + +#define LPDDR4__DENALI_PHY_1298_READ_MASK 0x0F0F0100U +#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0x0F0F0100U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 0U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR 0U +#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET 0U +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1298 +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES + +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1298 +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE + +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1298 +#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298 +#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1 + +#define LPDDR4__DENALI_PHY_1299_READ_MASK 0x010F0F01U +#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0x010F0F01U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1299 +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL + +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT 24U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1299 +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL + +#define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1300 +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1300 +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_WIDTH 16U +#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1300 +#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL + +#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x0001010FU +#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x0001010FU +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1301 +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1301 +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1301 +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1302_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_WIDTH 32U +#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1302 +#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS + +#define LPDDR4__DENALI_PHY_1303_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_WIDTH 16U +#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1303 +#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT + +#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1304 +#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1305 +#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0 + +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1305 +#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1 + +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1305 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0 + +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1305 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0 + +#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0 + +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0 + +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1 + +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1306 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1 + +#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x01FF0F0FU +#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x01FF0F0FU +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1 + +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1 + +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOSET 0U +#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1307 +#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE + +#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_SHIFT 0U +#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1308 +#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD + +#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_MASK 0x001FFF00U +#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_SHIFT 8U +#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1308 +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1309 +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE + +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WOSET 0U +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1309 +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK + +#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_WIDTH 19U +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1310 +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL + +#define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1310 +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS + +#define LPDDR4__DENALI_PHY_1311_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_SHIFT 0U +#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_WIDTH 10U +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_CYCLES__REG DENALI_PHY_1311 +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_CYCLES__FLD LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES + +#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__REG DENALI_PHY_1311 +#define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__FLD LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS + +#define LPDDR4__DENALI_PHY_1312_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1312 +#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0 + +#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1313 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0 + +#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_WIDTH 18U +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__REG DENALI_PHY_1314 +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0 + +#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1315 +#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1 + +#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1316 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1 + +#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_WIDTH 18U +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_1__REG DENALI_PHY_1317 +#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1 + +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT 24U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1317 +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x0001FF0FU +#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x0001FF0FU +#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_WIDTH 4U +#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1318 +#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT + +#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_SHIFT 8U +#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_WIDTH 8U +#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1318 +#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP + +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOSET 0U +#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1318 +#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN + +#define LPDDR4__DENALI_PHY_1319_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 0U +#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1319 +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG + +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_SHIFT 16U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WIDTH 1U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOCLR 0U +#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOSET 0U +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1319 +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY + +#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1320 +#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM + +#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1321 +#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM + +#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1322 +#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM + +#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1323 +#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM + +#define LPDDR4__DENALI_PHY_1324_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1324 +#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM + +#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1325 +#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM + +#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1326 +#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM + +#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1327 +#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM + +#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1328 +#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM + +#define LPDDR4__DENALI_PHY_1329_READ_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1329_WRITE_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_WIDTH 10U +#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1329 +#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL + +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1329 +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL + +#define LPDDR4__DENALI_PHY_1330_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1330_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_WIDTH 13U +#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1330 +#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0 + +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOSET 0U +#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1330 +#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1330 +#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0 + +#define LPDDR4__DENALI_PHY_1331_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1331_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1331 +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0 + +#define LPDDR4__DENALI_PHY_1332_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1332_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1332 +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1332 +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1333_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1333_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1333 +#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_1334_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1334_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1334 +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0 + +#define LPDDR4__DENALI_PHY_1335_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1335_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1335 +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0 + +#define LPDDR4__DENALI_PHY_1336_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1336 +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0 + +#define LPDDR4__DENALI_PHY_1337_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1337 +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0 + +#define LPDDR4__DENALI_PHY_1338_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1338_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1338 +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0 + +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_WIDTH 7U +#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1338 +#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0 + +#define LPDDR4__DENALI_PHY_1339_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1339_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOSET 0U +#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1339 +#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0 + +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1340 +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0 + +#define LPDDR4__DENALI_PHY_1341_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1341_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_WIDTH 32U +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1341 +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0 + +#define LPDDR4__DENALI_PHY_1342_READ_MASK 0x0FFFFF7FU +#define LPDDR4__DENALI_PHY_1342_WRITE_MASK 0x0FFFFF7FU +#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_WIDTH 7U +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0 + +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1342 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1343_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1343_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1343 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0 + +#define LPDDR4__DENALI_PHY_1344_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1344_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1344 +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0 + +#define LPDDR4__DENALI_PHY_1345_READ_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1345_WRITE_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1345 +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0 + +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1345 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346_READ_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1346_WRITE_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1346 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347_READ_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1347_WRITE_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1347 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1348_READ_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1348_WRITE_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1348 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1349_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1349_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_WIDTH 16U +#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1349 +#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL + +#define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_SHIFT 16U +#define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__REG DENALI_PHY_1349 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__FLD LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC + +#define LPDDR4__DENALI_PHY_1350_READ_MASK 0x03010000U +#define LPDDR4__DENALI_PHY_1350_WRITE_MASK 0x03010000U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1350 +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_SHIFT 8U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1350 +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR + +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOSET 0U +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1350 +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_WIDTH 2U +#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1350 +#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1351_READ_MASK 0x0F7F01FFU +#define LPDDR4__DENALI_PHY_1351_WRITE_MASK 0x0F7F01FFU +#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_WIDTH 9U +#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1351 +#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_WIDTH 7U +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1351 +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START + +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_WIDTH 4U +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1351 +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK + +#define LPDDR4__DENALI_PHY_1352_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1352_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1352 +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1353_READ_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1353_WRITE_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1353 +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1354_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1354_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1354 +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1354 +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1354 +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1355_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1355_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1355 +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE + +#define LPDDR4__DENALI_PHY_1356_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1356_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1356 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL + +#define LPDDR4__DENALI_PHY_1357_READ_MASK 0x031F01FFU +#define LPDDR4__DENALI_PHY_1357_WRITE_MASK 0x031F01FFU +#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U +#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1357 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH + +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_SHIFT 8U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOSET 0U +#define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1357 +#define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT + +#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_SHIFT 16U +#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_WIDTH 5U +#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1357 +#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP + +#define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1357 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 + +#define LPDDR4__DENALI_PHY_1358_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1358_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1358 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 + +#define LPDDR4__DENALI_PHY_1359_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_WIDTH 32U +#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1359 +#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE + +#define LPDDR4__DENALI_PHY_1360_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1360_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_WIDTH 26U +#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1360 +#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE + +#define LPDDR4__DENALI_PHY_1361_READ_MASK 0x07FF073FU +#define LPDDR4__DENALI_PHY_1361_WRITE_MASK 0x07FF073FU +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_WIDTH 6U +#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1361 +#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK + +#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_SHIFT 8U +#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_WIDTH 3U +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1361 +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG + +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT 16U +#define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1361 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC + +#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_SHIFT 24U +#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_WIDTH 3U +#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1361 +#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN + +#define LPDDR4__DENALI_PHY_1362_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1362_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_WIDTH 3U +#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1362 +#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS + +#define LPDDR4__DENALI_PHY_1363_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1363_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1363 +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1364_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1364_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1364 +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1365_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1365_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1365 +#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1366_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1366 +#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1367_READ_MASK 0x0F03FF03U +#define LPDDR4__DENALI_PHY_1367_WRITE_MASK 0x0F03FF03U +#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_WIDTH 2U +#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1367 +#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN + +#define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_WIDTH 10U +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1367 +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_WIDTH 4U +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1367 +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1368_READ_MASK 0x070F0101U +#define LPDDR4__DENALI_PHY_1368_WRITE_MASK 0x070F0101U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOSET 0U +#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1368 +#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK + +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__REG DENALI_PHY_1368 +#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE + +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH 4U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1368 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_WIDTH 3U +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1368 +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1369_READ_MASK 0x000707FFU +#define LPDDR4__DENALI_PHY_1369_WRITE_MASK 0x000707FFU +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1369 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS + +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_WIDTH 3U +#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1369 +#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS + +#define LPDDR4__DENALI_PHY_1370_READ_MASK 0x0707FF01U +#define LPDDR4__DENALI_PHY_1370_WRITE_MASK 0x0707FF01U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WOSET 0U +#define LPDDR4__PHY_PARITY_ERROR_INJECTION_ENABLE__REG DENALI_PHY_1370 +#define LPDDR4__PHY_PARITY_ERROR_INJECTION_ENABLE__FLD LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE + +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_WIDTH 11U +#define LPDDR4__PHY_PARITY_ERROR_REGIF_PS__REG DENALI_PHY_1370 +#define LPDDR4__PHY_PARITY_ERROR_REGIF_PS__FLD LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS + +#define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_WIDTH 3U +#define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__REG DENALI_PHY_1370 +#define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__FLD LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK + +#define LPDDR4__DENALI_PHY_1371_READ_MASK 0x00007F7FU +#define LPDDR4__DENALI_PHY_1371_WRITE_MASK 0x00007F7FU +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_WIDTH 7U +#define LPDDR4__PHY_PARITY_ERROR_INFO__REG DENALI_PHY_1371 +#define LPDDR4__PHY_PARITY_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_SHIFT 8U +#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_WIDTH 7U +#define LPDDR4__PHY_PARITY_ERROR_INFO_MASK__REG DENALI_PHY_1371 +#define LPDDR4__PHY_PARITY_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_SHIFT 16U +#define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_WIDTH 7U +#define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__REG DENALI_PHY_1371 +#define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1372_READ_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1372_WRITE_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_WIDTH 14U +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO__REG DENALI_PHY_1372 +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_WIDTH 14U +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__REG DENALI_PHY_1372 +#define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1373_READ_MASK 0x3F0F0000U +#define LPDDR4__DENALI_PHY_1373_WRITE_MASK 0x3F0F0000U +#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_WIDTH 14U +#define LPDDR4__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR__REG DENALI_PHY_1373 +#define LPDDR4__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_SHIFT 16U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_WIDTH 4U +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR__REG DENALI_PHY_1373 +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR + +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_WIDTH 6U +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__REG DENALI_PHY_1373 +#define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK + +#define LPDDR4__DENALI_PHY_1374_READ_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1374_WRITE_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_WIDTH 6U +#define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__REG DENALI_PHY_1374 +#define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__FLD LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR + +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_SHIFT 8U +#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_WIDTH 12U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__REG DENALI_PHY_1374 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN + +#define LPDDR4__DENALI_PHY_1375_READ_MASK 0x03030FFFU +#define LPDDR4__DENALI_PHY_1375_WRITE_MASK 0x03030FFFU +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_SHIFT 0U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_WIDTH 12U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__REG DENALI_PHY_1375 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX + +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_SHIFT 16U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_WIDTH 2U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO__REG DENALI_PHY_1375 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_WIDTH 2U +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__REG DENALI_PHY_1375 +#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1376_READ_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1376_WRITE_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__REG DENALI_PHY_1376 +#define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_SHIFT 8U +#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_WIDTH 9U +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO__REG DENALI_PHY_1376 +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1377_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1377_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_WIDTH 9U +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO_MASK__REG DENALI_PHY_1377 +#define LPDDR4__PHY_TOP_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_SHIFT 16U +#define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_WIDTH 9U +#define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__REG DENALI_PHY_1377 +#define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1378_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_1378_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_WIDTH 10U +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO__REG DENALI_PHY_1378 +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_WIDTH 10U +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__REG DENALI_PHY_1378 +#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1379_READ_MASK 0x03030000U +#define LPDDR4__DENALI_PHY_1379_WRITE_MASK 0x03030000U +#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_WIDTH 10U +#define LPDDR4__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR__REG DENALI_PHY_1379 +#define LPDDR4__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_SHIFT 16U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_WIDTH 2U +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO__REG DENALI_PHY_1379 +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_SHIFT 24U +#define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_WIDTH 2U +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1379 +#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1380_READ_MASK 0x007F7F00U +#define LPDDR4__DENALI_PHY_1380_WRITE_MASK 0x007F7F00U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 2U +#define LPDDR4__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380 +#define LPDDR4__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_SHIFT 8U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_WIDTH 7U +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO__REG DENALI_PHY_1380 +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_SHIFT 16U +#define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_WIDTH 7U +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1380 +#define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 24U +#define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 7U +#define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380 +#define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PHY_1381_READ_MASK 0x00003F3FU +#define LPDDR4__DENALI_PHY_1381_WRITE_MASK 0x00003F3FU +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_WIDTH 6U +#define LPDDR4__PHY_GLOBAL_ERROR_INFO__REG DENALI_PHY_1381 +#define LPDDR4__PHY_GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO + +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_SHIFT 8U +#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_WIDTH 6U +#define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__REG DENALI_PHY_1381 +#define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PHY_1382_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1382_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_WIDTH 20U +#define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__REG DENALI_PHY_1382 +#define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1383_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1383_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_WIDTH 20U +#define LPDDR4__PHY_INIT_TIMEOUT_VALUE__REG DENALI_PHY_1383 +#define LPDDR4__PHY_INIT_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1384_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1384_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_WIDTH 16U +#define LPDDR4__PHY_LP_TIMEOUT_VALUE__REG DENALI_PHY_1384 +#define LPDDR4__PHY_LP_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1385_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1385_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_WIDTH 32U +#define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__REG DENALI_PHY_1385 +#define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1386_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_PHY_1386_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_WIDTH 20U +#define LPDDR4__PHY_PHYMSTR_TIMEOUT_VALUE__REG DENALI_PHY_1386 +#define LPDDR4__PHY_PHYMSTR_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_WIDTH 5U +#define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__REG DENALI_PHY_1386 +#define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE + +#define LPDDR4__DENALI_PHY_1387_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1387_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_WIDTH 16U +#define LPDDR4__PHY_PLL_LOCK_TIMEOUT_VALUE__REG DENALI_PHY_1387 +#define LPDDR4__PHY_PLL_LOCK_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_WIDTH 8U +#define LPDDR4__PHY_RDDATA_VALID_TIMEOUT_VALUE__REG DENALI_PHY_1387 +#define LPDDR4__PHY_RDDATA_VALID_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE + +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_SHIFT 24U +#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_WIDTH 4U +#define LPDDR4__PHY_PLL_FREQUENCY_DELTA__REG DENALI_PHY_1387 +#define LPDDR4__PHY_PLL_FREQUENCY_DELTA__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA + +#define LPDDR4__DENALI_PHY_1388_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1388_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_WIDTH 16U +#define LPDDR4__PHY_PLL_FREQUENCY_COMPARE_INTERVAL__REG DENALI_PHY_1388 +#define LPDDR4__PHY_PLL_FREQUENCY_COMPARE_INTERVAL__FLD LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL + +#define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__REG DENALI_PHY_1388 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1389_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1389_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1389 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1389 +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1390_READ_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1390_WRITE_MASK 0x3FFF3FFFU +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_1__REG DENALI_PHY_1390 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1 + +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_WIDTH 14U +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_1390 +#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1 + +#define LPDDR4__DENALI_PHY_1391_READ_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1391_WRITE_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_WIDTH 14U +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_1391 +#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1 + +#define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_WIDTH 14U +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__REG DENALI_PHY_1391 +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0 + +#define LPDDR4__DENALI_PHY_1392_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1392_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_WIDTH 14U +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1392 +#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0 + +#define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U +#define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1392 +#define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0 + +#define LPDDR4__DENALI_PHY_1393_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1393_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1393 +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_1394_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1394_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_SHIFT 0U +#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_WIDTH 14U +#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1394 +#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG + +#define LPDDR4__DENALI_PHY_1395_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1395_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1395 +#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1396_READ_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1396_WRITE_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1396 +#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1396 +#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1397_READ_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1397_WRITE_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_SHIFT 0U +#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1397 +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC + +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1397 +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_WIDTH 4U +#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1397 +#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP + +#define LPDDR4__DENALI_PHY_1398_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1398_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_WIDTH 9U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1398 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN + +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1398 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN + +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET 0U +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1398 +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE + +#define LPDDR4__DENALI_PHY_1399_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1399_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1399 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1399 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1400_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1400_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1400 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1400 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1401_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1401_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1401 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1402_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1402_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1402 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1403_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1403_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1403 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1404_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1404_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1404 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1405_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1405_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_WIDTH 3U +#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1405 +#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL + +#define LPDDR4__DENALI_PHY_1406_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1406_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1406 +#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE + +#define LPDDR4__DENALI_PHY_1407_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1407_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1407 +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1408_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1408_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_WIDTH 31U +#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1408 +#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE + +#define LPDDR4__DENALI_PHY_1409_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1409_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1409 +#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE + +#define LPDDR4__DENALI_PHY_1410_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1410_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1410 +#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE + +#define LPDDR4__DENALI_PHY_1411_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1411_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1411 +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2 + +#define LPDDR4__DENALI_PHY_1412_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1412_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1412 +#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE + +#define LPDDR4__DENALI_PHY_1413_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1413_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_WIDTH 18U +#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1413 +#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1414_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1414_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1414 +#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE + +#define LPDDR4__DENALI_PHY_1415_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1415_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1415 +#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2 + +#define LPDDR4__DENALI_PHY_1416_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1416_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1416 +#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE + +#define LPDDR4__DENALI_PHY_1417_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1417_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1417 +#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2 + +#define LPDDR4__DENALI_PHY_1418_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1418_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1418 +#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE + +#define LPDDR4__DENALI_PHY_1419_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1419_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1419 +#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2 + +#define LPDDR4__DENALI_PHY_1420_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1420_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1420 +#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE + +#define LPDDR4__DENALI_PHY_1421_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1421_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_WIDTH 27U +#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1421 +#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2 + +#define LPDDR4__DENALI_PHY_1422_READ_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1422_WRITE_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1422 +#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH 16U +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1422 +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0 + +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_WIDTH 7U +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1422 +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0 + +#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h new file mode 100644 index 000000000..7f1754a49 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h @@ -0,0 +1,5396 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_PI_MACROS_H_ +#define REG_LPDDR4_PI_MACROS_H_ + +#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U +#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U +#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U +#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U +#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U +#define LPDDR4__PI_START__REG DENALI_PI_0 +#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START + +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U +#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0 +#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS + +#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U +#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1 +#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0 + +#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U +#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2 +#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1 + +#define LPDDR4__DENALI_PI_3_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U +#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U +#define LPDDR4__PI_ID__REG DENALI_PI_3 +#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID + +#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT 0U +#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH 32U +#define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4 +#define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0 + +#define LPDDR4__DENALI_PI_5_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT 0U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET 0U +#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5 +#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ + +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET 0U +#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5 +#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN + +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK 0x00010000U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT 16U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET 0U +#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5 +#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD + +#define LPDDR4__DENALI_PI_6_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT 0U +#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH 16U +#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6 +#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP + +#define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT 16U +#define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH 8U +#define LPDDR4__PI_RESERVED0__REG DENALI_PI_6 +#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0 + +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6 +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ + +#define LPDDR4__DENALI_PI_7_READ_MASK 0x01010301U +#define LPDDR4__DENALI_PI_7_WRITE_MASK 0x01010301U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK 0x00000001U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH 1U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET 0U +#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION + +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK 0x00000300U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT 8U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00010000U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 16U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R + +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x01000000U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 24U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U +#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7 +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R + +#define LPDDR4__DENALI_PI_8_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_8_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8 +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX + +#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9 +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP + +#define LPDDR4__DENALI_PI_10_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_10_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10 +#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP + +#define LPDDR4__DENALI_PI_11_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_11_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11 +#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX + +#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U +#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12 +#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP + +#define LPDDR4__DENALI_PI_13_READ_MASK 0x0101011FU +#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x0101011FU +#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT 0U +#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH 5U +#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13 +#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ + +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET 0U +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13 +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY + +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00010000U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 16U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U +#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13 +#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N + +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 24U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U +#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13 +#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1 + +#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU +#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU +#define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH 4U +#define LPDDR4__PI_CS_MAP__REG DENALI_PI_14 +#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP + +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U +#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14 +#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE + +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14 +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN + +#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U +#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U +#define LPDDR4__PI_TMRR__REG DENALI_PI_14 +#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR + +#define LPDDR4__DENALI_PI_15_READ_MASK 0x00010103U +#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x00010103U +#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK 0x00000003U +#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT 0U +#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15 +#define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT + +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 8U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15 +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY + +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x00010000U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 16U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U +#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15 +#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2 + +#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U +#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16 +#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL + +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U +#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16 +#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS + +#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U +#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17 +#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U +#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U +#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE + +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17 +#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0 + +#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U +#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1 + +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2 + +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3 + +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18 +#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0 + +#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1 + +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2 + +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3 + +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19 +#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0 + +#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U +#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20 +#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U +#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U +#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0 + +#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0 + +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21 +#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1 + +#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1 + +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1 + +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22 +#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1 + +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2 + +#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2 + +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2 + +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23 +#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2 + +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3 + +#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3 + +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3 + +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24 +#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3 + +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START + +#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25 +#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR + +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25 +#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD + +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25 +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ + +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25 +#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN + +#define LPDDR4__DENALI_PI_26_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26 +#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN + +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 8U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U +#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26 +#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY + +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 16U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U +#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26 +#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT + +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET 0U +#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26 +#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ + +#define LPDDR4__DENALI_PI_27_READ_MASK 0x003F3F03U +#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x003F3F03U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00000003U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 0U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U +#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27 +#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS + +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 8U +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U +#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27 +#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN + +#define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT 16U +#define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH 6U +#define LPDDR4__PI_WLMRD__REG DENALI_PI_27 +#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD + +#define LPDDR4__DENALI_PI_28_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL + +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK 0x00010000U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT 16U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC + +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U +#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP + +#define LPDDR4__DENALI_PI_30_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30 +#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30 +#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN + +#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31 +#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP + +#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32 +#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX + +#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33 +#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U +#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33 +#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR + +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U +#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33 +#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD + +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U +#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33 +#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE + +#define LPDDR4__DENALI_PI_34_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ + +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT 8U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ + +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00030000U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 16U +#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 2U +#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34 +#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS + +#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35 +#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0 + +#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36 +#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1 + +#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37 +#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2 + +#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38 +#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3 + +#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39 +#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4 + +#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40 +#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5 + +#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41 +#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6 + +#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42 +#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7 + +#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U +#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK 0x00000100U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT 8U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 24U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK 0x00000001U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS + +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE + +#define LPDDR4__DENALI_PI_45_READ_MASK 0x000F0F01U +#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x000F0F01U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE + +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP + +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 4U +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP + +#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U +#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U +#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46 +#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR + +#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47 +#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP + +#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48 +#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48 +#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN + +#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49 +#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX + +#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50 +#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U +#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50 +#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL + +#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL + +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START + +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM + +#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52 +#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52 +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM + +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52 +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52 +#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE + +#define LPDDR4__DENALI_PI_53_READ_MASK 0x03007F7FU +#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x03007F7FU +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 7U +#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53 +#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN + +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U +#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 7U +#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53 +#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT + +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U +#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53 +#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ + +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK 0x03000000U +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT 24U +#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH 2U +#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53 +#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS + +#define LPDDR4__DENALI_PI_54_READ_MASK 0x01030F01U +#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x01030F01U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK 0x00000001U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT 0U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH 1U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR 0U +#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET 0U +#define LPDDR4__PI_RESERVED3__REG DENALI_PI_54 +#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3 + +#define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT 8U +#define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH 4U +#define LPDDR4__PI_RESERVED4__REG DENALI_PI_54 +#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4 + +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x00030000U +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U +#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54 +#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN + +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54 +#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC + +#define LPDDR4__DENALI_PI_55_READ_MASK 0x0F010101U +#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x0F010101U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00000100U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 8U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 16U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U +#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE + +#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55 +#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP + +#define LPDDR4__DENALI_PI_56_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56 +#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN + +#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57 +#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP + +#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58 +#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX + +#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U +#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U +#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK + +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U +#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL + +#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U +#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U +#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60 +#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL + +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U +#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U +#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60 +#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD + +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U +#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U +#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60 +#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH + +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U +#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U +#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60 +#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT + +#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U +#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61 +#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN + +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61 +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U +#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61 +#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN + +#define LPDDR4__DENALI_PI_62_READ_MASK 0x7F1F0FFFU +#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x7F1F0FFFU +#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 0U +#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN + +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 8U +#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 4U +#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62 +#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH + +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62 +#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 24U +#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U +#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62 +#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF + +#define LPDDR4__DENALI_PI_63_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U +#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63 +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START + +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U +#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63 +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE + +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U +#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63 +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL + +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63 +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE + +#define LPDDR4__DENALI_PI_64_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64 +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE + +#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT 8U +#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH 16U +#define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64 +#define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK + +#define LPDDR4__DENALI_PI_65_READ_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_65_WRITE_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT 0U +#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH 16U +#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65 +#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR + +#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT 16U +#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH 16U +#define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65 +#define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO + +#define LPDDR4__DENALI_PI_66_READ_MASK 0x010F0701U +#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x010F0701U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK 0x00000700U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH 3U +#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT 16U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66 +#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE + +#define LPDDR4__DENALI_PI_67_READ_MASK 0x011F1F0FU +#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x011F1F0FU +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 8U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x01000000U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 24U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67 +#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC + +#define LPDDR4__DENALI_PI_68_READ_MASK 0x00FF0300U +#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x00FF0300U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT 0U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET 0U +#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68 +#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ + +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT 8U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH 2U +#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68 +#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS + +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68 +#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN + +#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69 +#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP + +#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70 +#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX + +#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL + +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT 24U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71 +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_72_READ_MASK 0x01010103U +#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72 +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72 +#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN + +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72 +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN + +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET 0U +#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72 +#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN + +#define LPDDR4__DENALI_PI_73_READ_MASK 0x0F1F0703U +#define LPDDR4__DENALI_PI_73_WRITE_MASK 0x0F1F0703U +#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK 0x00000003U +#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT 0U +#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH 2U +#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73 +#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF + +#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK 0x00000700U +#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT 8U +#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH 3U +#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73 +#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF + +#define LPDDR4__DENALI_PI_73__PI_TCCD_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT 16U +#define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH 5U +#define LPDDR4__PI_TCCD__REG DENALI_PI_73 +#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD + +#define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT 24U +#define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH 4U +#define LPDDR4__PI_RESERVED5__REG DENALI_PI_73 +#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5 + +#define LPDDR4__DENALI_PI_74_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT 0U +#define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH 4U +#define LPDDR4__PI_RESERVED6__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6 + +#define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT 8U +#define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH 4U +#define LPDDR4__PI_RESERVED7__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7 + +#define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT 16U +#define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH 4U +#define LPDDR4__PI_RESERVED8__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8 + +#define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT 24U +#define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH 4U +#define LPDDR4__PI_RESERVED9__REG DENALI_PI_74 +#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9 + +#define LPDDR4__DENALI_PI_75_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT 0U +#define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH 4U +#define LPDDR4__PI_RESERVED10__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10 + +#define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT 8U +#define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH 4U +#define LPDDR4__PI_RESERVED11__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11 + +#define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT 16U +#define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH 4U +#define LPDDR4__PI_RESERVED12__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12 + +#define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT 24U +#define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH 4U +#define LPDDR4__PI_RESERVED13__REG DENALI_PI_75 +#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13 + +#define LPDDR4__DENALI_PI_76_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT 0U +#define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH 4U +#define LPDDR4__PI_RESERVED14__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14 + +#define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT 8U +#define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH 4U +#define LPDDR4__PI_RESERVED15__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15 + +#define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT 16U +#define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH 4U +#define LPDDR4__PI_RESERVED16__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16 + +#define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT 24U +#define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH 4U +#define LPDDR4__PI_RESERVED17__REG DENALI_PI_76 +#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17 + +#define LPDDR4__DENALI_PI_77_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT 0U +#define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH 4U +#define LPDDR4__PI_RESERVED18__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18 + +#define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT 8U +#define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH 4U +#define LPDDR4__PI_RESERVED19__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19 + +#define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT 16U +#define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH 4U +#define LPDDR4__PI_RESERVED20__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20 + +#define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT 24U +#define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH 4U +#define LPDDR4__PI_RESERVED21__REG DENALI_PI_77 +#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21 + +#define LPDDR4__DENALI_PI_78_READ_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT 0U +#define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH 4U +#define LPDDR4__PI_RESERVED22__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22 + +#define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT 8U +#define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH 4U +#define LPDDR4__PI_RESERVED23__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23 + +#define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT 16U +#define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH 4U +#define LPDDR4__PI_RESERVED24__REG DENALI_PI_78 +#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24 + +#define LPDDR4__DENALI_PI_79_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH 28U +#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79 +#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS + +#define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT 0U +#define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH 27U +#define LPDDR4__PI_INT_ACK__REG DENALI_PI_80 +#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK + +#define LPDDR4__DENALI_PI_81_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH 28U +#define LPDDR4__PI_INT_MASK__REG DENALI_PI_81 +#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK + +#define LPDDR4__DENALI_PI_82_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_82_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82 +#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_PI_83_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_83_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83 +#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_PI_84_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_84_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84 +#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2 + +#define LPDDR4__DENALI_PI_85_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_85_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85 +#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3 + +#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86 +#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87 +#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88 +#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2 + +#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89 +#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3 + +#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90 +#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F1F07U +#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F1F07U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 3U +#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91 +#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U +#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 5U +#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91 +#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN + +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U +#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91 +#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK + +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U +#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91 +#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN + +#define LPDDR4__DENALI_PI_92_READ_MASK 0x03030301U +#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x03030301U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET 0U +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN + +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 8U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0 + +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 16U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1 + +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 24U +#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2 + +#define LPDDR4__DENALI_PI_93_READ_MASK 0x03FF0103U +#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x03FF0103U +#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000003U +#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 0U +#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3 + +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93 +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT 16U +#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93 +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U +#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93 +#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_PI_94_READ_MASK 0x013F0301U +#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x013F0301U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK 0x00000001U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT 0U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET 0U +#define LPDDR4__PI_BIST_GO__REG DENALI_PI_94 +#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO + +#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK 0x00000300U +#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT 8U +#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH 2U +#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94 +#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT + +#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT 16U +#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH 6U +#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94 +#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE + +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK 0x01000000U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT 24U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94 +#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK + +#define LPDDR4__DENALI_PI_95_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT 0U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95 +#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK + +#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96 +#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_PI_97_READ_MASK 0x0000FF07U +#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x0000FF07U +#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH 3U +#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97 +#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT 8U +#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH 8U +#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97 +#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN + +#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH 32U +#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98 +#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0 + +#define LPDDR4__DENALI_PI_99_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_99_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH 32U +#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99 +#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1 + +#define LPDDR4__DENALI_PI_100_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100 +#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT + +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT 16U +#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100 +#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP + +#define LPDDR4__DENALI_PI_101_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_101_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101 +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0 + +#define LPDDR4__DENALI_PI_102_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102 +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1 + +#define LPDDR4__DENALI_PI_103_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_103_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103 +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0 + +#define LPDDR4__DENALI_PI_104_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104 +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1 + +#define LPDDR4__DENALI_PI_105_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105 +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0 + +#define LPDDR4__DENALI_PI_106_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106 +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1 + +#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT 0U +#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107 +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0 + +#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT 0U +#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108 +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1 + +#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT 0U +#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109 +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0 + +#define LPDDR4__DENALI_PI_110_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_110_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT 0U +#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110 +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1 + +#define LPDDR4__DENALI_PI_111_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_111_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT 0U +#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111 +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0 + +#define LPDDR4__DENALI_PI_112_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_112_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT 0U +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112 +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1 + +#define LPDDR4__DENALI_PI_113_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_113_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT 0U +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113 +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0 + +#define LPDDR4__DENALI_PI_114_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_114_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT 0U +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114 +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1 + +#define LPDDR4__DENALI_PI_115_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_115_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT 0U +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115 +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0 + +#define LPDDR4__DENALI_PI_116_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_116_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT 0U +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116 +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1 + +#define LPDDR4__DENALI_PI_117_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_117_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT 0U +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117 +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0 + +#define LPDDR4__DENALI_PI_118_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_118_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT 0U +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118 +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1 + +#define LPDDR4__DENALI_PI_119_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_119_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT 0U +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119 +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0 + +#define LPDDR4__DENALI_PI_120_READ_MASK 0x0303070FU +#define LPDDR4__DENALI_PI_120_WRITE_MASK 0x0303070FU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT 0U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1 + +#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK 0x00000700U +#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT 8U +#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH 3U +#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE + +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT 16U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE + +#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK 0x03000000U +#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT 24U +#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE + +#define LPDDR4__DENALI_PI_121_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_121_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121 +#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0 + +#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122 +#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1 + +#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123 +#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2 + +#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124 +#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3 + +#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH 4U +#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125 +#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM + +#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126 +#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0 + +#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127 +#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1 + +#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT 0U +#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128 +#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2 + +#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT 0U +#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129 +#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3 + +#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT 0U +#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130 +#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4 + +#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT 0U +#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131 +#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5 + +#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT 0U +#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132 +#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6 + +#define LPDDR4__DENALI_PI_133_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT 0U +#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133 +#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7 + +#define LPDDR4__DENALI_PI_134_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT 0U +#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH 4U +#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134 +#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF + +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET 0U +#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134 +#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN + +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134 +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 24U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U +#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134 +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH + +#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010100U +#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010100U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT 0U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET 0U +#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135 +#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ + +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 8U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT + +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 16U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT + +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135 +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT + +#define LPDDR4__DENALI_PI_136_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT 0U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136 +#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH 32U +#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137 +#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON + +#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH 32U +#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138 +#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE + +#define LPDDR4__DENALI_PI_139_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_139_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK 0x00000001U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT 0U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH 1U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR 0U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET 0U +#define LPDDR4__PI_DLL_RST__REG DENALI_PI_139 +#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST + +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET 0U +#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139 +#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN + +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT 16U +#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139 +#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY + +#define LPDDR4__DENALI_PI_140_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT 0U +#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140 +#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_PI_141_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH 26U +#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141 +#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG + +#define LPDDR4__DENALI_PI_142_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH 8U +#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142 +#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS + +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x01FFFF00U +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 8U +#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U +#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142 +#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG + +#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143 +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0 + +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U +#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143 +#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT + +#define LPDDR4__DENALI_PI_144_READ_MASK 0x0101000FU +#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x0101000FU +#define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT 0U +#define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH 4U +#define LPDDR4__PI_RESERVED25__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25 + +#define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT 8U +#define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH 4U +#define LPDDR4__PI_RESERVED26__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26 + +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144 +#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING + +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK 0x01000000U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT 24U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH 1U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR 0U +#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET 0U +#define LPDDR4__PI_RESERVED27__REG DENALI_PI_144 +#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27 + +#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK 0x00000007U +#define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT 0U +#define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH 3U +#define LPDDR4__PI_RESERVED28__REG DENALI_PI_145 +#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0 + +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U +#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U +#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145 +#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0 + +#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U +#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1 + +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U +#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146 +#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2 + +#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U +#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3 + +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147 +#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3 + +#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U +#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4 + +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U +#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U +#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148 +#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4 + +#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U +#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5 + +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U +#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149 +#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6 + +#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U +#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7 + +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150 +#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7 + +#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U +#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U +#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151 +#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7 + +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U +#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U +#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152 +#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE + +#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U +#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U +#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153 +#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK + +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U +#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153 +#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS + +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U +#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153 +#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM + +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK 0x01000000U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT 24U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH 1U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR 0U +#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET 0U +#define LPDDR4__PI_RESERVED29__REG DENALI_PI_153 +#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29 + +#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U +#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U +#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154 +#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK 0x00000100U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT 8U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET 0U +#define LPDDR4__PI_RESERVED30__REG DENALI_PI_154 +#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30 + +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U +#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154 +#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN + +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK 0x01000000U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT 24U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH 1U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR 0U +#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET 0U +#define LPDDR4__PI_RESERVED31__REG DENALI_PI_154 +#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31 + +#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK 0x00000001U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET 0U +#define LPDDR4__PI_RESERVED32__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK 0x00000100U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT 8U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET 0U +#define LPDDR4__PI_RESERVED33__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK 0x00010000U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT 16U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET 0U +#define LPDDR4__PI_RESERVED34__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34 + +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x01000000U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 24U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U +#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155 +#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35 + +#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK 0x00000001U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET 0U +#define LPDDR4__PI_RESERVED36__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK 0x00000100U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT 8U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET 0U +#define LPDDR4__PI_RESERVED37__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK 0x00010000U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT 16U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET 0U +#define LPDDR4__PI_RESERVED38__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x01000000U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 24U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U +#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39 + +#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK 0x00000001U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET 0U +#define LPDDR4__PI_RESERVED40__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK 0x00000100U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT 8U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET 0U +#define LPDDR4__PI_RESERVED41__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK 0x00010000U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT 16U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET 0U +#define LPDDR4__PI_RESERVED42__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42 + +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x01000000U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 24U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U +#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43 + +#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK 0x00000001U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET 0U +#define LPDDR4__PI_RESERVED44__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK 0x00000100U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT 8U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET 0U +#define LPDDR4__PI_RESERVED45__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK 0x00010000U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT 16U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET 0U +#define LPDDR4__PI_RESERVED46__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46 + +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x01000000U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 24U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U +#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158 +#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47 + +#define LPDDR4__DENALI_PI_159_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 0U +#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159 +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND + +#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK 0x0001FF00U +#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT 8U +#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH 9U +#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159 +#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR + +#define LPDDR4__DENALI_PI_160_READ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U +#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160 +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY + +#define LPDDR4__DENALI_PI_161_READ_MASK 0x0F011F01U +#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0F011F01U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161 +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT 8U +#define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH 5U +#define LPDDR4__PI_RESERVED48__REG DENALI_PI_161 +#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48 + +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET 0U +#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161 +#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN + +#define LPDDR4__DENALI_PI_161__PI_CATR_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT 24U +#define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH 4U +#define LPDDR4__PI_CATR__REG DENALI_PI_161 +#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR + +#define LPDDR4__DENALI_PI_162_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 0U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U +#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162 +#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ + +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK 0x00000100U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT 8U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162 +#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE + +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK 0x00010000U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT 16U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET 0U +#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162 +#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC + +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT 24U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET 0U +#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162 +#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START + +#define LPDDR4__DENALI_PI_163_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_PI_163_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK 0x00000001U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT 0U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH 1U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR 0U +#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET 0U +#define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163 +#define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13 + +#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH 8U +#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163 +#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0 + +#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH 8U +#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163 +#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1 + +#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH 8U +#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163 +#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2 + +#define LPDDR4__DENALI_PI_164_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0 + +#define LPDDR4__DENALI_PI_165_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1 + +#define LPDDR4__DENALI_PI_166_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2 + +#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166 +#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0 + +#define LPDDR4__DENALI_PI_167_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167 +#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1 + +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167 +#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2 + +#define LPDDR4__DENALI_PI_168_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH 7U +#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168 +#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0 + +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168 +#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0 + +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH 7U +#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168 +#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1 + +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168 +#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1 + +#define LPDDR4__DENALI_PI_169_READ_MASK 0x03FF7F7FU +#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x03FF7F7FU +#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH 7U +#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169 +#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2 + +#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169 +#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2 + +#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH 10U +#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169 +#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0 + +#define LPDDR4__DENALI_PI_170_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH 20U +#define LPDDR4__PI_TREF_F0__REG DENALI_PI_170 +#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0 + +#define LPDDR4__DENALI_PI_171_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH 10U +#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171 +#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1 + +#define LPDDR4__DENALI_PI_172_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH 20U +#define LPDDR4__PI_TREF_F1__REG DENALI_PI_172 +#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1 + +#define LPDDR4__DENALI_PI_173_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH 10U +#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173 +#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2 + +#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH 20U +#define LPDDR4__PI_TREF_F2__REG DENALI_PI_174 +#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2 + +#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_PI_175_READ_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175 +#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0 + +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175 +#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1 + +#define LPDDR4__DENALI_PI_176_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176 +#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2 + +#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176 +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0 + +#define LPDDR4__DENALI_PI_177_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177 +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1 + +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177 +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2 + +#define LPDDR4__DENALI_PI_178_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178 +#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0 + +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET 0U +#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178 +#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0 + +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178 +#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1 + +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET 0U +#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178 +#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1 + +#define LPDDR4__DENALI_PI_179_READ_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179 +#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2 + +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET 0U +#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179 +#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2 + +#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH 4U +#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179 +#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0 + +#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179 +#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0 + +#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH 4U +#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180 +#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1 + +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180 +#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1 + +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH 4U +#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180 +#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2 + +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180 +#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2 + +#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0 + +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0 + +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1 + +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181 +#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1 + +#define LPDDR4__DENALI_PI_182_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2 + +#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2 + +#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0 + +#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0 + +#define LPDDR4__DENALI_PI_183_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0 + +#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0 + +#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1 + +#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1 + +#define LPDDR4__DENALI_PI_184_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1 + +#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1 + +#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2 + +#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2 + +#define LPDDR4__DENALI_PI_185_READ_MASK 0x7F7F0303U +#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x7F7F0303U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185 +#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2 + +#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185 +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2 + +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185 +#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185 +#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_186_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186 +#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH 7U +#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186 +#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH 7U +#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186 +#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH 7U +#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186 +#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_187_READ_MASK 0x00070707U +#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x00070707U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000007U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK 0x00000700U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK 0x00070000U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_PI_188_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188 +#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0 + +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0 + +#define LPDDR4__DENALI_PI_189_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189 +#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1 + +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1 + +#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190 +#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2 + +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2 + +#define LPDDR4__DENALI_PI_191_READ_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191 +#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0 + +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191 +#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1 + +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191 +#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2 + +#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH 5U +#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191 +#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0 + +#define LPDDR4__DENALI_PI_192_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH 14U +#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192 +#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0 + +#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH 5U +#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192 +#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1 + +#define LPDDR4__DENALI_PI_193_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH 14U +#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193 +#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1 + +#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH 5U +#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193 +#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2 + +#define LPDDR4__DENALI_PI_194_READ_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH 14U +#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194 +#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2 + +#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194 +#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0 + +#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194 +#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0 + +#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195 +#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0 + +#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195 +#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0 + +#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196 +#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1 + +#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196 +#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1 + +#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196 +#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1 + +#define LPDDR4__DENALI_PI_197_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197 +#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1 + +#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197 +#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2 + +#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197 +#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2 + +#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198 +#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2 + +#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198 +#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2 + +#define LPDDR4__DENALI_PI_199_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_200_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200 +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_201_READ_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_201_WRITE_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201 +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0 + +#define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH 5U +#define LPDDR4__PI_TXP_F0__REG DENALI_PI_201 +#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0 + +#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201 +#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0 + +#define LPDDR4__DENALI_PI_202_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_202_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202 +#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0 + +#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1 + +#define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH 5U +#define LPDDR4__PI_TXP_F1__REG DENALI_PI_202 +#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1 + +#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202 +#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1 + +#define LPDDR4__DENALI_PI_203_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_203_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203 +#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1 + +#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2 + +#define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH 5U +#define LPDDR4__PI_TXP_F2__REG DENALI_PI_203 +#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2 + +#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203 +#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2 + +#define LPDDR4__DENALI_PI_204_READ_MASK 0x0003FF1FU +#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x0003FF1FU +#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204 +#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2 + +#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204 +#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_PI_205_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH 16U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205 +#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH 16U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206 +#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_PI_207_READ_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x003FFFFFU +#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH 16U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207 +#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0 + +#define LPDDR4__DENALI_PI_208_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH 10U +#define LPDDR4__PI_TFC_F0__REG DENALI_PI_208 +#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0 + +#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208 +#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1 + +#define LPDDR4__DENALI_PI_209_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH 10U +#define LPDDR4__PI_TFC_F1__REG DENALI_PI_209 +#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1 + +#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209 +#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2 + +#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH 10U +#define LPDDR4__PI_TFC_F2__REG DENALI_PI_210 +#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2 + +#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0 + +#define LPDDR4__DENALI_PI_211_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0 + +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_212_READ_MASK 0x0003030FU +#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x0003030FU +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212 +#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0 + +#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212 +#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0 + +#define LPDDR4__DENALI_PI_213_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1 + +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1 + +#define LPDDR4__DENALI_PI_214_READ_MASK 0x030F7F7FU +#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x030F7F7FU +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214 +#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1 + +#define LPDDR4__DENALI_PI_215_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215 +#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1 + +#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2 + +#define LPDDR4__DENALI_PI_216_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2 + +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_217_READ_MASK 0xFF03030FU +#define LPDDR4__DENALI_PI_217_WRITE_MASK 0xFF03030FU +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217 +#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2 + +#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217 +#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2 + +#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH 8U +#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217 +#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0 + +#define LPDDR4__DENALI_PI_218_READ_MASK 0xFF3FFFFFU +#define LPDDR4__DENALI_PI_218_WRITE_MASK 0xFF3FFFFFU +#define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH 8U +#define LPDDR4__PI_TRP_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0 + +#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH 8U +#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0 + +#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH 6U +#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0 + +#define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH 8U +#define LPDDR4__PI_TWR_F0__REG DENALI_PI_218 +#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0 + +#define LPDDR4__DENALI_PI_219_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_219_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH 17U +#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219 +#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0 + +#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH 8U +#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219 +#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0 + +#define LPDDR4__DENALI_PI_220_READ_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_220_WRITE_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0 + +#define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH 8U +#define LPDDR4__PI_TSR_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0 + +#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH 8U +#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220 +#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0 + +#define LPDDR4__DENALI_PI_221_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH 8U +#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221 +#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0 + +#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH 8U +#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221 +#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1 + +#define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH 8U +#define LPDDR4__PI_TRP_F1__REG DENALI_PI_221 +#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1 + +#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH 8U +#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221 +#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1 + +#define LPDDR4__DENALI_PI_222_READ_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH 6U +#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222 +#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1 + +#define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH 8U +#define LPDDR4__PI_TWR_F1__REG DENALI_PI_222 +#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1 + +#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH 17U +#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223 +#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1 + +#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH 8U +#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223 +#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1 + +#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1 + +#define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH 8U +#define LPDDR4__PI_TSR_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1 + +#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH 8U +#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224 +#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1 + +#define LPDDR4__DENALI_PI_225_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_225_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH 8U +#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225 +#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1 + +#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH 8U +#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225 +#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2 + +#define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH 8U +#define LPDDR4__PI_TRP_F2__REG DENALI_PI_225 +#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2 + +#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH 8U +#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225 +#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2 + +#define LPDDR4__DENALI_PI_226_READ_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x0000FF3FU +#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH 6U +#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226 +#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2 + +#define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH 8U +#define LPDDR4__PI_TWR_F2__REG DENALI_PI_226 +#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2 + +#define LPDDR4__DENALI_PI_227_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_227_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH 17U +#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227 +#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2 + +#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH 8U +#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227 +#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2 + +#define LPDDR4__DENALI_PI_228_READ_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_228_WRITE_MASK 0xFFFF3F0FU +#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2 + +#define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH 8U +#define LPDDR4__PI_TSR_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2 + +#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH 8U +#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2 + +#define LPDDR4__DENALI_PI_229_READ_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH 8U +#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229 +#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2 + +#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x1FFFFF00U +#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_PI_230_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_230_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_PI_231_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_PI_232_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_232_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_PI_233_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_PI_234_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_234_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH 16U +#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235 +#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0 + +#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH 16U +#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235 +#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1 + +#define LPDDR4__DENALI_PI_236_READ_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH 16U +#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236 +#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2 + +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236 +#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0 + +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236 +#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1 + +#define LPDDR4__DENALI_PI_237_READ_MASK 0xFFFFFF3FU +#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFFFFFF3FU +#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237 +#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2 + +#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH 24U +#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237 +#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0 + +#define LPDDR4__DENALI_PI_238_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH 24U +#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238 +#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0 + +#define LPDDR4__DENALI_PI_239_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH 24U +#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239 +#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0 + +#define LPDDR4__DENALI_PI_240_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH 24U +#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240 +#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0 + +#define LPDDR4__DENALI_PI_241_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH 16U +#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241 +#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0 + +#define LPDDR4__DENALI_PI_242_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH 24U +#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242 +#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1 + +#define LPDDR4__DENALI_PI_243_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH 24U +#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243 +#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1 + +#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH 24U +#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244 +#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1 + +#define LPDDR4__DENALI_PI_245_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH 24U +#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245 +#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1 + +#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH 16U +#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246 +#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1 + +#define LPDDR4__DENALI_PI_247_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH 24U +#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247 +#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2 + +#define LPDDR4__DENALI_PI_248_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_248_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH 24U +#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248 +#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2 + +#define LPDDR4__DENALI_PI_249_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH 24U +#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249 +#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2 + +#define LPDDR4__DENALI_PI_250_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH 24U +#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250 +#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2 + +#define LPDDR4__DENALI_PI_251_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH 16U +#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251 +#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2 + +#define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT 16U +#define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH 12U +#define LPDDR4__PI_RESERVED49__REG DENALI_PI_251 +#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49 + +#define LPDDR4__DENALI_PI_252_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_252_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT 0U +#define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH 12U +#define LPDDR4__PI_RESERVED50__REG DENALI_PI_252 +#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50 + +#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252 +#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0 + +#define LPDDR4__DENALI_PI_253_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_253_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253 +#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0 + +#define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT 8U +#define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH 12U +#define LPDDR4__PI_RESERVED51__REG DENALI_PI_253 +#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51 + +#define LPDDR4__DENALI_PI_254_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT 0U +#define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH 12U +#define LPDDR4__PI_RESERVED52__REG DENALI_PI_254 +#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52 + +#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254 +#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1 + +#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255 +#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1 + +#define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT 8U +#define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH 12U +#define LPDDR4__PI_RESERVED53__REG DENALI_PI_255 +#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53 + +#define LPDDR4__DENALI_PI_256_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT 0U +#define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH 12U +#define LPDDR4__PI_RESERVED54__REG DENALI_PI_256 +#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54 + +#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256 +#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2 + +#define LPDDR4__DENALI_PI_257_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_257_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257 +#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2 + +#define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT 8U +#define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH 12U +#define LPDDR4__PI_RESERVED55__REG DENALI_PI_257 +#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55 + +#define LPDDR4__DENALI_PI_258_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT 0U +#define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH 12U +#define LPDDR4__PI_RESERVED56__REG DENALI_PI_258 +#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56 + +#define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT 16U +#define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH 12U +#define LPDDR4__PI_RESERVED57__REG DENALI_PI_258 +#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57 + +#define LPDDR4__DENALI_PI_259_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_259_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0 + +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1 + +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2 + +#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259 +#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0 + +#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0 + +#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0 + +#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0 + +#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260 +#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0 + +#define LPDDR4__DENALI_PI_261_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_261_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261 +#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0 + +#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261 +#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0 + +#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261 +#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1 + +#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261 +#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1 + +#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1 + +#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT 8U +#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1 + +#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1 + +#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262 +#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1 + +#define LPDDR4__DENALI_PI_263_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_263_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263 +#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1 + +#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263 +#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2 + +#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT 16U +#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263 +#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2 + +#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT 24U +#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263 +#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2 + +#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2 + +#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2 + +#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT 16U +#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2 + +#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT 24U +#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264 +#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2 + +#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3 + +#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT 8U +#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3 + +#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT 16U +#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3 + +#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT 24U +#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265 +#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3 + +#define LPDDR4__DENALI_PI_266_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266 +#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3 + +#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT 8U +#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266 +#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3 + +#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT 16U +#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266 +#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3 + +#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266 +#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0 + +#define LPDDR4__DENALI_PI_267_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267 +#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1 + +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT 8U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267 +#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2 + +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT 16U +#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH 4U +#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267 +#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3 + +#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH 4U +#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267 +#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0 + +#define LPDDR4__DENALI_PI_268_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH 4U +#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268 +#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1 + +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT 8U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH 4U +#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268 +#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2 + +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT 16U +#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH 4U +#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268 +#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3 + +#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268 +#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0 + +#define LPDDR4__DENALI_PI_269_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269 +#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1 + +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT 8U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269 +#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2 + +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT 16U +#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH 4U +#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269 +#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3 + +#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269 +#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_PI_270_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270 +#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270 +#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2 + +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT 16U +#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH 8U +#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270 +#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3 + +#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270 +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_PI_271_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT 8U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT 24U +#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271 +#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2 + +#define LPDDR4__DENALI_PI_272_READ_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2 + +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT 8U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272 +#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3 + +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3 + +#define LPDDR4__DENALI_PI_273_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_273_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0 + +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0 + +#define LPDDR4__DENALI_PI_274_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_274_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1 + +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1 + +#define LPDDR4__DENALI_PI_275_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_275_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0 + +#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0 + +#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0 + +#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275 +#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_276_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0 + +#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276 +#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0 + +#define LPDDR4__DENALI_PI_277_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_277_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0 + +#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT 8U +#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0 + +#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0 + +#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277 +#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_278_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT 8U +#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0 + +#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278 +#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0 + +#define LPDDR4__DENALI_PI_279_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_279_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0 + +#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0 + +#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0 + +#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279 +#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_280_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0 + +#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280 +#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0 + +#define LPDDR4__DENALI_PI_281_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_281_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1 + +#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1 + +#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1 + +#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281 +#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_282_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1 + +#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282 +#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1 + +#define LPDDR4__DENALI_PI_283_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_283_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1 + +#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1 + +#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1 + +#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283 +#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_284_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1 + +#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284 +#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1 + +#define LPDDR4__DENALI_PI_285_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_285_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1 + +#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1 + +#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1 + +#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285 +#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1 + +#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286 +#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1 + +#define LPDDR4__DENALI_PI_287_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_287_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2 + +#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT 8U +#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2 + +#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT 16U +#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2 + +#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT 24U +#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287 +#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT 8U +#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT 16U +#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2 + +#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT 24U +#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288 +#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2 + +#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2 + +#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT 8U +#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2 + +#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT 16U +#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2 + +#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT 24U +#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289 +#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_290_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT 8U +#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT 16U +#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2 + +#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT 24U +#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290 +#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2 + +#define LPDDR4__DENALI_PI_291_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_291_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2 + +#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT 8U +#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2 + +#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT 16U +#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2 + +#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT 24U +#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291 +#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_292_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT 8U +#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT 16U +#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2 + +#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT 24U +#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292 +#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2 + +#define LPDDR4__DENALI_PI_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3 + +#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT 8U +#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3 + +#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT 16U +#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3 + +#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT 24U +#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293 +#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_294_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT 8U +#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT 16U +#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3 + +#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT 24U +#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294 +#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3 + +#define LPDDR4__DENALI_PI_295_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_295_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3 + +#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT 8U +#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3 + +#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT 16U +#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3 + +#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT 24U +#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295 +#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT 8U +#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT 16U +#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3 + +#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT 24U +#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296 +#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3 + +#define LPDDR4__DENALI_PI_297_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_297_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3 + +#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT 8U +#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3 + +#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT 16U +#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3 + +#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT 24U +#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297 +#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_298_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT 8U +#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT 16U +#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3 + +#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT 24U +#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298 +#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3 + +#define LPDDR4__DENALI_PI_299_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK 0x000007FFU +#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH 11U +#define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299 +#define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF + +#endif /* REG_LPDDR4_PI_MACROS_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/Makefile b/roms/u-boot/drivers/ram/k3-ddrss/Makefile new file mode 100644 index 000000000..8be00118f --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ +# + +obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o +obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o +obj-$(CONFIG_K3_DDRSS) += lpddr4.o +ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/ + +obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o +obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o +ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/ + +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o +ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/cps_drv_lpddr4.h b/roms/u-boot/drivers/ram/k3-ddrss/cps_drv_lpddr4.h new file mode 100644 index 000000000..298aa5e6c --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/cps_drv_lpddr4.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef CPS_DRV_H_ +#define CPS_DRV_H_ + +#ifdef DEMO_TB +#include +#else +#include +#endif + +#define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg))) + +#define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value))) + +#define CPS_FLD_MASK(fld) (fld ## _MASK) +#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT) +#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH) +#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR) +#define CPS_FLD_WOSET(fld) (fld ## _WOSET) + +#define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \ + (u32)(CPS_FLD_SHIFT(fld)), \ + (u32)(reg_value))) + +#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \ + (u32)(CPS_FLD_SHIFT(fld)), \ + (u32)(reg_value), (u32)(value))) + +#define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \ + (u32)(CPS_FLD_MASK(fld)), \ + (u32)(CPS_FLD_WOCLR(fld)), \ + (u32)(reg_value))) + +#ifdef CLR_USED +#define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \ + (u32)(CPS_FLD_MASK(fld)), \ + (u32)(CPS_FLD_WOSET(fld)), \ + (u32)(CPS_FLD_WOCLR(fld)), \ + (u32)(reg_value))) + +#endif +static inline u32 cps_regread(volatile u32 *reg); +static inline u32 cps_regread(volatile u32 *reg) +{ + return readl(reg); +} + +static inline void cps_regwrite(volatile u32 *reg, u32 value); +static inline void cps_regwrite(volatile u32 *reg, u32 value) +{ + writel(value, reg); +} + +static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value); +static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value) +{ + u32 result = (reg_value & mask) >> shift; + + return result; +} + +static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value); +static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value) +{ + u32 new_value = (value << shift) & mask; + + new_value = (reg_value & ~mask) | new_value; + return new_value; +} + +static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value); +static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value) +{ + u32 new_value = reg_value; + + if ((width == 1U) && (is_woclr == 0U)) + new_value |= mask; + + return new_value; +} + +#ifdef CLR_USED +static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value); +static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value) +{ + u32 new_value = reg_value; + + if ((width == 1U) && (is_woset == 0U)) + new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U); + + return new_value; +} +#endif /* CLR_USED */ + +#endif /* CPS_DRV_H_ */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/k3-ddrss.c b/roms/u-boot/drivers/ram/k3-ddrss/k3-ddrss.c new file mode 100644 index 000000000..cb8edcbc1 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/k3-ddrss.c @@ -0,0 +1,478 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' K3 DDRSS driver + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lpddr4_obj_if.h" +#include "lpddr4_if.h" +#include "lpddr4_structs_if.h" +#include "lpddr4_ctl_regs.h" + +#define SRAM_MAX 512 + +#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80 +#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0 + +#define DDRSS_V2A_R1_MAT_REG 0x0020 +#define DDRSS_ECC_CTRL_REG 0x0120 + +struct k3_ddrss_desc { + struct udevice *dev; + void __iomem *ddrss_ss_cfg; + void __iomem *ddrss_ctrl_mmr; + struct power_domain ddrcfg_pwrdmn; + struct power_domain ddrdata_pwrdmn; + struct clk ddr_clk; + struct clk osc_clk; + u32 ddr_freq1; + u32 ddr_freq2; + u32 ddr_fhs_cnt; + struct udevice *vtt_supply; +}; + +static lpddr4_obj *driverdt; +static lpddr4_config config; +static lpddr4_privatedata pd; + +static struct k3_ddrss_desc *ddrss; + +struct reginitdata { + u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT]; + u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT]; + u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT]; + u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT]; + u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT]; + u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT]; +}; + +#define TH_MACRO_EXP(fld, str) (fld##str) + +#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK) +#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT) +#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH) +#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR) +#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET) + +#define str(s) #s +#define xstr(s) str(s) + +#define CTL_SHIFT 11 +#define PHY_SHIFT 11 +#define PI_SHIFT 10 + +#define DENALI_CTL_0_DRAM_CLASS_DDR4 0xA +#define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xB + +#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\ + char *i, *pstr = xstr(REG); offset = 0;\ + for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\ + offset = offset * 10 + (*i - '0'); } \ + } while (0) + +static u32 k3_lpddr4_read_ddr_type(void) +{ + u32 status = 0U; + u32 offset = 0U; + u32 regval = 0U; + u32 dram_class = 0U; + + TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset); + status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); + if (status > 0U) { + printf("%s: Failed to read DRAM_CLASS\n", __func__); + hang(); + } + + dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >> + TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD)); + return dram_class; +} + +static void k3_lpddr4_freq_update(void) +{ + unsigned int req_type, counter; + + for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) { + if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, + true, 10000, false)) { + printf("Timeout during frequency handshake\n"); + hang(); + } + + req_type = readl(ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03; + + debug("%s: received freq change req: req type = %d, req no. = %d\n", + __func__, req_type, counter); + + if (req_type == 1) + clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); + else if (req_type == 2) + clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2); + else if (req_type == 0) + /* Put DDR pll in bypass mode */ + clk_set_rate(&ddrss->ddr_clk, + clk_get_rate(&ddrss->osc_clk)); + else + printf("%s: Invalid freq request type\n", __func__); + + writel(0x1, ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); + if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, + false, 10, false)) { + printf("Timeout during frequency handshake\n"); + hang(); + } + writel(0x0, ddrss->ddrss_ctrl_mmr + + CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); + } +} + +static void k3_lpddr4_ack_freq_upd_req(void) +{ + u32 dram_class; + + debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); + + dram_class = k3_lpddr4_read_ddr_type(); + + switch (dram_class) { + case DENALI_CTL_0_DRAM_CLASS_DDR4: + break; + case DENALI_CTL_0_DRAM_CLASS_LPDDR4: + k3_lpddr4_freq_update(); + break; + default: + printf("Unrecognized dram_class cannot update frequency!\n"); + } +} + +static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) +{ + u32 dram_class; + int ret; + + dram_class = k3_lpddr4_read_ddr_type(); + + switch (dram_class) { + case DENALI_CTL_0_DRAM_CLASS_DDR4: + /* Set to ddr_freq1 from DT for DDR4 */ + ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); + break; + case DENALI_CTL_0_DRAM_CLASS_LPDDR4: + /* Set to bypass frequency for LPDDR4*/ + ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk)); + break; + default: + ret = -EINVAL; + printf("Unrecognized dram_class cannot init frequency!\n"); + } + + if (ret < 0) + dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret); + else + ret = 0; + + return ret; +} + +static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd, + lpddr4_infotype infotype) +{ + if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) + k3_lpddr4_ack_freq_upd_req(); +} + +static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss) +{ + int ret; + + debug("%s(ddrss=%p)\n", __func__, ddrss); + + ret = power_domain_on(&ddrss->ddrcfg_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = power_domain_on(&ddrss->ddrdata_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = device_get_supply_regulator(ddrss->dev, "vtt-supply", + &ddrss->vtt_supply); + if (ret) { + dev_dbg(ddrss->dev, "vtt-supply not found.\n"); + } else { + ret = regulator_set_value(ddrss->vtt_supply, 3300000); + if (ret) + return ret; + dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n", + regulator_get_value(ddrss->vtt_supply)); + } + + return 0; +} + +static int k3_ddrss_ofdata_to_priv(struct udevice *dev) +{ + struct k3_ddrss_desc *ddrss = dev_get_priv(dev); + phys_addr_t reg; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + reg = dev_read_addr_name(dev, "cfg"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for DDRSS wrapper logic\n"); + return -EINVAL; + } + ddrss->ddrss_ss_cfg = (void *)reg; + + reg = dev_read_addr_name(dev, "ctrl_mmr_lp4"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for CTRL MMR\n"); + return -EINVAL; + } + ddrss->ddrss_ctrl_mmr = (void *)reg; + + ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk); + if (ret) + dev_err(dev, "clk get failed%d\n", ret); + + ret = clk_get_by_index(dev, 1, &ddrss->osc_clk); + if (ret) + dev_err(dev, "clk get failed for osc clk %d\n", ret); + + ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1); + if (ret) + dev_err(dev, "ddr freq1 not populated %d\n", ret); + + ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2); + if (ret) + dev_err(dev, "ddr freq2 not populated %d\n", ret); + + ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt); + if (ret) + dev_err(dev, "ddr fhs cnt not populated %d\n", ret); + + return ret; +} + +void k3_lpddr4_probe(void) +{ + u32 status = 0U; + u16 configsize = 0U; + + status = driverdt->probe(&config, &configsize); + + if ((status != 0) || (configsize != sizeof(lpddr4_privatedata)) + || (configsize > SRAM_MAX)) { + printf("%s: FAIL\n", __func__); + hang(); + } else { + debug("%s: PASS\n", __func__); + } +} + +void k3_lpddr4_init(void) +{ + u32 status = 0U; + + if ((sizeof(pd) != sizeof(lpddr4_privatedata)) + || (sizeof(pd) > SRAM_MAX)) { + printf("%s: FAIL\n", __func__); + hang(); + } + + config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg; + config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler; + + status = driverdt->init(&pd, &config); + + if ((status > 0U) || + (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) || + (pd.ctlinterrupthandler != config.ctlinterrupthandler) || + (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) { + printf("%s: FAIL\n", __func__); + hang(); + } else { + debug("%s: PASS\n", __func__); + } +} + +void populate_data_array_from_dt(struct reginitdata *reginit_data) +{ + int ret, i; + + ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data", + (u32 *)reginit_data->ctl_regs, + LPDDR4_INTR_CTL_REG_COUNT); + if (ret) + printf("Error reading ctrl data %d\n", ret); + + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) + reginit_data->ctl_regs_offs[i] = i; + + ret = dev_read_u32_array(ddrss->dev, "ti,pi-data", + (u32 *)reginit_data->pi_regs, + LPDDR4_INTR_PHY_INDEP_REG_COUNT); + if (ret) + printf("Error reading PI data\n"); + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + reginit_data->pi_regs_offs[i] = i; + + ret = dev_read_u32_array(ddrss->dev, "ti,phy-data", + (u32 *)reginit_data->phy_regs, + LPDDR4_INTR_PHY_REG_COUNT); + if (ret) + printf("Error reading PHY data %d\n", ret); + + for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++) + reginit_data->phy_regs_offs[i] = i; +} + +void k3_lpddr4_hardware_reg_init(void) +{ + u32 status = 0U; + struct reginitdata reginitdata; + + populate_data_array_from_dt(®initdata); + + status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs, + reginitdata.ctl_regs_offs, + LPDDR4_INTR_CTL_REG_COUNT); + if (!status) + status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs, + reginitdata.pi_regs_offs, + LPDDR4_INTR_PHY_INDEP_REG_COUNT); + if (!status) + status = driverdt->writephyconfig(&pd, reginitdata.phy_regs, + reginitdata.phy_regs_offs, + LPDDR4_INTR_PHY_REG_COUNT); + if (status) { + printf("%s: FAIL\n", __func__); + hang(); + } +} + +void k3_lpddr4_start(void) +{ + u32 status = 0U; + u32 regval = 0U; + u32 offset = 0U; + + TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset); + + status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); + if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) { + printf("%s: Pre start FAIL\n", __func__); + hang(); + } + + status = driverdt->start(&pd); + if (status > 0U) { + printf("%s: FAIL\n", __func__); + hang(); + } + + status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val); + if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) { + printf("%s: Post start FAIL\n", __func__); + hang(); + } else { + debug("%s: Post start PASS\n", __func__); + } +} + +static int k3_ddrss_probe(struct udevice *dev) +{ + int ret; + + ddrss = dev_get_priv(dev); + + debug("%s(dev=%p)\n", __func__, dev); + + ret = k3_ddrss_ofdata_to_priv(dev); + if (ret) + return ret; + + ddrss->dev = dev; + ret = k3_ddrss_power_on(ddrss); + if (ret) + return ret; + +#ifdef CONFIG_K3_AM64_DDRSS + + writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG); + writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); +#endif + + driverdt = lpddr4_getinstance(); + k3_lpddr4_probe(); + k3_lpddr4_init(); + k3_lpddr4_hardware_reg_init(); + + ret = k3_ddrss_init_freq(ddrss); + if (ret) + return ret; + + k3_lpddr4_start(); + + return ret; +} + +static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) +{ + return 0; +} + +static struct ram_ops k3_ddrss_ops = { + .get_info = k3_ddrss_get_info, +}; + +static const struct udevice_id k3_ddrss_ids[] = { + {.compatible = "ti,am64-ddrss"}, + {.compatible = "ti,j721e-ddrss"}, + {} +}; + +U_BOOT_DRIVER(k3_ddrss) = { + .name = "k3_ddrss", + .id = UCLASS_RAM, + .of_match = k3_ddrss_ids, + .ops = &k3_ddrss_ops, + .probe = k3_ddrss_probe, + .priv_auto = sizeof(struct k3_ddrss_desc), +}; diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4.c b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4.c new file mode 100644 index 000000000..78ad966a1 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4.c @@ -0,0 +1,1079 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +#include "cps_drv_lpddr4.h" +#include "lpddr4_if.h" +#include "lpddr4.h" +#include "lpddr4_structs_if.h" + +#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY +#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U +#endif + +#ifndef LPDDR4_CPS_NS_DELAY_TIME +#define LPDDR4_CPS_NS_DELAY_TIME 10000000U +#endif + +static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay); +static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd); +static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd); +static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval); +static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); +static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); +static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); +static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); +static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits); +static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound); +static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound); +static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles); +static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles); +static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles); +static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles); +static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles); +static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles); +static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles); +static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles); +static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles); +static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles); +static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles); +static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles); +static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles); +static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles); +static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles); +static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles); +static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max); +static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max); +static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max); +#ifdef REG_WRITE_VERIF +static u32 lpddr4_getphyrwmask(u32 regoffset); +static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue); +#endif + +u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay) +{ + u32 result = 0U; + u32 timeout = 0U; + bool irqstatus = false; + + do { + if (++timeout == delay) { + result = (u32)EIO; + break; + } + result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus); + } while ((irqstatus == (bool)false) && (result == (u32)0)); + + return result; +} + +static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay) +{ + u32 result = 0U; + u32 timeout = 0U; + bool irqstatus = false; + + do { + if (++timeout == delay) { + result = (u32)EIO; + break; + } + result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus); + } while ((irqstatus == (bool)false) && (result == (u32)0)); + + return result; +} + +static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd) +{ + u32 result = 0U; + + result = lpddr4_pollphyindepirq(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT, LPDDR4_CUSTOM_TIMEOUT_DELAY); + + if (result == (u32)0) + result = lpddr4_ackphyindepinterrupt(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT); + if (result == (u32)0) + result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MC_INIT_DONE, LPDDR4_CUSTOM_TIMEOUT_DELAY); + if (result == (u32)0) + result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MC_INIT_DONE); + return result; +} + +static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd) +{ + u32 result = 0U; + u32 regval = 0U; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + lpddr4_infotype infotype; + + regval = CPS_FLD_SET(LPDDR4__PI_START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG))); + CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval); + + regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG))); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval); + + if (pd->infohandler != (lpddr4_infocallback)NULL) { + infotype = LPDDR4_DRV_SOC_PLL_UPDATE; + pd->infohandler(pd, infotype); + } + + result = lpddr4_pollandackirq(pd); + + return result; +} + +volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset) +{ + volatile u32 *local_addr = addr; + volatile u32 *regaddr = &local_addr[regoffset]; + + return regaddr; +} + +u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize) +{ + u32 result; + + result = (u32)(lpddr4_probesf(config, configsize)); + if (result == (u32)0) + *configsize = (u16)(sizeof(lpddr4_privatedata)); + return result; +} + +u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg) +{ + u32 result = 0U; + + result = lpddr4_initsf(pd, cfg); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)cfg->ctlbase; + pd->ctlbase = ctlregbase; + pd->infohandler = (lpddr4_infocallback)cfg->infohandler; + pd->ctlinterrupthandler = (lpddr4_ctlcallback)cfg->ctlinterrupthandler; + pd->phyindepinterrupthandler = (lpddr4_phyindepcallback)cfg->phyindepinterrupthandler; + } + return result; +} + +u32 lpddr4_start(const lpddr4_privatedata *pd) +{ + u32 result = 0U; + + result = lpddr4_startsf(pd); + if (result == (u32)0) { + result = lpddr4_enablepiinitiator(pd); + result = lpddr4_startsequencecontroller(pd); + } + return result; +} + +u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue) +{ + u32 result = 0U; + + result = lpddr4_readregsf(pd, cpp, regvalue); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + if (cpp == LPDDR4_CTL_REGS) { + if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT) + result = (u32)EINVAL; + else + *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset)); + } else if (cpp == LPDDR4_PHY_REGS) { + if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT) + result = (u32)EINVAL; + else + *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset)); + + } else { + if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT) + result = (u32)EINVAL; + else + *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset)); + } + } + return result; +} + +#ifdef REG_WRITE_VERIF + +static u32 lpddr4_getphyrwmask(u32 regoffset) +{ + u32 rwmask = 0U; + u32 arrayoffset = 0U; + u32 slicenum, sliceoffset = 0U; + + for (slicenum = (u32)0U; slicenum <= (DSLICE_NUM + ASLICE_NUM); slicenum++) { + sliceoffset = sliceoffset + (u32)SLICE_WIDTH; + if (regoffset < sliceoffset) + break; + } + arrayoffset = regoffset - (sliceoffset - (u32)SLICE_WIDTH); + + if (slicenum < DSLICE_NUM) { + rwmask = lpddr4_getdslicemask(slicenum, arrayoffset); + } else { + if (slicenum == DSLICE_NUM) { + if (arrayoffset < ASLICE0_REG_COUNT) + rwmask = g_lpddr4_address_slice_0_rw_mask[arrayoffset]; + } else { + if (arrayoffset < PHY_CORE_REG_COUNT) + rwmask = g_lpddr4_phy_core_rw_mask[arrayoffset]; + } + } + return rwmask; +} + +static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue) +{ + u32 result = (u32)0; + u32 regreadval = 0U; + u32 rwmask = 0U; + + result = lpddr4_readreg(pd, cpp, regoffset, ®readval); + + if (result == (u32)0) { + switch (cpp) { + case LPDDR4_PHY_INDEP_REGS: + rwmask = g_lpddr4_pi_rw_mask[regoffset]; + break; + case LPDDR4_PHY_REGS: + rwmask = lpddr4_getphyrwmask(regoffset); + break; + default: + rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset]; + break; + } + + if ((rwmask & regreadval) != (regvalue & rwmask)) + result = EIO; + } + return result; +} +#endif + +u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue) +{ + u32 result = 0U; + + result = lpddr4_writeregsf(pd, cpp); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + if (cpp == LPDDR4_CTL_REGS) { + if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT) + result = (u32)EINVAL; + else + CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset), regvalue); + } else if (cpp == LPDDR4_PHY_REGS) { + if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT) + result = (u32)EINVAL; + else + CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset), regvalue); + } else { + if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT) + result = (u32)EINVAL; + else + CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue); + } + } +#ifdef REG_WRITE_VERIF + if (result == (u32)0) + result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue); + +#endif + + return result; +} + +u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus) +{ + u32 result = 0U; + u32 tdelay = 1000U; + u32 regval = 0U; + + result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__READ_MODEREG__REG)), readmoderegval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval); + + result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_READ_DONE, tdelay); + } + if (result == (u32)0) + result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus); + return result; +} + +static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval) +{ + u32 result = (u32)0; + u32 tdelay = 1000U; + u32 regval = 0U; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG)), writemoderegval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval); + + result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_WRITE_DONE, tdelay); + + return result; +} + +u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus) +{ + u32 result = 0U; + + result = lpddr4_setmmrregistersf(pd, mrwstatus); + if (result == (u32)0) { + result = lpddr4_writemmrregister(pd, writemoderegval); + + if (result == (u32)0) + result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_WRITE_DONE); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + *mrwstatus = (u8)CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRW_STATUS__REG))); + if ((*mrwstatus) != 0U) + result = (u32)EIO; + } + } + +#ifdef ASILC +#endif + + return result; +} + +u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount) +{ + u32 result; + u32 aindex; + + result = lpddr4_writectlconfigsf(pd); + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL)) + result = EINVAL; + + if (result == (u32)0) { + for (aindex = 0; aindex < regcount; aindex++) + result = (u32)lpddr4_writereg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex], + (u32)regvalues[aindex]); + } + return result; +} + +u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount) +{ + u32 result; + u32 aindex; + + result = lpddr4_writephyindepconfigsf(pd); + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL)) + result = EINVAL; + if (result == (u32)0) { + for (aindex = 0; aindex < regcount; aindex++) + result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex], + (u32)regvalues[aindex]); + } + return result; +} + +u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount) +{ + u32 result; + u32 aindex; + + result = lpddr4_writephyconfigsf(pd); + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL)) + result = EINVAL; + if (result == (u32)0) { + for (aindex = 0; aindex < regcount; aindex++) + result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex], + (u32)regvalues[aindex]); + } + return result; +} + +u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount) +{ + u32 result; + u32 aindex; + + result = lpddr4_readctlconfigsf(pd); + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL)) + result = EINVAL; + if (result == (u32)0) { + for (aindex = 0; aindex < regcount; aindex++) + result = (u32)lpddr4_readreg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex], + (u32 *)(®values[aindex])); + } + return result; +} + +u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount) +{ + u32 result; + u32 aindex; + + result = lpddr4_readphyindepconfigsf(pd); + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL)) + result = EINVAL; + if (result == (u32)0) { + for (aindex = 0; aindex < regcount; aindex++) + result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex], + (u32 *)(®values[aindex])); + } + return result; +} + +u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount) +{ + u32 result; + u32 aindex; + + result = lpddr4_readphyconfigsf(pd); + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL)) + result = EINVAL; + if (result == (u32)0) { + for (aindex = 0; aindex < regcount; aindex++) + result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex], + (u32 *)(®values[aindex])); + } + return result; +} + +u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask) +{ + u32 result; + + result = lpddr4_getphyindepinterruptmsf(pd, mask); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + *mask = CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG))); + } + return result; +} + +u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask) +{ + u32 result; + u32 regval = 0; + const u32 ui32irqcount = (u32)LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U; + + result = lpddr4_setphyindepinterruptmsf(pd, mask); + if ((result == (u32)0) && (ui32irqcount < WORD_SHIFT)) { + if (*mask >= (1U << ui32irqcount)) + result = (u32)EINVAL; + } + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)), *mask); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval); + } + return result; +} + +u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus) +{ + u32 result = 0; + u32 phyindepirqstatus = 0; + + result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus); + if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG)); + *irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U); + } + return result; +} + +u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr) +{ + u32 result = 0U; + u32 regval = 0U; + + result = LPDDR4_INTR_AckPhyIndepIntSF(pd, intr); + if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = ((u32)LPDDR4_BIT_MASK << (u32)intr); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval); + } + + return result; +} + +static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr) +{ + u32 regval; + u32 errbitmask = 0U; + u32 snum; + volatile u32 *regaddress; + + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG)); + errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK); + for (snum = 0U; snum < ASLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != CA_TRAIN_RL) { + debuginfo->catraingerror = CDN_TRUE; + *errfoundptr = true; + } + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } +} + +static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr) +{ + u32 regval; + u32 errbitmask = 0U; + u32 snum; + volatile u32 *regaddress; + + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG)); + errbitmask = GATE_LVL_ERROR_FIELDS; + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->gatelvlerror = CDN_TRUE; + *errfoundptr = true; + } + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } +} + +static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr) +{ + u32 regval; + u32 errbitmask = 0U; + u32 snum; + volatile u32 *regaddress; + + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG)); + errbitmask = READ_LVL_ERROR_FIELDS; + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->readlvlerror = CDN_TRUE; + *errfoundptr = true; + } + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } +} + +static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr) +{ + u32 regval; + u32 errbitmask = 0U; + u32 snum; + volatile u32 *regaddress; + + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG)); + errbitmask = DQ_LVL_STATUS; + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->dqtrainingerror = CDN_TRUE; + *errfoundptr = true; + } + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } +} + +bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound) +{ + bool localerrfound = errfound; + + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + if (localerrfound == (bool)false) + lpddr4_checkcatrainingerror(ctlregbase, debuginfo, &localerrfound); + + if (localerrfound == (bool)false) + lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound); + + if (localerrfound == (bool)false) + lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound); + + if (localerrfound == (bool)false) + lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound); + + if (localerrfound == (bool)false) + lpddr4_checkdqtrainingerror(ctlregbase, debuginfo, &localerrfound); + return localerrfound; +} + +static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits) +{ + u32 regval = 0U; + + regval = CPS_REG_READ(reg); + if ((regval & errbitmask) != errorinfobits) + *errfoundptr = CDN_TRUE; + return *errfoundptr; +} + +void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr) +{ + u32 errbitmask = (LPDDR4_BIT_MASK << 0x1U) | (LPDDR4_BIT_MASK); + + debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG), + errbitmask, errfoundptr, PLL_READY); + if (*errfoundptr == CDN_FALSE) + debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG), + errbitmask, errfoundptr, PLL_READY); + + if (*errfoundptr == CDN_FALSE) + debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT_OBS_0__REG), + IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE); + if (*errfoundptr == CDN_FALSE) + debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT2_OBS_0__REG), + IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE); + if (*errfoundptr == CDN_FALSE) + debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT3_OBS_0__REG), + IO_CALIB_FIELD, errfoundptr, IO_CALIB_STATE); +} + +static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound) +{ + u32 snum = 0U; + volatile u32 *regaddress; + u32 regval = 0U; + + if (errorfound == (bool)false) { + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG)); + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) { + regval = CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress)); + CPS_REG_WRITE(regaddress, regval); + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } + } +} + +static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound) +{ + u32 snum = 0U; + volatile u32 *regaddress; + u32 regval = 0U; + + if (errorfound == (bool)false) { + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG)); + for (snum = (u32)0U; snum < ASLICE_NUM; snum++) { + regval = CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress)); + CPS_REG_WRITE(regaddress, regval); + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } + } +} + +void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound) +{ + lpddr4_setphysnapsettings(ctlregbase, errorfound); + lpddr4_setphyadrsnapsettings(ctlregbase, errorfound); +} + +static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles) +{ + if (*fspnum == LPDDR4_FSP_0) + *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG))); + else if (*fspnum == LPDDR4_FSP_1) + *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG))); + else + *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG))); +} + +static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles) +{ + if (*fspnum == LPDDR4_FSP_0) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG))); + else if (*fspnum == LPDDR4_FSP_1) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG))); + else + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG))); +} + +static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles) +{ + if (*fspnum == LPDDR4_FSP_0) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG))); + else if (*fspnum == LPDDR4_FSP_1) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG))); + else + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG))); +} + +static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles) +{ + if (*fspnum == LPDDR4_FSP_0) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG))); + else if (*fspnum == LPDDR4_FSP_1) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG))); + else + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG))); +} + +static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles) +{ + if (*fspnum == LPDDR4_FSP_0) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG))); + else if (*fspnum == LPDDR4_FSP_1) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG))); + else + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG))); +} + +static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles) +{ + if (*fspnum == LPDDR4_FSP_0) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG))); + else if (*fspnum == LPDDR4_FSP_1) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG))); + else + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG))); +} + +static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles) +{ + if (*fspnum == LPDDR4_FSP_0) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG))); + else if (*fspnum == LPDDR4_FSP_1) + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG))); + else + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG))); + +} + +static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles) +{ + if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) + readpdwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) + readsrshortwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) + readsrlongwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) + readsrlonggatewakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) + readsrdpshortwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) + readsrdplongwakeup(fspnum, ctlregbase, cycles); + else + readsrdplonggatewakeup(fspnum, ctlregbase, cycles); +} + +u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles) +{ + u32 result = 0U; + + result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles); + } + return result; +} + +static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles) +{ + u32 regval = 0U; + + if (*fspnum == LPDDR4_FSP_0) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), regval); + } else { + regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), regval); + } +} + +static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles) +{ + u32 regval = 0U; + + if (*fspnum == LPDDR4_FSP_0) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG), regval); + } else { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG), regval); + } +} + +static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles) +{ + u32 regval = 0U; + + if (*fspnum == LPDDR4_FSP_0) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), regval); + } else { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), regval); + } +} + +static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles) +{ + u32 regval = 0U; + + if (*fspnum == LPDDR4_FSP_0) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval); + } else { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval); + } +} + +static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles) +{ + u32 regval = 0U; + + if (*fspnum == LPDDR4_FSP_0) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval); + } else { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval); + } +} + +static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles) +{ + u32 regval = 0U; + + if (*fspnum == LPDDR4_FSP_0) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval); + } else { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval); + } +} +static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles) +{ + u32 regval = 0U; + + if (*fspnum == LPDDR4_FSP_0) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval); + } else if (*fspnum == LPDDR4_FSP_1) { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval); + } else { + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval); + } +} + +static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles) +{ + if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) + writepdwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) + writesrshortwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) + writesrlongwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) + writesrlonggatewakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) + writesrdpshortwakeup(fspnum, ctlregbase, cycles); + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) + writesrdplongwakeup(fspnum, ctlregbase, cycles); + else + writesrdplonggatewakeup(fspnum, ctlregbase, cycles); +} + +u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles) +{ + u32 result = 0U; + + result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles); + if (result == (u32)0) { + if (*cycles > NIBBLE_MASK) + result = (u32)EINVAL; + } + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles); + } + return result; +} + +u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off) +{ + u32 result = 0U; + + result = lpddr4_getdbireadmodesf(pd, on_off); + + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + if (CPS_FLD_READ(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) == 0U) + *on_off = false; + else + *on_off = true; + } + return result; +} + +u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off) +{ + u32 result = 0U; + + result = lpddr4_getdbireadmodesf(pd, on_off); + + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + if (CPS_FLD_READ(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) == 0U) + *on_off = false; + else + *on_off = true; + } + return result; +} + +u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode) +{ + u32 result = 0U; + u32 regval = 0U; + + result = lpddr4_setdbimodesf(pd, mode); + + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + if (*mode == LPDDR4_DBI_RD_ON) + regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 1U); + else if (*mode == LPDDR4_DBI_RD_OFF) + regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 0U); + else if (*mode == LPDDR4_DBI_WR_ON) + regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 1U); + else + regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 0U); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval); + } + return result; +} + +u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max) +{ + u32 result = 0U; + + result = lpddr4_getrefreshratesf(pd, fspnum, tref, tras_max); + + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + switch (*fspnum) { + case LPDDR4_FSP_2: + *tref = CPS_FLD_READ(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG))); + *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG))); + break; + case LPDDR4_FSP_1: + *tref = CPS_FLD_READ(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG))); + *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG))); + break; + default: + *tref = CPS_FLD_READ(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG))); + *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG))); + break; + } + } + return result; +} + +static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max) +{ + u32 regval = 0U; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)), *tref); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), regval); + regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)), *tras_max); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG), regval); +} + +static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max) +{ + u32 regval = 0U; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)), *tref); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), regval); + regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)), *tras_max); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG), regval);; +} + +static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max) +{ + u32 regval = 0U; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)), *tref); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), regval); + regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)), *tras_max); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG), regval); +} + +u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max) +{ + u32 result = 0U; + + result = lpddr4_setrefreshratesf(pd, fspnum, tref, tras_max); + + if (result == (u32)0) { + switch (*fspnum) { + case LPDDR4_FSP_2: + lpddr4_updatefsp2refrateparams(pd, tref, tras_max); + break; + case LPDDR4_FSP_1: + lpddr4_updatefsp1refrateparams(pd, tref, tras_max); + break; + default: + lpddr4_updatefsp0refrateparams(pd, tref, tras_max); + break; + } + } + return result; +} + +u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval) +{ + u32 result = 0U; + u32 regval = 0U; + + result = lpddr4_refreshperchipselectsf(pd); + + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + regval = CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG)), trefinterval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), regval); + } + return result; +} diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4.h new file mode 100644 index 000000000..5b77ea9e6 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_H +#define LPDDR4_H + +#include "lpddr4_ctl_regs.h" +#include "lpddr4_sanity.h" +#ifdef CONFIG_K3_AM64_DDRSS +#include "lpddr4_16bit.h" +#include "lpddr4_16bit_sanity.h" +#else +#include "lpddr4_32bit.h" +#include "lpddr4_32bit_sanity.h" +#endif + +#ifdef REG_WRITE_VERIF +#include "lpddr4_ctl_regs_rw_masks.h" +#endif +#ifdef __cplusplus +extern "C" { +#endif + +#define PRODUCT_ID (0x1046U) + +#define LPDDR4_BIT_MASK (0x1U) +#define BYTE_MASK (0xffU) +#define NIBBLE_MASK (0xfU) + +#define WORD_SHIFT (32U) +#define WORD_MASK (0xffffffffU) +#define SLICE_WIDTH (0x100) + +#define CTL_OFFSET 0 +#define PI_OFFSET (((u32)1) << 11) +#define PHY_OFFSET (((u32)1) << 12) + +#define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT) + +#define PLL_READY (0x3U) +#define IO_CALIB_DONE ((u32)0x1U << 23U) +#define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U) +#define IO_CALIB_STATE ((u32)0xBU << 28U) +#define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U) +#define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U)) +#define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U) +#define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U)) +#define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U)) +#define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U)) + +#define CDN_TRUE 1U +#define CDN_FALSE 0U + +void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound); +volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset); +u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay); +bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound); +void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr); + +u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd); +void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); +u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus); +u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset); +#ifdef __cplusplus +} +#endif + +#endif /* LPDDR4_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.c b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.c new file mode 100644 index 000000000..b749b7489 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.c @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +#include "cps_drv_lpddr4.h" +#include "lpddr4_ctl_regs.h" +#include "lpddr4_if.h" +#include "lpddr4.h" +#include "lpddr4_structs_if.h" + +static u32 ctlintmap[51][3] = { + { 0, 0, 7 }, + { 1, 0, 8 }, + { 2, 0, 9 }, + { 3, 0, 14 }, + { 4, 0, 15 }, + { 5, 0, 16 }, + { 6, 0, 17 }, + { 7, 0, 19 }, + { 8, 1, 0 }, + { 9, 2, 0 }, + { 10, 2, 3 }, + { 11, 3, 0 }, + { 12, 4, 0 }, + { 13, 5, 11 }, + { 14, 5, 12 }, + { 15, 5, 13 }, + { 16, 5, 14 }, + { 17, 5, 15 }, + { 18, 6, 0 }, + { 19, 6, 1 }, + { 20, 6, 2 }, + { 21, 6, 6 }, + { 22, 6, 7 }, + { 23, 7, 3 }, + { 24, 7, 4 }, + { 25, 7, 5 }, + { 26, 7, 6 }, + { 27, 7, 7 }, + { 28, 8, 0 }, + { 29, 9, 0 }, + { 30, 10, 0 }, + { 31, 10, 1 }, + { 32, 10, 2 }, + { 33, 10, 3 }, + { 34, 10, 4 }, + { 35, 10, 5 }, + { 36, 11, 0 }, + { 37, 12, 0 }, + { 38, 12, 1 }, + { 39, 12, 2 }, + { 40, 12, 3 }, + { 41, 12, 4 }, + { 42, 12, 5 }, + { 43, 13, 0 }, + { 44, 13, 1 }, + { 45, 13, 3 }, + { 46, 14, 0 }, + { 47, 14, 2 }, + { 48, 14, 3 }, + { 49, 15, 2 }, + { 50, 16, 0 }, +}; + +static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag); +static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag); +static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag); +static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr); +static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr); +static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr); + +u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd) +{ + u32 result = 0U; + u32 regval = 0U; + + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG))); + CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval); + regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG))); + CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval); + return result; +} + +u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask) +{ + u32 result = 0U; + + result = lpddr4_getctlinterruptmasksf(pd, mask); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + *mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)))); + } + return result; +} + +u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask) +{ + u32 result; + u32 regval = 0; + const u64 ui64one = 1ULL; + const u32 ui32irqcount = (u32)32U; + + result = lpddr4_setctlinterruptmasksf(pd, mask); + if ((result == (u32)0) && (ui32irqcount < 64U)) { + if (*mask >= (ui64one << ui32irqcount)) + result = (u32)EINVAL; + } + + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)), *mask); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval); + } + return result; +} + +static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, + u32 *ctlgrpirqstatus, u32 *ctlmasterintflag) +{ + if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE)) + *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_INIT__REG))); + else if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE)) + *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG)); + else if (intr == LPDDR4_INTR_BIST_DONE) + *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_BIST__REG))); + else if (intr == LPDDR4_INTR_PARITY_ERROR) + *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_PARITY__REG))); + else + *ctlmasterintflag = (u32)1U; +} + +static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, + u32 *ctlgrpirqstatus, u32 *ctlmasterintflag) +{ + if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE)) + *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_FREQ__REG))); + else if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT)) + *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_LOWPOWER__REG))); + else + lpddr4_checkctlinterrupt_4(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag); +} + +static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, + u32 *ctlgrpirqstatus, u32 *ctlmasterintflag) +{ + if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) + *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG)); + else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT)) + *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG)); + else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING)) + *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG)); + else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS)) + *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_MISC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MISC__REG))); + else if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT)) + *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_DFI__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_DFI__REG))); + else + lpddr4_checkctlinterrupt_3(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag); +} + +u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus) +{ + u32 result; + u32 ctlmasterirqstatus = 0U; + u32 ctlgrpirqstatus = 0U; + u32 ctlmasterintflag = 0U; + + result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 31))); + + lpddr4_checkctlinterrupt_2(ctlregbase, intr, &ctlgrpirqstatus, &ctlmasterintflag); + + if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) { + if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) && + (((ctlgrpirqstatus >> ctlintmap[intr][INT_SHIFT]) & LPDDR4_BIT_MASK) > 0U) && + (ctlmasterintflag == (u32)0)) + *irqstatus = true; + else if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) && + (ctlmasterintflag == (u32)1U)) + *irqstatus = true; + else + *irqstatus = false; + } + } + return result; +} + +static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr) +{ + u32 regval = 0; + + if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]); + } else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG)), + (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval); + } else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG)), + (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval); + } else { + } +} + +static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr) +{ + u32 regval = 0; + + if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG)), + (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval); + } else if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG)), + (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval); + } else { + lpddr4_ackctlinterrupt_4(ctlregbase, intr); + } +} + +static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr) +{ + u32 regval = 0; + + if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_DFI__REG), (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + } else if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG)), + (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval); + } else { + lpddr4_ackctlinterrupt_3(ctlregbase, intr); + } +} + +u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr) +{ + u32 result; + + result = LPDDR4_INTR_AckCtlIntSF(pd, intr); + if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TIMEOUT__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT)) + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TRAINING__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING)) + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_USERIF__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS)) + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT])); + else + lpddr4_ackctlinterrupt_2(ctlregbase, intr); + } + + return result; +} + +void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr) +{ + u32 regval; + u32 errbitmask = 0U; + u32 snum; + volatile u32 *regaddress; + + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG)); + errbitmask = ((u32)LPDDR4_BIT_MASK << (u32)12U); + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->wrlvlerror = CDN_TRUE; + *errfoundptr = true; + } + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } +} + +u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo) +{ + u32 result = 0U; + bool errorfound = false; + + result = lpddr4_getdebuginitinfosf(pd, debuginfo); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound); + lpddr4_setsettings(ctlregbase, errorfound); + errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound); + } + + if (errorfound == (bool)true) + result = (u32)EPROTO; + + return result; +} + +u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode) +{ + u32 result = 0U; + + result = lpddr4_getreducmodesf(pd, mode); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + if (CPS_FLD_READ(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG))) == 0U) + *mode = LPDDR4_REDUC_ON; + else + *mode = LPDDR4_REDUC_OFF; + } + return result; +} + +u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode) +{ + u32 result = 0U; + u32 regval = 0U; + + result = lpddr4_setreducmodesf(pd, mode); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + regval = (u32)CPS_FLD_WRITE(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG)), *mode); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG), regval); + } + return result; +} + +u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus) +{ + u32 lowerdata; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + u32 result = (u32)0; + + if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) { + *mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG))); + *mmrvalue = (u64)0; + result = (u32)EIO; + } else { + *mrrstatus = (u8)0; + lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG)); + *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata); + result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE); + } + return result; +} + +#ifdef REG_WRITE_VERIF + +u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset) +{ + u32 rwmask = 0U; + + switch (dslicenum) { + case 0: + if (arrayoffset < DSLICE0_REG_COUNT) + rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset]; + break; + default: + if (arrayoffset < DSLICE1_REG_COUNT) + rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset]; + break; + } + return rwmask; +} +#endif + +u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam) +{ + u32 result = 0U; + + result = lpddr4_geteccenablesf(pd, eccparam); + if (result == (u32)0) { + *eccparam = LPDDR4_ECC_DISABLED; + result = (u32)EOPNOTSUPP; + } + + return result; +} +u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam) +{ + u32 result = 0U; + + result = lpddr4_seteccenablesf(pd, eccparam); + if (result == (u32)0) + result = (u32)EOPNOTSUPP; + + return result; +} diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.h new file mode 100644 index 000000000..d663389e6 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_16BIT_H +#define LPDDR4_16BIT_H + +#define DSLICE_NUM (2U) +#define ASLICE_NUM (3U) + +#ifdef __cplusplus +extern "C" { +#endif + +#define DSLICE0_REG_COUNT (126U) +#define DSLICE1_REG_COUNT (126U) +#define ASLICE0_REG_COUNT (42U) +#define ASLICE1_REG_COUNT (42U) +#define ASLICE2_REG_COUNT (42U) +#define PHY_CORE_REG_COUNT (126U) + +#define GRP_SHIFT 1 +#define INT_SHIFT 2 + +#ifdef __cplusplus +} +#endif + +#endif /* LPDDR4_16BIT_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c new file mode 100644 index 000000000..09b0e3c5a --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c @@ -0,0 +1,1309 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "lpddr4_ctl_regs_rw_masks.h" + +u32 g_lpddr4_ddr_controller_rw_mask[] = { + 0x00000F01U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x01FFFFFFU, + 0x03030300U, + 0x01030100U, + 0x1F1F013FU, + 0x0303031FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0xFFFFFF01U, + 0x0001FFFFU, + 0x000F7FFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF00FFFFU, + 0x0000FFFFU, + 0x00000000U, + 0x00000000U, + 0x0F3F7F7FU, + 0xFFFFFFFFU, + 0x0F3F7F7FU, + 0xFFFFFFFFU, + 0x0F3F7F7FU, + 0xFFFFFFFFU, + 0xFF1F1F07U, + 0x0001FFFFU, + 0x3F3F01FFU, + 0x1F01FFFFU, + 0x01FFFFFFU, + 0x3F3F01FFU, + 0x1F01FFFFU, + 0x01FFFFFFU, + 0x3F3F01FFU, + 0xFF01FFFFU, + 0x00FFFFFFU, + 0x1F0FFFFFU, + 0xFFFF3FFFU, + 0x0000FFFFU, + 0x1F0FFFFFU, + 0xFFFF3FFFU, + 0x0000FFFFU, + 0x1F0FFFFFU, + 0x07073FFFU, + 0xFFFF0107U, + 0xFFFFFFFFU, + 0x0101010FU, + 0x3FFFFFFFU, + 0xFFFFFFFFU, + 0x0301FFFFU, + 0x00010101U, + 0x03FFFFFFU, + 0x01000000U, + 0x03FF3F07U, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x010FFFFFU, + 0x0FFFFF01U, + 0x001F1F01U, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x00000000U, + 0x1FFFFFFFU, + 0x1F0F1F1FU, + 0x1F0F1F1FU, + 0x1F0F1F1FU, + 0x1F011F01U, + 0x00FFFF01U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x1F1F07FFU, + 0xFF1F1F1FU, + 0x1F1F1F07U, + 0x07FF1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x07010101U, + 0x00017F00U, + 0xFFFFFFFFU, + 0x0700FFFFU, + 0xFFFFFF07U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x010FFFFFU, + 0x00010100U, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x01FFFFFFU, + 0x0000FF00U, + 0x0001FFFFU, + 0x0F01FFFFU, + 0x00000001U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0100U, + 0xFFFFFFFFU, + 0x0F0F0003U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x00013F0FU, + 0x0FFF0FFFU, + 0x0F0F0007U, + 0x000FFF07U, + 0xFFFF0FFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x01010101U, + 0x0101FF01U, + 0x00000107U, + 0xFFFFFFFFU, + 0x00FFFF0FU, + 0x00000303U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x07FFFFFFU, + 0x01FFFF00U, + 0x00000000U, + 0x00030100U, + 0x03FF03FFU, + 0x1F1F03FFU, + 0x000FFFFFU, + 0x03FF03FFU, + 0x1F1F03FFU, + 0x000FFFFFU, + 0x03FF03FFU, + 0x1F1F03FFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x01FFFF01U, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x01FFFF00U, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x01FFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x01FFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0101FFFFU, + 0x00000101U, + 0x01010101U, + 0x03010101U, + 0x3F000003U, + 0x00000101U, + 0xFFFFFFFFU, + 0x00000001U, + 0xFFFFFFFFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x000FFF00U, + 0x1F000000U, + 0x1F1F1F1FU, + 0xFFFF070FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x000FFF00U, + 0x0FFF0FFFU, + 0x007F0FFFU, + 0x0FFF0FFFU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x037F0FFFU, + 0x0FFF0000U, + 0x0FFF0FFFU, + 0x03030101U, + 0x03030303U, + 0x0F0F0707U, + 0xFFFFFFFFU, + 0x00FFFF03U, + 0xFFFFFFFFU, + 0x03FFFF03U, + 0x1F011F01U, + 0x0101FFFFU, + 0x01010101U, + 0x03010101U, + 0x0301011FU, + 0x07010F03U, + 0x03030307U, + 0x03011F03U, + 0x01010000U, + 0x01030303U, + 0x00000101U, + 0x00010000U, + 0x00000000U, + 0xFFFFFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFF000000U, + 0x0FFF0F0FU, + 0x0F0FFF0FU, + 0x01010101U, + 0x033F3F3FU, + 0x3F030303U, + 0x1F1F3F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x0F1F1F1FU, + 0x0F070F07U, + 0x07010107U, + 0xFF000007U, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0xFFFF070FU, + 0x00FFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0xFFFF070FU, + 0x00FFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0xFFFF070FU, + 0xFFFFFFFFU, + 0x000300FFU, + 0x0F0FFFFFU, + 0x0701FF07U, + 0x07070707U, + 0x0F0F0F07U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0xFFFFFF0FU, + 0x007F7F7FU +}; + +u32 g_lpddr4_pi_rw_mask[] = { + 0x00000F01U, + 0x00000000U, + 0x00000000U, + 0x01000000U, + 0xFFFF0301U, + 0x030100FFU, + 0x00000101U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x0000011FU, + 0xFFFFFFFFU, + 0x01030101U, + 0x0F011F03U, + 0x0101070FU, + 0x000FFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000007U, + 0x00000000U, + 0x00000000U, + 0x01000000U, + 0x00010101U, + 0x3F3F0103U, + 0x0101FFFFU, + 0x01030103U, + 0x0000FF00U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x030F0F1FU, + 0x00000003U, + 0x03FFFFFFU, + 0x00000F07U, + 0x00000103U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0101010FU, + 0x01010101U, + 0x00030301U, + 0x000003FFU, + 0xFFFFFFFFU, + 0x0000FF03U, + 0xFFFFFFFFU, + 0x00FFFF00U, + 0x0F0FFFFFU, + 0x01011F1FU, + 0x03000000U, + 0x030F0101U, + 0x01010101U, + 0x0000FF03U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0001U, + 0x1F1F3F1FU, + 0xFF0F0F01U, + 0x017F1FFFU, + 0xFF01FFFFU, + 0x01010101U, + 0x030701FFU, + 0x1F1F0301U, + 0x01030001U, + 0x000000FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0101FFFFU, + 0x00030001U, + 0xFFFFFFFFU, + 0x00010101U, + 0x010003FFU, + 0x01010101U, + 0x1F070303U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x00000000U, + 0x00000000U, + 0x3FFFFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x011F3F00U, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x0101011FU, + 0x00FFFF01U, + 0x00000107U, + 0x000101FFU, + 0xFFFFFFFFU, + 0x0000FF01U, + 0xFFFFFFFFU, + 0x0FFF0000U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x03030703U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000003FU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x0101010FU, + 0x00010101U, + 0x01010101U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0101U, + 0x000000FFU, + 0x03FFFFFFU, + 0x00000100U, + 0x0001FFFFU, + 0x01000000U, + 0x01000003U, + 0x00010F07U, + 0x0F00010FU, + 0x010F0001U, + 0x00010F00U, + 0x0F00010FU, + 0x010F0001U, + 0x00000000U, + 0x00000000U, + 0x011F0000U, + 0x01010103U, + 0x01010101U, + 0x01010101U, + 0x01010101U, + 0x01010101U, + 0x00FF0101U, + 0x000001FFU, + 0x0000001FU, + 0x01031F01U, + 0x01010101U, + 0x00FFFF07U, + 0xFFFFFFFFU, + 0x00FFFFFFU, + 0x000000FFU, + 0x000000FFU, + 0x000FFFFFU, + 0x0FFF0FFFU, + 0xFF0F3F7FU, + 0x0F3F7F7FU, + 0x3F7F7FFFU, + 0x007FFF0FU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x0F0FFFFFU, + 0x03030F0FU, + 0x0003FF03U, + 0x03FF03FFU, + 0x01FF01FFU, + 0x0F0F01FFU, + 0x0F0F0F0FU, + 0x3F3F3F3FU, + 0x03033F3FU, + 0x03030303U, + 0x03FFFFFFU, + 0x03030303U, + 0x03030303U, + 0xFF030303U, + 0xFFFFFFFFU, + 0x070707FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F030303U, + 0x001F3FFFU, + 0x001F3FFFU, + 0x1F1F3FFFU, + 0x03FF03FFU, + 0x03FF1F1FU, + 0x1F1F03FFU, + 0x03FF03FFU, + 0x7F7F7F7FU, + 0x0F0F7F7FU, + 0xFF1F0F0FU, + 0xFF1F0F1FU, + 0xFF1F0F1FU, + 0xFFFFFF1FU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x3FFFFFFFU, + 0x003F03FFU, + 0x003F03FFU, + 0x030303FFU, + 0x0003FF03U, + 0x7F7F03FFU, + 0x1F03030FU, + 0x03FFFFFFU, + 0x7F7F03FFU, + 0x1F03030FU, + 0x03FFFFFFU, + 0x7F7F03FFU, + 0x1F03030FU, + 0x0303FFFFU, + 0xFFFFFF03U, + 0x00FF3F1FU, + 0x000FFFFFU, + 0x3F0F01FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF3F1FFFU, + 0x000FFFFFU, + 0x3F0F01FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF3F1FFFU, + 0x000FFFFFU, + 0x3F0F01FFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x3F3FFFFFU, + 0x00FFFF3FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0FFFFFFFU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x030F0F0FU, + 0x07070303U, + 0x03030303U, + 0x7F7F7F7FU, + 0x00000303U, + 0xFFFF0000U, + 0x00FFFFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x01FFFFFFU, + 0x1F1F1FFFU, + 0x1F1F1F1FU, + 0x01FFFF1FU, + 0x0301FFFFU, + 0x00030303U, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU +}; + +u32 g_lpddr4_data_slice_0_rw_mask[] = { + 0x07FF7F07U, + 0x0703FF0FU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x1F030F3FU, + 0x030F0F1FU, + 0x01FF031FU, + 0x00000101U, + 0xFFFFFFFFU, + 0x00000000U, + 0x7F0101FFU, + 0x010101FFU, + 0x03FF003FU, + 0x01FF000FU, + 0x01FF0701U, + 0x00000003U, + 0x00000000U, + 0x00000003U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0x3F030001U, + 0x0F3FFF0FU, + 0x1F030F3FU, + 0x03FFFFFFU, + 0x00073FFFU, + 0x0F0F07FFU, + 0x000FFFFFU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0x071F07FFU, + 0x01010101U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x007F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F0703FFU, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x0303FFFFU, + 0x1F1F0103U, + 0x000F1F1FU, + 0xFF3F07FFU, + 0x0FFF0FFFU, + 0x001F0F3FU, + 0x03FF03FFU, + 0x01FF0FFFU, + 0x00000F01U, + 0x000003FFU, + 0x7F7F0703U, + 0x0000001FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0x003FFFFFU +}; + +u32 g_lpddr4_data_slice_1_rw_mask[] = { + 0x07FF7F07U, + 0x0703FF0FU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x1F030F3FU, + 0x030F0F1FU, + 0x01FF031FU, + 0x00000101U, + 0xFFFFFFFFU, + 0x00000000U, + 0x7F0101FFU, + 0x010101FFU, + 0x03FF003FU, + 0x01FF000FU, + 0x01FF0701U, + 0x00000003U, + 0x00000000U, + 0x00000003U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0x3F030001U, + 0x0F3FFF0FU, + 0x1F030F3FU, + 0x03FFFFFFU, + 0x00073FFFU, + 0x0F0F07FFU, + 0x000FFFFFU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0x071F07FFU, + 0x01010101U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x007F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F0703FFU, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x0303FFFFU, + 0x1F1F0103U, + 0x000F1F1FU, + 0xFF3F07FFU, + 0x0FFF0FFFU, + 0x001F0F3FU, + 0x03FF03FFU, + 0x01FF0FFFU, + 0x00000F01U, + 0x000003FFU, + 0x7F7F0703U, + 0x0000001FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0x003FFFFFU +}; + +u32 g_lpddr4_address_slice_0_rw_mask[] = { + 0x000107FFU, + 0x00000000U, + 0x0F000000U, + 0x00000000U, + 0x01000707U, + 0x011F7F7FU, + 0x01000301U, + 0x07FFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x07FF07FFU, + 0x000007FFU, + 0x00FFFFFFU, + 0x03FFFFFFU, + 0x01FF0F03U, + 0x07000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x3FFFFFFFU, + 0x3F3F03FFU, + 0x3F0F3F3FU, + 0x0000003FU, + 0x0707FFFFU, + 0x1F07FF1FU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x000F07FFU, + 0xFF3F07FFU, + 0x0103FFFFU, + 0x0000000FU, + 0x0000010FU +}; + +u32 g_lpddr4_address_slice_1_rw_mask[] = { + 0x000107FFU, + 0x00000000U, + 0x0F000000U, + 0x00000000U, + 0x01000707U, + 0x011F7F7FU, + 0x01000301U, + 0x07FFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x07FF07FFU, + 0x000007FFU, + 0x00FFFFFFU, + 0x03FFFFFFU, + 0x01FF0F03U, + 0x07000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x3FFFFFFFU, + 0x3F3F03FFU, + 0x3F0F3F3FU, + 0x0000003FU, + 0x0707FFFFU, + 0x1F07FF1FU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x000F07FFU, + 0xFF3F07FFU, + 0x0103FFFFU, + 0x0000000FU, + 0x0000010FU +}; + +u32 g_lpddr4_address_slice_2_rw_mask[] = { + 0x000107FFU, + 0x00000000U, + 0x0F000000U, + 0x00000000U, + 0x01000707U, + 0x011F7F7FU, + 0x01000301U, + 0x07FFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x07FF07FFU, + 0x000007FFU, + 0x00FFFFFFU, + 0x03FFFFFFU, + 0x01FF0F03U, + 0x07000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x3FFFFFFFU, + 0x3F3F03FFU, + 0x3F0F3F3FU, + 0x0000003FU, + 0x0707FFFFU, + 0x1F07FF1FU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x000F07FFU, + 0xFF3F07FFU, + 0x0103FFFFU, + 0x0000000FU, + 0x0000010FU +}; + +u32 g_lpddr4_phy_core_rw_mask[] = { + 0x00000003U, + 0x1F030101U, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x001F1F1FU, + 0x011F07FFU, + 0x07FF0100U, + 0x000107FFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x0101FF01U, + 0x0007FF03U, + 0x070F07FFU, + 0x01010300U, + 0x0F010001U, + 0x010F0F0FU, + 0x0F0F0F0FU, + 0x00010101U, + 0x010FFFFFU, + 0x00000001U, + 0x00000000U, + 0x0000FFFFU, + 0x00000001U, + 0x0F0F0F0FU, + 0x03030303U, + 0x03030303U, + 0x03030303U, + 0x03030303U, + 0xFFFF1FFFU, + 0x0000FF01U, + 0x00000000U, + 0x00000000U, + 0x0FFF0FFFU, + 0x00000000U, + 0x00000000U, + 0x0FFF0FFFU, + 0xFF0F0101U, + 0x0003FF01U, + 0x0101FFFFU, + 0x0003FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x1FFF03FFU, + 0x00001FFFU, + 0xFFFFFFFFU, + 0x000007FFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7F000000U, + 0x01FFFFFFU, + 0x00000000U, + 0x00000000U, + 0x0FFFFFFFU, + 0x000FFFFFU, + 0x01FFFFFFU, + 0x3F7FFFFFU, + 0x3F3F1F3FU, + 0x1F3F3F1FU, + 0x001F3F3FU, + 0x0000FFFFU, + 0x01FF0F03U, + 0x00000F7FU, + 0x00000000U, + 0x003F0101U, + 0x01010000U, + 0x00000001U, + 0xFFFFFFFFU, + 0x03071FFFU, + 0x00030303U, + 0xFFFFFFFFU, + 0x03FFFFFFU, + 0x00FF073FU, + 0x0707FFFFU, + 0x00000000U, + 0x00000000U, + 0x00000003U, + 0x0F1F0101U, + 0x00000000U, + 0x0003FFFFU, + 0x0007FFFFU, + 0x00000001U, + 0x00011FFFU, + 0x0F0F0FFFU, + 0x010103FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x000007FFU, + 0x000007FFU, + 0x000007FFU, + 0x000007FFU, + 0x3FFFFFFFU, + 0x0003FFFFU, + 0x7FFFFFFFU, + 0xFFFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0xFFFFFFFFU, + 0x0007FFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x7FFFFF07U +}; diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h new file mode 100644 index 000000000..fde05cea1 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_16BIT_SANITY_H +#define LPDDR4_16BIT_SANITY_H + +#include +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus); +static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr); +static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus); +static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr); + +#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1 +#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2 +#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3 +#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4 + +static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if (irqstatus == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) && + (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) && + (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) && + (intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) && + (intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) && + (intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) && + (intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) && + (intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) && + (intr != LPDDR4_INTR_ECC_ERROR) && + (intr != LPDDR4_INTR_LP_DONE) && + (intr != LPDDR4_INTR_LP_TIMEOUT) && + (intr != LPDDR4_INTR_PORT_TIMEOUT) && + (intr != LPDDR4_INTR_RFIFO_TIMEOUT) && + (intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) && + (intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && + (intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) && + (intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) && + (intr != LPDDR4_INTR_USERIF_WRAP) && + (intr != LPDDR4_INTR_USERIF_INVAL_SETTING) && + (intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) && + (intr != LPDDR4_INTR_MISC_SW_REQ_MODE) && + (intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) && + (intr != LPDDR4_INTR_MISC_TEMP_ALERT) && + (intr != LPDDR4_INTR_MISC_REFRESH_STATUS) && + (intr != LPDDR4_INTR_BIST_DONE) && + (intr != LPDDR4_INTR_CRC) && + (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) && + (intr != LPDDR4_INTR_DFI_PHY_ERROR) && + (intr != LPDDR4_INTR_DFI_BUS_ERROR) && + (intr != LPDDR4_INTR_DFI_STATE_CHANGE) && + (intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) && + (intr != LPDDR4_INTR_DFI_TIMEOUT) && + (intr != LPDDR4_INTR_DIMM) && + (intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && + (intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) && + (intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) && + (intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) && + (intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) && + (intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) && + (intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) && + (intr != LPDDR4_INTR_MC_INIT_DONE) && + (intr != LPDDR4_INTR_INIT_POWER_ON_STATE) && + (intr != LPDDR4_INTR_MRR_ERROR) && + (intr != LPDDR4_INTR_MR_READ_DONE) && + (intr != LPDDR4_INTR_MR_WRITE_DONE) && + (intr != LPDDR4_INTR_PARITY_ERROR) && + (intr != LPDDR4_INTR_LOR_BITS) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) && + (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) && + (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) && + (intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) && + (intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) && + (intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) && + (intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) && + (intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) && + (intr != LPDDR4_INTR_ECC_ERROR) && + (intr != LPDDR4_INTR_LP_DONE) && + (intr != LPDDR4_INTR_LP_TIMEOUT) && + (intr != LPDDR4_INTR_PORT_TIMEOUT) && + (intr != LPDDR4_INTR_RFIFO_TIMEOUT) && + (intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) && + (intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) && + (intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && + (intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) && + (intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) && + (intr != LPDDR4_INTR_USERIF_WRAP) && + (intr != LPDDR4_INTR_USERIF_INVAL_SETTING) && + (intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) && + (intr != LPDDR4_INTR_MISC_SW_REQ_MODE) && + (intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) && + (intr != LPDDR4_INTR_MISC_TEMP_ALERT) && + (intr != LPDDR4_INTR_MISC_REFRESH_STATUS) && + (intr != LPDDR4_INTR_BIST_DONE) && + (intr != LPDDR4_INTR_CRC) && + (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) && + (intr != LPDDR4_INTR_DFI_PHY_ERROR) && + (intr != LPDDR4_INTR_DFI_BUS_ERROR) && + (intr != LPDDR4_INTR_DFI_STATE_CHANGE) && + (intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) && + (intr != LPDDR4_INTR_DFI_TIMEOUT) && + (intr != LPDDR4_INTR_DIMM) && + (intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && + (intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) && + (intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) && + (intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) && + (intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) && + (intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) && + (intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) && + (intr != LPDDR4_INTR_MC_INIT_DONE) && + (intr != LPDDR4_INTR_INIT_POWER_ON_STATE) && + (intr != LPDDR4_INTR_MRR_ERROR) && + (intr != LPDDR4_INTR_MR_READ_DONE) && + (intr != LPDDR4_INTR_MR_WRITE_DONE) && + (intr != LPDDR4_INTR_PARITY_ERROR) && + (intr != LPDDR4_INTR_LOR_BITS) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if (irqstatus == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif /* LPDDR4_16BIT_SANITY_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.c b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.c new file mode 100644 index 000000000..ab2e44891 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include + +#include "cps_drv_lpddr4.h" +#include "lpddr4_ctl_regs.h" +#include "lpddr4_if.h" +#include "lpddr4.h" +#include "lpddr4_structs_if.h" + +static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound); + +u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd) +{ + u32 result = 0U; + u32 regval = 0U; + + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG))); + regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval); + CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval); + return result; +} + +u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask) +{ + u32 result = 0U; + u32 lowermask = 0U; + + result = lpddr4_getctlinterruptmasksf(pd, mask); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + lowermask = (u32)(CPS_FLD_READ(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)))); + *mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)))); + *mask = (u64)((*mask << WORD_SHIFT) | lowermask); + } + return result; +} + +u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask) +{ + u32 result; + u32 regval = 0; + const u64 ui64one = 1ULL; + const u32 ui32irqcount = (u32)LPDDR4_INTR_LOR_BITS + 1U; + + result = lpddr4_setctlinterruptmasksf(pd, mask); + if ((result == (u32)0) && (ui32irqcount < 64U)) { + if (*mask >= (ui64one << ui32irqcount)) + result = (u32)EINVAL; + } + + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = (u32)(*mask & WORD_MASK); + regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)), regval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval); + + regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK); + regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)), regval); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval); + } + return result; +} + +u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus) +{ + u32 result; + u32 ctlirqstatus = 0; + u32 fieldshift = 0; + + result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + if ((u32)intr >= (u32)WORD_SHIFT) { + ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG)); + fieldshift = (u32)intr - ((u32)WORD_SHIFT); + } else { + ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG)); + fieldshift = (u32)intr; + } + + if (fieldshift < WORD_SHIFT) { + if (((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) > 0U) + *irqstatus = true; + else + *irqstatus = false; + } + } + return result; +} + +u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr) +{ + u32 result = 0; + u32 regval = 0; + u32 localinterrupt = (u32)intr; + + result = LPDDR4_INTR_AckCtlIntSF(pd, intr); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + if (localinterrupt > WORD_SHIFT) { + localinterrupt = (localinterrupt - (u32)WORD_SHIFT); + regval = ((u32)LPDDR4_BIT_MASK << localinterrupt); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval); + } else { + regval = ((u32)LPDDR4_BIT_MASK << localinterrupt); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval); + } + } + + return result; +} + +void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr) +{ + u32 regval; + u32 errbitmask = 0U; + u32 snum; + volatile u32 *regaddress; + + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG)); + errbitmask = (LPDDR4_BIT_MASK << 1) | (LPDDR4_BIT_MASK); + for (snum = 0U; snum < DSLICE_NUM; snum++) { + regval = CPS_REG_READ(regaddress); + if ((regval & errbitmask) != 0U) { + debuginfo->wrlvlerror = CDN_TRUE; + *errfoundptr = true; + } + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } +} + +static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound) +{ + volatile u32 *regaddress; + u32 snum = 0U; + u32 errbitmask = 0U; + u32 regval = 0U; + + if (*errorfound == (bool)false) { + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG)); + errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK); + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) { + regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress)); + if ((regval & errbitmask) != RX_CAL_DONE) { + debuginfo->rxoffseterror = (u8)true; + *errorfound = true; + } + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH); + } + } +} + +u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo) +{ + u32 result = 0U; + bool errorfound = false; + + result = lpddr4_getdebuginitinfosf(pd, debuginfo); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound); + lpddr4_setsettings(ctlregbase, errorfound); + lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound); + errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound); + } + + if (errorfound == (bool)true) + result = (u32)EPROTO; + + return result; +} + +u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam) +{ + u32 result = 0U; + u32 fldval = 0U; + + result = lpddr4_geteccenablesf(pd, eccparam); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG))); + switch (fldval) { + case 3: + *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT; + break; + case 2: + *eccparam = LPDDR4_ECC_ERR_DETECT; + break; + case 1: + *eccparam = LPDDR4_ECC_ENABLED; + break; + default: + *eccparam = LPDDR4_ECC_DISABLED; + break; + } + } + return result; +} + +u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam) +{ + u32 result = 0U; + u32 regval = 0U; + + result = lpddr4_seteccenablesf(pd, eccparam); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + + regval = CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)), *eccparam); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval); + } + return result; +} + +u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode) +{ + u32 result = 0U; + + result = lpddr4_getreducmodesf(pd, mode); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) + *mode = LPDDR4_REDUC_ON; + else + *mode = LPDDR4_REDUC_OFF; + } + return result; +} +u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode) +{ + u32 result = 0U; + u32 regval = 0U; + + result = lpddr4_setreducmodesf(pd, mode); + if (result == (u32)0) { + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *mode); + CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval); + } + return result; +} + +u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus) +{ + u32 lowerdata; + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase; + u32 result = (u32)0; + + if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) { + *mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG))); + *mmrvalue = (u64)0; + result = (u32)EIO; + } else { + *mrrstatus = (u8)0; + lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG)); + *mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG)); + *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata); + result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE); + } + return result; +} + +#ifdef REG_WRITE_VERIF + +u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset) +{ + u32 rwmask = 0U; + + switch (dslicenum) { + case 0: + if (arrayoffset < DSLICE0_REG_COUNT) + rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset]; + break; + case 1: + if (arrayoffset < DSLICE1_REG_COUNT) + rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset]; + break; + case 2: + if (arrayoffset < DSLICE2_REG_COUNT) + rwmask = g_lpddr4_data_slice_2_rw_mask[arrayoffset]; + break; + default: + if (arrayoffset < DSLICE3_REG_COUNT) + rwmask = g_lpddr4_data_slice_3_rw_mask[arrayoffset]; + break; + } + return rwmask; +} +#endif diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.h new file mode 100644 index 000000000..1f7fe658a --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_32BIT_H +#define LPDDR4_32BIT_H + +#define DSLICE_NUM (4U) +#define ASLICE_NUM (1U) + +#ifdef __cplusplus +extern "C" { +#endif + +#define DSLICE0_REG_COUNT (140U) +#define DSLICE1_REG_COUNT (140U) +#define DSLICE2_REG_COUNT (140U) +#define DSLICE3_REG_COUNT (140U) +#define ASLICE0_REG_COUNT (52U) +#define PHY_CORE_REG_COUNT (140U) + +#ifdef __cplusplus +} +#endif + +#endif /* LPDDR4_32BIT_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c new file mode 100644 index 000000000..70f0ef594 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c @@ -0,0 +1,1548 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "lpddr4_ctl_regs_rw_masks.h" + +u32 g_lpddr4_ddr_controller_rw_mask[] = { + 0x00000F01U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x01FFFFFFU, + 0x01010100U, + 0x03013F01U, + 0x1F1F1F03U, + 0x00030303U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFF01U, + 0x0001FFFFU, + 0xFF0F7FFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7F7F0000U, + 0x7F7F7F7FU, + 0x00FF1F07U, + 0x3FFF01FFU, + 0xFF01FFFFU, + 0x3FFF01FFU, + 0xFF01FFFFU, + 0x3FFF01FFU, + 0x3F01FFFFU, + 0x00FFFFFFU, + 0x1F01FFFFU, + 0xFFFFFFFFU, + 0x1F01FFFFU, + 0xFFFFFFFFU, + 0x1F01FFFFU, + 0x070707FFU, + 0xFFFFFF01U, + 0x0FFFFFFFU, + 0x3F03FF1FU, + 0x1F1F1F1FU, + 0x0101011FU, + 0x1FFFFFFFU, + 0xFFFFFFFFU, + 0x0301FFFFU, + 0x0101017FU, + 0x07010000U, + 0x0003FF3FU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x03FF0101U, + 0x03FFFFFFU, + 0x03FFFFFFU, + 0xFFFFFFFFU, + 0x1F1F010FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x1F1F1FFFU, + 0x1F010F1FU, + 0x0F1F1F1FU, + 0x1F1F1F01U, + 0x00010F1FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF1F1F1FU, + 0x1F1F1F07U, + 0xFF1F1F1FU, + 0x1F1F1F07U, + 0xFF1F1F1FU, + 0x1F1F1F07U, + 0x07010101U, + 0x01010000U, + 0x00010101U, + 0xFFFFFFFFU, + 0x0700FFFFU, + 0xFFFFFF07U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x010FFFFFU, + 0x00010100U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x01FFFFFFU, + 0x01000107U, + 0xFFFFFF03U, + 0x00FFFFFFU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x3F0F0F0FU, + 0x070FFF01U, + 0x0F0F0000U, + 0x000FFF07U, + 0xFFFF0FFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x01010101U, + 0x3F3F0101U, + 0x01FF03FFU, + 0xFFFF03FFU, + 0xFFFF03FFU, + 0xFFFF03FFU, + 0x00000100U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00FFFF0FU, + 0x07FFFFFFU, + 0x01FFFF00U, + 0x00000000U, + 0x00000000U, + 0x00010000U, + 0x03FF0003U, + 0x03FF03FFU, + 0xFFFF1F1FU, + 0x03FF03FFU, + 0x1F1F03FFU, + 0x03FFFFFFU, + 0x03FF03FFU, + 0xFFFF1F1FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF00FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF00FFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00FFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFF00U, + 0x010101FFU, + 0x01000000U, + 0x01010101U, + 0x03030101U, + 0x013F0000U, + 0x00000001U, + 0xFFFFFFFFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0FFF0000U, + 0x07030000U, + 0x010F0101U, + 0x01FFFF01U, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFF0000U, + 0x7FFF7FFFU, + 0x7FFF7FFFU, + 0x00077FFFU, + 0x010FFF00U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00000007U, + 0xFFFFFFFFU, + 0x1F1F1F07U, + 0x000F1F1FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0007FFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FF00U, + 0x00000000U, + 0x0FFF0FFFU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x007F0FFFU, + 0x0FFF0FFFU, + 0x0FFF0FFFU, + 0x0000037FU, + 0x0FFF0FFFU, + 0x01010FFFU, + 0x03030303U, + 0x07070303U, + 0xFFFF0F0FU, + 0x0007FFFFU, + 0xFFFFFFFFU, + 0xFFFF0307U, + 0x1F01FFFFU, + 0xFFFF1F01U, + 0x01010101U, + 0x01010101U, + 0x011F0301U, + 0x01030301U, + 0x0003FFFFU, + 0x00000000U, + 0x0103FFFFU, + 0x01010103U, + 0x01010101U, + 0x01010101U, + 0x01010101U, + 0x0F0F0F07U, + 0x0F0F070FU, + 0x011F0F0FU, + 0x01000003U, + 0x03030301U, + 0x00010101U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFFFFFFFFU, + 0x00001FFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x03000000U, + 0xFF030303U, + 0x0FFF0F0FU, + 0x0F0FFF0FU, + 0x01010101U, + 0x3F3F3F3FU, + 0x1F1F3F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x0F1F1F1FU, + 0x0F070F07U, + 0x00000707U, + 0x00000000U, + 0x00010000U, + 0x013F3F01U, + 0x0F010101U, + 0x00030101U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x010F0F01U, + 0x01010101U, + 0x01010101U, + 0x03030101U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00000100U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x010FFFFFU, + 0x0101030FU, + 0x03010101U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0101FFFFU, + 0x00000707U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00FFFFFFU, + 0x7F7F7F00U, + 0x00FF0300U, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0x00007F7FU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0x00007F7FU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0x0F0F7F7FU, + 0xFF0F0F0FU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003FFFFU, + 0xFFFFFFFFU, + 0x000101FFU, + 0xFFFFFFFFU, + 0x00FF0000U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x07000101U, + 0x7F7F0707U, + 0x7F7F7F7FU, + 0x010101FFU, + 0x07070701U, + 0x0F070707U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0xFF0F0F0FU, + 0xFFFF00FFU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x01010101U, + 0x01010101U, + 0x00010101U, + 0x00000000U, + 0x00000000U, + 0x00000100U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00000007U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000000FU +}; + +u32 g_lpddr4_pi_rw_mask[] = { + 0x00000F01U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00010101U, + 0x00FFFFFFU, + 0x01010301U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFFFFFFFFU, + 0x0101011FU, + 0x0F011F0FU, + 0x00010103U, + 0x000FFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000007U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x01000000U, + 0x00010101U, + 0x003F3F03U, + 0x0101FFFFU, + 0x0F010F01U, + 0x0000FF00U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0F0F0F1FU, + 0x00030000U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0101010FU, + 0x01010101U, + 0x000F0F01U, + 0x000003FFU, + 0xFFFFFFFFU, + 0x0000FF0FU, + 0xFFFFFFFFU, + 0x00FFFF00U, + 0x0F0FFFFFU, + 0x01011F1FU, + 0x03000000U, + 0x01030F01U, + 0x0F010101U, + 0x000000FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0001U, + 0x1F1F3F1FU, + 0xFF0F0F01U, + 0x7F1F0FFFU, + 0x0101FFFFU, + 0x00FFFF01U, + 0x00000000U, + 0x010F0701U, + 0x011F1F0FU, + 0x00FF0300U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0101FFFFU, + 0x01010100U, + 0x0F1F0703U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x000F0F0FU, + 0x00000000U, + 0x00000000U, + 0x0FFFFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x011F1F00U, + 0x03030301U, + 0x00FF0103U, + 0x013F0001U, + 0x00000001U, + 0xFFFFFFFFU, + 0x0000FF07U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0FFF0000U, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0303070FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x0101010FU, + 0x01010100U, + 0x00000001U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0101U, + 0x000000FFU, + 0x03FFFFFFU, + 0x01FFFF00U, + 0x01000000U, + 0x0100000FU, + 0x00010F07U, + 0x0F00010FU, + 0x010F0001U, + 0x00010F00U, + 0x0F00010FU, + 0x010F0001U, + 0x00000000U, + 0x00000000U, + 0x011F0000U, + 0x01010103U, + 0x01010101U, + 0x01010101U, + 0x01010101U, + 0x01010101U, + 0x0001FFFFU, + 0x0000001FU, + 0x0F011F01U, + 0x01010101U, + 0xFFFFFF01U, + 0x000000FFU, + 0x000000FFU, + 0x000FFFFFU, + 0x0FFF0FFFU, + 0x7F7F7F7FU, + 0x03FF7F7FU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x0F0FFFFFU, + 0x03030F0FU, + 0x0003FF03U, + 0x03FF03FFU, + 0x01FF01FFU, + 0x0F0F01FFU, + 0x0F0F0F0FU, + 0x03030303U, + 0x03030303U, + 0x03030303U, + 0x03030303U, + 0x7F7F0303U, + 0x7F7F7F7FU, + 0x00070707U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F030303U, + 0x001F3FFFU, + 0x001F3FFFU, + 0x1F1F3FFFU, + 0x03FF03FFU, + 0x03FF1F1FU, + 0x1F1F03FFU, + 0x03FF03FFU, + 0x7F7F7F7FU, + 0x0F0F7F7FU, + 0xFF1F0F0FU, + 0xFF1F0F1FU, + 0xFF1F0F1FU, + 0x0003FF1FU, + 0x03FFFFFFU, + 0x03FFFFFFU, + 0x003FFFFFU, + 0x003F03FFU, + 0x003F03FFU, + 0x03FF03FFU, + 0x7F7F03FFU, + 0x0003030FU, + 0x03FF03FFU, + 0x030F7F7FU, + 0x0003FF03U, + 0x7F7F03FFU, + 0xFF03030FU, + 0xFF3FFFFFU, + 0xFF01FFFFU, + 0xFFFF3F0FU, + 0xFFFFFFFFU, + 0x0000FF3FU, + 0xFF01FFFFU, + 0xFFFF3F0FU, + 0xFFFFFFFFU, + 0x0000FF3FU, + 0xFF01FFFFU, + 0xFFFF3F0FU, + 0x1FFFFFFFU, + 0xFFFFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x3F3FFFFFU, + 0xFFFFFF3FU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0FFFFFFFU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0xFF0F0F0FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0FFFFFFFU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0xFF0F0F0FU, + 0x0FFFFFFFU, + 0x0F0F0F0FU, + 0x000F0F0FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x000007FFU +}; + +u32 g_lpddr4_data_slice_0_rw_mask[] = { + 0x000F07FFU, + 0x000703FFU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0xFFFFFFFFU, + 0x00000000U, + 0x0101FF7FU, + 0x00003F01U, + 0x000F03FFU, + 0x070101FFU, + 0x000301FFU, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0xFF030001U, + 0x00FF0F3FU, + 0x0F3F03FFU, + 0x1F030F3FU, + 0x3FFFFFFFU, + 0x0F07FF07U, + 0x0000FF0FU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x010001FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0x00000000U, + 0x017F7F01U, + 0x07FF0FFFU, + 0x03FFFF1FU, + 0x01FFFF3FU, + 0x07030101U, + 0x01010101U, + 0x000007FFU, + 0x00003FFFU, + 0x00001F00U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x003F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x000703FFU, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F1F0103U, + 0x3F07FF0FU, + 0xFF0FFFFFU, + 0x1F0F3F0FU, + 0x03FF03FFU, + 0x0F010FFFU, + 0x000003FFU, + 0x3F0103FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F3F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_data_slice_1_rw_mask[] = { + 0x000F07FFU, + 0x000703FFU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0xFFFFFFFFU, + 0x00000000U, + 0x0101FF7FU, + 0x00003F01U, + 0x000F03FFU, + 0x070101FFU, + 0x000301FFU, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0xFF030001U, + 0x00FF0F3FU, + 0x0F3F03FFU, + 0x1F030F3FU, + 0x3FFFFFFFU, + 0x0F07FF07U, + 0x0000FF0FU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x010001FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0x00000000U, + 0x017F7F01U, + 0x07FF0FFFU, + 0x03FFFF1FU, + 0x01FFFF3FU, + 0x07030101U, + 0x01010101U, + 0x000007FFU, + 0x00003FFFU, + 0x00001F00U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x003F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x000703FFU, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F1F0103U, + 0x3F07FF0FU, + 0xFF0FFFFFU, + 0x1F0F3F0FU, + 0x03FF03FFU, + 0x0F010FFFU, + 0x000003FFU, + 0x3F0103FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F3F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_data_slice_2_rw_mask[] = { + 0x000F07FFU, + 0x000703FFU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0xFFFFFFFFU, + 0x00000000U, + 0x0101FF7FU, + 0x00003F01U, + 0x000F03FFU, + 0x070101FFU, + 0x000301FFU, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0xFF030001U, + 0x00FF0F3FU, + 0x0F3F03FFU, + 0x1F030F3FU, + 0x3FFFFFFFU, + 0x0F07FF07U, + 0x0000FF0FU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x010001FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0x00000000U, + 0x017F7F01U, + 0x07FF0FFFU, + 0x03FFFF1FU, + 0x01FFFF3FU, + 0x07030101U, + 0x01010101U, + 0x000007FFU, + 0x00003FFFU, + 0x00001F00U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x003F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x000703FFU, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F1F0103U, + 0x3F07FF0FU, + 0xFF0FFFFFU, + 0x1F0F3F0FU, + 0x03FF03FFU, + 0x0F010FFFU, + 0x000003FFU, + 0x3F0103FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F3F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_data_slice_3_rw_mask[] = { + 0x000F07FFU, + 0x000703FFU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0xFFFFFFFFU, + 0x00000000U, + 0x0101FF7FU, + 0x00003F01U, + 0x000F03FFU, + 0x070101FFU, + 0x000301FFU, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0xFF030001U, + 0x00FF0F3FU, + 0x0F3F03FFU, + 0x1F030F3FU, + 0x3FFFFFFFU, + 0x0F07FF07U, + 0x0000FF0FU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x010001FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0x00000000U, + 0x017F7F01U, + 0x07FF0FFFU, + 0x03FFFF1FU, + 0x01FFFF3FU, + 0x07030101U, + 0x01010101U, + 0x000007FFU, + 0x00003FFFU, + 0x00001F00U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x003F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x000703FFU, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F1F0103U, + 0x3F07FF0FU, + 0xFF0FFFFFU, + 0x1F0F3F0FU, + 0x03FF03FFU, + 0x0F010FFFU, + 0x000003FFU, + 0x3F0103FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F3F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_address_slice_0_rw_mask[] = { + 0x000107FFU, + 0x00000000U, + 0x0F000000U, + 0x00000000U, + 0x01000707U, + 0x011F7F7FU, + 0x01000301U, + 0x07FFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x07FF07FFU, + 0x000007FFU, + 0x00FFFFFFU, + 0x03FFFFFFU, + 0x01FF0F03U, + 0x07000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x00FFFFFFU, + 0x3F3F03FFU, + 0x3F0F3F3FU, + 0xFFFFFF03U, + 0x01FFFFFFU, + 0x3F03FFFFU, + 0x0101FFFFU, + 0x07FF3F01U, + 0x01FF0000U, + 0x01000000U, + 0x00000000U, + 0x07FF07FFU, + 0x1F07FF1FU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x000F07FFU, + 0xFF3F07FFU, + 0x0103FFFFU, + 0x0000000FU, + 0x03FF010FU, + 0x0000FF01U +}; + +u32 g_lpddr4_phy_core_rw_mask[] = { + 0x00000003U, + 0x1F030101U, + 0x1F1F1F1FU, + 0x001F1F1FU, + 0x011F07FFU, + 0x07FF0100U, + 0x000107FFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x0101FF01U, + 0x0007FF0FU, + 0xFF0F07FFU, + 0x01030007U, + 0xFFFF0101U, + 0xFF3F0103U, + 0x010101FFU, + 0x0F0F0100U, + 0x010F0F01U, + 0xFFFF0101U, + 0x0001010FU, + 0x00000000U, + 0x0000FFFFU, + 0x00000001U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x01FF0F0FU, + 0x001FFFFFU, + 0x0001FFFFU, + 0x0007FFFFU, + 0x000003FFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x01000000U, + 0x0001FF0FU, + 0x000103FFU, + 0x0003FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x1FFF03FFU, + 0x00001FFFU, + 0xFFFFFFFFU, + 0x000007FFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7F000000U, + 0x01FFFFFFU, + 0x00000000U, + 0x00000000U, + 0x0FFFFF7FU, + 0x000FFFFFU, + 0x01FFFFFFU, + 0x3F7FFFFFU, + 0x3F3F1F3FU, + 0x1F3F3F1FU, + 0x001F3F3FU, + 0x07FFFFFFU, + 0x03010000U, + 0x0F7F01FFU, + 0x00000000U, + 0x003F0101U, + 0x01010000U, + 0x00000001U, + 0xFFFFFFFFU, + 0x031F01FFU, + 0x00000003U, + 0xFFFFFFFFU, + 0x03FFFFFFU, + 0x07FF073FU, + 0x00000007U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000003U, + 0x070F0101U, + 0x00000000U, + 0x0707FF01U, + 0x00007F00U, + 0x3FFF0000U, + 0x3F000000U, + 0x000FFF00U, + 0x03000FFFU, + 0x00000000U, + 0x000001FFU, + 0x03FF0000U, + 0x03000000U, + 0x007F0000U, + 0x00003F00U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x0000FFFFU, + 0xFFFFFFFFU, + 0x1F0FFFFFU, + 0x0FFFFFFFU, + 0x0000FFFFU, + 0x00003FFFU, + 0x3FFF0000U, + 0x00000000U, + 0x00003FFFU, + 0x0003FFFFU, + 0x00003FFFU, + 0x00000001U, + 0x00011FFFU, + 0x0F0F0FFFU, + 0x010101FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x000007FFU, + 0x000007FFU, + 0x000007FFU, + 0x000007FFU, + 0x00000007U, + 0x3FFFFFFFU, + 0x0003FFFFU, + 0x7FFFFFFFU, + 0xFFFFFFFFU, + 0x3FFFFFFFU, + 0x07FFFFFFU, + 0xFFFFFFFFU, + 0x0003FFFFU, + 0x3FFFFFFFU, + 0x07FFFFFFU, + 0x3FFFFFFFU, + 0x07FFFFFFU, + 0x3FFFFFFFU, + 0x07FFFFFFU, + 0x3FFFFFFFU, + 0x07FFFFFFU, + 0x7FFFFF07U +}; diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h new file mode 100644 index 000000000..334eecc8a --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_32BIT_SANITY_H +#define LPDDR4_32BIT_SANITY_H + +#include +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus); +static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr); +static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus); +static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr); + +#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1 +#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2 +#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3 +#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4 + +static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if (irqstatus == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_RESET_DONE) && + (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) && + (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) && + (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) && + (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) && + (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) && + (intr != LPDDR4_INTR_ECC_SCRUB_DONE) && + (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) && + (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) && + (intr != LPDDR4_INTR_MC_INIT_DONE) && + (intr != LPDDR4_INTR_LP_DONE) && + (intr != LPDDR4_INTR_BIST_DONE) && + (intr != LPDDR4_INTR_WRAP_ERROR) && + (intr != LPDDR4_INTR_INVALID_BURST_ERROR) && + (intr != LPDDR4_INTR_RDLVL_ERROR) && + (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) && + (intr != LPDDR4_INTR_WRLVL_ERROR) && + (intr != LPDDR4_INTR_CA_TRAINING_ERROR) && + (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) && + (intr != LPDDR4_INTR_MRR_ERROR) && + (intr != LPDDR4_INTR_PHY_MASTER_ERROR) && + (intr != LPDDR4_INTR_WRLVL_REQ) && + (intr != LPDDR4_INTR_RDLVL_REQ) && + (intr != LPDDR4_INTR_RDLVL_GATE_REQ) && + (intr != LPDDR4_INTR_CA_TRAINING_REQ) && + (intr != LPDDR4_INTR_LEVELING_DONE) && + (intr != LPDDR4_INTR_PHY_ERROR) && + (intr != LPDDR4_INTR_MR_READ_DONE) && + (intr != LPDDR4_INTR_TEMP_CHANGE) && + (intr != LPDDR4_INTR_TEMP_ALERT) && + (intr != LPDDR4_INTR_SW_DQS_COMPLETE) && + (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) && + (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) && + (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) && + (intr != LPDDR4_INTR_MR_WRITE_DONE) && + (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) && + (intr != LPDDR4_INTR_DFI_INIT_STATE) && + (intr != LPDDR4_INTR_DLL_RESYNC_DONE) && + (intr != LPDDR4_INTR_TDFI_TO) && + (intr != LPDDR4_INTR_DFS_DONE) && + (intr != LPDDR4_INTR_DFS_STATUS) && + (intr != LPDDR4_INTR_REFRESH_STATUS) && + (intr != LPDDR4_INTR_ZQ_STATUS) && + (intr != LPDDR4_INTR_SW_REQ_MODE) && + (intr != LPDDR4_INTR_LOR_BITS) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_RESET_DONE) && + (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) && + (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) && + (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) && + (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) && + (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) && + (intr != LPDDR4_INTR_ECC_SCRUB_DONE) && + (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) && + (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) && + (intr != LPDDR4_INTR_MC_INIT_DONE) && + (intr != LPDDR4_INTR_LP_DONE) && + (intr != LPDDR4_INTR_BIST_DONE) && + (intr != LPDDR4_INTR_WRAP_ERROR) && + (intr != LPDDR4_INTR_INVALID_BURST_ERROR) && + (intr != LPDDR4_INTR_RDLVL_ERROR) && + (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) && + (intr != LPDDR4_INTR_WRLVL_ERROR) && + (intr != LPDDR4_INTR_CA_TRAINING_ERROR) && + (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) && + (intr != LPDDR4_INTR_MRR_ERROR) && + (intr != LPDDR4_INTR_PHY_MASTER_ERROR) && + (intr != LPDDR4_INTR_WRLVL_REQ) && + (intr != LPDDR4_INTR_RDLVL_REQ) && + (intr != LPDDR4_INTR_RDLVL_GATE_REQ) && + (intr != LPDDR4_INTR_CA_TRAINING_REQ) && + (intr != LPDDR4_INTR_LEVELING_DONE) && + (intr != LPDDR4_INTR_PHY_ERROR) && + (intr != LPDDR4_INTR_MR_READ_DONE) && + (intr != LPDDR4_INTR_TEMP_CHANGE) && + (intr != LPDDR4_INTR_TEMP_ALERT) && + (intr != LPDDR4_INTR_SW_DQS_COMPLETE) && + (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) && + (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) && + (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) && + (intr != LPDDR4_INTR_MR_WRITE_DONE) && + (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) && + (intr != LPDDR4_INTR_DFI_INIT_STATE) && + (intr != LPDDR4_INTR_DLL_RESYNC_DONE) && + (intr != LPDDR4_INTR_TDFI_TO) && + (intr != LPDDR4_INTR_DFS_DONE) && + (intr != LPDDR4_INTR_DFS_STATUS) && + (intr != LPDDR4_INTR_REFRESH_STATUS) && + (intr != LPDDR4_INTR_ZQ_STATUS) && + (intr != LPDDR4_INTR_SW_REQ_MODE) && + (intr != LPDDR4_INTR_LOR_BITS) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if (irqstatus == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr) +{ + u32 ret = 0; + + if (pd == NULL) { + ret = EINVAL; + } else if ( + (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) && + (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif /* LPDDR4_32BIT_SANITY_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_if.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_if.h new file mode 100644 index 000000000..7562989d9 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_if.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_IF_H +#define LPDDR4_IF_H + +#include +#ifdef CONFIG_K3_AM64_DDRSS +#include +#else +#include +#endif + +typedef struct lpddr4_config_s lpddr4_config; +typedef struct lpddr4_privatedata_s lpddr4_privatedata; +typedef struct lpddr4_debuginfo_s lpddr4_debuginfo; +typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs; + +typedef enum { + LPDDR4_CTL_REGS = 0U, + LPDDR4_PHY_REGS = 1U, + LPDDR4_PHY_INDEP_REGS = 2U +} lpddr4_regblock; + +typedef enum { + LPDDR4_DRV_NONE = 0U, + LPDDR4_DRV_SOC_PLL_UPDATE = 1U +} lpddr4_infotype; + +typedef enum { + LPDDR4_LPI_PD_WAKEUP_FN = 0U, + LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U, + LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U, + LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U, + LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U, + LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U, + LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U +} lpddr4_lpiwakeupparam; + +typedef enum { + LPDDR4_REDUC_ON = 0U, + LPDDR4_REDUC_OFF = 1U +} lpddr4_reducmode; + +typedef enum { + LPDDR4_ECC_DISABLED = 0U, + LPDDR4_ECC_ENABLED = 1U, + LPDDR4_ECC_ERR_DETECT = 2U, + LPDDR4_ECC_ERR_DETECT_CORRECT = 3U +} lpddr4_eccenable; + +typedef enum { + LPDDR4_DBI_RD_ON = 0U, + LPDDR4_DBI_RD_OFF = 1U, + LPDDR4_DBI_WR_ON = 2U, + LPDDR4_DBI_WR_OFF = 3U +} lpddr4_dbimode; + +typedef enum { + LPDDR4_FSP_0 = 0U, + LPDDR4_FSP_1 = 1U, + LPDDR4_FSP_2 = 2U +} lpddr4_ctlfspnum; + +typedef void (*lpddr4_infocallback)(const lpddr4_privatedata *pd, lpddr4_infotype infotype); + +typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt ctlinterrupt, u8 chipselect); + +typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt phyindepinterrupt, u8 chipselect); + +u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize); + +u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg); + +u32 lpddr4_start(const lpddr4_privatedata *pd); + +u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue); + +u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue); + +u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus); + +u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus); + +u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + +u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + +u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + +u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + +u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + +u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + +u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask); + +u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask); + +u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus); + +u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr); + +u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask); + +u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask); + +u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus); + +u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr); + +u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo); + +u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles); + +u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles); + +u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam); + +u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam); + +u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode); + +u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); + +u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off); + +u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off); + +u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode); + +u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max); + +u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); + +u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval); + +#endif /* LPDDR4_IF_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.c b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.c new file mode 100644 index 000000000..370242f5b --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "lpddr4_obj_if.h" + +lpddr4_obj *lpddr4_getinstance(void) +{ + static lpddr4_obj driver = { + .probe = lpddr4_probe, + .init = lpddr4_init, + .start = lpddr4_start, + .readreg = lpddr4_readreg, + .writereg = lpddr4_writereg, + .getmmrregister = lpddr4_getmmrregister, + .setmmrregister = lpddr4_setmmrregister, + .writectlconfig = lpddr4_writectlconfig, + .writephyconfig = lpddr4_writephyconfig, + .writephyindepconfig = lpddr4_writephyindepconfig, + .readctlconfig = lpddr4_readctlconfig, + .readphyconfig = lpddr4_readphyconfig, + .readphyindepconfig = lpddr4_readphyindepconfig, + .getctlinterruptmask = lpddr4_getctlinterruptmask, + .setctlinterruptmask = lpddr4_setctlinterruptmask, + .checkctlinterrupt = lpddr4_checkctlinterrupt, + .ackctlinterrupt = lpddr4_ackctlinterrupt, + .getphyindepinterruptmask = lpddr4_getphyindepinterruptmask, + .setphyindepinterruptmask = lpddr4_setphyindepinterruptmask, + .checkphyindepinterrupt = lpddr4_checkphyindepinterrupt, + .ackphyindepinterrupt = lpddr4_ackphyindepinterrupt, + .getdebuginitinfo = lpddr4_getdebuginitinfo, + .getlpiwakeuptime = lpddr4_getlpiwakeuptime, + .setlpiwakeuptime = lpddr4_setlpiwakeuptime, + .geteccenable = lpddr4_geteccenable, + .seteccenable = lpddr4_seteccenable, + .getreducmode = lpddr4_getreducmode, + .setreducmode = lpddr4_setreducmode, + .getdbireadmode = lpddr4_getdbireadmode, + .getdbiwritemode = lpddr4_getdbiwritemode, + .setdbimode = lpddr4_setdbimode, + .getrefreshrate = lpddr4_getrefreshrate, + .setrefreshrate = lpddr4_setrefreshrate, + .refreshperchipselect = lpddr4_refreshperchipselect, + }; + + return &driver; +} diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.h new file mode 100644 index 000000000..d538e61b7 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_obj_if.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef lpddr4_obj_if_h +#define lpddr4_obj_if_h + +#include "lpddr4_if.h" + +typedef struct lpddr4_obj_s { + u32 (*probe)(const lpddr4_config *config, u16 *configsize); + + u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg); + + u32 (*start)(const lpddr4_privatedata *pd); + + u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue); + + u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue); + + u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus); + + u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus); + + u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + + u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + + u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + + u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + + u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + + u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); + + u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask); + + u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask); + + u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus); + + u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr); + + u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask); + + u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask); + + u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus); + + u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr); + + u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo); + + u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles); + + u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles); + + u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam); + + u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam); + + u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode); + + u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); + + u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off); + + u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off); + + u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode); + + u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max); + + u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); + + u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval); +} lpddr4_obj; + +extern lpddr4_obj *lpddr4_getinstance(void); + +#endif /* lpddr4_obj_if_h */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_private.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_private.h new file mode 100644 index 000000000..3d5017ea4 --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_private.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/********************************************************************** + * Copyright (C) 2012-2018 Cadence Design Systems, Inc. + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + ********************************************************************** + * Cadence Core Driver for LPDDR4. + ********************************************************************** + */ + +#ifndef LPDDR4_PRIV_H +#define LPDDR4_PRIV_H + +#define PRODUCT_ID (0x1046U) +#define VERSION_0 (0x54d5da40U) +#define VERSION_1 (0xc1865a1U) + +#define LPDDR4_BIT_MASK (0x1U) +#define BYTE_MASK (0xffU) +#define NIBBLE_MASK (0xfU) + +#define WORD_SHIFT (32U) +#define WORD_MASK (0xffffffffU) +#define SLICE_WIDTH (0x100) +/* Number of Data slices */ +#define DSLICE_NUM (4U) +/*Number of Address Slices */ +#define ASLICE_NUM (1U) + +/* Number of accessible registers in each slice */ +#define DSLICE0_REG_COUNT (140U) +#define DSLICE1_REG_COUNT (140U) +#define DSLICE2_REG_COUNT (140U) +#define DSLICE3_REG_COUNT (140U) +#define ASLICE0_REG_COUNT (52U) +#define PHY_CORE_REG_COUNT (140U) + +#define CTL_OFFSET 0 +#define PI_OFFSET (((uint32_t)1) << 11) +#define PHY_OFFSET (((uint32_t)1) << 12) + +/* BIT[17] on INT_MASK_1 register. */ +#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT) + +/* Init Error information bits */ +#define PLL_READY (0x3U) +#define IO_CALIB_DONE ((uint32_t)0x1U << 23U) +#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U) +#define IO_CALIB_STATE ((uint32_t)0xBU << 28U) +#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U) +#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \ + ((uint32_t)LPDDR4_BIT_MASK << 4U)) +#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U) +#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \ + ((uint32_t)LPDDR4_BIT_MASK << 6U)) +#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \ + (((uint32_t)BYTE_MASK) << 16U)) +#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \ + (((uint32_t)BYTE_MASK) << 18U)) + +#endif /* LPDDR4_PRIV_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_sanity.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_sanity.h new file mode 100644 index 000000000..750e00d3f --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_sanity.h @@ -0,0 +1,445 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_SANITY_H +#define LPDDR4_SANITY_H + +#include +#include +#include "lpddr4_if.h" +#ifdef __cplusplus +extern "C" { +#endif + +static inline u32 lpddr4_configsf(const lpddr4_config *obj); +static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj); + +static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize); +static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg); +static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd); +static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue); +static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp); +static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus); +static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus); +static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask); +static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask); +static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask); +static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo); +static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles); +static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam); +static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam); +static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); +static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); +static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off); +static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode); +static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); +static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); + +#define lpddr4_probesf lpddr4_sanityfunction1 +#define lpddr4_initsf lpddr4_sanityfunction2 +#define lpddr4_startsf lpddr4_sanityfunction3 +#define lpddr4_readregsf lpddr4_sanityfunction4 +#define lpddr4_writeregsf lpddr4_sanityfunction5 +#define lpddr4_getmmrregistersf lpddr4_sanityfunction6 +#define lpddr4_setmmrregistersf lpddr4_sanityfunction7 +#define lpddr4_writectlconfigsf lpddr4_sanityfunction3 +#define lpddr4_writephyconfigsf lpddr4_sanityfunction3 +#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction3 +#define lpddr4_readctlconfigsf lpddr4_sanityfunction3 +#define lpddr4_readphyconfigsf lpddr4_sanityfunction3 +#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction3 +#define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14 +#define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15 +#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction16 +#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction16 +#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction18 +#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction19 +#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction19 +#define lpddr4_geteccenablesf lpddr4_sanityfunction21 +#define lpddr4_seteccenablesf lpddr4_sanityfunction22 +#define lpddr4_getreducmodesf lpddr4_sanityfunction23 +#define lpddr4_setreducmodesf lpddr4_sanityfunction24 +#define lpddr4_getdbireadmodesf lpddr4_sanityfunction25 +#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction25 +#define lpddr4_setdbimodesf lpddr4_sanityfunction27 +#define lpddr4_getrefreshratesf lpddr4_sanityfunction28 +#define lpddr4_setrefreshratesf lpddr4_sanityfunction29 +#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3 + +static inline u32 lpddr4_configsf(const lpddr4_config *obj) +{ + u32 ret = 0; + + if (obj == NULL) + ret = EINVAL; + + return ret; +} + +static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj) +{ + u32 ret = 0; + + if (obj == NULL) + ret = EINVAL; + + return ret; +} + +static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize) +{ + u32 ret = 0; + + if (configsize == NULL) { + ret = EINVAL; + } else if (lpddr4_configsf(config) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg) +{ + u32 ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if (lpddr4_configsf(cfg) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd) +{ + u32 ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) + ret = EINVAL; + + return ret; +} + +static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue) +{ + u32 ret = 0; + + if (regvalue == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (cpp != LPDDR4_CTL_REGS) && + (cpp != LPDDR4_PHY_REGS) && + (cpp != LPDDR4_PHY_INDEP_REGS) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp) +{ + u32 ret = 0; + + if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (cpp != LPDDR4_CTL_REGS) && + (cpp != LPDDR4_PHY_REGS) && + (cpp != LPDDR4_PHY_INDEP_REGS) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus) +{ + u32 ret = 0; + + if (mmrvalue == NULL) { + ret = EINVAL; + } else if (mmrstatus == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus) +{ + u32 ret = 0; + + if (mrwstatus == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask) +{ + u32 ret = 0; + + if (mask == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask) +{ + u32 ret = 0; + + if (mask == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask) +{ + u32 ret = 0; + + if (mask == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo) +{ + u32 ret = 0; + + if (debuginfo == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles) +{ + u32 ret = 0; + + if (lpiwakeupparam == NULL) { + ret = EINVAL; + } else if (fspnum == NULL) { + ret = EINVAL; + } else if (cycles == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) && + (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN) + ) { + ret = EINVAL; + } else if ( + (*fspnum != LPDDR4_FSP_0) && + (*fspnum != LPDDR4_FSP_1) && + (*fspnum != LPDDR4_FSP_2) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam) +{ + u32 ret = 0; + + if (eccparam == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam) +{ + u32 ret = 0; + + if (eccparam == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (*eccparam != LPDDR4_ECC_DISABLED) && + (*eccparam != LPDDR4_ECC_ENABLED) && + (*eccparam != LPDDR4_ECC_ERR_DETECT) && + (*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode) +{ + u32 ret = 0; + + if (mode == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode) +{ + u32 ret = 0; + + if (mode == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (*mode != LPDDR4_REDUC_ON) && + (*mode != LPDDR4_REDUC_OFF) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off) +{ + u32 ret = 0; + + if (on_off == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode) +{ + u32 ret = 0; + + if (mode == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (*mode != LPDDR4_DBI_RD_ON) && + (*mode != LPDDR4_DBI_RD_OFF) && + (*mode != LPDDR4_DBI_WR_ON) && + (*mode != LPDDR4_DBI_WR_OFF) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max) +{ + u32 ret = 0; + + if (fspnum == NULL) { + ret = EINVAL; + } else if (tref == NULL) { + ret = EINVAL; + } else if (tras_max == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (*fspnum != LPDDR4_FSP_0) && + (*fspnum != LPDDR4_FSP_1) && + (*fspnum != LPDDR4_FSP_2) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max) +{ + u32 ret = 0; + + if (fspnum == NULL) { + ret = EINVAL; + } else if (tref == NULL) { + ret = EINVAL; + } else if (tras_max == NULL) { + ret = EINVAL; + } else if (lpddr4_privatedatasf(pd) == EINVAL) { + ret = EINVAL; + } else if ( + (*fspnum != LPDDR4_FSP_0) && + (*fspnum != LPDDR4_FSP_1) && + (*fspnum != LPDDR4_FSP_2) + ) { + ret = EINVAL; + } else { + } + + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif /* LPDDR4_SANITY_H */ diff --git a/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_structs_if.h new file mode 100644 index 000000000..e41cbb7ff --- /dev/null +++ b/roms/u-boot/drivers/ram/k3-ddrss/lpddr4_structs_if.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_STRUCTS_IF_H +#define LPDDR4_STRUCTS_IF_H + +#include +#include "lpddr4_if.h" + +struct lpddr4_config_s { + struct lpddr4_ctlregs_s *ctlbase; + lpddr4_infocallback infohandler; + lpddr4_ctlcallback ctlinterrupthandler; + lpddr4_phyindepcallback phyindepinterrupthandler; +}; + +struct lpddr4_privatedata_s { + struct lpddr4_ctlregs_s *ctlbase; + lpddr4_infocallback infohandler; + lpddr4_ctlcallback ctlinterrupthandler; + lpddr4_phyindepcallback phyindepinterrupthandler; +}; + +struct lpddr4_debuginfo_s { + u8 pllerror; + u8 iocaliberror; + u8 rxoffseterror; + u8 catraingerror; + u8 wrlvlerror; + u8 gatelvlerror; + u8 readlvlerror; + u8 dqtrainingerror; +}; + +struct lpddr4_fspmoderegs_s { + u8 mr1data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr2data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr3data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr11data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr12data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr13data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr14data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr22data_fn[LPDDR4_INTR_MAX_CS]; +}; + +#endif /* LPDDR4_STRUCTS_IF_H */ diff --git a/roms/u-boot/drivers/ram/mediatek/Makefile b/roms/u-boot/drivers/ram/mediatek/Makefile new file mode 100644 index 000000000..95507b593 --- /dev/null +++ b/roms/u-boot/drivers/ram/mediatek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 MediaTek Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_TARGET_MT7629) = ddr3-mt7629.o diff --git a/roms/u-boot/drivers/ram/mediatek/ddr3-mt7629.c b/roms/u-boot/drivers/ram/mediatek/ddr3-mt7629.c new file mode 100644 index 000000000..d12a3b4f4 --- /dev/null +++ b/roms/u-boot/drivers/ram/mediatek/ddr3-mt7629.c @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DDR3 driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Wu Zou + * Ryder Lee + */ + +#include +#include +#include +#include +#include +#include +#include + +/* EMI */ +#define EMI_CONA 0x000 +#define EMI_CONF 0x028 +#define EMI_CONM 0x060 + +/* DDR PHY */ +#define DDRPHY_PLL1 0x0000 +#define DDRPHY_PLL2 0x0004 +#define DDRPHY_PLL3 0x0008 +#define DDRPHY_PLL4 0x000c +#define DDRPHY_PLL5 0x0010 +#define DDRPHY_PLL7 0x0018 +#define DDRPHY_B0_DLL_ARPI0 0x0080 +#define DDRPHY_B0_DLL_ARPI1 0x0084 +#define DDRPHY_B0_DLL_ARPI2 0x0088 +#define DDRPHY_B0_DLL_ARPI3 0x008c +#define DDRPHY_B0_DLL_ARPI4 0x0090 +#define DDRPHY_B0_DLL_ARPI5 0x0094 +#define DDRPHY_B0_DQ2 0x00a0 +#define DDRPHY_B0_DQ3 0x00a4 +#define DDRPHY_B0_DQ4 0x00a8 +#define DDRPHY_B0_DQ5 0x00ac +#define DDRPHY_B0_DQ6 0x00b0 +#define DDRPHY_B0_DQ7 0x00b4 +#define DDRPHY_B0_DQ8 0x00b8 +#define DDRPHY_B1_DLL_ARPI0 0x0100 +#define DDRPHY_B1_DLL_ARPI1 0x0104 +#define DDRPHY_B1_DLL_ARPI2 0x0108 +#define DDRPHY_B1_DLL_ARPI3 0x010c +#define DDRPHY_B1_DLL_ARPI4 0x0110 +#define DDRPHY_B1_DLL_ARPI5 0x0114 +#define DDRPHY_B1_DQ2 0x0120 +#define DDRPHY_B1_DQ3 0x0124 +#define DDRPHY_B1_DQ4 0x0128 +#define DDRPHY_B1_DQ5 0x012c +#define DDRPHY_B1_DQ6 0x0130 +#define DDRPHY_B1_DQ7 0x0134 +#define DDRPHY_B1_DQ8 0x0138 +#define DDRPHY_CA_DLL_ARPI0 0x0180 +#define DDRPHY_CA_DLL_ARPI1 0x0184 +#define DDRPHY_CA_DLL_ARPI2 0x0188 +#define DDRPHY_CA_DLL_ARPI3 0x018c +#define DDRPHY_CA_DLL_ARPI4 0x0190 +#define DDRPHY_CA_DLL_ARPI5 0x0194 +#define DDRPHY_CA_CMD2 0x01a0 +#define DDRPHY_CA_CMD3 0x01a4 +#define DDRPHY_CA_CMD5 0x01ac +#define DDRPHY_CA_CMD6 0x01b0 +#define DDRPHY_CA_CMD7 0x01b4 +#define DDRPHY_CA_CMD8 0x01b8 +#define DDRPHY_MISC_VREF_CTRL 0x0264 +#define DDRPHY_MISC_IMP_CTRL0 0x0268 +#define DDRPHY_MISC_IMP_CTRL1 0x026c +#define DDRPHY_MISC_SHU_OPT 0x0270 +#define DDRPHY_MISC_SPM_CTRL0 0x0274 +#define DDRPHY_MISC_SPM_CTRL1 0x0278 +#define DDRPHY_MISC_SPM_CTRL2 0x027c +#define DDRPHY_MISC_CG_CTRL0 0x0284 +#define DDRPHY_MISC_CG_CTRL1 0x0288 +#define DDRPHY_MISC_CG_CTRL2 0x028c +#define DDRPHY_MISC_CG_CTRL4 0x0294 +#define DDRPHY_MISC_CTRL0 0x029c +#define DDRPHY_MISC_CTRL1 0x02a0 +#define DDRPHY_MISC_CTRL3 0x02a8 +#define DDRPHY_MISC_RXDVS1 0x05e4 +#define DDRPHY_SHU1_B0_DQ4 0x0c10 +#define DDRPHY_SHU1_B0_DQ5 0x0c14 +#define DDRPHY_SHU1_B0_DQ6 0x0c18 +#define DDRPHY_SHU1_B0_DQ7 0x0c1c +#define DDRPHY_SHU1_B1_DQ4 0x0c90 +#define DDRPHY_SHU1_B1_DQ5 0x0c94 +#define DDRPHY_SHU1_B1_DQ6 0x0c98 +#define DDRPHY_SHU1_B1_DQ7 0x0c9c +#define DDRPHY_SHU1_CA_CMD2 0x0d08 +#define DDRPHY_SHU1_CA_CMD4 0x0d10 +#define DDRPHY_SHU1_CA_CMD5 0x0d14 +#define DDRPHY_SHU1_CA_CMD6 0x0d18 +#define DDRPHY_SHU1_CA_CMD7 0x0d1c +#define DDRPHY_SHU1_PLL0 0x0d80 +#define DDRPHY_SHU1_PLL1 0x0d84 +#define DDRPHY_SHU1_PLL4 0x0d90 +#define DDRPHY_SHU1_PLL5 0x0d94 +#define DDRPHY_SHU1_PLL6 0x0d98 +#define DDRPHY_SHU1_PLL7 0x0d9C +#define DDRPHY_SHU1_PLL8 0x0da0 +#define DDRPHY_SHU1_PLL9 0x0da4 +#define DDRPHY_SHU1_PLL10 0x0da8 +#define DDRPHY_SHU1_PLL11 0x0dac +#define DDRPHY_SHU1_R0_B0_DQ2 0x0e08 +#define DDRPHY_SHU1_R0_B0_DQ3 0x0e0c +#define DDRPHY_SHU1_R0_B0_DQ4 0x0e10 +#define DDRPHY_SHU1_R0_B0_DQ5 0x0e14 +#define DDRPHY_SHU1_R0_B0_DQ6 0x0e18 +#define DDRPHY_SHU1_R0_B0_DQ7 0x0e1c +#define DDRPHY_SHU1_R0_B1_DQ2 0x0e58 +#define DDRPHY_SHU1_R0_B1_DQ3 0x0e5c +#define DDRPHY_SHU1_R0_B1_DQ4 0x0e60 +#define DDRPHY_SHU1_R0_B1_DQ5 0x0e64 +#define DDRPHY_SHU1_R0_B1_DQ6 0x0e68 +#define DDRPHY_SHU1_R0_B1_DQ7 0x0e6c +#define DDRPHY_SHU1_R0_CA_CMD9 0x0ec4 +#define DDRPHY_SHU1_R1_B0_DQ2 0x0f08 +#define DDRPHY_SHU1_R1_B0_DQ3 0x0f0c +#define DDRPHY_SHU1_R1_B0_DQ4 0x0f10 +#define DDRPHY_SHU1_R1_B0_DQ5 0x0f14 +#define DDRPHY_SHU1_R1_B0_DQ6 0x0f18 +#define DDRPHY_SHU1_R1_B0_DQ7 0x0f1c +#define DDRPHY_SHU1_R1_B1_DQ2 0x0f58 +#define DDRPHY_SHU1_R1_B1_DQ3 0x0f5c +#define DDRPHY_SHU1_R1_B1_DQ4 0x0f60 +#define DDRPHY_SHU1_R1_B1_DQ5 0x0f64 +#define DDRPHY_SHU1_R1_B1_DQ6 0x0f68 +#define DDRPHY_SHU1_R1_B1_DQ7 0x0f6c +#define DDRPHY_SHU1_R1_CA_CMD9 0x0fc4 + +/* DRAMC */ +#define DRAMC_DDRCONF0 0x0000 +#define DRAMC_DRAMCTRL 0x0004 +#define DRAMC_MISCTL0 0x0008 +#define DRAMC_PERFCTL0 0x000c +#define DRAMC_ARBCTL 0x0010 +#define DRAMC_RSTMASK 0x001c +#define DRAMC_PADCTRL 0x0020 +#define DRAMC_CKECTRL 0x0024 +#define DRAMC_RKCFG 0x0034 +#define DRAMC_DRAMC_PD_CTRL 0x0038 +#define DRAMC_CLKAR 0x003c +#define DRAMC_CLKCTRL 0x0040 +#define DRAMC_SREFCTRL 0x0048 +#define DRAMC_REFCTRL0 0x004c +#define DRAMC_REFCTRL1 0x0050 +#define DRAMC_REFRATRE_FILTER 0x0054 +#define DRAMC_ZQCS 0x0058 +#define DRAMC_MRS 0x005c +#define DRAMC_SPCMD 0x0060 +#define DRAMC_SPCMDCTRL 0x0064 +#define DRAMC_HW_MRR_FUN 0x0074 +#define DRAMC_TEST2_1 0x0094 +#define DRAMC_TEST2_2 0x0098 +#define DRAMC_TEST2_3 0x009c +#define DRAMC_TEST2_4 0x00a0 +#define DRAMC_CATRAINING1 0x00b0 +#define DRAMC_DUMMY_RD 0x00d0 +#define DRAMC_SHUCTRL 0x00d4 +#define DRAMC_SHUCTRL2 0x00dc +#define DRAMC_STBCAL 0x0200 +#define DRAMC_STBCAL1 0x0204 +#define DRAMC_EYESCAN 0x020c +#define DRAMC_DVFSDLL 0x0210 +#define DRAMC_SHU_ACTIM0 0x0800 +#define DRAMC_SHU_ACTIM1 0x0804 +#define DRAMC_SHU_ACTIM2 0x0808 +#define DRAMC_SHU_ACTIM3 0x080c +#define DRAMC_SHU_ACTIM4 0x0810 +#define DRAMC_SHU_ACTIM5 0x0814 +#define DRAMC_SHU_ACTIM_XRT 0x081c +#define DRAMC_SHU_AC_TIME_05T 0x0820 +#define DRAMC_SHU_CONF0 0x0840 +#define DRAMC_SHU_CONF1 0x0844 +#define DRAMC_SHU_CONF2 0x0848 +#define DRAMC_SHU_CONF3 0x084c +#define DRAMC_SHU_RANKCTL 0x0858 +#define DRAMC_SHU_CKECTRL 0x085c +#define DRAMC_SHU_ODTCTRL 0x0860 +#define DRAMC_SHU_PIPE 0x0878 +#define DRAMC_SHU_SELPH_CA1 0x0880 +#define DRAMC_SHU_SELPH_CA2 0x0884 +#define DRAMC_SHU_SELPH_CA3 0x0888 +#define DRAMC_SHU_SELPH_CA4 0x088c +#define DRAMC_SHU_SELPH_CA5 0x0890 +#define DRAMC_SHU_SELPH_CA6 0x0894 +#define DRAMC_SHU_SELPH_CA7 0x0898 +#define DRAMC_SHU_SELPH_CA8 0x089c +#define DRAMC_SHU_SELPH_DQS0 0x08a0 +#define DRAMC_SHU_SELPH_DQS1 0x08a4 +#define DRAMC_SHU1_DRVING1 0x08a8 +#define DRAMC_SHU1_DRVING2 0x08ac +#define DRAMC_SHU1_WODT 0x08c0 +#define DRAMC_SHU_SCINTV 0x08c8 +#define DRAMC_SHURK0_DQSCTL 0x0a00 +#define DRAMC_SHURK0_DQSIEN 0x0a04 +#define DRAMC_SHURK0_SELPH_ODTEN0 0x0a1c +#define DRAMC_SHURK0_SELPH_ODTEN1 0x0a20 +#define DRAMC_SHURK0_SELPH_DQSG0 0x0a24 +#define DRAMC_SHURK0_SELPH_DQSG1 0x0a28 +#define DRAMC_SHURK0_SELPH_DQ0 0x0a2c +#define DRAMC_SHURK0_SELPH_DQ1 0x0a30 +#define DRAMC_SHURK0_SELPH_DQ2 0x0a34 +#define DRAMC_SHURK0_SELPH_DQ3 0x0a38 +#define DRAMC_SHURK1_DQSCTL 0x0b00 +#define DRAMC_SHURK1_SELPH_ODTEN0 0x0b1c +#define DRAMC_SHURK1_SELPH_ODTEN1 0x0b20 +#define DRAMC_SHURK1_SELPH_DQSG0 0x0b24 +#define DRAMC_SHURK1_SELPH_DQSG1 0x0b28 +#define DRAMC_SHURK1_SELPH_DQ0 0x0b2c +#define DRAMC_SHURK1_SELPH_DQ1 0x0b30 +#define DRAMC_SHURK1_SELPH_DQ2 0x0b34 +#define DRAMC_SHURK1_SELPH_DQ3 0x0b38 +#define DRAMC_SHURK2_SELPH_ODTEN0 0x0c1c +#define DRAMC_SHURK2_SELPH_ODTEN1 0x0c20 +#define DRAMC_SHU_DQSG_RETRY 0x0c54 + +#define EMI_COL_ADDR_MASK GENMASK(13, 12) +#define EMI_COL_ADDR_SHIFT 12 +#define WALKING_PATTERN 0x12345678 +#define WALKING_STEP 0x4000000 + +struct mtk_ddr3_priv { + fdt_addr_t emi; + fdt_addr_t ddrphy; + fdt_addr_t dramc_ao; + struct clk phy; + struct clk phy_mux; + struct clk mem; + struct clk mem_mux; +}; + +#ifdef CONFIG_SPL_BUILD +static int mtk_ddr3_rank_size_detect(struct udevice *dev) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + int step; + u32 start, test; + + /* To detect size, we have to make sure it's single rank + * and it has maximum addressing region + */ + + writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE); + + if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN) + return -EINVAL; + + for (step = 0; step < 5; step++) { + writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE + + (WALKING_STEP << step)); + + start = readl(CONFIG_SYS_SDRAM_BASE); + test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step)); + if ((test != ~WALKING_PATTERN) || test == start) + break; + } + + step = step ? step - 1 : 3; + clrsetbits_le32(priv->emi + EMI_CONA, EMI_COL_ADDR_MASK, + step << EMI_COL_ADDR_SHIFT); + + return 0; +} + +static int mtk_ddr3_init(struct udevice *dev) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_set_parent(&priv->phy, &priv->phy_mux); + if (ret) + return ret; + + /* EMI Setting */ + writel(0x00003010, priv->emi + EMI_CONA); + writel(0x00000000, priv->emi + EMI_CONF); + writel(0x000006b8, priv->emi + EMI_CONM); + /* DQS */ + writel(0x20c00, priv->dramc_ao + DRAMC_SHU1_DRVING1); + /* Clock */ + writel(0x8320c83, priv->dramc_ao + DRAMC_SHU1_DRVING2); + + /* DDRPHY setting */ + writel(0x2201, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL); + writel(0xe08, priv->ddrphy + DDRPHY_CA_CMD5); + writel(0x60e, priv->ddrphy + DDRPHY_SHU1_CA_CMD5); + writel(0x0, priv->ddrphy + DDRPHY_MISC_SPM_CTRL1); + writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL0); + writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL2); + writel(0x6003bf, priv->ddrphy + DDRPHY_MISC_CG_CTRL2); + writel(0x13300000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4); + + writel(0x1, priv->ddrphy + DDRPHY_SHU1_CA_CMD7); + writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7); + writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7); + writel(0xfff0, priv->ddrphy + DDRPHY_CA_CMD2); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); + writel(0x0, priv->ddrphy + DDRPHY_B1_DQ2); + writel(0x7, priv->ddrphy + DDRPHY_MISC_RXDVS1); + writel(0x10, priv->ddrphy + DDRPHY_PLL3); + writel(0x8e8e0000, priv->ddrphy + DDRPHY_MISC_VREF_CTRL); + writel(0x2e0040, priv->ddrphy + DDRPHY_MISC_IMP_CTRL0); + writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); + writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5); + udelay(1); + + writel(0x10, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0x10, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x3f600, priv->ddrphy + DDRPHY_MISC_CG_CTRL1); + writel(0x1010, priv->ddrphy + DDRPHY_B0_DQ4); + writel(0x1110e0e, priv->ddrphy + DDRPHY_B0_DQ5); + writel(0x10c10d0, priv->ddrphy + DDRPHY_B0_DQ6); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5); + writel(0x1010, priv->ddrphy + DDRPHY_B1_DQ4); + writel(0x1110e0e, priv->ddrphy + DDRPHY_B1_DQ5); + writel(0x10c10d0, priv->ddrphy + DDRPHY_B1_DQ6); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5); + writel(0x7fffffc, priv->ddrphy + DDRPHY_CA_CMD3); + writel(0xc0010, priv->ddrphy + DDRPHY_CA_CMD6); + writel(0x101, priv->ddrphy + DDRPHY_SHU1_CA_CMD2); + writel(0x41e, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0x41e, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x180101, priv->ddrphy + DDRPHY_CA_CMD8); + writel(0x0, priv->ddrphy + DDRPHY_MISC_IMP_CTRL1); + writel(0x11400000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4); + writel(0xfff0f0f0, priv->ddrphy + DDRPHY_MISC_SHU_OPT); + writel(0x1f, priv->ddrphy + DDRPHY_MISC_CG_CTRL0); + + writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); + writel(0x40000, priv->ddrphy + DDRPHY_PLL4); + writel(0x0, priv->ddrphy + DDRPHY_PLL1); + writel(0x0, priv->ddrphy + DDRPHY_PLL2); + writel(0x666008, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); + writel(0x80666008, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); + writel(0x80666008, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); + writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0x400, priv->ddrphy + DDRPHY_CA_DLL_ARPI2); + writel(0x20400, priv->ddrphy + DDRPHY_B0_DLL_ARPI2); + writel(0x20400, priv->ddrphy + DDRPHY_B1_DLL_ARPI2); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL9); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL11); + writel(0xf7f, priv->ddrphy + DDRPHY_SHU1_PLL0); + writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL8); + writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL10); + writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL4); + writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL6); + + writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL5); + writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL7); + + writel(0x14d0002, priv->ddrphy + DDRPHY_PLL5); + writel(0x14d0002, priv->ddrphy + DDRPHY_PLL7); + writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL8); + writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL10); + writel(0xf, priv->ddrphy + DDRPHY_SHU1_PLL1); + writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0x698600, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); + writel(0xc0778600, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); + writel(0xc0778600, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); + writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI4); + writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI4); + writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI4); + writel(0x2ba800, priv->ddrphy + DDRPHY_CA_DLL_ARPI1); + writel(0x2ae806, priv->ddrphy + DDRPHY_B0_DLL_ARPI1); + writel(0xae806, priv->ddrphy + DDRPHY_B1_DLL_ARPI1); + writel(0xba000, priv->ddrphy + DDRPHY_CA_DLL_ARPI3); + writel(0x2e800, priv->ddrphy + DDRPHY_B0_DLL_ARPI3); + writel(0x2e800, priv->ddrphy + DDRPHY_B1_DLL_ARPI3); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD4); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ4); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ4); + writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0x32cf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); + writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); + writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); + writel(0x80010000, priv->ddrphy + DDRPHY_PLL1); + writel(0x80000000, priv->ddrphy + DDRPHY_PLL2); + udelay(100); + + writel(0xc, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x9, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x9, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0xd0000, priv->ddrphy + DDRPHY_PLL4); + udelay(1); + + writel(0x82, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x2, priv->dramc_ao + DRAMC_DDRCONF0); + writel(0x3acf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); + writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); + writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); + udelay(1); + + writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI2); + writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI2); + writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI2); + writel(0x80, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x0, priv->dramc_ao + DRAMC_DDRCONF0); + writel(0x80000000, priv->ddrphy + DDRPHY_PLL1); + udelay(1); + + writel(0x698e00, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); + udelay(1); + + writel(0xc0778e00, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); + udelay(1); + + writel(0xc0778e00, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); + udelay(1); + + ret = clk_set_parent(&priv->mem, &priv->mem_mux); + if (ret) + return ret; + + /* DDR PHY PLL setting */ + writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0x51e, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x80101, priv->ddrphy + DDRPHY_CA_CMD8); + writel(0x100, priv->ddrphy + DDRPHY_CA_CMD7); + writel(0x0, priv->ddrphy + DDRPHY_CA_CMD7); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ7); + writel(0x0, priv->ddrphy + DDRPHY_B1_DQ7); + writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0xff051e, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); + writel(0x1ff, priv->ddrphy + DDRPHY_B1_DQ2); + + /* Update initial setting */ + writel(0x5fc, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0xff05fc, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x10c12d9, priv->ddrphy + DDRPHY_B0_DQ6); + writel(0x10c12d9, priv->ddrphy + DDRPHY_B1_DQ6); + writel(0xc0259, priv->ddrphy + DDRPHY_CA_CMD6); + writel(0x4000, priv->ddrphy + DDRPHY_B0_DQ2); + writel(0x41ff, priv->ddrphy + DDRPHY_B1_DQ2); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ8); + writel(0x100, priv->ddrphy + DDRPHY_B1_DQ8); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5); + writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); + writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5); + writel(0x39eff6, priv->dramc_ao + DRAMC_SHU_SCINTV); + writel(0x204ffff, priv->dramc_ao + DRAMC_CLKAR); + writel(0x31b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x0, priv->dramc_ao + DRAMC_PERFCTL0); + writel(0x80000, priv->dramc_ao + DRAMC_PERFCTL0); + + /* Dramc setting PC3 */ + writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0); + + writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3); + writel(0x200600, priv->dramc_ao + DRAMC_SHU_DQSG_RETRY); + writel(0x101d007, priv->dramc_ao + DRAMC_SHUCTRL2); + writel(0xe090601, priv->dramc_ao + DRAMC_DVFSDLL); + writel(0x20003000, priv->dramc_ao + DRAMC_DDRCONF0); + writel(0x3900020f, priv->ddrphy + DDRPHY_MISC_CTRL0); + writel(0xa20810bf, priv->dramc_ao + DRAMC_SHU_CONF0); + writel(0x30050, priv->dramc_ao + DRAMC_SHU_ODTCTRL); + writel(0x25712000, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0xb0100000, priv->dramc_ao + DRAMC_STBCAL); + writel(0x8000000, priv->dramc_ao + DRAMC_SREFCTRL); + writel(0xc0000000, priv->dramc_ao + DRAMC_SHU_PIPE); + writel(0x731004, priv->dramc_ao + DRAMC_RKCFG); + writel(0x8007320f, priv->dramc_ao + DRAMC_SHU_CONF2); + writel(0x2a7c0, priv->dramc_ao + DRAMC_SHU_SCINTV); + writel(0xc110, priv->dramc_ao + DRAMC_SHUCTRL); + writel(0x30000700, priv->dramc_ao + DRAMC_REFCTRL1); + writel(0x6543b321, priv->dramc_ao + DRAMC_REFRATRE_FILTER); + + /* Update PCDDR3 default setting */ + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA1); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA2); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA3); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA4); + writel(0x10000111, priv->dramc_ao + DRAMC_SHU_SELPH_CA5); + writel(0x1000000, priv->dramc_ao + DRAMC_SHU_SELPH_CA6); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA7); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA8); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_CA_CMD9); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_CA_CMD9); + writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0); + writel(0x33331111, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ0); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ1); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ2); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ3); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ7); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ7); + writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN0); + writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN1); + writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN0); + writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN1); + writel(0x0, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN0); + writel(0x66666666, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN1); + writel(0x2c000b0f, priv->dramc_ao + DRAMC_SHU_CONF1); + writel(0x11111111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0); + writel(0x64646464, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1); + writel(0x11111111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG0); + writel(0x64646464, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG1); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ6); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ6); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ6); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ6); + writel(0x20000001, priv->dramc_ao + DRAMC_SHU_RANKCTL); + writel(0x2, priv->dramc_ao + DRAMC_SHURK0_DQSCTL); + writel(0x2, priv->dramc_ao + DRAMC_SHURK1_DQSCTL); + writel(0x4020b07, priv->dramc_ao + DRAMC_SHU_ACTIM0); + writel(0xb060400, priv->dramc_ao + DRAMC_SHU_ACTIM1); + writel(0x8090200, priv->dramc_ao + DRAMC_SHU_ACTIM2); + writel(0x810018, priv->dramc_ao + DRAMC_SHU_ACTIM3); + writel(0x1e9700ff, priv->dramc_ao + DRAMC_SHU_ACTIM4); + writel(0x1000908, priv->dramc_ao + DRAMC_SHU_ACTIM5); + writel(0x801040b, priv->dramc_ao + DRAMC_SHU_ACTIM_XRT); + writel(0x20000D1, priv->dramc_ao + DRAMC_SHU_AC_TIME_05T); + writel(0x80010000, priv->ddrphy + DDRPHY_PLL2); + udelay(500); + + writel(0x81080000, priv->dramc_ao + DRAMC_MISCTL0); + writel(0xacf13, priv->dramc_ao + DRAMC_PERFCTL0); + writel(0xacf12, priv->dramc_ao + DRAMC_PERFCTL0); + writel(0x80, priv->dramc_ao + DRAMC_ARBCTL); + writel(0x9, priv->dramc_ao + DRAMC_PADCTRL); + writel(0x80000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); + writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL); + writel(0x25714001, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x4300000, priv->dramc_ao + DRAMC_CATRAINING1); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0x731414, priv->dramc_ao + DRAMC_RKCFG); + writel(0x733414, priv->dramc_ao + DRAMC_RKCFG); + udelay(20); + + writel(0x80002050, priv->dramc_ao + DRAMC_CKECTRL); + udelay(100); + + writel(0x400000, priv->dramc_ao + DRAMC_MRS); + writel(0x401800, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x601800, priv->dramc_ao + DRAMC_MRS); + writel(0x600000, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x200000, priv->dramc_ao + DRAMC_MRS); + writel(0x200400, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x400, priv->dramc_ao + DRAMC_MRS); + writel(0x1d7000, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x702201, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x10, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + writel(0x20, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + writel(0x1, priv->dramc_ao + DRAMC_HW_MRR_FUN); + writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0xa56, priv->dramc_ao + DRAMC_ZQCS); + writel(0xff0000, priv->dramc_ao + DRAMC_SHU_CONF3); + writel(0x15b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x2cb00b0f, priv->dramc_ao + DRAMC_SHU_CONF1); + writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0x48000000, priv->dramc_ao + DRAMC_SREFCTRL); + writel(0xc0000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); + writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN); + writel(0x15e00, priv->dramc_ao + DRAMC_STBCAL1); + writel(0x100000, priv->dramc_ao + DRAMC_TEST2_1); + writel(0x4000, priv->dramc_ao + DRAMC_TEST2_2); + writel(0x12000480, priv->dramc_ao + DRAMC_TEST2_3); + writel(0x301d007, priv->dramc_ao + DRAMC_SHUCTRL2); + writel(0x4782321, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x30210000, priv->dramc_ao + DRAMC_SHU_CKECTRL); + writel(0x20000, priv->dramc_ao + DRAMC_DUMMY_RD); + writel(0x4080110d, priv->dramc_ao + DRAMC_TEST2_4); + writel(0x30000721, priv->dramc_ao + DRAMC_REFCTRL1); + writel(0x0, priv->dramc_ao + DRAMC_RSTMASK); + writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x80002000, priv->dramc_ao + DRAMC_CKECTRL); + writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0); + + /* Apply config before calibration */ + writel(0x120, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); + writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3); + writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_CG_CTRL0); + writel(0x2a7fe, priv->dramc_ao + DRAMC_SHU_SCINTV); + writel(0xff01ff, priv->dramc_ao + DRAMC_SHU_CONF3); + writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0xa56, priv->dramc_ao + DRAMC_ZQCS); + writel(0x80000000, priv->dramc_ao + DRAMC_SHU1_WODT); + writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7); + writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN); + writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + + /* Write leveling */ + writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); + writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); + writel(0x33221100, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1); + writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0); + + /* RX dqs gating cal */ + writel(0x11111010, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0); + writel(0x20201717, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1); + writel(0x1d1f, priv->dramc_ao + DRAMC_SHURK0_DQSIEN); + + /* RX window per-bit cal */ + writel(0x03030404, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2); + writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3); + writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4); + writel(0x01010000, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5); + writel(0x03030606, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2); + writel(0x02020202, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3); + writel(0x04040303, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4); + writel(0x06060101, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5); + + /* RX datlat cal */ + writel(0x28b00a0e, priv->dramc_ao + DRAMC_SHU_CONF1); + + /* TX window per-byte with 2UI cal */ + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0); + writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1); + writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3); + writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); + writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); + + return mtk_ddr3_rank_size_detect(dev); +} +#endif + +static int mtk_ddr3_probe(struct udevice *dev) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + + priv->emi = dev_read_addr_index(dev, 0); + if (priv->emi == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->ddrphy = dev_read_addr_index(dev, 1); + if (priv->ddrphy == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->dramc_ao = dev_read_addr_index(dev, 2); + if (priv->dramc_ao == FDT_ADDR_T_NONE) + return -EINVAL; + +#ifdef CONFIG_SPL_BUILD + int ret; + + ret = clk_get_by_index(dev, 0, &priv->phy); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &priv->phy_mux); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 2, &priv->mem); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 3, &priv->mem_mux); + if (ret) + return ret; + + ret = mtk_ddr3_init(dev); + if (ret) + return ret; +#endif + return 0; +} + +static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + u32 val = readl(priv->emi + EMI_CONA); + + info->base = CONFIG_SYS_SDRAM_BASE; + + switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) { + case 0: + info->size = SZ_128M; + break; + case 1: + info->size = SZ_256M; + break; + case 2: + info->size = SZ_512M; + break; + case 3: + info->size = SZ_1G; + break; + default: + return -EINVAL; + } + + return 0; +} + +static struct ram_ops mtk_ddr3_ops = { + .get_info = mtk_ddr3_get_info, +}; + +static const struct udevice_id mtk_ddr3_ids[] = { + { .compatible = "mediatek,mt7629-dramc" }, + { } +}; + +U_BOOT_DRIVER(mediatek_ddr3) = { + .name = "mediatek_ddr3", + .id = UCLASS_RAM, + .of_match = mtk_ddr3_ids, + .ops = &mtk_ddr3_ops, + .probe = mtk_ddr3_probe, + .priv_auto = sizeof(struct mtk_ddr3_priv), +}; diff --git a/roms/u-boot/drivers/ram/mpc83xx_sdram.c b/roms/u-boot/drivers/ram/mpc83xx_sdram.c new file mode 100644 index 000000000..a53ff93a6 --- /dev/null +++ b/roms/u-boot/drivers/ram/mpc83xx_sdram.c @@ -0,0 +1,1100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Masks for the CS config register */ +static const u32 CSCONFIG_ENABLE = 0x80000000; + +static const u32 BANK_BITS_2; +static const u32 BANK_BITS_3 = 0x00004000; + +static const u32 ROW_BITS_12; +static const u32 ROW_BITS_13 = 0x00000100; +static const u32 ROW_BITS_14 = 0x00000200; + +static const u32 COL_BITS_8; +static const u32 COL_BITS_9 = 0x00000001; +static const u32 COL_BITS_10 = 0x00000002; +static const u32 COL_BITS_11 = 0x00000003; + +/* Shifts for the DDR SDRAM Timing Configuration 3 register */ +static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15); + +/* Shifts for the DDR SDRAM Timing Configuration 0 register */ +static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1); +static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3); +static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5); +static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7); +static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11); +static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15); +static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23); +static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Timing Configuration 1 register */ +static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3); +static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7); +static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11); +static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15); +static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19); +static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23); +static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27); +static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Timing Configuration 2 register */ +static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8); +static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21); +static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3); +static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12); +static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18); +static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25); +static const uint TIMING_CFG2_FOUR_ACT_SHIFT; + +/* Shifts for the DDR SDRAM Control Configuration register */ +static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1); +static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2); +static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3); +static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7); +static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10); +static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12); +static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14); +static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16); +static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23); +static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27); +static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28); +static const uint SDRAM_CFG_BI_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Control Configuration 2 register */ +static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0); +static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2); +static const uint SDRAM_CFG2_DQS_CFG = (31 - 5); +static const uint SDRAM_CFG2_ODT_CFG = (31 - 10); +static const uint SDRAM_CFG2_NUM_PR = (31 - 19); + +/* Shifts for the DDR SDRAM Mode register */ +static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15); +static const uint SDRAM_MODE_SD_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Mode 2 register */ +static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15); +static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Interval Configuration register */ +static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15); +static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31); + +/* Mask for the DDR SDRAM Mode Control register */ +static const u32 SDRAM_CFG_MEM_EN = 0x80000000; + +int dram_init(void) +{ + struct udevice *ram_ctrl; + int ret; + + /* Current assumption: There is only one RAM controller */ + ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl); + if (ret) { + debug("%s: uclass_first_device_err failed: %d\n", + __func__, ret); + return ret; + } + + /* FIXME(mario.six@gdsys.cc): Set gd->ram_size? */ + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + if (!IS_ENABLED(CONFIG_VERY_BIG_RAM)) + return gd->ram_size; + + /* Limit stack to what we can reasonable map */ + return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size); +} + +/** + * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers + * @total_size: The total size of all RAM modules associated with this RAM + * controller in bytes + */ +struct mpc83xx_sdram_priv { + ulong total_size; +}; + +/** + * mpc83xx_sdram_static_init() - Statically initialize a RAM module. + * @node: Device tree node associated with ths module in question + * @cs: The chip select to use for this RAM module + * @mapaddr: The address where the RAM module should be mapped + * @size: The size of the RAM module to be mapped in bytes + * + * Return: 0 if OK, -ve on error + */ +static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = size; + u32 msize_log2 = __ilog2(msize); + u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits, + col_bits; + u32 bank_bits_mask, row_bits_mask, col_bits_mask; + + /* Configure the DDR local access window */ + out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1)); + + out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24); + + auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0); + switch (auto_precharge) { + case AUTO_PRECHARGE_ENABLE: + case AUTO_PRECHARGE_DISABLE: + break; + default: + debug("%s: auto_precharge value %d invalid.\n", + ofnode_get_name(node), auto_precharge); + return -EINVAL; + } + + odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0); + switch (odt_rd_cfg) { + case ODT_RD_ONLY_OTHER_DIMM: + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + debug("%s: odt_rd_cfg value %d invalid.\n", + ofnode_get_name(node), odt_rd_cfg); + return -EINVAL; + } + /* fall through */ + case ODT_RD_NEVER: + case ODT_RD_ONLY_CURRENT: + case ODT_RD_ONLY_OTHER_CS: + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + debug("%s: odt_rd_cfg value %d invalid.\n", + ofnode_get_name(node), odt_rd_cfg); + return -EINVAL; + } + /* fall through */ + /* Only MPC832x knows this value */ + case ODT_RD_ALL: + break; + default: + debug("%s: odt_rd_cfg value %d invalid.\n", + ofnode_get_name(node), odt_rd_cfg); + return -EINVAL; + } + + odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0); + switch (odt_wr_cfg) { + case ODT_WR_ONLY_OTHER_DIMM: + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + debug("%s: odt_wr_cfg value %d invalid.\n", + ofnode_get_name(node), odt_wr_cfg); + return -EINVAL; + } + /* fall through */ + case ODT_WR_NEVER: + case ODT_WR_ONLY_CURRENT: + case ODT_WR_ONLY_OTHER_CS: + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + debug("%s: odt_wr_cfg value %d invalid.\n", + ofnode_get_name(node), odt_wr_cfg); + return -EINVAL; + } + /* fall through */ + /* MPC832x only knows this value */ + case ODT_WR_ALL: + break; + default: + debug("%s: odt_wr_cfg value %d invalid.\n", + ofnode_get_name(node), odt_wr_cfg); + return -EINVAL; + } + + bank_bits = ofnode_read_u32_default(node, "bank_bits", 0); + switch (bank_bits) { + case 2: + bank_bits_mask = BANK_BITS_2; + break; + case 3: + bank_bits_mask = BANK_BITS_3; + break; + default: + debug("%s: bank_bits value %d invalid.\n", + ofnode_get_name(node), bank_bits); + return -EINVAL; + } + + row_bits = ofnode_read_u32_default(node, "row_bits", 0); + switch (row_bits) { + case 12: + row_bits_mask = ROW_BITS_12; + break; + case 13: + row_bits_mask = ROW_BITS_13; + break; + case 14: + row_bits_mask = ROW_BITS_14; + break; + default: + debug("%s: row_bits value %d invalid.\n", + ofnode_get_name(node), row_bits); + return -EINVAL; + } + + col_bits = ofnode_read_u32_default(node, "col_bits", 0); + switch (col_bits) { + case 8: + col_bits_mask = COL_BITS_8; + break; + case 9: + col_bits_mask = COL_BITS_9; + break; + case 10: + col_bits_mask = COL_BITS_10; + break; + case 11: + col_bits_mask = COL_BITS_11; + break; + default: + debug("%s: col_bits value %d invalid.\n", + ofnode_get_name(node), col_bits); + return -EINVAL; + } + + /* Write CS config value */ + out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge | + odt_rd_cfg | odt_wr_cfg | + bank_bits_mask | row_bits_mask | + col_bits_mask); + return 0; +} + +/** + * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash. + * @node: Device tree node associated with ths module in question + * @cs: The chip select to use for this RAM module + * @mapaddr: The address where the RAM module should be mapped + * @size: The size of the RAM module to be mapped in bytes + * + * Return: 0 if OK, -ve on error + */ +static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size) +{ + /* TODO(mario.six@gdsys.cc): Implement */ + return 0; +} + +static int mpc83xx_sdram_of_to_plat(struct udevice *dev) +{ + return 0; +} + +static int mpc83xx_sdram_probe(struct udevice *dev) +{ + struct mpc83xx_sdram_priv *priv = dev_get_priv(dev); + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + int ret = 0; + ofnode subnode; + /* DDR control driver register values */ + u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr; + u32 ddrcdr; + /* DDR SDRAM Clock Control register values */ + u32 clock_adjust; + /* DDR SDRAM Timing Configuration 3 register values */ + u32 ext_refresh_rec, ext_refresh_rec_mask; + /* DDR SDRAM Timing Configuration 0 register values */ + u32 read_to_write, write_to_read, read_to_read, write_to_write, + active_powerdown_exit, precharge_powerdown_exit, + odt_powerdown_exit, mode_reg_set_cycle; + u32 timing_cfg_0; + /* DDR SDRAM Timing Configuration 1 register values */ + u32 precharge_to_activate, activate_to_precharge, + activate_to_readwrite, mcas_latency, refresh_recovery, + last_data_to_precharge, activate_to_activate, + last_write_data_to_read; + u32 timing_cfg_1; + /* DDR SDRAM Timing Configuration 2 register values */ + u32 additive_latency, mcas_to_preamble_override, write_latency, + read_to_precharge, write_cmd_to_write_data, + minimum_cke_pulse_width, four_activates_window; + u32 timing_cfg_2; + /* DDR SDRAM Control Configuration register values */ + u32 self_refresh, ecc, registered_dram, sdram_type, + dynamic_power_management, databus_width, nc_auto_precharge, + timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength, + bypass_initialization; + u32 sdram_cfg; + /* DDR SDRAM Control Configuration 2 register values */ + u32 force_self_refresh, dll_reset, dqs_config, odt_config, + posted_refreshes; + u32 sdram_cfg2; + /* DDR SDRAM Mode Configuration register values */ + u32 sdmode, esdmode; + u32 sdram_mode; + /* DDR SDRAM Mode Configuration 2 register values */ + u32 esdmode2, esdmode3; + u32 sdram_mode2; + /* DDR SDRAM Interval Configuration register values */ + u32 refresh_interval, precharge_interval; + u32 sdram_interval; + + priv->total_size = 0; + + /* Disable both banks initially (might be re-enabled in loop below) */ + out_be32(&im->ddr.cs_config[0], 0); + out_be32(&im->ddr.cs_config[1], 0); + + dso = dev_read_u32_default(dev, "driver_software_override", 0); + if (dso > 1) { + debug("%s: driver_software_override value %d invalid.\n", + dev->name, dso); + return -EINVAL; + } + + pz_override = dev_read_u32_default(dev, "p_impedance_override", 0); + + switch (pz_override) { + case DSO_P_IMPEDANCE_HIGHEST_Z: + case DSO_P_IMPEDANCE_MUCH_HIGHER_Z: + case DSO_P_IMPEDANCE_HIGHER_Z: + case DSO_P_IMPEDANCE_NOMINAL: + case DSO_P_IMPEDANCE_LOWER_Z: + break; + default: + debug("%s: p_impedance_override value %d invalid.\n", + dev->name, pz_override); + return -EINVAL; + } + + nz_override = dev_read_u32_default(dev, "n_impedance_override", 0); + + switch (nz_override) { + case DSO_N_IMPEDANCE_HIGHEST_Z: + case DSO_N_IMPEDANCE_MUCH_HIGHER_Z: + case DSO_N_IMPEDANCE_HIGHER_Z: + case DSO_N_IMPEDANCE_NOMINAL: + case DSO_N_IMPEDANCE_LOWER_Z: + break; + default: + debug("%s: n_impedance_override value %d invalid.\n", + dev->name, nz_override); + return -EINVAL; + } + + odt_term = dev_read_u32_default(dev, "odt_termination_value", 0); + if (odt_term > 1) { + debug("%s: odt_termination_value value %d invalid.\n", + dev->name, odt_term); + return -EINVAL; + } + + ddr_type = dev_read_u32_default(dev, "ddr_type", 0); + if (ddr_type > 1) { + debug("%s: ddr_type value %d invalid.\n", + dev->name, ddr_type); + return -EINVAL; + } + + mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0); + if (mvref_sel > 1) { + debug("%s: mvref_sel value %d invalid.\n", + dev->name, mvref_sel); + return -EINVAL; + } + + m_odr = dev_read_u32_default(dev, "m_odr", 0); + if (mvref_sel > 1) { + debug("%s: m_odr value %d invalid.\n", + dev->name, m_odr); + return -EINVAL; + } + + ddrcdr = dso << (31 - 1) | + pz_override << (31 - 5) | + nz_override << (31 - 9) | + odt_term << (31 - 12) | + ddr_type << (31 - 13) | + mvref_sel << (31 - 29) | + m_odr << (31 - 30) | 1; + + /* Configure the DDR control driver register */ + out_be32(&im->sysconf.ddrcdr, ddrcdr); + + dev_for_each_subnode(subnode, dev) { + u32 val[3]; + u32 cs, addr, size; + + /* CS, map address, size -> three values */ + ofnode_read_u32_array(subnode, "reg", val, 3); + + cs = val[0]; + addr = val[1]; + size = val[2]; + + if (cs > 1) { + debug("%s: chip select value %d invalid.\n", + dev->name, cs); + return -EINVAL; + } + + /* TODO(mario.six@gdsys.cc): Sanity check for size. */ + + if (ofnode_read_bool(subnode, "read-spd")) + ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size); + else + ret = mpc83xx_sdram_static_init(subnode, cs, addr, + size); + if (ret) { + debug("%s: RAM init failed.\n", dev->name); + return ret; + } + }; + + /* + * TODO(mario.six@gdsys.cc): This should only occur for static + * configuration + */ + + clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0); + switch (clock_adjust) { + case CLOCK_ADJUST_025: + case CLOCK_ADJUST_05: + case CLOCK_ADJUST_075: + case CLOCK_ADJUST_1: + break; + default: + debug("%s: clock_adjust value %d invalid.\n", + dev->name, clock_adjust); + return -EINVAL; + } + + /* Configure the DDR SDRAM Clock Control register */ + out_be32(&im->ddr.sdram_clk_cntl, clock_adjust); + + ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0); + switch (ext_refresh_rec) { + case 0: + ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 16: + ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 32: + ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 48: + ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 64: + ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 80: + ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 96: + ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 112: + ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + default: + debug("%s: ext_refresh_rec value %d invalid.\n", + dev->name, ext_refresh_rec); + return -EINVAL; + } + + /* Configure the DDR SDRAM Timing Configuration 3 register */ + out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask); + + read_to_write = dev_read_u32_default(dev, "read_to_write", 0); + if (read_to_write > 3) { + debug("%s: read_to_write value %d invalid.\n", + dev->name, read_to_write); + return -EINVAL; + } + + write_to_read = dev_read_u32_default(dev, "write_to_read", 0); + if (write_to_read > 3) { + debug("%s: write_to_read value %d invalid.\n", + dev->name, write_to_read); + return -EINVAL; + } + + read_to_read = dev_read_u32_default(dev, "read_to_read", 0); + if (read_to_read > 3) { + debug("%s: read_to_read value %d invalid.\n", + dev->name, read_to_read); + return -EINVAL; + } + + write_to_write = dev_read_u32_default(dev, "write_to_write", 0); + if (write_to_write > 3) { + debug("%s: write_to_write value %d invalid.\n", + dev->name, write_to_write); + return -EINVAL; + } + + active_powerdown_exit = + dev_read_u32_default(dev, "active_powerdown_exit", 0); + if (active_powerdown_exit > 7) { + debug("%s: active_powerdown_exit value %d invalid.\n", + dev->name, active_powerdown_exit); + return -EINVAL; + } + + precharge_powerdown_exit = + dev_read_u32_default(dev, "precharge_powerdown_exit", 0); + if (precharge_powerdown_exit > 7) { + debug("%s: precharge_powerdown_exit value %d invalid.\n", + dev->name, precharge_powerdown_exit); + return -EINVAL; + } + + odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0); + if (odt_powerdown_exit > 15) { + debug("%s: odt_powerdown_exit value %d invalid.\n", + dev->name, odt_powerdown_exit); + return -EINVAL; + } + + mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0); + if (mode_reg_set_cycle > 15) { + debug("%s: mode_reg_set_cycle value %d invalid.\n", + dev->name, mode_reg_set_cycle); + return -EINVAL; + } + + timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT | + write_to_read << TIMING_CFG0_WRT_SHIFT | + read_to_read << TIMING_CFG0_RRT_SHIFT | + write_to_write << TIMING_CFG0_WWT_SHIFT | + active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT | + precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT | + odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT | + mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT; + + out_be32(&im->ddr.timing_cfg_0, timing_cfg_0); + + precharge_to_activate = + dev_read_u32_default(dev, "precharge_to_activate", 0); + if (precharge_to_activate > 7 || precharge_to_activate == 0) { + debug("%s: precharge_to_activate value %d invalid.\n", + dev->name, precharge_to_activate); + return -EINVAL; + } + + activate_to_precharge = + dev_read_u32_default(dev, "activate_to_precharge", 0); + if (activate_to_precharge > 19) { + debug("%s: activate_to_precharge value %d invalid.\n", + dev->name, activate_to_precharge); + return -EINVAL; + } + + activate_to_readwrite = + dev_read_u32_default(dev, "activate_to_readwrite", 0); + if (activate_to_readwrite > 7 || activate_to_readwrite == 0) { + debug("%s: activate_to_readwrite value %d invalid.\n", + dev->name, activate_to_readwrite); + return -EINVAL; + } + + mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0); + switch (mcas_latency) { + case CASLAT_20: + case CASLAT_25: + if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) { + debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n", + dev->name); + return -EINVAL; + } + /* fall through */ + case CASLAT_30: + case CASLAT_35: + case CASLAT_40: + case CASLAT_45: + case CASLAT_50: + case CASLAT_55: + case CASLAT_60: + case CASLAT_65: + case CASLAT_70: + case CASLAT_75: + case CASLAT_80: + break; + default: + debug("%s: mcas_latency value %d invalid.\n", + dev->name, mcas_latency); + return -EINVAL; + } + + refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0); + if (refresh_recovery > 23 || refresh_recovery < 8) { + debug("%s: refresh_recovery value %d invalid.\n", + dev->name, refresh_recovery); + return -EINVAL; + } + + last_data_to_precharge = + dev_read_u32_default(dev, "last_data_to_precharge", 0); + if (last_data_to_precharge > 7 || last_data_to_precharge == 0) { + debug("%s: last_data_to_precharge value %d invalid.\n", + dev->name, last_data_to_precharge); + return -EINVAL; + } + + activate_to_activate = + dev_read_u32_default(dev, "activate_to_activate", 0); + if (activate_to_activate > 7 || activate_to_activate == 0) { + debug("%s: activate_to_activate value %d invalid.\n", + dev->name, activate_to_activate); + return -EINVAL; + } + + last_write_data_to_read = + dev_read_u32_default(dev, "last_write_data_to_read", 0); + if (last_write_data_to_read > 7 || last_write_data_to_read == 0) { + debug("%s: last_write_data_to_read value %d invalid.\n", + dev->name, last_write_data_to_read); + return -EINVAL; + } + + timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT | + (activate_to_precharge > 15 ? + activate_to_precharge - 16 : + activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT | + activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT | + mcas_latency << TIMING_CFG1_CASLAT_SHIFT | + (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT | + last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT | + activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT | + last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT; + + /* Configure the DDR SDRAM Timing Configuration 1 register */ + out_be32(&im->ddr.timing_cfg_1, timing_cfg_1); + + additive_latency = dev_read_u32_default(dev, "additive_latency", 0); + if (additive_latency > 5) { + debug("%s: additive_latency value %d invalid.\n", + dev->name, additive_latency); + return -EINVAL; + } + + mcas_to_preamble_override = + dev_read_u32_default(dev, "mcas_to_preamble_override", 0); + switch (mcas_to_preamble_override) { + case READ_LAT_PLUS_1: + case READ_LAT: + case READ_LAT_PLUS_1_4: + case READ_LAT_PLUS_1_2: + case READ_LAT_PLUS_3_4: + case READ_LAT_PLUS_5_4: + case READ_LAT_PLUS_3_2: + case READ_LAT_PLUS_7_4: + case READ_LAT_PLUS_2: + case READ_LAT_PLUS_9_4: + case READ_LAT_PLUS_5_2: + case READ_LAT_PLUS_11_4: + case READ_LAT_PLUS_3: + case READ_LAT_PLUS_13_4: + case READ_LAT_PLUS_7_2: + case READ_LAT_PLUS_15_4: + case READ_LAT_PLUS_4: + case READ_LAT_PLUS_17_4: + case READ_LAT_PLUS_9_2: + case READ_LAT_PLUS_19_4: + break; + default: + debug("%s: mcas_to_preamble_override value %d invalid.\n", + dev->name, mcas_to_preamble_override); + return -EINVAL; + } + + write_latency = dev_read_u32_default(dev, "write_latency", 0); + if (write_latency > 7 || write_latency == 0) { + debug("%s: write_latency value %d invalid.\n", + dev->name, write_latency); + return -EINVAL; + } + + read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0); + if (read_to_precharge > 4 || read_to_precharge == 0) { + debug("%s: read_to_precharge value %d invalid.\n", + dev->name, read_to_precharge); + return -EINVAL; + } + + write_cmd_to_write_data = + dev_read_u32_default(dev, "write_cmd_to_write_data", 0); + switch (write_cmd_to_write_data) { + case CLOCK_DELAY_0: + case CLOCK_DELAY_1_4: + case CLOCK_DELAY_1_2: + case CLOCK_DELAY_3_4: + case CLOCK_DELAY_1: + case CLOCK_DELAY_5_4: + case CLOCK_DELAY_3_2: + break; + default: + debug("%s: write_cmd_to_write_data value %d invalid.\n", + dev->name, write_cmd_to_write_data); + return -EINVAL; + } + + minimum_cke_pulse_width = + dev_read_u32_default(dev, "minimum_cke_pulse_width", 0); + if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) { + debug("%s: minimum_cke_pulse_width value %d invalid.\n", + dev->name, minimum_cke_pulse_width); + return -EINVAL; + } + + four_activates_window = + dev_read_u32_default(dev, "four_activates_window", 0); + if (four_activates_window > 20 || four_activates_window == 0) { + debug("%s: four_activates_window value %d invalid.\n", + dev->name, four_activates_window); + return -EINVAL; + } + + timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT | + mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT | + write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT | + read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT | + write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT | + minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT | + four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT; + + out_be32(&im->ddr.timing_cfg_2, timing_cfg_2); + + self_refresh = dev_read_u32_default(dev, "self_refresh", 0); + switch (self_refresh) { + case SREN_DISABLE: + case SREN_ENABLE: + break; + default: + debug("%s: self_refresh value %d invalid.\n", + dev->name, self_refresh); + return -EINVAL; + } + + ecc = dev_read_u32_default(dev, "ecc", 0); + switch (ecc) { + case ECC_DISABLE: + case ECC_ENABLE: + break; + default: + debug("%s: ecc value %d invalid.\n", dev->name, ecc); + return -EINVAL; + } + + registered_dram = dev_read_u32_default(dev, "registered_dram", 0); + switch (registered_dram) { + case RD_DISABLE: + case RD_ENABLE: + break; + default: + debug("%s: registered_dram value %d invalid.\n", + dev->name, registered_dram); + return -EINVAL; + } + + sdram_type = dev_read_u32_default(dev, "sdram_type", 0); + switch (sdram_type) { + case TYPE_DDR1: + case TYPE_DDR2: + break; + default: + debug("%s: sdram_type value %d invalid.\n", + dev->name, sdram_type); + return -EINVAL; + } + + dynamic_power_management = + dev_read_u32_default(dev, "dynamic_power_management", 0); + switch (dynamic_power_management) { + case DYN_PWR_DISABLE: + case DYN_PWR_ENABLE: + break; + default: + debug("%s: dynamic_power_management value %d invalid.\n", + dev->name, dynamic_power_management); + return -EINVAL; + } + + databus_width = dev_read_u32_default(dev, "databus_width", 0); + switch (databus_width) { + case DATA_BUS_WIDTH_16: + case DATA_BUS_WIDTH_32: + break; + default: + debug("%s: databus_width value %d invalid.\n", + dev->name, databus_width); + return -EINVAL; + } + + nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0); + switch (nc_auto_precharge) { + case NCAP_DISABLE: + case NCAP_ENABLE: + break; + default: + debug("%s: nc_auto_precharge value %d invalid.\n", + dev->name, nc_auto_precharge); + return -EINVAL; + } + + timing_2t = dev_read_u32_default(dev, "timing_2t", 0); + switch (timing_2t) { + case TIMING_1T: + case TIMING_2T: + break; + default: + debug("%s: timing_2t value %d invalid.\n", + dev->name, timing_2t); + return -EINVAL; + } + + bank_interleaving_ctrl = + dev_read_u32_default(dev, "bank_interleaving_ctrl", 0); + switch (bank_interleaving_ctrl) { + case INTERLEAVE_NONE: + case INTERLEAVE_1_AND_2: + break; + default: + debug("%s: bank_interleaving_ctrl value %d invalid.\n", + dev->name, bank_interleaving_ctrl); + return -EINVAL; + } + + precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0); + switch (precharge_bit_8) { + case PRECHARGE_MA_10: + case PRECHARGE_MA_8: + break; + default: + debug("%s: precharge_bit_8 value %d invalid.\n", + dev->name, precharge_bit_8); + return -EINVAL; + } + + half_strength = dev_read_u32_default(dev, "half_strength", 0); + switch (half_strength) { + case STRENGTH_FULL: + case STRENGTH_HALF: + break; + default: + debug("%s: half_strength value %d invalid.\n", + dev->name, half_strength); + return -EINVAL; + } + + bypass_initialization = + dev_read_u32_default(dev, "bypass_initialization", 0); + switch (bypass_initialization) { + case INITIALIZATION_DONT_BYPASS: + case INITIALIZATION_BYPASS: + break; + default: + debug("%s: bypass_initialization value %d invalid.\n", + dev->name, bypass_initialization); + return -EINVAL; + } + + sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT | + ecc << SDRAM_CFG_ECC_EN_SHIFT | + registered_dram << SDRAM_CFG_RD_EN_SHIFT | + sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT | + dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT | + databus_width << SDRAM_CFG_DBW_SHIFT | + nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT | + timing_2t << SDRAM_CFG_2T_EN_SHIFT | + bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT | + precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT | + half_strength << SDRAM_CFG_HSE_SHIFT | + bypass_initialization << SDRAM_CFG_BI_SHIFT; + + out_be32(&im->ddr.sdram_cfg, sdram_cfg); + + force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0); + switch (force_self_refresh) { + case MODE_NORMAL: + case MODE_REFRESH: + break; + default: + debug("%s: force_self_refresh value %d invalid.\n", + dev->name, force_self_refresh); + return -EINVAL; + } + + dll_reset = dev_read_u32_default(dev, "dll_reset", 0); + switch (dll_reset) { + case DLL_RESET_ENABLE: + case DLL_RESET_DISABLE: + break; + default: + debug("%s: dll_reset value %d invalid.\n", + dev->name, dll_reset); + return -EINVAL; + } + + dqs_config = dev_read_u32_default(dev, "dqs_config", 0); + switch (dqs_config) { + case DQS_TRUE: + break; + default: + debug("%s: dqs_config value %d invalid.\n", + dev->name, dqs_config); + return -EINVAL; + } + + odt_config = dev_read_u32_default(dev, "odt_config", 0); + switch (odt_config) { + case ODT_ASSERT_NEVER: + case ODT_ASSERT_WRITES: + case ODT_ASSERT_READS: + case ODT_ASSERT_ALWAYS: + break; + default: + debug("%s: odt_config value %d invalid.\n", + dev->name, odt_config); + return -EINVAL; + } + + posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0); + if (posted_refreshes > 8 || posted_refreshes == 0) { + debug("%s: posted_refreshes value %d invalid.\n", + dev->name, posted_refreshes); + return -EINVAL; + } + + sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT | + dll_reset << SDRAM_CFG2_DLL_RST_DIS | + dqs_config << SDRAM_CFG2_DQS_CFG | + odt_config << SDRAM_CFG2_ODT_CFG | + posted_refreshes << SDRAM_CFG2_NUM_PR; + + out_be32(&im->ddr.sdram_cfg2, sdram_cfg2); + + sdmode = dev_read_u32_default(dev, "sdmode", 0); + if (sdmode > 0xFFFF) { + debug("%s: sdmode value %d invalid.\n", + dev->name, sdmode); + return -EINVAL; + } + + esdmode = dev_read_u32_default(dev, "esdmode", 0); + if (esdmode > 0xFFFF) { + debug("%s: esdmode value %d invalid.\n", dev->name, esdmode); + return -EINVAL; + } + + sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT | + esdmode << SDRAM_MODE_ESD_SHIFT; + + out_be32(&im->ddr.sdram_mode, sdram_mode); + + esdmode2 = dev_read_u32_default(dev, "esdmode2", 0); + if (esdmode2 > 0xFFFF) { + debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2); + return -EINVAL; + } + + esdmode3 = dev_read_u32_default(dev, "esdmode3", 0); + if (esdmode3 > 0xFFFF) { + debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3); + return -EINVAL; + } + + sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT | + esdmode3 << SDRAM_MODE2_ESD3_SHIFT; + + out_be32(&im->ddr.sdram_mode2, sdram_mode2); + + refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0); + if (refresh_interval > 0xFFFF) { + debug("%s: refresh_interval value %d invalid.\n", + dev->name, refresh_interval); + return -EINVAL; + } + + precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0); + if (precharge_interval > 0x3FFF) { + debug("%s: precharge_interval value %d invalid.\n", + dev->name, precharge_interval); + return -EINVAL; + } + + sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT | + precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT; + + out_be32(&im->ddr.sdram_interval, sdram_interval); + sync(); + + /* Enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + dev_for_each_subnode(subnode, dev) { + u32 val[3]; + u32 addr, size; + + /* CS, map address, size -> three values */ + ofnode_read_u32_array(subnode, "reg", val, 3); + + addr = val[1]; + size = val[2]; + + priv->total_size += get_ram_size((long int *)addr, size); + }; + + gd->ram_size = priv->total_size; + + return 0; +} + +static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info) +{ + /* TODO(mario.six@gdsys.cc): Implement */ + return 0; +} + +static struct ram_ops mpc83xx_sdram_ops = { + .get_info = mpc83xx_sdram_get_info, +}; + +static const struct udevice_id mpc83xx_sdram_ids[] = { + { .compatible = "fsl,mpc83xx-mem-controller" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mpc83xx_sdram) = { + .name = "mpc83xx_sdram", + .id = UCLASS_RAM, + .of_match = mpc83xx_sdram_ids, + .ops = &mpc83xx_sdram_ops, + .of_to_plat = mpc83xx_sdram_of_to_plat, + .probe = mpc83xx_sdram_probe, + .priv_auto = sizeof(struct mpc83xx_sdram_priv), +}; diff --git a/roms/u-boot/drivers/ram/octeon/Kconfig b/roms/u-boot/drivers/ram/octeon/Kconfig new file mode 100644 index 000000000..eb5a1208e --- /dev/null +++ b/roms/u-boot/drivers/ram/octeon/Kconfig @@ -0,0 +1,17 @@ +config RAM_OCTEON + bool "Ram drivers for Octeon SoCs" + depends on RAM && ARCH_OCTEON + default n + help + This enables support for RAM drivers for Octeon SoCs. + +if RAM_OCTEON + +config RAM_OCTEON_DDR4 + bool "Octeon III DDR4 RAM support" + default n + help + This enables support for DDR4 RAM suppoort for Octeon III. This does + not include support for Octeon CN70XX. + +endif # RAM_OCTEON diff --git a/roms/u-boot/drivers/ram/octeon/Makefile b/roms/u-boot/drivers/ram/octeon/Makefile new file mode 100644 index 000000000..27649d1e6 --- /dev/null +++ b/roms/u-boot/drivers/ram/octeon/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2020 Marvell, Inc. +# + +obj-$(CONFIG_RAM_OCTEON_DDR4) += octeon_ddr.o +obj-$(CONFIG_RAM_OCTEON_DDR4) += octeon3_lmc.o +obj-y += dimm_spd_eeprom.o diff --git a/roms/u-boot/drivers/ram/octeon/dimm_spd_eeprom.c b/roms/u-boot/drivers/ram/octeon/dimm_spd_eeprom.c new file mode 100644 index 000000000..30db54804 --- /dev/null +++ b/roms/u-boot/drivers/ram/octeon/dimm_spd_eeprom.c @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include + +#include + +#define DEVICE_TYPE DDR4_SPD_KEY_BYTE_DEVICE_TYPE // same for DDR3 and DDR4 +#define MODULE_TYPE DDR4_SPD_KEY_BYTE_MODULE_TYPE // same for DDR3 and DDR4 +#define BUS_WIDTH(t) (((t) == DDR4_DRAM) ? \ + DDR4_SPD_MODULE_MEMORY_BUS_WIDTH : \ + DDR3_SPD_MEMORY_BUS_WIDTH) + +/* + * Allow legacy code to encode bus number in the upper bits of the address + * These are only supported in read_spd() + */ +#define OCTEON_TWSI_BUS_IN_ADDR_BIT 12 +#define OCTEON_TWSI_BUS_IN_ADDR_MASK (15 << OCTEON_TWSI_BUS_IN_ADDR_BIT) +#define OCTEON_TWSI_GET_BUS(addr) \ + (((addr) >> OCTEON_TWSI_BUS_IN_ADDR_BIT) & 0xf) + +const char *ddr3_dimm_types[] = { + /* 0000 */ "Undefined", + /* 0001 */ "RDIMM", + /* 0010 */ "UDIMM", + /* 0011 */ "SO-DIMM", + /* 0100 */ "Micro-DIMM", + /* 0101 */ "Mini-RDIMM", + /* 0110 */ "Mini-UDIMM", + /* 0111 */ "Mini-CDIMM", + /* 1000 */ "72b-SO-UDIMM", + /* 1001 */ "72b-SO-RDIMM", + /* 1010 */ "72b-SO-CDIMM" + /* 1011 */ "LRDIMM", + /* 1100 */ "16b-SO-DIMM", + /* 1101 */ "32b-SO-DIMM", + /* 1110 */ "Reserved", + /* 1111 */ "Reserved" +}; + +const char *ddr4_dimm_types[] = { + /* 0000 */ "Extended", + /* 0001 */ "RDIMM", + /* 0010 */ "UDIMM", + /* 0011 */ "SO-DIMM", + /* 0100 */ "LRDIMM", + /* 0101 */ "Mini-RDIMM", + /* 0110 */ "Mini-UDIMM", + /* 0111 */ "Reserved", + /* 1000 */ "72b-SO-RDIMM", + /* 1001 */ "72b-SO-UDIMM", + /* 1010 */ "Reserved", + /* 1011 */ "Reserved", + /* 1100 */ "16b-SO-DIMM", + /* 1101 */ "32b-SO-DIMM", + /* 1110 */ "Reserved", + /* 1111 */ "Reserved" +}; + +static u16 ddr3_crc16(u8 *ptr, int count) +{ + /* From DDR3 SPD specification */ + int crc, i; + + crc = 0; + while (--count >= 0) { + crc = crc ^ (int)*ptr++ << 8; + for (i = 0; i < 8; ++i) { + if (crc & 0x8000) + crc = crc << 1 ^ 0x1021; + else + crc = crc << 1; + } + } + + return (crc & 0xFFFF); +} + +static int validate_spd_checksum_ddr4(struct dimm_config *dimm_config, + int dimm_index, int twsi_addr, int silent) +{ + u8 *spd_data = dimm_config->spd_data[dimm_index]; + int crc_bytes = 126; + u16 crc_comp; + + /* Check byte 0 to see how many bytes checksum is over */ + if (spd_data[0] & 0x80) + crc_bytes = 117; + + crc_comp = ddr3_crc16(spd_data, crc_bytes); + + if (spd_data[126] == (crc_comp & 0xff) && + spd_data[127] == (crc_comp >> 8)) + return 1; + + if (!silent) { + printf("DDR4 SPD CRC error, spd addr: 0x%x, calculated crc: 0x%04x, read crc: 0x%02x%02x\n", + twsi_addr, crc_comp, spd_data[127], spd_data[126]); + } + + return 0; +} + +static int validate_spd_checksum(struct ddr_priv *priv, + struct dimm_config *dimm_config, + int dimm_index, int twsi_addr, + int silent, u8 rv) +{ + if (ddr_verbose(priv)) + debug("Validating DIMM at address 0x%x\n", twsi_addr); + + if (rv >= 0x8 && rv <= 0xA) + printf("%s: Error: DDR2 support disabled\n", __func__); + + if (rv == 0xB) + printf("%s: Error: DDR3 support disabled\n", __func__); + + if (rv == 0xC) { + return validate_spd_checksum_ddr4(dimm_config, dimm_index, + twsi_addr, silent); + } + + if (!silent) { + printf("Unrecognized DIMM type: 0x%x at spd address: 0x%x\n", + rv, twsi_addr); + } + + return 0; +} + +/* + * Read an DIMM SPD value, either using TWSI to read it from the DIMM, or + * from a provided array. + */ +int read_spd(struct dimm_config *dimm_config, int dimm_index, int spd_field) +{ + dimm_index = !!dimm_index; + + if (spd_field >= SPD_EEPROM_SIZE) { + printf("ERROR: Trying to read unsupported SPD EEPROM value %d\n", + spd_field); + } + + /* + * If pointer to data is provided, use it, otherwise read from SPD + * over twsi + */ + if (dimm_config->spd_ptrs[dimm_index]) + return dimm_config->spd_ptrs[dimm_index][spd_field]; + else if (dimm_config->spd_addrs[dimm_index]) + return dimm_config->spd_data[dimm_index][spd_field]; + + return -1; +} + +int read_spd_init(struct dimm_config *dimm_config, int dimm_index) +{ + u8 busno = OCTEON_TWSI_GET_BUS(dimm_config->spd_addrs[dimm_index]); + u8 cmdno = dimm_config->spd_addrs[dimm_index]; + struct udevice *dev_i2c; + u8 *spd_data; + int ret; + + if (dimm_config->spd_cached[dimm_index]) + return 0; + + dimm_config->spd_cached[dimm_index] = 1; + spd_data = dimm_config->spd_data[dimm_index]; + + ret = i2c_get_chip_for_busnum(busno, cmdno, 2, &dev_i2c); + if (ret) { + debug("Cannot find SPL EEPROM: %d\n", ret); + return -ENODEV; + } + + ret = dm_i2c_read(dev_i2c, 0, spd_data, SPD_EEPROM_SIZE); + + return ret; +} + +int validate_dimm(struct ddr_priv *priv, struct dimm_config *dimm_config, + int dimm_index) +{ + int spd_addr; + + dimm_index = !!dimm_index; /* Normalize to 0/1 */ + spd_addr = dimm_config->spd_addrs[dimm_index]; + + debug("Validating dimm %d, spd addr: 0x%02x spd ptr: %p\n", + dimm_index, + dimm_config->spd_addrs[dimm_index], + dimm_config->spd_ptrs[dimm_index]); + + /* Only validate 'real' dimms, assume compiled in values are OK */ + if (!dimm_config->spd_ptrs[dimm_index]) { + int val0, val1; + int dimm_type; + int ret; + + ret = read_spd_init(dimm_config, dimm_index); + if (ret) + return 0; + + dimm_type = read_spd(dimm_config, dimm_index, + DDR2_SPD_MEM_TYPE) & 0xff; + switch (dimm_type) { + case 0x0B: /* DDR3 */ + if (ddr_verbose(priv)) + printf("Validating DDR3 DIMM %d\n", dimm_index); + val0 = read_spd(dimm_config, dimm_index, + DDR3_SPD_DENSITY_BANKS); + val1 = read_spd(dimm_config, dimm_index, + DDR3_SPD_ADDRESSING_ROW_COL_BITS); + if (val0 < 0 && val1 < 0) { + if (ddr_verbose(priv)) + printf("Error reading SPD for DIMM %d\n", + dimm_index); + return 0; /* Failed to read dimm */ + } + if (val0 == 0xff && val1 == 0xff) { + if (ddr_verbose(priv)) + printf("Blank or unreadable SPD for DIMM %d\n", + dimm_index); + /* Blank SPD or otherwise unreadable device */ + return 0; + } + + /* Don't treat bad checksums as fatal */ + validate_spd_checksum(priv, dimm_config, dimm_index, + spd_addr, 0, dimm_type); + break; + + case 0x0C: /* DDR4 */ + if (ddr_verbose(priv)) + printf("Validating DDR4 DIMM %d\n", dimm_index); + val0 = read_spd(dimm_config, dimm_index, + DDR4_SPD_DENSITY_BANKS); + val1 = read_spd(dimm_config, dimm_index, + DDR4_SPD_ADDRESSING_ROW_COL_BITS); + if (val0 < 0 && val1 < 0) { + if (ddr_verbose(priv)) + printf("Error reading SPD for DIMM %d\n", + dimm_index); + return 0; /* Failed to read dimm */ + } + if (val0 == 0xff && val1 == 0xff) { + if (ddr_verbose(priv)) { + printf("Blank or unreadable SPD for DIMM %d\n", + dimm_index); + } + /* Blank SPD or otherwise unreadable device */ + return 0; + } + + /* Don't treat bad checksums as fatal */ + validate_spd_checksum(priv, dimm_config, dimm_index, + spd_addr, 0, dimm_type); + break; + + case 0x00: + /* Terminator detected. Fail silently. */ + return 0; + + default: + debug("Unknown DIMM type 0x%x for DIMM %d @ 0x%x\n", + dimm_type, dimm_index, + dimm_config->spd_addrs[dimm_index]); + return 0; /* Failed to read dimm */ + } + } + + return 1; +} + +int get_ddr_type(struct dimm_config *dimm_config, int upper_dimm) +{ + int spd_ddr_type; + + spd_ddr_type = read_spd(dimm_config, upper_dimm, DEVICE_TYPE); + + debug("%s:%d spd_ddr_type=0x%02x\n", __func__, __LINE__, + spd_ddr_type); + + /* we return only DDR4 or DDR3 */ + return (spd_ddr_type == 0x0C) ? DDR4_DRAM : DDR3_DRAM; +} + +static int get_dimm_ecc(struct dimm_config *dimm_config, int upper_dimm, + int ddr_type) +{ + return !!(read_spd(dimm_config, upper_dimm, BUS_WIDTH(ddr_type)) & 8); +} + +int get_dimm_module_type(struct dimm_config *dimm_config, int upper_dimm, + int ddr_type) +{ + return read_spd(dimm_config, upper_dimm, MODULE_TYPE) & 0x0f; +} + +char *printable_rank_spec(char *buffer, int num_ranks, int dram_width, + int spd_package) +{ + int die_count = ((spd_package >> 4) & 7) + 1; + + if (spd_package & 0x80) { // non-monolithic + if ((spd_package & 3) == 2) { // 3DS + sprintf(buffer, "%dS%dRx%d", num_ranks, die_count, + dram_width); + } else { // MLS + char hchar = (die_count == 2) ? 'D' : 'Q'; + + sprintf(buffer, "%d%cRx%d", num_ranks, hchar, + dram_width); + } + } else { + sprintf(buffer, "%dRx%d", num_ranks, dram_width); + } + + return buffer; +} + +static void report_common_dimm(struct dimm_config *dimm_config, int upper_dimm, + int dimm, const char **dimm_types, int ddr_type, + char *volt_str, int if_num, + int num_ranks, int dram_width, int spd_package) +{ + unsigned int spd_module_type; + char rank_spec[8]; + int spd_ecc; + + spd_module_type = get_dimm_module_type(dimm_config, upper_dimm, + ddr_type); + spd_ecc = get_dimm_ecc(dimm_config, upper_dimm, ddr_type); + + printable_rank_spec(rank_spec, num_ranks, dram_width, spd_package); + printf("LMC%d.DIMM%d: DDR%d %s %s %s, %s\n", + if_num, dimm, ddr_type, dimm_types[spd_module_type], + rank_spec, spd_ecc ? "ECC" : "non-ECC", volt_str); +} + +static void report_ddr3_dimm(struct dimm_config *dimm_config, int upper_dimm, + int dimm, int if_num) +{ + int spd_voltage; + char *volt_str; + int spd_org = read_spd(dimm_config, upper_dimm, + DDR3_SPD_MODULE_ORGANIZATION); + int num_ranks = 1 + ((spd_org >> 3) & 0x7); + int dram_width = 4 << ((spd_org >> 0) & 0x7); + + spd_voltage = read_spd(dimm_config, upper_dimm, + DDR3_SPD_NOMINAL_VOLTAGE); + if (spd_voltage == 0 || spd_voltage & 3) + volt_str = "1.5V"; + if (spd_voltage & 2) + volt_str = "1.35V"; + if (spd_voltage & 4) + volt_str = "1.2xV"; + + report_common_dimm(dimm_config, upper_dimm, dimm, ddr3_dimm_types, + DDR3_DRAM, volt_str, if_num, + num_ranks, dram_width, /*spd_package*/0); +} + +static void report_ddr4_dimm(struct dimm_config *dimm_config, int upper_dimm, + int dimm, int if_num) +{ + int spd_voltage; + char *volt_str; + int spd_package = 0xff & read_spd(dimm_config, upper_dimm, + DDR4_SPD_PACKAGE_TYPE); + int spd_org = 0xff & read_spd(dimm_config, upper_dimm, + DDR4_SPD_MODULE_ORGANIZATION); + int num_ranks = 1 + ((spd_org >> 3) & 0x7); + int dram_width = 4 << ((spd_org >> 0) & 0x7); + + spd_voltage = read_spd(dimm_config, upper_dimm, + DDR4_SPD_MODULE_NOMINAL_VOLTAGE); + if (spd_voltage == 0x01 || spd_voltage & 0x02) + volt_str = "1.2V"; + if (spd_voltage == 0x04 || spd_voltage & 0x08) + volt_str = "TBD1 V"; + if (spd_voltage == 0x10 || spd_voltage & 0x20) + volt_str = "TBD2 V"; + + report_common_dimm(dimm_config, upper_dimm, dimm, ddr4_dimm_types, + DDR4_DRAM, volt_str, if_num, + num_ranks, dram_width, spd_package); +} + +void report_dimm(struct dimm_config *dimm_config, int upper_dimm, + int dimm, int if_num) +{ + int ddr_type; + + /* ddr_type only indicates DDR4 or DDR3 */ + ddr_type = get_ddr_type(dimm_config, upper_dimm); + + if (ddr_type == DDR4_DRAM) + report_ddr4_dimm(dimm_config, 0, dimm, if_num); + else + report_ddr3_dimm(dimm_config, 0, dimm, if_num); +} diff --git a/roms/u-boot/drivers/ram/octeon/octeon3_lmc.c b/roms/u-boot/drivers/ram/octeon/octeon3_lmc.c new file mode 100644 index 000000000..349abc179 --- /dev/null +++ b/roms/u-boot/drivers/ram/octeon/octeon3_lmc.c @@ -0,0 +1,11024 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* Random number generator stuff */ + +#define CVMX_OCT_DID_RNG 8ULL + +static u64 cvmx_rng_get_random64(void) +{ + return csr_rd(cvmx_build_io_address(CVMX_OCT_DID_RNG, 0)); +} + +static void cvmx_rng_enable(void) +{ + u64 val; + + val = csr_rd(CVMX_RNM_CTL_STATUS); + val |= BIT(0) | BIT(1); + csr_wr(CVMX_RNM_CTL_STATUS, val); +} + +#define RLEVEL_PRINTALL_DEFAULT 1 +#define WLEVEL_PRINTALL_DEFAULT 1 + +/* + * Define how many HW WL samples to take for majority voting. + * MUST BE odd!! + * Assume there should only be 2 possible values that will show up, + * so treat ties as a problem!!! + * NOTE: Do not change this without checking the code!!! + */ +#define WLEVEL_LOOPS_DEFAULT 5 + +#define ENABLE_COMPUTED_VREF_ADJUSTMENT 1 +#define SW_WLEVEL_HW_DEFAULT 1 +#define DEFAULT_BEST_RANK_SCORE 9999999 +#define MAX_RANK_SCORE_LIMIT 99 + +/* + * Define how many HW RL samples per rank to take multiple samples will + * allow looking for the best sample score + */ +#define RLEVEL_SAMPLES_DEFAULT 3 + +#define ddr_seq_print(format, ...) do {} while (0) + +struct wlevel_bitcnt { + int bitcnt[4]; +}; + +static void display_dac_dbi_settings(int lmc, int dac_or_dbi, + int ecc_ena, int *settings, char *title); + +static unsigned short load_dac_override(struct ddr_priv *priv, int if_num, + int dac_value, int byte); + +/* "mode" arg */ +#define DBTRAIN_TEST 0 +#define DBTRAIN_DBI 1 +#define DBTRAIN_LFSR 2 + +static int run_best_hw_patterns(struct ddr_priv *priv, int lmc, u64 phys_addr, + int mode, u64 *xor_data); + +#define LMC_DDR3_RESET_ASSERT 0 +#define LMC_DDR3_RESET_DEASSERT 1 + +static void cn7xxx_lmc_ddr3_reset(struct ddr_priv *priv, int if_num, int reset) +{ + union cvmx_lmcx_reset_ctl reset_ctl; + + /* + * 4. Deassert DDRn_RESET_L pin by writing + * LMC(0..3)_RESET_CTL[DDR3RST] = 1 + * without modifying any other LMC(0..3)_RESET_CTL fields. + * 5. Read LMC(0..3)_RESET_CTL and wait for the result. + * 6. Wait a minimum of 500us. This guarantees the necessary T = 500us + * delay between DDRn_RESET_L deassertion and DDRn_DIMM*_CKE* + * assertion. + */ + debug("LMC%d %s DDR_RESET_L\n", if_num, + (reset == + LMC_DDR3_RESET_DEASSERT) ? "De-asserting" : "Asserting"); + + reset_ctl.u64 = lmc_rd(priv, CVMX_LMCX_RESET_CTL(if_num)); + reset_ctl.cn78xx.ddr3rst = reset; + lmc_wr(priv, CVMX_LMCX_RESET_CTL(if_num), reset_ctl.u64); + + lmc_rd(priv, CVMX_LMCX_RESET_CTL(if_num)); + + udelay(500); +} + +static void perform_lmc_reset(struct ddr_priv *priv, int node, int if_num) +{ + /* + * 5.9.6 LMC RESET Initialization + * + * The purpose of this step is to assert/deassert the RESET# pin at the + * DDR3/DDR4 parts. + * + * This LMC RESET step is done for all enabled LMCs. + * + * It may be appropriate to skip this step if the DDR3/DDR4 DRAM parts + * are in self refresh and are currently preserving their + * contents. (Software can determine this via + * LMC(0..3)_RESET_CTL[DDR3PSV] in some circumstances.) The remainder of + * this section assumes that the DRAM contents need not be preserved. + * + * The remainder of this section assumes that the CN78XX DDRn_RESET_L + * pin is attached to the RESET# pin of the attached DDR3/DDR4 parts, + * as will be appropriate in many systems. + * + * (In other systems, such as ones that can preserve DDR3/DDR4 part + * contents while CN78XX is powered down, it will not be appropriate to + * directly attach the CN78XX DDRn_RESET_L pin to DRESET# of the + * DDR3/DDR4 parts, and this section may not apply.) + * + * The remainder of this section describes the sequence for LMCn. + * + * Perform the following six substeps for LMC reset initialization: + * + * 1. If not done already, assert DDRn_RESET_L pin by writing + * LMC(0..3)_RESET_ CTL[DDR3RST] = 0 without modifying any other + * LMC(0..3)_RESET_CTL fields. + */ + + if (!ddr_memory_preserved(priv)) { + /* + * 2. Read LMC(0..3)_RESET_CTL and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_RESET_CTL(if_num)); + + /* + * 3. Wait until RESET# assertion-time requirement from JEDEC + * DDR3/DDR4 specification is satisfied (200 us during a + * power-on ramp, 100ns when power is already stable). + */ + + udelay(200); + + /* + * 4. Deassert DDRn_RESET_L pin by writing + * LMC(0..3)_RESET_CTL[DDR3RST] = 1 + * without modifying any other LMC(0..3)_RESET_CTL fields. + * 5. Read LMC(0..3)_RESET_CTL and wait for the result. + * 6. Wait a minimum of 500us. This guarantees the necessary + * T = 500us delay between DDRn_RESET_L deassertion and + * DDRn_DIMM*_CKE* assertion. + */ + cn7xxx_lmc_ddr3_reset(priv, if_num, LMC_DDR3_RESET_DEASSERT); + + /* Toggle Reset Again */ + /* That is, assert, then de-assert, one more time */ + cn7xxx_lmc_ddr3_reset(priv, if_num, LMC_DDR3_RESET_ASSERT); + cn7xxx_lmc_ddr3_reset(priv, if_num, LMC_DDR3_RESET_DEASSERT); + } +} + +void oct3_ddr3_seq(struct ddr_priv *priv, int rank_mask, int if_num, + int sequence) +{ + /* + * 3. Without changing any other fields in LMC(0)_CONFIG, write + * LMC(0)_CONFIG[RANKMASK] then write both + * LMC(0)_SEQ_CTL[SEQ_SEL,INIT_START] = 1 with a single CSR write + * operation. LMC(0)_CONFIG[RANKMASK] bits should be set to indicate + * the ranks that will participate in the sequence. + * + * The LMC(0)_SEQ_CTL[SEQ_SEL] value should select power-up/init or + * selfrefresh exit, depending on whether the DRAM parts are in + * self-refresh and whether their contents should be preserved. While + * LMC performs these sequences, it will not perform any other DDR3 + * transactions. When the sequence is complete, hardware sets the + * LMC(0)_CONFIG[INIT_STATUS] bits for the ranks that have been + * initialized. + * + * If power-up/init is selected immediately following a DRESET + * assertion, LMC executes the sequence described in the "Reset and + * Initialization Procedure" section of the JEDEC DDR3 + * specification. This includes activating CKE, writing all four DDR3 + * mode registers on all selected ranks, and issuing the required + * ZQCL + * command. The LMC(0)_CONFIG[RANKMASK] value should select all ranks + * with attached DRAM in this case. If LMC(0)_CONTROL[RDIMM_ENA] = 1, + * LMC writes the JEDEC standard SSTE32882 control words selected by + * LMC(0)_DIMM_CTL[DIMM*_WMASK] between DDR_CKE* signal assertion and + * the first DDR3 mode register write operation. + * LMC(0)_DIMM_CTL[DIMM*_WMASK] should be cleared to 0 if the + * corresponding DIMM is not present. + * + * If self-refresh exit is selected, LMC executes the required SRX + * command followed by a refresh and ZQ calibration. Section 4.5 + * describes behavior of a REF + ZQCS. LMC does not write the DDR3 + * mode registers as part of this sequence, and the mode register + * parameters must match at self-refresh entry and exit times. + * + * 4. Read LMC(0)_SEQ_CTL and wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] + * to be set. + * + * 5. Read LMC(0)_CONFIG[INIT_STATUS] and confirm that all ranks have + * been initialized. + */ + + union cvmx_lmcx_seq_ctl seq_ctl; + union cvmx_lmcx_config lmc_config; + int timeout; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + lmc_config.s.rankmask = rank_mask; + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), lmc_config.u64); + + seq_ctl.u64 = 0; + + seq_ctl.s.init_start = 1; + seq_ctl.s.seq_sel = sequence; + + ddr_seq_print + ("Performing LMC sequence: rank_mask=0x%02x, sequence=0x%x, %s\n", + rank_mask, sequence, sequence_str[sequence]); + + if (seq_ctl.s.seq_sel == 3) + debug("LMC%d: Exiting Self-refresh Rank_mask:%x\n", if_num, + rank_mask); + + lmc_wr(priv, CVMX_LMCX_SEQ_CTL(if_num), seq_ctl.u64); + lmc_rd(priv, CVMX_LMCX_SEQ_CTL(if_num)); + + timeout = 100; + do { + udelay(100); /* Wait a while */ + seq_ctl.u64 = lmc_rd(priv, CVMX_LMCX_SEQ_CTL(if_num)); + if (--timeout == 0) { + printf("Sequence %d timed out\n", sequence); + break; + } + } while (seq_ctl.s.seq_complete != 1); + + ddr_seq_print(" LMC sequence=%x: Completed.\n", sequence); +} + +#define bdk_numa_get_address(n, p) ((p) | ((u64)n) << CVMX_NODE_MEM_SHIFT) +#define AREA_BASE_OFFSET BIT_ULL(26) + +static int test_dram_byte64(struct ddr_priv *priv, int lmc, u64 p, + u64 bitmask, u64 *xor_data) +{ + u64 p1, p2, d1, d2; + u64 v, v1; + u64 p2offset = (1ULL << 26); // offset to area 2 + u64 datamask; + u64 xor; + u64 i, j, k; + u64 ii; + int errors = 0; + //u64 index; + u64 pattern1 = cvmx_rng_get_random64(); + u64 pattern2 = 0; + u64 bad_bits[2] = { 0, 0 }; + int kbitno = (octeon_is_cpuid(OCTEON_CN7XXX)) ? 20 : 18; + union cvmx_l2c_ctl l2c_ctl; + int burst; + int saved_dissblkdty; + int node = 0; + + // Force full cacheline write-backs to boost traffic + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + saved_dissblkdty = l2c_ctl.cn78xx.dissblkdty; + l2c_ctl.cn78xx.dissblkdty = 1; + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64); + + if (octeon_is_cpuid(OCTEON_CN73XX) || octeon_is_cpuid(OCTEON_CNF75XX)) + kbitno = 18; + + // Byte lanes may be clear in the mask to indicate no testing on that + //lane. + datamask = bitmask; + + /* + * Add offset to both test regions to not clobber boot stuff + * when running from L2 for NAND boot. + */ + p += AREA_BASE_OFFSET; // make sure base is out of the way of boot + + // final address must include LMC and node + p |= (lmc << 7); /* Map address into proper interface */ + p = bdk_numa_get_address(node, p); /* Map to node */ + p |= 1ull << 63; + +#define II_INC BIT_ULL(22) +#define II_MAX BIT_ULL(22) +#define K_INC BIT_ULL(14) +#define K_MAX BIT_ULL(kbitno) +#define J_INC BIT_ULL(9) +#define J_MAX BIT_ULL(12) +#define I_INC BIT_ULL(3) +#define I_MAX BIT_ULL(7) + + debug("N%d.LMC%d: %s: phys_addr=0x%llx/0x%llx (0x%llx)\n", + node, lmc, __func__, p, p + p2offset, 1ULL << kbitno); + + // loops are ordered so that only a single 64-bit slot is written to + // each cacheline at one time, then the cachelines are forced out; + // this should maximize read/write traffic + + // FIXME? extend the range of memory tested!! + for (ii = 0; ii < II_MAX; ii += II_INC) { + for (i = 0; i < I_MAX; i += I_INC) { + for (k = 0; k < K_MAX; k += K_INC) { + for (j = 0; j < J_MAX; j += J_INC) { + p1 = p + ii + k + j; + p2 = p1 + p2offset; + + v = pattern1 * (p1 + i); + // write the same thing to both areas + v1 = v; + + cvmx_write64_uint64(p1 + i, v); + cvmx_write64_uint64(p2 + i, v1); + + CVMX_CACHE_WBIL2(p1, 0); + CVMX_CACHE_WBIL2(p2, 0); + } + } + } + } + + CVMX_DCACHE_INVALIDATE; + + debug("N%d.LMC%d: dram_tuning_mem_xor: done INIT loop\n", node, lmc); + + /* Make a series of passes over the memory areas. */ + + for (burst = 0; burst < 1 /* was: dram_tune_use_bursts */ ; burst++) { + u64 this_pattern = cvmx_rng_get_random64(); + + pattern2 ^= this_pattern; + + /* + * XOR the data with a random value, applying the change to both + * memory areas. + */ + + // FIXME? extend the range of memory tested!! + for (ii = 0; ii < II_MAX; ii += II_INC) { + // FIXME: rearranged, did not make much difference? + for (i = 0; i < I_MAX; i += I_INC) { + for (k = 0; k < K_MAX; k += K_INC) { + for (j = 0; j < J_MAX; j += J_INC) { + p1 = p + ii + k + j; + p2 = p1 + p2offset; + + v = cvmx_read64_uint64(p1 + + i) ^ + this_pattern; + v1 = cvmx_read64_uint64(p2 + + i) ^ + this_pattern; + + cvmx_write64_uint64(p1 + i, v); + cvmx_write64_uint64(p2 + i, v1); + + CVMX_CACHE_WBIL2(p1, 0); + CVMX_CACHE_WBIL2(p2, 0); + } + } + } + } + + CVMX_DCACHE_INVALIDATE; + + debug("N%d.LMC%d: dram_tuning_mem_xor: done MODIFY loop\n", + node, lmc); + + /* + * Look for differences in the areas. If there is a mismatch, + * reset both memory locations with the same pattern. Failing + * to do so means that on all subsequent passes the pair of + * locations remain out of sync giving spurious errors. + */ + + // FIXME: Change the loop order so that an entire cache line + // is compared at one time. This is so that a read + // error that occurs *anywhere* on the cacheline will + // be caught, rather than comparing only 1 cacheline + // slot at a time, where an error on a different + // slot will be missed that time around + // Does the above make sense? + + // FIXME? extend the range of memory tested!! + for (ii = 0; ii < II_MAX; ii += II_INC) { + for (k = 0; k < K_MAX; k += K_INC) { + for (j = 0; j < J_MAX; j += J_INC) { + p1 = p + ii + k + j; + p2 = p1 + p2offset; + + // process entire cachelines in the + //innermost loop + for (i = 0; i < I_MAX; i += I_INC) { + int bybit = 1; + // start in byte lane 0 + u64 bymsk = 0xffULL; + + // FIXME: this should predict + // what we find...??? + v = ((p1 + i) * pattern1) ^ + pattern2; + d1 = cvmx_read64_uint64(p1 + i); + d2 = cvmx_read64_uint64(p2 + i); + + // union of error bits only in + // active byte lanes + xor = ((d1 ^ v) | (d2 ^ v)) & + datamask; + + if (!xor) + continue; + + // accumulate bad bits + bad_bits[0] |= xor; + + while (xor != 0) { + debug("ERROR(%03d): [0x%016llX] [0x%016llX] expected 0x%016llX d1 %016llX d2 %016llX\n", + burst, p1, p2, v, + d1, d2); + // error(s) in this lane + if (xor & bymsk) { + // set the byte + // error bit + errors |= bybit; + // clear byte + // lane in + // error bits + xor &= ~bymsk; + // clear the + // byte lane in + // the mask + datamask &= ~bymsk; +#if EXIT_WHEN_ALL_LANES_HAVE_ERRORS + // nothing + // left to do + if (datamask == 0) { + return errors; + } +#endif /* EXIT_WHEN_ALL_LANES_HAVE_ERRORS */ + } + // move mask into + // next byte lane + bymsk <<= 8; + // move bit into next + // byte position + bybit <<= 1; + } + } + CVMX_CACHE_WBIL2(p1, 0); + CVMX_CACHE_WBIL2(p2, 0); + } + } + } + + debug("N%d.LMC%d: dram_tuning_mem_xor: done TEST loop\n", + node, lmc); + } + + if (xor_data) { // send the bad bits back... + xor_data[0] = bad_bits[0]; + xor_data[1] = bad_bits[1]; // let it be zeroed + } + + // Restore original setting that could enable partial cacheline writes + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + l2c_ctl.cn78xx.dissblkdty = saved_dissblkdty; + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64); + + return errors; +} + +static void ddr4_mrw(struct ddr_priv *priv, int if_num, int rank, + int mr_wr_addr, int mr_wr_sel, int mr_wr_bg1) +{ + union cvmx_lmcx_mr_mpr_ctl lmc_mr_mpr_ctl; + + lmc_mr_mpr_ctl.u64 = 0; + lmc_mr_mpr_ctl.cn78xx.mr_wr_addr = (mr_wr_addr == -1) ? 0 : mr_wr_addr; + lmc_mr_mpr_ctl.cn78xx.mr_wr_sel = mr_wr_sel; + lmc_mr_mpr_ctl.cn78xx.mr_wr_rank = rank; + lmc_mr_mpr_ctl.cn78xx.mr_wr_use_default_value = + (mr_wr_addr == -1) ? 1 : 0; + lmc_mr_mpr_ctl.cn78xx.mr_wr_bg1 = mr_wr_bg1; + lmc_wr(priv, CVMX_LMCX_MR_MPR_CTL(if_num), lmc_mr_mpr_ctl.u64); + + /* Mode Register Write */ + oct3_ddr3_seq(priv, 1 << rank, if_num, 0x8); +} + +#define INV_A0_17(x) ((x) ^ 0x22bf8) + +static void set_mpr_mode(struct ddr_priv *priv, int rank_mask, + int if_num, int dimm_count, int mpr, int bg1) +{ + int rankx; + + debug("All Ranks: Set mpr mode = %x %c-side\n", + mpr, (bg1 == 0) ? 'A' : 'B'); + + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + if (bg1 == 0) { + /* MR3 A-side */ + ddr4_mrw(priv, if_num, rankx, mpr << 2, 3, bg1); + } else { + /* MR3 B-side */ + ddr4_mrw(priv, if_num, rankx, INV_A0_17(mpr << 2), ~3, + bg1); + } + } +} + +static void do_ddr4_mpr_read(struct ddr_priv *priv, int if_num, + int rank, int page, int location) +{ + union cvmx_lmcx_mr_mpr_ctl lmc_mr_mpr_ctl; + + lmc_mr_mpr_ctl.u64 = lmc_rd(priv, CVMX_LMCX_MR_MPR_CTL(if_num)); + lmc_mr_mpr_ctl.cn70xx.mr_wr_addr = 0; + lmc_mr_mpr_ctl.cn70xx.mr_wr_sel = page; /* Page */ + lmc_mr_mpr_ctl.cn70xx.mr_wr_rank = rank; + lmc_mr_mpr_ctl.cn70xx.mpr_loc = location; + lmc_mr_mpr_ctl.cn70xx.mpr_wr = 0; /* Read=0, Write=1 */ + lmc_wr(priv, CVMX_LMCX_MR_MPR_CTL(if_num), lmc_mr_mpr_ctl.u64); + + /* MPR register access sequence */ + oct3_ddr3_seq(priv, 1 << rank, if_num, 0x9); + + debug("LMC_MR_MPR_CTL : 0x%016llx\n", + lmc_mr_mpr_ctl.u64); + debug("lmc_mr_mpr_ctl.cn70xx.mr_wr_addr: 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mr_wr_addr); + debug("lmc_mr_mpr_ctl.cn70xx.mr_wr_sel : 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mr_wr_sel); + debug("lmc_mr_mpr_ctl.cn70xx.mpr_loc : 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mpr_loc); + debug("lmc_mr_mpr_ctl.cn70xx.mpr_wr : 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mpr_wr); +} + +static int set_rdimm_mode(struct ddr_priv *priv, int if_num, int enable) +{ + union cvmx_lmcx_control lmc_control; + int save_rdimm_mode; + + lmc_control.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + save_rdimm_mode = lmc_control.s.rdimm_ena; + lmc_control.s.rdimm_ena = enable; + debug("Setting RDIMM_ENA = %x\n", enable); + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), lmc_control.u64); + + return save_rdimm_mode; +} + +static void ddr4_mpr_read(struct ddr_priv *priv, int if_num, int rank, + int page, int location, u64 *mpr_data) +{ + do_ddr4_mpr_read(priv, if_num, rank, page, location); + + mpr_data[0] = lmc_rd(priv, CVMX_LMCX_MPR_DATA0(if_num)); +} + +/* Display MPR values for Page */ +static void display_mpr_page(struct ddr_priv *priv, int rank_mask, + int if_num, int page) +{ + int rankx, location; + u64 mpr_data[3]; + + for (rankx = 0; rankx < 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + debug("N0.LMC%d.R%d: MPR Page %d loc [0:3]: ", + if_num, rankx, page); + for (location = 0; location < 4; location++) { + ddr4_mpr_read(priv, if_num, rankx, page, location, + mpr_data); + debug("0x%02llx ", mpr_data[0] & 0xFF); + } + debug("\n"); + + } /* for (rankx = 0; rankx < 4; rankx++) */ +} + +static void ddr4_mpr_write(struct ddr_priv *priv, int if_num, int rank, + int page, int location, u8 mpr_data) +{ + union cvmx_lmcx_mr_mpr_ctl lmc_mr_mpr_ctl; + + lmc_mr_mpr_ctl.u64 = 0; + lmc_mr_mpr_ctl.cn70xx.mr_wr_addr = mpr_data; + lmc_mr_mpr_ctl.cn70xx.mr_wr_sel = page; /* Page */ + lmc_mr_mpr_ctl.cn70xx.mr_wr_rank = rank; + lmc_mr_mpr_ctl.cn70xx.mpr_loc = location; + lmc_mr_mpr_ctl.cn70xx.mpr_wr = 1; /* Read=0, Write=1 */ + lmc_wr(priv, CVMX_LMCX_MR_MPR_CTL(if_num), lmc_mr_mpr_ctl.u64); + + /* MPR register access sequence */ + oct3_ddr3_seq(priv, 1 << rank, if_num, 0x9); + + debug("LMC_MR_MPR_CTL : 0x%016llx\n", + lmc_mr_mpr_ctl.u64); + debug("lmc_mr_mpr_ctl.cn70xx.mr_wr_addr: 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mr_wr_addr); + debug("lmc_mr_mpr_ctl.cn70xx.mr_wr_sel : 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mr_wr_sel); + debug("lmc_mr_mpr_ctl.cn70xx.mpr_loc : 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mpr_loc); + debug("lmc_mr_mpr_ctl.cn70xx.mpr_wr : 0x%02x\n", + lmc_mr_mpr_ctl.cn70xx.mpr_wr); +} + +static void set_vref(struct ddr_priv *priv, int if_num, int rank, + int range, int value) +{ + union cvmx_lmcx_mr_mpr_ctl lmc_mr_mpr_ctl; + union cvmx_lmcx_modereg_params3 lmc_modereg_params3; + int mr_wr_addr = 0; + + lmc_mr_mpr_ctl.u64 = 0; + lmc_modereg_params3.u64 = lmc_rd(priv, + CVMX_LMCX_MODEREG_PARAMS3(if_num)); + + /* A12:A10 tCCD_L */ + mr_wr_addr |= lmc_modereg_params3.s.tccd_l << 10; + mr_wr_addr |= 1 << 7; /* A7 1 = Enable(Training Mode) */ + mr_wr_addr |= range << 6; /* A6 vrefDQ Training Range */ + mr_wr_addr |= value << 0; /* A5:A0 vrefDQ Training Value */ + + lmc_mr_mpr_ctl.cn70xx.mr_wr_addr = mr_wr_addr; + lmc_mr_mpr_ctl.cn70xx.mr_wr_sel = 6; /* Write MR6 */ + lmc_mr_mpr_ctl.cn70xx.mr_wr_rank = rank; + lmc_wr(priv, CVMX_LMCX_MR_MPR_CTL(if_num), lmc_mr_mpr_ctl.u64); + + /* 0x8 = Mode Register Write */ + oct3_ddr3_seq(priv, 1 << rank, if_num, 0x8); + + /* + * It is vendor specific whether vref_value is captured with A7=1. + * A subsequent MRS might be necessary. + */ + oct3_ddr3_seq(priv, 1 << rank, if_num, 0x8); + + mr_wr_addr &= ~(1 << 7); /* A7 0 = Disable(Training Mode) */ + lmc_mr_mpr_ctl.cn70xx.mr_wr_addr = mr_wr_addr; + lmc_wr(priv, CVMX_LMCX_MR_MPR_CTL(if_num), lmc_mr_mpr_ctl.u64); +} + +static void set_dram_output_inversion(struct ddr_priv *priv, int if_num, + int dimm_count, int rank_mask, + int inversion) +{ + union cvmx_lmcx_ddr4_dimm_ctl lmc_ddr4_dimm_ctl; + union cvmx_lmcx_dimmx_params lmc_dimmx_params; + union cvmx_lmcx_dimm_ctl lmc_dimm_ctl; + int dimm_no; + + /* Don't touch extenced register control words */ + lmc_ddr4_dimm_ctl.u64 = 0; + lmc_wr(priv, CVMX_LMCX_DDR4_DIMM_CTL(if_num), lmc_ddr4_dimm_ctl.u64); + + debug("All DIMMs: Register Control Word RC0 : %x\n", + (inversion & 1)); + + for (dimm_no = 0; dimm_no < dimm_count; ++dimm_no) { + lmc_dimmx_params.u64 = + lmc_rd(priv, CVMX_LMCX_DIMMX_PARAMS(dimm_no, if_num)); + lmc_dimmx_params.s.rc0 = + (lmc_dimmx_params.s.rc0 & ~1) | (inversion & 1); + + lmc_wr(priv, + CVMX_LMCX_DIMMX_PARAMS(dimm_no, if_num), + lmc_dimmx_params.u64); + } + + /* LMC0_DIMM_CTL */ + lmc_dimm_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DIMM_CTL(if_num)); + lmc_dimm_ctl.s.dimm0_wmask = 0x1; + lmc_dimm_ctl.s.dimm1_wmask = (dimm_count > 1) ? 0x0001 : 0x0000; + + debug("LMC DIMM_CTL : 0x%016llx\n", + lmc_dimm_ctl.u64); + lmc_wr(priv, CVMX_LMCX_DIMM_CTL(if_num), lmc_dimm_ctl.u64); + + oct3_ddr3_seq(priv, rank_mask, if_num, 0x7); /* Init RCW */ +} + +static void write_mpr_page0_pattern(struct ddr_priv *priv, int rank_mask, + int if_num, int dimm_count, int pattern, + int location_mask) +{ + int rankx; + int location; + + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + for (location = 0; location < 4; ++location) { + if (!(location_mask & (1 << location))) + continue; + + ddr4_mpr_write(priv, if_num, rankx, + /* page */ 0, /* location */ location, + pattern); + } + } +} + +static void change_rdimm_mpr_pattern(struct ddr_priv *priv, int rank_mask, + int if_num, int dimm_count) +{ + int save_ref_zqcs_int; + union cvmx_lmcx_config lmc_config; + + /* + * Okay, here is the latest sequence. This should work for all + * chips and passes (78,88,73,etc). This sequence should be run + * immediately after DRAM INIT. The basic idea is to write the + * same pattern into each of the 4 MPR locations in the DRAM, so + * that the same value is returned when doing MPR reads regardless + * of the inversion state. My advice is to put this into a + * function, change_rdimm_mpr_pattern or something like that, so + * that it can be called multiple times, as I think David wants a + * clock-like pattern for OFFSET training, but does not want a + * clock pattern for Bit-Deskew. You should then be able to call + * this at any point in the init sequence (after DRAM init) to + * change the pattern to a new value. + * Mike + * + * A correction: PHY doesn't need any pattern during offset + * training, but needs clock like pattern for internal vref and + * bit-dskew training. So for that reason, these steps below have + * to be conducted before those trainings to pre-condition + * the pattern. David + * + * Note: Step 3, 4, 8 and 9 have to be done through RDIMM + * sequence. If you issue MRW sequence to do RCW write (in o78 pass + * 1 at least), LMC will still do two commands because + * CONTROL[RDIMM_ENA] is still set high. We don't want it to have + * any unintentional mode register write so it's best to do what + * Mike is doing here. + * Andrew + */ + + /* 1) Disable refresh (REF_ZQCS_INT = 0) */ + + debug("1) Disable refresh (REF_ZQCS_INT = 0)\n"); + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + save_ref_zqcs_int = lmc_config.cn78xx.ref_zqcs_int; + lmc_config.cn78xx.ref_zqcs_int = 0; + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), lmc_config.u64); + + /* + * 2) Put all devices in MPR mode (Run MRW sequence (sequence=8) + * with MODEREG_PARAMS0[MPRLOC]=0, + * MODEREG_PARAMS0[MPR]=1, MR_MPR_CTL[MR_WR_SEL]=3, and + * MR_MPR_CTL[MR_WR_USE_DEFAULT_VALUE]=1) + */ + + debug("2) Put all devices in MPR mode (Run MRW sequence (sequence=8)\n"); + + /* A-side */ + set_mpr_mode(priv, rank_mask, if_num, dimm_count, 1, 0); + /* B-side */ + set_mpr_mode(priv, rank_mask, if_num, dimm_count, 1, 1); + + /* + * a. Or you can set MR_MPR_CTL[MR_WR_USE_DEFAULT_VALUE]=0 and set + * the value you would like directly into + * MR_MPR_CTL[MR_WR_ADDR] + */ + + /* + * 3) Disable RCD Parity (if previously enabled) - parity does not + * work if inversion disabled + */ + + debug("3) Disable RCD Parity\n"); + + /* + * 4) Disable Inversion in the RCD. + * a. I did (3&4) via the RDIMM sequence (seq_sel=7), but it + * may be easier to use the MRW sequence (seq_sel=8). Just set + * MR_MPR_CTL[MR_WR_SEL]=7, MR_MPR_CTL[MR_WR_ADDR][3:0]=data, + * MR_MPR_CTL[MR_WR_ADDR][7:4]=RCD reg + */ + + debug("4) Disable Inversion in the RCD.\n"); + + set_dram_output_inversion(priv, if_num, dimm_count, rank_mask, 1); + + /* + * 5) Disable CONTROL[RDIMM_ENA] so that MR sequence goes out + * non-inverted. + */ + + debug("5) Disable CONTROL[RDIMM_ENA]\n"); + + set_rdimm_mode(priv, if_num, 0); + + /* + * 6) Write all 4 MPR registers with the desired pattern (have to + * do this for all enabled ranks) + * a. MR_MPR_CTL.MPR_WR=1, MR_MPR_CTL.MPR_LOC=0..3, + * MR_MPR_CTL.MR_WR_SEL=0, MR_MPR_CTL.MR_WR_ADDR[7:0]=pattern + */ + + debug("6) Write all 4 MPR page 0 Training Patterns\n"); + + write_mpr_page0_pattern(priv, rank_mask, if_num, dimm_count, 0x55, 0x8); + + /* 7) Re-enable RDIMM_ENA */ + + debug("7) Re-enable RDIMM_ENA\n"); + + set_rdimm_mode(priv, if_num, 1); + + /* 8) Re-enable RDIMM inversion */ + + debug("8) Re-enable RDIMM inversion\n"); + + set_dram_output_inversion(priv, if_num, dimm_count, rank_mask, 0); + + /* 9) Re-enable RDIMM parity (if desired) */ + + debug("9) Re-enable RDIMM parity (if desired)\n"); + + /* + * 10)Take B-side devices out of MPR mode (Run MRW sequence + * (sequence=8) with MODEREG_PARAMS0[MPRLOC]=0, + * MODEREG_PARAMS0[MPR]=0, MR_MPR_CTL[MR_WR_SEL]=3, and + * MR_MPR_CTL[MR_WR_USE_DEFAULT_VALUE]=1) + */ + + debug("10)Take B-side devices out of MPR mode\n"); + + set_mpr_mode(priv, rank_mask, if_num, dimm_count, + /* mpr */ 0, /* bg1 */ 1); + + /* + * a. Or you can set MR_MPR_CTL[MR_WR_USE_DEFAULT_VALUE]=0 and + * set the value you would like directly into MR_MPR_CTL[MR_WR_ADDR] + */ + + /* 11)Re-enable refresh (REF_ZQCS_INT=previous value) */ + + debug("11)Re-enable refresh (REF_ZQCS_INT=previous value)\n"); + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + lmc_config.cn78xx.ref_zqcs_int = save_ref_zqcs_int; + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), lmc_config.u64); +} + +static int validate_hwl_seq(int *wl, int *seq) +{ + // sequence index, step through the sequence array + int seqx; + int bitnum; + + seqx = 0; + + while (seq[seqx + 1] >= 0) { // stop on next seq entry == -1 + // but now, check current versus next + bitnum = (wl[seq[seqx]] << 2) | wl[seq[seqx + 1]]; + // magic validity number (see matrix above) + if (!((1 << bitnum) & 0xBDE7)) + return 1; + seqx++; + } + + return 0; +} + +static int validate_hw_wl_settings(int if_num, + union cvmx_lmcx_wlevel_rankx + *lmc_wlevel_rank, int is_rdimm, int ecc_ena) +{ + int wl[9], byte, errors; + + // arrange the sequences so + // index 0 has byte 0, etc, ECC in middle + int useq[] = { 0, 1, 2, 3, 8, 4, 5, 6, 7, -1 }; + // index 0 is ECC, then go down + int rseq1[] = { 8, 3, 2, 1, 0, -1 }; + // index 0 has byte 4, then go up + int rseq2[] = { 4, 5, 6, 7, -1 }; + // index 0 has byte 0, etc, no ECC + int useqno[] = { 0, 1, 2, 3, 4, 5, 6, 7, -1 }; + // index 0 is byte 3, then go down, no ECC + int rseq1no[] = { 3, 2, 1, 0, -1 }; + + // in the CSR, bytes 0-7 are always data, byte 8 is ECC + for (byte = 0; byte < (8 + ecc_ena); byte++) { + // preprocess :-) + wl[byte] = (get_wl_rank(lmc_wlevel_rank, byte) >> + 1) & 3; + } + + errors = 0; + if (is_rdimm) { // RDIMM order + errors = validate_hwl_seq(wl, (ecc_ena) ? rseq1 : rseq1no); + errors += validate_hwl_seq(wl, rseq2); + } else { // UDIMM order + errors = validate_hwl_seq(wl, (ecc_ena) ? useq : useqno); + } + + return errors; +} + +static unsigned int extr_wr(u64 u, int x) +{ + return (unsigned int)(((u >> (x * 12 + 5)) & 0x3ULL) | + ((u >> (51 + x - 2)) & 0x4ULL)); +} + +static void insrt_wr(u64 *up, int x, int v) +{ + u64 u = *up; + + u &= ~(((0x3ULL) << (x * 12 + 5)) | ((0x1ULL) << (51 + x))); + *up = (u | ((v & 0x3ULL) << (x * 12 + 5)) | + ((v & 0x4ULL) << (51 + x - 2))); +} + +/* Read out Deskew Settings for DDR */ + +struct deskew_bytes { + u16 bits[8]; +}; + +struct deskew_data { + struct deskew_bytes bytes[9]; +}; + +struct dac_data { + int bytes[9]; +}; + +// T88 pass 1, skip 4=DAC +static const u8 dsk_bit_seq_p1[8] = { 0, 1, 2, 3, 5, 6, 7, 8 }; +// T88 Pass 2, skip 4=DAC and 5=DBI +static const u8 dsk_bit_seq_p2[8] = { 0, 1, 2, 3, 6, 7, 8, 9 }; + +static void get_deskew_settings(struct ddr_priv *priv, int if_num, + struct deskew_data *dskdat) +{ + union cvmx_lmcx_phy_ctl phy_ctl; + union cvmx_lmcx_config lmc_config; + int bit_index; + int byte_lane, byte_limit; + // NOTE: these are for pass 2.x + int is_o78p2 = !octeon_is_cpuid(OCTEON_CN78XX_PASS1_X); + const u8 *bit_seq = (is_o78p2) ? dsk_bit_seq_p2 : dsk_bit_seq_p1; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + byte_limit = ((!lmc_config.s.mode32b) ? 8 : 4) + lmc_config.s.ecc_ena; + + memset(dskdat, 0, sizeof(*dskdat)); + + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.dsk_dbg_clk_scaler = 3; + + for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) { + phy_ctl.s.dsk_dbg_byte_sel = byte_lane; // set byte lane + + for (bit_index = 0; bit_index < 8; ++bit_index) { + // set bit number and start read sequence + phy_ctl.s.dsk_dbg_bit_sel = bit_seq[bit_index]; + phy_ctl.s.dsk_dbg_rd_start = 1; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + // poll for read sequence to complete + do { + phy_ctl.u64 = + lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + } while (phy_ctl.s.dsk_dbg_rd_complete != 1); + + // record the data + dskdat->bytes[byte_lane].bits[bit_index] = + phy_ctl.s.dsk_dbg_rd_data & 0x3ff; + } + } +} + +static void display_deskew_settings(struct ddr_priv *priv, int if_num, + struct deskew_data *dskdat, + int print_enable) +{ + int byte_lane; + int bit_num; + u16 flags, deskew; + union cvmx_lmcx_config lmc_config; + int byte_limit; + const char *fc = " ?-=+*#&"; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + byte_limit = ((lmc_config.s.mode32b) ? 4 : 8) + lmc_config.s.ecc_ena; + + if (print_enable) { + debug("N0.LMC%d: Deskew Data: Bit => :", + if_num); + for (bit_num = 7; bit_num >= 0; --bit_num) + debug(" %3d ", bit_num); + debug("\n"); + } + + for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) { + if (print_enable) + debug("N0.LMC%d: Bit Deskew Byte %d %s :", + if_num, byte_lane, + (print_enable >= 3) ? "FINAL" : " "); + + for (bit_num = 7; bit_num >= 0; --bit_num) { + flags = dskdat->bytes[byte_lane].bits[bit_num] & 7; + deskew = dskdat->bytes[byte_lane].bits[bit_num] >> 3; + + if (print_enable) + debug(" %3d %c", deskew, fc[flags ^ 1]); + + } /* for (bit_num = 7; bit_num >= 0; --bit_num) */ + + if (print_enable) + debug("\n"); + } +} + +static void override_deskew_settings(struct ddr_priv *priv, int if_num, + struct deskew_data *dskdat) +{ + union cvmx_lmcx_phy_ctl phy_ctl; + union cvmx_lmcx_config lmc_config; + + int bit, byte_lane, byte_limit; + u64 csr_data; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + byte_limit = ((lmc_config.s.mode32b) ? 4 : 8) + lmc_config.s.ecc_ena; + + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + + phy_ctl.s.phy_reset = 0; + phy_ctl.s.dsk_dbg_num_bits_sel = 1; + phy_ctl.s.dsk_dbg_offset = 0; + phy_ctl.s.dsk_dbg_clk_scaler = 3; + + phy_ctl.s.dsk_dbg_wr_mode = 1; + phy_ctl.s.dsk_dbg_load_dis = 0; + phy_ctl.s.dsk_dbg_overwrt_ena = 0; + + phy_ctl.s.phy_dsk_reset = 0; + + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + + for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) { + csr_data = 0; + // FIXME: can we ignore DBI? + for (bit = 0; bit < 8; ++bit) { + // fetch input and adjust + u64 bits = (dskdat->bytes[byte_lane].bits[bit] >> 3) & + 0x7F; + + /* + * lmc_general_purpose0.data[6:0] // DQ0 + * lmc_general_purpose0.data[13:7] // DQ1 + * lmc_general_purpose0.data[20:14] // DQ2 + * lmc_general_purpose0.data[27:21] // DQ3 + * lmc_general_purpose0.data[34:28] // DQ4 + * lmc_general_purpose0.data[41:35] // DQ5 + * lmc_general_purpose0.data[48:42] // DQ6 + * lmc_general_purpose0.data[55:49] // DQ7 + * lmc_general_purpose0.data[62:56] // DBI + */ + csr_data |= (bits << (7 * bit)); + + } /* for (bit = 0; bit < 8; ++bit) */ + + // update GP0 with the bit data for this byte lane + lmc_wr(priv, CVMX_LMCX_GENERAL_PURPOSE0(if_num), csr_data); + lmc_rd(priv, CVMX_LMCX_GENERAL_PURPOSE0(if_num)); + + // start the deskew load sequence + phy_ctl.s.dsk_dbg_byte_sel = byte_lane; + phy_ctl.s.dsk_dbg_rd_start = 1; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + // poll for read sequence to complete + do { + udelay(100); + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + } while (phy_ctl.s.dsk_dbg_rd_complete != 1); + } + + // tell phy to use the new settings + phy_ctl.s.dsk_dbg_overwrt_ena = 1; + phy_ctl.s.dsk_dbg_rd_start = 0; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + phy_ctl.s.dsk_dbg_wr_mode = 0; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); +} + +static void process_by_rank_dac(struct ddr_priv *priv, int if_num, + int rank_mask, struct dac_data *dacdat) +{ + union cvmx_lmcx_config lmc_config; + int rankx, byte_lane; + int byte_limit; + int rank_count; + struct dac_data dacsum; + int lane_probs; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + byte_limit = ((lmc_config.s.mode32b) ? 4 : 8) + lmc_config.s.ecc_ena; + + memset((void *)&dacsum, 0, sizeof(dacsum)); + rank_count = 0; + lane_probs = 0; + + for (rankx = 0; rankx < 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + rank_count++; + + display_dac_dbi_settings(if_num, /*dac */ 1, + lmc_config.s.ecc_ena, + &dacdat[rankx].bytes[0], + "By-Ranks VREF"); + // sum + for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) { + if (rank_count == 2) { + int ranks_diff = + abs((dacsum.bytes[byte_lane] - + dacdat[rankx].bytes[byte_lane])); + + // FIXME: is 19 a good number? + if (ranks_diff > 19) + lane_probs |= (1 << byte_lane); + } + dacsum.bytes[byte_lane] += + dacdat[rankx].bytes[byte_lane]; + } + } + + // average + for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) + dacsum.bytes[byte_lane] /= rank_count; // FIXME: nint? + + display_dac_dbi_settings(if_num, /*dac */ 1, lmc_config.s.ecc_ena, + &dacsum.bytes[0], "All-Rank VREF"); + + if (lane_probs) { + debug("N0.LMC%d: All-Rank VREF DAC Problem Bytelane(s): 0x%03x\n", + if_num, lane_probs); + } + + // finally, write the averaged DAC values + for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) { + load_dac_override(priv, if_num, dacsum.bytes[byte_lane], + byte_lane); + } +} + +static void process_by_rank_dsk(struct ddr_priv *priv, int if_num, + int rank_mask, struct deskew_data *dskdat) +{ + union cvmx_lmcx_config lmc_config; + int rankx, lane, bit; + int byte_limit; + struct deskew_data dsksum, dskcnt; + u16 deskew; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + byte_limit = ((lmc_config.s.mode32b) ? 4 : 8) + lmc_config.s.ecc_ena; + + memset((void *)&dsksum, 0, sizeof(dsksum)); + memset((void *)&dskcnt, 0, sizeof(dskcnt)); + + for (rankx = 0; rankx < 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + // sum ranks + for (lane = 0; lane < byte_limit; lane++) { + for (bit = 0; bit < 8; ++bit) { + deskew = dskdat[rankx].bytes[lane].bits[bit]; + // if flags indicate sat hi or lo, skip it + if (deskew & 6) + continue; + + // clear flags + dsksum.bytes[lane].bits[bit] += + deskew & ~7; + // count entries + dskcnt.bytes[lane].bits[bit] += 1; + } + } + } + + // average ranks + for (lane = 0; lane < byte_limit; lane++) { + for (bit = 0; bit < 8; ++bit) { + int div = dskcnt.bytes[lane].bits[bit]; + + if (div > 0) { + dsksum.bytes[lane].bits[bit] /= div; + // clear flags + dsksum.bytes[lane].bits[bit] &= ~7; + // set LOCK + dsksum.bytes[lane].bits[bit] |= 1; + } else { + // FIXME? use reset value? + dsksum.bytes[lane].bits[bit] = + (64 << 3) | 1; + } + } + } + + // TME for FINAL version + display_deskew_settings(priv, if_num, &dsksum, /*VBL_TME */ 3); + + // finally, write the averaged DESKEW values + override_deskew_settings(priv, if_num, &dsksum); +} + +struct deskew_counts { + int saturated; // number saturated + int unlocked; // number unlocked + int nibrng_errs; // nibble range errors + int nibunl_errs; // nibble unlocked errors + int bitval_errs; // bit value errors +}; + +#define MIN_BITVAL 17 +#define MAX_BITVAL 110 + +static void validate_deskew_training(struct ddr_priv *priv, int rank_mask, + int if_num, struct deskew_counts *counts, + int print_flags) +{ + int byte_lane, bit_index, nib_num; + int nibrng_errs, nibunl_errs, bitval_errs; + union cvmx_lmcx_config lmc_config; + s16 nib_min[2], nib_max[2], nib_unl[2]; + int byte_limit; + int print_enable = print_flags & 1; + struct deskew_data dskdat; + s16 flags, deskew; + const char *fc = " ?-=+*#&"; + int bit_last; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + byte_limit = ((!lmc_config.s.mode32b) ? 8 : 4) + lmc_config.s.ecc_ena; + + memset(counts, 0, sizeof(struct deskew_counts)); + + get_deskew_settings(priv, if_num, &dskdat); + + if (print_enable) { + debug("N0.LMC%d: Deskew Settings: Bit => :", + if_num); + for (bit_index = 7; bit_index >= 0; --bit_index) + debug(" %3d ", bit_index); + debug("\n"); + } + + for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) { + if (print_enable) + debug("N0.LMC%d: Bit Deskew Byte %d %s :", + if_num, byte_lane, + (print_flags & 2) ? "FINAL" : " "); + + nib_min[0] = 127; + nib_min[1] = 127; + nib_max[0] = 0; + nib_max[1] = 0; + nib_unl[0] = 0; + nib_unl[1] = 0; + + if (lmc_config.s.mode32b == 1 && byte_lane == 4) { + bit_last = 3; + if (print_enable) + debug(" "); + } else { + bit_last = 7; + } + + for (bit_index = bit_last; bit_index >= 0; --bit_index) { + nib_num = (bit_index > 3) ? 1 : 0; + + flags = dskdat.bytes[byte_lane].bits[bit_index] & 7; + deskew = dskdat.bytes[byte_lane].bits[bit_index] >> 3; + + counts->saturated += !!(flags & 6); + + // Do range calc even when locked; it could happen + // that a bit is still unlocked after final retry, + // and we want to have an external retry if a RANGE + // error is present at exit... + nib_min[nib_num] = min(nib_min[nib_num], deskew); + nib_max[nib_num] = max(nib_max[nib_num], deskew); + + if (!(flags & 1)) { // only when not locked + counts->unlocked += 1; + nib_unl[nib_num] += 1; + } + + if (print_enable) + debug(" %3d %c", deskew, fc[flags ^ 1]); + } + + /* + * Now look for nibble errors + * + * For bit 55, it looks like a bit deskew problem. When the + * upper nibble of byte 6 needs to go to saturation, bit 7 + * of byte 6 locks prematurely at 64. For DIMMs with raw + * card A and B, can we reset the deskew training when we + * encounter this case? The reset criteria should be looking + * at one nibble at a time for raw card A and B; if the + * bit-deskew setting within a nibble is different by > 33, + * we'll issue a reset to the bit deskew training. + * + * LMC0 Bit Deskew Byte(6): 64 0 - 0 - 0 - 26 61 35 64 + */ + // upper nibble range, then lower nibble range + nibrng_errs = ((nib_max[1] - nib_min[1]) > 33) ? 1 : 0; + nibrng_errs |= ((nib_max[0] - nib_min[0]) > 33) ? 1 : 0; + + // check for nibble all unlocked + nibunl_errs = ((nib_unl[0] == 4) || (nib_unl[1] == 4)) ? 1 : 0; + + // check for bit value errors, ie < 17 or > 110 + // FIXME? assume max always > MIN_BITVAL and min < MAX_BITVAL + bitval_errs = ((nib_max[1] > MAX_BITVAL) || + (nib_max[0] > MAX_BITVAL)) ? 1 : 0; + bitval_errs |= ((nib_min[1] < MIN_BITVAL) || + (nib_min[0] < MIN_BITVAL)) ? 1 : 0; + + if ((nibrng_errs != 0 || nibunl_errs != 0 || + bitval_errs != 0) && print_enable) { + debug(" %c%c%c", + (nibrng_errs) ? 'R' : ' ', + (nibunl_errs) ? 'U' : ' ', + (bitval_errs) ? 'V' : ' '); + } + + if (print_enable) + debug("\n"); + + counts->nibrng_errs |= (nibrng_errs << byte_lane); + counts->nibunl_errs |= (nibunl_errs << byte_lane); + counts->bitval_errs |= (bitval_errs << byte_lane); + } +} + +static unsigned short load_dac_override(struct ddr_priv *priv, int if_num, + int dac_value, int byte) +{ + union cvmx_lmcx_dll_ctl3 ddr_dll_ctl3; + // single bytelanes incr by 1; A is for ALL + int bytex = (byte == 0x0A) ? byte : byte + 1; + + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + + SET_DDR_DLL_CTL3(byte_sel, bytex); + SET_DDR_DLL_CTL3(offset, dac_value >> 1); + + ddr_dll_ctl3.cn73xx.bit_select = 0x9; /* No-op */ + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + + ddr_dll_ctl3.cn73xx.bit_select = 0xC; /* vref bypass setting load */ + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + + ddr_dll_ctl3.cn73xx.bit_select = 0xD; /* vref bypass on. */ + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + + ddr_dll_ctl3.cn73xx.bit_select = 0x9; /* No-op */ + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + + lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); // flush writes + + return (unsigned short)GET_DDR_DLL_CTL3(offset); +} + +// arg dac_or_dbi is 1 for DAC, 0 for DBI +// returns 9 entries (bytelanes 0 through 8) in settings[] +// returns 0 if OK, -1 if a problem +static int read_dac_dbi_settings(struct ddr_priv *priv, int if_num, + int dac_or_dbi, int *settings) +{ + union cvmx_lmcx_phy_ctl phy_ctl; + int byte_lane, bit_num; + int deskew; + int dac_value; + int new_deskew_layout = 0; + + new_deskew_layout = octeon_is_cpuid(OCTEON_CN73XX) || + octeon_is_cpuid(OCTEON_CNF75XX); + new_deskew_layout |= (octeon_is_cpuid(OCTEON_CN78XX) && + !octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)); + + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.dsk_dbg_clk_scaler = 3; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + bit_num = (dac_or_dbi) ? 4 : 5; + // DBI not available + if (bit_num == 5 && !new_deskew_layout) + return -1; + + // FIXME: always assume ECC is available + for (byte_lane = 8; byte_lane >= 0; --byte_lane) { + //set byte lane and bit to read + phy_ctl.s.dsk_dbg_bit_sel = bit_num; + phy_ctl.s.dsk_dbg_byte_sel = byte_lane; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + //start read sequence + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.dsk_dbg_rd_start = 1; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + //poll for read sequence to complete + do { + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + } while (phy_ctl.s.dsk_dbg_rd_complete != 1); + + // keep the flag bits where they are for DBI + deskew = phy_ctl.s.dsk_dbg_rd_data; /* >> 3 */ + dac_value = phy_ctl.s.dsk_dbg_rd_data & 0xff; + + settings[byte_lane] = (dac_or_dbi) ? dac_value : deskew; + } + + return 0; +} + +// print out the DBI settings array +// arg dac_or_dbi is 1 for DAC, 0 for DBI +static void display_dac_dbi_settings(int lmc, int dac_or_dbi, + int ecc_ena, int *settings, char *title) +{ + int byte; + int flags; + int deskew; + const char *fc = " ?-=+*#&"; + + debug("N0.LMC%d: %s %s Settings %d:0 :", + lmc, title, (dac_or_dbi) ? "DAC" : "DBI", 7 + ecc_ena); + // FIXME: what about 32-bit mode? + for (byte = (7 + ecc_ena); byte >= 0; --byte) { + if (dac_or_dbi) { // DAC + flags = 1; // say its locked to get blank + deskew = settings[byte] & 0xff; + } else { // DBI + flags = settings[byte] & 7; + deskew = (settings[byte] >> 3) & 0x7f; + } + debug(" %3d %c", deskew, fc[flags ^ 1]); + } + debug("\n"); +} + +// Find a HWL majority +static int find_wl_majority(struct wlevel_bitcnt *bc, int *mx, int *mc, + int *xc, int *cc) +{ + int ix, ic; + + *mx = -1; + *mc = 0; + *xc = 0; + *cc = 0; + + for (ix = 0; ix < 4; ix++) { + ic = bc->bitcnt[ix]; + + // make a bitmask of the ones with a count + if (ic > 0) { + *mc |= (1 << ix); + *cc += 1; // count how many had non-zero counts + } + + // find the majority + if (ic > *xc) { // new max? + *xc = ic; // yes + *mx = ix; // set its index + } + } + + return (*mx << 1); +} + +// Evaluate the DAC settings array +static int evaluate_dac_settings(int if_64b, int ecc_ena, int *settings) +{ + int byte, lane, dac, comp; + int last = (if_64b) ? 7 : 3; + + // FIXME: change the check...??? + // this looks only for sets of DAC values whose max/min differ by a lot + // let any EVEN go so long as it is within range... + for (byte = (last + ecc_ena); byte >= 0; --byte) { + dac = settings[byte] & 0xff; + + for (lane = (last + ecc_ena); lane >= 0; --lane) { + comp = settings[lane] & 0xff; + if (abs((dac - comp)) > 25) + return 1; + } + } + + return 0; +} + +static void perform_offset_training(struct ddr_priv *priv, int rank_mask, + int if_num) +{ + union cvmx_lmcx_phy_ctl lmc_phy_ctl; + u64 orig_phy_ctl; + const char *s; + + /* + * 4.8.6 LMC Offset Training + * + * LMC requires input-receiver offset training. + * + * 1. Write LMC(0)_PHY_CTL[DAC_ON] = 1 + */ + lmc_phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + orig_phy_ctl = lmc_phy_ctl.u64; + lmc_phy_ctl.s.dac_on = 1; + + // allow full CSR override + s = lookup_env_ull(priv, "ddr_phy_ctl"); + if (s) + lmc_phy_ctl.u64 = strtoull(s, NULL, 0); + + // do not print or write if CSR does not change... + if (lmc_phy_ctl.u64 != orig_phy_ctl) { + debug("PHY_CTL : 0x%016llx\n", + lmc_phy_ctl.u64); + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), lmc_phy_ctl.u64); + } + + /* + * 2. Write LMC(0)_SEQ_CTL[SEQ_SEL] = 0x0B and + * LMC(0)_SEQ_CTL[INIT_START] = 1. + * + * 3. Wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] to be set to 1. + */ + /* Start Offset training sequence */ + oct3_ddr3_seq(priv, rank_mask, if_num, 0x0B); +} + +static void perform_internal_vref_training(struct ddr_priv *priv, + int rank_mask, int if_num) +{ + union cvmx_lmcx_ext_config ext_config; + union cvmx_lmcx_dll_ctl3 ddr_dll_ctl3; + + // First, make sure all byte-lanes are out of VREF bypass mode + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + + ddr_dll_ctl3.cn78xx.byte_sel = 0x0A; /* all byte-lanes */ + ddr_dll_ctl3.cn78xx.bit_select = 0x09; /* No-op */ + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + + ddr_dll_ctl3.cn78xx.bit_select = 0x0E; /* vref bypass off. */ + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + + ddr_dll_ctl3.cn78xx.bit_select = 0x09; /* No-op */ + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + + /* + * 4.8.7 LMC Internal vref Training + * + * LMC requires input-reference-voltage training. + * + * 1. Write LMC(0)_EXT_CONFIG[VREFINT_SEQ_DESKEW] = 0. + */ + ext_config.u64 = lmc_rd(priv, CVMX_LMCX_EXT_CONFIG(if_num)); + ext_config.s.vrefint_seq_deskew = 0; + + ddr_seq_print("Performing LMC sequence: vrefint_seq_deskew = %d\n", + ext_config.s.vrefint_seq_deskew); + + lmc_wr(priv, CVMX_LMCX_EXT_CONFIG(if_num), ext_config.u64); + + /* + * 2. Write LMC(0)_SEQ_CTL[SEQ_SEL] = 0x0a and + * LMC(0)_SEQ_CTL[INIT_START] = 1. + * + * 3. Wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] to be set to 1. + */ + /* Start LMC Internal vref Training */ + oct3_ddr3_seq(priv, rank_mask, if_num, 0x0A); +} + +#define dbg_avg(format, ...) // debug(format, ##__VA_ARGS__) + +static int process_samples_average(s16 *bytes, int num_samples, + int lmc, int lane_no) +{ + int i, sadj, sum = 0, ret, asum, trunc; + s16 smin = 32767, smax = -32768; + int nmin, nmax; + //int rng; + + dbg_avg("DBG_AVG%d.%d: ", lmc, lane_no); + + for (i = 0; i < num_samples; i++) { + sum += bytes[i]; + if (bytes[i] < smin) + smin = bytes[i]; + if (bytes[i] > smax) + smax = bytes[i]; + dbg_avg(" %3d", bytes[i]); + } + + nmin = 0; + nmax = 0; + for (i = 0; i < num_samples; i++) { + if (bytes[i] == smin) + nmin += 1; + if (bytes[i] == smax) + nmax += 1; + } + dbg_avg(" (min=%3d/%d, max=%3d/%d, range=%2d, samples=%2d)", + smin, nmin, smax, nmax, rng, num_samples); + + asum = sum - smin - smax; + + sadj = divide_nint(asum * 10, (num_samples - 2)); + + trunc = asum / (num_samples - 2); + + dbg_avg(" [%3d.%d, %3d]", sadj / 10, sadj % 10, trunc); + + sadj = divide_nint(sadj, 10); + if (trunc & 1) + ret = trunc; + else if (sadj & 1) + ret = sadj; + else + ret = trunc + 1; + + dbg_avg(" -> %3d\n", ret); + + return ret; +} + +#define DEFAULT_SAT_RETRY_LIMIT 11 // 1 + 10 retries + +#define default_lock_retry_limit 20 // 20 retries +#define deskew_validation_delay 10000 // 10 millisecs + +static int perform_deskew_training(struct ddr_priv *priv, int rank_mask, + int if_num, int spd_rawcard_aorb) +{ + int unsaturated, locked; + int sat_retries, sat_retries_limit; + int lock_retries, lock_retries_total, lock_retries_limit; + int print_first; + int print_them_all; + struct deskew_counts dsk_counts; + union cvmx_lmcx_phy_ctl phy_ctl; + char *s; + int has_no_sat = octeon_is_cpuid(OCTEON_CN78XX_PASS2_X) || + octeon_is_cpuid(OCTEON_CNF75XX); + int disable_bitval_retries = 1; // default to disabled + + debug("N0.LMC%d: Performing Deskew Training.\n", if_num); + + sat_retries = 0; + sat_retries_limit = (has_no_sat) ? 5 : DEFAULT_SAT_RETRY_LIMIT; + + lock_retries_total = 0; + unsaturated = 0; + print_first = 1; // print the first one + // set to true for printing all normal deskew attempts + print_them_all = 0; + + // provide override for bitval_errs causing internal VREF retries + s = env_get("ddr_disable_bitval_retries"); + if (s) + disable_bitval_retries = !!simple_strtoul(s, NULL, 0); + + lock_retries_limit = default_lock_retry_limit; + if ((octeon_is_cpuid(OCTEON_CN78XX_PASS2_X)) || + (octeon_is_cpuid(OCTEON_CN73XX)) || + (octeon_is_cpuid(OCTEON_CNF75XX))) + lock_retries_limit *= 2; // give new chips twice as many + + do { /* while (sat_retries < sat_retry_limit) */ + /* + * 4.8.8 LMC Deskew Training + * + * LMC requires input-read-data deskew training. + * + * 1. Write LMC(0)_EXT_CONFIG[VREFINT_SEQ_DESKEW] = 1. + */ + + union cvmx_lmcx_ext_config ext_config; + + ext_config.u64 = lmc_rd(priv, CVMX_LMCX_EXT_CONFIG(if_num)); + ext_config.s.vrefint_seq_deskew = 1; + + ddr_seq_print + ("Performing LMC sequence: vrefint_seq_deskew = %d\n", + ext_config.s.vrefint_seq_deskew); + + lmc_wr(priv, CVMX_LMCX_EXT_CONFIG(if_num), ext_config.u64); + + /* + * 2. Write LMC(0)_SEQ_CTL[SEQ_SEL] = 0x0A and + * LMC(0)_SEQ_CTL[INIT_START] = 1. + * + * 3. Wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] to be set to 1. + */ + + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.phy_dsk_reset = 1; /* RESET Deskew sequence */ + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + /* LMC Deskew Training */ + oct3_ddr3_seq(priv, rank_mask, if_num, 0x0A); + + lock_retries = 0; + +perform_deskew_training: + + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.phy_dsk_reset = 0; /* Normal Deskew sequence */ + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + /* LMC Deskew Training */ + oct3_ddr3_seq(priv, rank_mask, if_num, 0x0A); + + // Moved this from validate_deskew_training + /* Allow deskew results to stabilize before evaluating them. */ + udelay(deskew_validation_delay); + + // Now go look at lock and saturation status... + validate_deskew_training(priv, rank_mask, if_num, &dsk_counts, + print_first); + // after printing the first and not doing them all, no more + if (print_first && !print_them_all) + print_first = 0; + + unsaturated = (dsk_counts.saturated == 0); + locked = (dsk_counts.unlocked == 0); + + // only do locking retries if unsaturated or rawcard A or B, + // otherwise full SAT retry + if (unsaturated || (spd_rawcard_aorb && !has_no_sat)) { + if (!locked) { // and not locked + lock_retries++; + lock_retries_total++; + if (lock_retries <= lock_retries_limit) { + goto perform_deskew_training; + } else { + debug("N0.LMC%d: LOCK RETRIES failed after %d retries\n", + if_num, lock_retries_limit); + } + } else { + // only print if we did try + if (lock_retries_total > 0) + debug("N0.LMC%d: LOCK RETRIES successful after %d retries\n", + if_num, lock_retries); + } + } /* if (unsaturated || spd_rawcard_aorb) */ + + ++sat_retries; + + /* + * At this point, check for a DDR4 RDIMM that will not + * benefit from SAT retries; if so, exit + */ + if (spd_rawcard_aorb && !has_no_sat) { + debug("N0.LMC%d: Deskew Training Loop: Exiting for RAWCARD == A or B.\n", + if_num); + break; // no sat or lock retries + } + + } while (!unsaturated && (sat_retries < sat_retries_limit)); + + debug("N0.LMC%d: Deskew Training %s. %d sat-retries, %d lock-retries\n", + if_num, (sat_retries >= DEFAULT_SAT_RETRY_LIMIT) ? + "Timed Out" : "Completed", sat_retries - 1, lock_retries_total); + + // FIXME? add saturation to reasons for fault return - give it a + // chance via Internal VREF + // FIXME? add OPTIONAL bit value to reasons for fault return - + // give it a chance via Internal VREF + if (dsk_counts.nibrng_errs != 0 || dsk_counts.nibunl_errs != 0 || + (dsk_counts.bitval_errs != 0 && !disable_bitval_retries) || + !unsaturated) { + debug("N0.LMC%d: Nibble or Saturation Error(s) found, returning FAULT\n", + if_num); + // FIXME: do we want this output always for errors? + validate_deskew_training(priv, rank_mask, if_num, + &dsk_counts, 1); + return -1; // we did retry locally, they did not help + } + + // NOTE: we (currently) always print one last training validation + // before starting Read Leveling... + + return 0; +} + +#define SCALING_FACTOR (1000) + +// NOTE: this gets called for 1-rank and 2-rank DIMMs in single-slot config +static int compute_vref_1slot_2rank(int rtt_wr, int rtt_park, int dqx_ctl, + int rank_count, int dram_connection) +{ + u64 reff_s; + u64 rser_s = (dram_connection) ? 0 : 15; + u64 vdd = 1200; + u64 vref; + // 99 == HiZ + u64 rtt_wr_s = (((rtt_wr == 0) || rtt_wr == 99) ? + 1 * 1024 * 1024 : rtt_wr); + u64 rtt_park_s = (((rtt_park == 0) || ((rank_count == 1) && + (rtt_wr != 0))) ? + 1 * 1024 * 1024 : rtt_park); + u64 dqx_ctl_s = (dqx_ctl == 0 ? 1 * 1024 * 1024 : dqx_ctl); + int vref_value; + u64 rangepc = 6000; // range1 base + u64 vrefpc; + int vref_range = 0; + + reff_s = divide_nint((rtt_wr_s * rtt_park_s), (rtt_wr_s + rtt_park_s)); + + vref = (((rser_s + dqx_ctl_s) * SCALING_FACTOR) / + (rser_s + dqx_ctl_s + reff_s)) + SCALING_FACTOR; + + vref = (vref * vdd) / 2 / SCALING_FACTOR; + + vrefpc = (vref * 100 * 100) / vdd; + + if (vrefpc < rangepc) { // < range1 base, use range2 + vref_range = 1 << 6; // set bit A6 for range2 + rangepc = 4500; // range2 base is 45% + } + + vref_value = divide_nint(vrefpc - rangepc, 65); + if (vref_value < 0) + vref_value = vref_range; // set to base of range + else + vref_value |= vref_range; + + debug("rtt_wr: %d, rtt_park: %d, dqx_ctl: %d, rank_count: %d\n", + rtt_wr, rtt_park, dqx_ctl, rank_count); + debug("rtt_wr_s: %lld, rtt_park_s: %lld, dqx_ctl_s: %lld, vref_value: 0x%x, range: %d\n", + rtt_wr_s, rtt_park_s, dqx_ctl_s, vref_value ^ vref_range, + vref_range ? 2 : 1); + + return vref_value; +} + +// NOTE: this gets called for 1-rank and 2-rank DIMMs in two-slot configs +static int compute_vref_2slot_2rank(int rtt_wr, int rtt_park_00, + int rtt_park_01, + int dqx_ctl, int rtt_nom, + int dram_connection) +{ + u64 rser = (dram_connection) ? 0 : 15; + u64 vdd = 1200; + u64 vl, vlp, vcm; + u64 rd0, rd1, rpullup; + // 99 == HiZ + u64 rtt_wr_s = (((rtt_wr == 0) || rtt_wr == 99) ? + 1 * 1024 * 1024 : rtt_wr); + u64 rtt_park_00_s = (rtt_park_00 == 0 ? 1 * 1024 * 1024 : rtt_park_00); + u64 rtt_park_01_s = (rtt_park_01 == 0 ? 1 * 1024 * 1024 : rtt_park_01); + u64 dqx_ctl_s = (dqx_ctl == 0 ? 1 * 1024 * 1024 : dqx_ctl); + u64 rtt_nom_s = (rtt_nom == 0 ? 1 * 1024 * 1024 : rtt_nom); + int vref_value; + u64 rangepc = 6000; // range1 base + u64 vrefpc; + int vref_range = 0; + + // rd0 = (RTT_NOM (parallel) RTT_WR) + = + // ((RTT_NOM * RTT_WR) / (RTT_NOM + RTT_WR)) + RSER + rd0 = divide_nint((rtt_nom_s * rtt_wr_s), + (rtt_nom_s + rtt_wr_s)) + rser; + + // rd1 = (RTT_PARK_00 (parallel) RTT_PARK_01) + RSER = + // ((RTT_PARK_00 * RTT_PARK_01) / (RTT_PARK_00 + RTT_PARK_01)) + RSER + rd1 = divide_nint((rtt_park_00_s * rtt_park_01_s), + (rtt_park_00_s + rtt_park_01_s)) + rser; + + // rpullup = rd0 (parallel) rd1 = (rd0 * rd1) / (rd0 + rd1) + rpullup = divide_nint((rd0 * rd1), (rd0 + rd1)); + + // vl = (DQX_CTL / (DQX_CTL + rpullup)) * 1.2 + vl = divide_nint((dqx_ctl_s * vdd), (dqx_ctl_s + rpullup)); + + // vlp = ((RSER / rd0) * (1.2 - vl)) + vl + vlp = divide_nint((rser * (vdd - vl)), rd0) + vl; + + // vcm = (vlp + 1.2) / 2 + vcm = divide_nint((vlp + vdd), 2); + + // vrefpc = (vcm / 1.2) * 100 + vrefpc = divide_nint((vcm * 100 * 100), vdd); + + if (vrefpc < rangepc) { // < range1 base, use range2 + vref_range = 1 << 6; // set bit A6 for range2 + rangepc = 4500; // range2 base is 45% + } + + vref_value = divide_nint(vrefpc - rangepc, 65); + if (vref_value < 0) + vref_value = vref_range; // set to base of range + else + vref_value |= vref_range; + + debug("rtt_wr:%d, rtt_park_00:%d, rtt_park_01:%d, dqx_ctl:%d, rtt_nom:%d, vref_value:%d (0x%x)\n", + rtt_wr, rtt_park_00, rtt_park_01, dqx_ctl, rtt_nom, vref_value, + vref_value); + + return vref_value; +} + +// NOTE: only call this for DIMMs with 1 or 2 ranks, not 4. +static int compute_vref_val(struct ddr_priv *priv, int if_num, int rankx, + int dimm_count, int rank_count, + struct impedence_values *imp_values, + int is_stacked_die, int dram_connection) +{ + int computed_final_vref_value = 0; + int enable_adjust = ENABLE_COMPUTED_VREF_ADJUSTMENT; + const char *s; + int rtt_wr, dqx_ctl, rtt_nom, index; + union cvmx_lmcx_modereg_params1 lmc_modereg_params1; + union cvmx_lmcx_modereg_params2 lmc_modereg_params2; + union cvmx_lmcx_comp_ctl2 comp_ctl2; + int rtt_park; + int rtt_park_00; + int rtt_park_01; + + debug("N0.LMC%d.R%d: %s(...dram_connection = %d)\n", + if_num, rankx, __func__, dram_connection); + + // allow some overrides... + s = env_get("ddr_adjust_computed_vref"); + if (s) { + enable_adjust = !!simple_strtoul(s, NULL, 0); + if (!enable_adjust) { + debug("N0.LMC%d.R%d: DISABLE adjustment of computed VREF\n", + if_num, rankx); + } + } + + s = env_get("ddr_set_computed_vref"); + if (s) { + int new_vref = simple_strtoul(s, NULL, 0); + + debug("N0.LMC%d.R%d: OVERRIDE computed VREF to 0x%x (%d)\n", + if_num, rankx, new_vref, new_vref); + return new_vref; + } + + /* + * Calculate an alternative to the measured vref value + * but only for configurations we know how to... + */ + // We have code for 2-rank DIMMs in both 1-slot or 2-slot configs, + // and can use the 2-rank 1-slot code for 1-rank DIMMs in 1-slot + // configs, and can use the 2-rank 2-slot code for 1-rank DIMMs + // in 2-slot configs. + + lmc_modereg_params1.u64 = + lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS1(if_num)); + lmc_modereg_params2.u64 = + lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS2(if_num)); + comp_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + dqx_ctl = imp_values->dqx_strength[comp_ctl2.s.dqx_ctl]; + + // WR always comes from the current rank + index = (lmc_modereg_params1.u64 >> (rankx * 12 + 5)) & 0x03; + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) + index |= lmc_modereg_params1.u64 >> (51 + rankx - 2) & 0x04; + rtt_wr = imp_values->rtt_wr_ohms[index]; + + // separate calculations for 1 vs 2 DIMMs per LMC + if (dimm_count == 1) { + // PARK comes from this rank if 1-rank, otherwise other rank + index = + (lmc_modereg_params2.u64 >> + ((rankx ^ (rank_count - 1)) * 10 + 0)) & 0x07; + rtt_park = imp_values->rtt_nom_ohms[index]; + computed_final_vref_value = + compute_vref_1slot_2rank(rtt_wr, rtt_park, dqx_ctl, + rank_count, dram_connection); + } else { + // get both PARK values from the other DIMM + index = + (lmc_modereg_params2.u64 >> ((rankx ^ 0x02) * 10 + 0)) & + 0x07; + rtt_park_00 = imp_values->rtt_nom_ohms[index]; + index = + (lmc_modereg_params2.u64 >> ((rankx ^ 0x03) * 10 + 0)) & + 0x07; + rtt_park_01 = imp_values->rtt_nom_ohms[index]; + // NOM comes from this rank if 1-rank, otherwise other rank + index = + (lmc_modereg_params1.u64 >> + ((rankx ^ (rank_count - 1)) * 12 + 9)) & 0x07; + rtt_nom = imp_values->rtt_nom_ohms[index]; + computed_final_vref_value = + compute_vref_2slot_2rank(rtt_wr, rtt_park_00, rtt_park_01, + dqx_ctl, rtt_nom, dram_connection); + } + + if (enable_adjust) { + union cvmx_lmcx_config lmc_config; + union cvmx_lmcx_control lmc_control; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + lmc_control.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + + /* + * New computed vref = existing computed vref – X + * + * The value of X is depending on different conditions. + * Both #122 and #139 are 2Rx4 RDIMM, while #124 is stacked + * die 2Rx4, so I conclude the results into two conditions: + * + * 1. Stacked Die: 2Rx4 + * 1-slot: offset = 7. i, e New computed vref = existing + * computed vref – 7 + * 2-slot: offset = 6 + * + * 2. Regular: 2Rx4 + * 1-slot: offset = 3 + * 2-slot: offset = 2 + */ + // we know we never get called unless DDR4, so test just + // the other conditions + if (lmc_control.s.rdimm_ena == 1 && + rank_count == 2 && lmc_config.s.mode_x4dev) { + // it must first be RDIMM and 2-rank and x4 + int adj; + + // now do according to stacked die or not... + if (is_stacked_die) + adj = (dimm_count == 1) ? -7 : -6; + else + adj = (dimm_count == 1) ? -3 : -2; + + // we must have adjusted it, so print it out if + // verbosity is right + debug("N0.LMC%d.R%d: adjusting computed vref from %2d (0x%02x) to %2d (0x%02x)\n", + if_num, rankx, computed_final_vref_value, + computed_final_vref_value, + computed_final_vref_value + adj, + computed_final_vref_value + adj); + computed_final_vref_value += adj; + } + } + + return computed_final_vref_value; +} + +static void unpack_rlevel_settings(int if_bytemask, int ecc_ena, + struct rlevel_byte_data *rlevel_byte, + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank) +{ + if ((if_bytemask & 0xff) == 0xff) { + if (ecc_ena) { + rlevel_byte[8].delay = lmc_rlevel_rank.s.byte7; + rlevel_byte[7].delay = lmc_rlevel_rank.s.byte6; + rlevel_byte[6].delay = lmc_rlevel_rank.s.byte5; + rlevel_byte[5].delay = lmc_rlevel_rank.s.byte4; + /* ECC */ + rlevel_byte[4].delay = lmc_rlevel_rank.s.byte8; + } else { + rlevel_byte[7].delay = lmc_rlevel_rank.s.byte7; + rlevel_byte[6].delay = lmc_rlevel_rank.s.byte6; + rlevel_byte[5].delay = lmc_rlevel_rank.s.byte5; + rlevel_byte[4].delay = lmc_rlevel_rank.s.byte4; + } + } else { + rlevel_byte[8].delay = lmc_rlevel_rank.s.byte8; /* unused */ + rlevel_byte[7].delay = lmc_rlevel_rank.s.byte7; /* unused */ + rlevel_byte[6].delay = lmc_rlevel_rank.s.byte6; /* unused */ + rlevel_byte[5].delay = lmc_rlevel_rank.s.byte5; /* unused */ + rlevel_byte[4].delay = lmc_rlevel_rank.s.byte4; /* ECC */ + } + + rlevel_byte[3].delay = lmc_rlevel_rank.s.byte3; + rlevel_byte[2].delay = lmc_rlevel_rank.s.byte2; + rlevel_byte[1].delay = lmc_rlevel_rank.s.byte1; + rlevel_byte[0].delay = lmc_rlevel_rank.s.byte0; +} + +static void pack_rlevel_settings(int if_bytemask, int ecc_ena, + struct rlevel_byte_data *rlevel_byte, + union cvmx_lmcx_rlevel_rankx + *final_rlevel_rank) +{ + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank = *final_rlevel_rank; + + if ((if_bytemask & 0xff) == 0xff) { + if (ecc_ena) { + lmc_rlevel_rank.s.byte7 = rlevel_byte[8].delay; + lmc_rlevel_rank.s.byte6 = rlevel_byte[7].delay; + lmc_rlevel_rank.s.byte5 = rlevel_byte[6].delay; + lmc_rlevel_rank.s.byte4 = rlevel_byte[5].delay; + /* ECC */ + lmc_rlevel_rank.s.byte8 = rlevel_byte[4].delay; + } else { + lmc_rlevel_rank.s.byte7 = rlevel_byte[7].delay; + lmc_rlevel_rank.s.byte6 = rlevel_byte[6].delay; + lmc_rlevel_rank.s.byte5 = rlevel_byte[5].delay; + lmc_rlevel_rank.s.byte4 = rlevel_byte[4].delay; + } + } else { + lmc_rlevel_rank.s.byte8 = rlevel_byte[8].delay; + lmc_rlevel_rank.s.byte7 = rlevel_byte[7].delay; + lmc_rlevel_rank.s.byte6 = rlevel_byte[6].delay; + lmc_rlevel_rank.s.byte5 = rlevel_byte[5].delay; + lmc_rlevel_rank.s.byte4 = rlevel_byte[4].delay; + } + + lmc_rlevel_rank.s.byte3 = rlevel_byte[3].delay; + lmc_rlevel_rank.s.byte2 = rlevel_byte[2].delay; + lmc_rlevel_rank.s.byte1 = rlevel_byte[1].delay; + lmc_rlevel_rank.s.byte0 = rlevel_byte[0].delay; + + *final_rlevel_rank = lmc_rlevel_rank; +} + +/////////////////// These are the RLEVEL settings display routines + +// flags +#define WITH_NOTHING 0 +#define WITH_SCORE 1 +#define WITH_AVERAGE 2 +#define WITH_FINAL 4 +#define WITH_COMPUTE 8 + +static void do_display_rl(int if_num, + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank, + int rank, int flags, int score) +{ + char score_buf[16]; + char *msg_buf; + char hex_buf[20]; + + if (flags & WITH_SCORE) { + snprintf(score_buf, sizeof(score_buf), "(%d)", score); + } else { + score_buf[0] = ' '; + score_buf[1] = 0; + } + + if (flags & WITH_AVERAGE) { + msg_buf = " DELAY AVERAGES "; + } else if (flags & WITH_FINAL) { + msg_buf = " FINAL SETTINGS "; + } else if (flags & WITH_COMPUTE) { + msg_buf = " COMPUTED DELAYS "; + } else { + snprintf(hex_buf, sizeof(hex_buf), "0x%016llX", + (unsigned long long)lmc_rlevel_rank.u64); + msg_buf = hex_buf; + } + + debug("N0.LMC%d.R%d: Rlevel Rank %#4x, %s : %5d %5d %5d %5d %5d %5d %5d %5d %5d %s\n", + if_num, rank, lmc_rlevel_rank.s.status, msg_buf, + lmc_rlevel_rank.s.byte8, lmc_rlevel_rank.s.byte7, + lmc_rlevel_rank.s.byte6, lmc_rlevel_rank.s.byte5, + lmc_rlevel_rank.s.byte4, lmc_rlevel_rank.s.byte3, + lmc_rlevel_rank.s.byte2, lmc_rlevel_rank.s.byte1, + lmc_rlevel_rank.s.byte0, score_buf); +} + +static void display_rl(int if_num, + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank, int rank) +{ + do_display_rl(if_num, lmc_rlevel_rank, rank, 0, 0); +} + +static void display_rl_with_score(int if_num, + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank, + int rank, int score) +{ + do_display_rl(if_num, lmc_rlevel_rank, rank, 1, score); +} + +static void display_rl_with_final(int if_num, + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank, + int rank) +{ + do_display_rl(if_num, lmc_rlevel_rank, rank, 4, 0); +} + +static void display_rl_with_computed(int if_num, + union cvmx_lmcx_rlevel_rankx + lmc_rlevel_rank, int rank, int score) +{ + do_display_rl(if_num, lmc_rlevel_rank, rank, 9, score); +} + +// flag values +#define WITH_RODT_BLANK 0 +#define WITH_RODT_SKIPPING 1 +#define WITH_RODT_BESTROW 2 +#define WITH_RODT_BESTSCORE 3 +// control +#define SKIP_SKIPPING 1 + +static const char *with_rodt_canned_msgs[4] = { + " ", "SKIPPING ", "BEST ROW ", "BEST SCORE" +}; + +static void display_rl_with_rodt(int if_num, + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank, + int rank, int score, + int nom_ohms, int rodt_ohms, int flag) +{ + const char *msg_buf; + char set_buf[20]; + +#if SKIP_SKIPPING + if (flag == WITH_RODT_SKIPPING) + return; +#endif + + msg_buf = with_rodt_canned_msgs[flag]; + if (nom_ohms < 0) { + snprintf(set_buf, sizeof(set_buf), " RODT %3d ", + rodt_ohms); + } else { + snprintf(set_buf, sizeof(set_buf), "NOM %3d RODT %3d", nom_ohms, + rodt_ohms); + } + + debug("N0.LMC%d.R%d: Rlevel %s %s : %5d %5d %5d %5d %5d %5d %5d %5d %5d (%d)\n", + if_num, rank, set_buf, msg_buf, lmc_rlevel_rank.s.byte8, + lmc_rlevel_rank.s.byte7, lmc_rlevel_rank.s.byte6, + lmc_rlevel_rank.s.byte5, lmc_rlevel_rank.s.byte4, + lmc_rlevel_rank.s.byte3, lmc_rlevel_rank.s.byte2, + lmc_rlevel_rank.s.byte1, lmc_rlevel_rank.s.byte0, score); +} + +static void do_display_wl(int if_num, + union cvmx_lmcx_wlevel_rankx lmc_wlevel_rank, + int rank, int flags) +{ + char *msg_buf; + char hex_buf[20]; + + if (flags & WITH_FINAL) { + msg_buf = " FINAL SETTINGS "; + } else { + snprintf(hex_buf, sizeof(hex_buf), "0x%016llX", + (unsigned long long)lmc_wlevel_rank.u64); + msg_buf = hex_buf; + } + + debug("N0.LMC%d.R%d: Wlevel Rank %#4x, %s : %5d %5d %5d %5d %5d %5d %5d %5d %5d\n", + if_num, rank, lmc_wlevel_rank.s.status, msg_buf, + lmc_wlevel_rank.s.byte8, lmc_wlevel_rank.s.byte7, + lmc_wlevel_rank.s.byte6, lmc_wlevel_rank.s.byte5, + lmc_wlevel_rank.s.byte4, lmc_wlevel_rank.s.byte3, + lmc_wlevel_rank.s.byte2, lmc_wlevel_rank.s.byte1, + lmc_wlevel_rank.s.byte0); +} + +static void display_wl(int if_num, + union cvmx_lmcx_wlevel_rankx lmc_wlevel_rank, int rank) +{ + do_display_wl(if_num, lmc_wlevel_rank, rank, WITH_NOTHING); +} + +static void display_wl_with_final(int if_num, + union cvmx_lmcx_wlevel_rankx lmc_wlevel_rank, + int rank) +{ + do_display_wl(if_num, lmc_wlevel_rank, rank, WITH_FINAL); +} + +// pretty-print bitmask adjuster +static u64 ppbm(u64 bm) +{ + if (bm != 0ul) { + while ((bm & 0x0fful) == 0ul) + bm >>= 4; + } + + return bm; +} + +// xlate PACKED index to UNPACKED index to use with rlevel_byte +#define XPU(i, e) (((i) < 4) ? (i) : (((i) < 8) ? (i) + (e) : 4)) +// xlate UNPACKED index to PACKED index to use with rlevel_bitmask +#define XUP(i, e) (((i) < 4) ? (i) : (e) ? (((i) > 4) ? (i) - 1 : 8) : (i)) + +// flag values +#define WITH_WL_BITMASKS 0 +#define WITH_RL_BITMASKS 1 +#define WITH_RL_MASK_SCORES 2 +#define WITH_RL_SEQ_SCORES 3 + +static void do_display_bm(int if_num, int rank, void *bm, + int flags, int ecc) +{ + if (flags == WITH_WL_BITMASKS) { + // wlevel_bitmask array in PACKED index order, so just + // print them + int *bitmasks = (int *)bm; + + debug("N0.LMC%d.R%d: Wlevel Debug Bitmasks : %05x %05x %05x %05x %05x %05x %05x %05x %05x\n", + if_num, rank, bitmasks[8], bitmasks[7], bitmasks[6], + bitmasks[5], bitmasks[4], bitmasks[3], bitmasks[2], + bitmasks[1], bitmasks[0] + ); + } else if (flags == WITH_RL_BITMASKS) { + // rlevel_bitmask array in PACKED index order, so just + // print them + struct rlevel_bitmask *rlevel_bitmask = + (struct rlevel_bitmask *)bm; + + debug("N0.LMC%d.R%d: Rlevel Debug Bitmasks 8:0 : %05llx %05llx %05llx %05llx %05llx %05llx %05llx %05llx %05llx\n", + if_num, rank, ppbm(rlevel_bitmask[8].bm), + ppbm(rlevel_bitmask[7].bm), ppbm(rlevel_bitmask[6].bm), + ppbm(rlevel_bitmask[5].bm), ppbm(rlevel_bitmask[4].bm), + ppbm(rlevel_bitmask[3].bm), ppbm(rlevel_bitmask[2].bm), + ppbm(rlevel_bitmask[1].bm), ppbm(rlevel_bitmask[0].bm) + ); + } else if (flags == WITH_RL_MASK_SCORES) { + // rlevel_bitmask array in PACKED index order, so just + // print them + struct rlevel_bitmask *rlevel_bitmask = + (struct rlevel_bitmask *)bm; + + debug("N0.LMC%d.R%d: Rlevel Debug Bitmask Scores 8:0 : %5d %5d %5d %5d %5d %5d %5d %5d %5d\n", + if_num, rank, rlevel_bitmask[8].errs, + rlevel_bitmask[7].errs, rlevel_bitmask[6].errs, + rlevel_bitmask[5].errs, rlevel_bitmask[4].errs, + rlevel_bitmask[3].errs, rlevel_bitmask[2].errs, + rlevel_bitmask[1].errs, rlevel_bitmask[0].errs); + } else if (flags == WITH_RL_SEQ_SCORES) { + // rlevel_byte array in UNPACKED index order, so xlate + // and print them + struct rlevel_byte_data *rlevel_byte = + (struct rlevel_byte_data *)bm; + + debug("N0.LMC%d.R%d: Rlevel Debug Non-seq Scores 8:0 : %5d %5d %5d %5d %5d %5d %5d %5d %5d\n", + if_num, rank, rlevel_byte[XPU(8, ecc)].sqerrs, + rlevel_byte[XPU(7, ecc)].sqerrs, + rlevel_byte[XPU(6, ecc)].sqerrs, + rlevel_byte[XPU(5, ecc)].sqerrs, + rlevel_byte[XPU(4, ecc)].sqerrs, + rlevel_byte[XPU(3, ecc)].sqerrs, + rlevel_byte[XPU(2, ecc)].sqerrs, + rlevel_byte[XPU(1, ecc)].sqerrs, + rlevel_byte[XPU(0, ecc)].sqerrs); + } +} + +static void display_wl_bm(int if_num, int rank, int *bitmasks) +{ + do_display_bm(if_num, rank, (void *)bitmasks, WITH_WL_BITMASKS, 0); +} + +static void display_rl_bm(int if_num, int rank, + struct rlevel_bitmask *bitmasks, int ecc_ena) +{ + do_display_bm(if_num, rank, (void *)bitmasks, WITH_RL_BITMASKS, + ecc_ena); +} + +static void display_rl_bm_scores(int if_num, int rank, + struct rlevel_bitmask *bitmasks, int ecc_ena) +{ + do_display_bm(if_num, rank, (void *)bitmasks, WITH_RL_MASK_SCORES, + ecc_ena); +} + +static void display_rl_seq_scores(int if_num, int rank, + struct rlevel_byte_data *bytes, int ecc_ena) +{ + do_display_bm(if_num, rank, (void *)bytes, WITH_RL_SEQ_SCORES, ecc_ena); +} + +#define RODT_OHMS_COUNT 8 +#define RTT_NOM_OHMS_COUNT 8 +#define RTT_NOM_TABLE_COUNT 8 +#define RTT_WR_OHMS_COUNT 8 +#define DIC_OHMS_COUNT 3 +#define DRIVE_STRENGTH_COUNT 15 + +static unsigned char ddr4_rodt_ohms[RODT_OHMS_COUNT] = { + 0, 40, 60, 80, 120, 240, 34, 48 }; +static unsigned char ddr4_rtt_nom_ohms[RTT_NOM_OHMS_COUNT] = { + 0, 60, 120, 40, 240, 48, 80, 34 }; +static unsigned char ddr4_rtt_nom_table[RTT_NOM_TABLE_COUNT] = { + 0, 4, 2, 6, 1, 5, 3, 7 }; +// setting HiZ ohms to 99 for computed vref +static unsigned char ddr4_rtt_wr_ohms[RTT_WR_OHMS_COUNT] = { + 0, 120, 240, 99, 80 }; +static unsigned char ddr4_dic_ohms[DIC_OHMS_COUNT] = { 34, 48 }; +static short ddr4_drive_strength[DRIVE_STRENGTH_COUNT] = { + 0, 0, 26, 30, 34, 40, 48, 68, 0, 0, 0, 0, 0, 0, 0 }; +static short ddr4_dqx_strength[DRIVE_STRENGTH_COUNT] = { + 0, 24, 27, 30, 34, 40, 48, 60, 0, 0, 0, 0, 0, 0, 0 }; +struct impedence_values ddr4_impedence_val = { + .rodt_ohms = ddr4_rodt_ohms, + .rtt_nom_ohms = ddr4_rtt_nom_ohms, + .rtt_nom_table = ddr4_rtt_nom_table, + .rtt_wr_ohms = ddr4_rtt_wr_ohms, + .dic_ohms = ddr4_dic_ohms, + .drive_strength = ddr4_drive_strength, + .dqx_strength = ddr4_dqx_strength, +}; + +static unsigned char ddr3_rodt_ohms[RODT_OHMS_COUNT] = { + 0, 20, 30, 40, 60, 120, 0, 0 }; +static unsigned char ddr3_rtt_nom_ohms[RTT_NOM_OHMS_COUNT] = { + 0, 60, 120, 40, 20, 30, 0, 0 }; +static unsigned char ddr3_rtt_nom_table[RTT_NOM_TABLE_COUNT] = { + 0, 2, 1, 3, 5, 4, 0, 0 }; +static unsigned char ddr3_rtt_wr_ohms[RTT_WR_OHMS_COUNT] = { 0, 60, 120 }; +static unsigned char ddr3_dic_ohms[DIC_OHMS_COUNT] = { 40, 34 }; +static short ddr3_drive_strength[DRIVE_STRENGTH_COUNT] = { + 0, 24, 27, 30, 34, 40, 48, 60, 0, 0, 0, 0, 0, 0, 0 }; +static struct impedence_values ddr3_impedence_val = { + .rodt_ohms = ddr3_rodt_ohms, + .rtt_nom_ohms = ddr3_rtt_nom_ohms, + .rtt_nom_table = ddr3_rtt_nom_table, + .rtt_wr_ohms = ddr3_rtt_wr_ohms, + .dic_ohms = ddr3_dic_ohms, + .drive_strength = ddr3_drive_strength, + .dqx_strength = ddr3_drive_strength, +}; + +static u64 hertz_to_psecs(u64 hertz) +{ + /* Clock in psecs */ + return divide_nint((u64)1000 * 1000 * 1000 * 1000, hertz); +} + +#define DIVIDEND_SCALE 1000 /* Scale to avoid rounding error. */ + +static u64 psecs_to_mts(u64 psecs) +{ + return divide_nint(divide_nint((u64)(2 * 1000000 * DIVIDEND_SCALE), + psecs), DIVIDEND_SCALE); +} + +#define WITHIN(v, b, m) (((v) >= ((b) - (m))) && ((v) <= ((b) + (m)))) + +static unsigned long pretty_psecs_to_mts(u64 psecs) +{ + u64 ret = 0; // default to error + + if (WITHIN(psecs, 2500, 1)) + ret = 800; + else if (WITHIN(psecs, 1875, 1)) + ret = 1066; + else if (WITHIN(psecs, 1500, 1)) + ret = 1333; + else if (WITHIN(psecs, 1250, 1)) + ret = 1600; + else if (WITHIN(psecs, 1071, 1)) + ret = 1866; + else if (WITHIN(psecs, 937, 1)) + ret = 2133; + else if (WITHIN(psecs, 833, 1)) + ret = 2400; + else if (WITHIN(psecs, 750, 1)) + ret = 2666; + return ret; +} + +static u64 mts_to_hertz(u64 mts) +{ + return ((mts * 1000 * 1000) / 2); +} + +static int compute_rc3x(int64_t tclk_psecs) +{ + long speed; + long tclk_psecs_min, tclk_psecs_max; + long data_rate_mhz, data_rate_mhz_min, data_rate_mhz_max; + int rc3x; + +#define ENCODING_BASE 1240 + + data_rate_mhz = psecs_to_mts(tclk_psecs); + + /* + * 2400 MT/s is a special case. Using integer arithmetic it rounds + * from 833 psecs to 2401 MT/s. Force it to 2400 to pick the + * proper setting from the table. + */ + if (tclk_psecs == 833) + data_rate_mhz = 2400; + + for (speed = ENCODING_BASE; speed < 3200; speed += 20) { + int error = 0; + + /* Clock in psecs */ + tclk_psecs_min = hertz_to_psecs(mts_to_hertz(speed + 00)); + /* Clock in psecs */ + tclk_psecs_max = hertz_to_psecs(mts_to_hertz(speed + 18)); + + data_rate_mhz_min = psecs_to_mts(tclk_psecs_min); + data_rate_mhz_max = psecs_to_mts(tclk_psecs_max); + + /* Force alingment to multiple to avound rounding errors. */ + data_rate_mhz_min = ((data_rate_mhz_min + 18) / 20) * 20; + data_rate_mhz_max = ((data_rate_mhz_max + 18) / 20) * 20; + + error += (speed + 00 != data_rate_mhz_min); + error += (speed + 20 != data_rate_mhz_max); + + rc3x = (speed - ENCODING_BASE) / 20; + + if (data_rate_mhz <= (speed + 20)) + break; + } + + return rc3x; +} + +/* + * static global variables needed, so that functions (loops) can be + * restructured from the main huge function. Its not elegant, but the + * only way to break the original functions like init_octeon3_ddr3_interface() + * into separate logical smaller functions with less indentation levels. + */ +static int if_num __section(".data"); +static u32 if_mask __section(".data"); +static int ddr_hertz __section(".data"); + +static struct ddr_conf *ddr_conf __section(".data"); +static const struct dimm_odt_config *odt_1rank_config __section(".data"); +static const struct dimm_odt_config *odt_2rank_config __section(".data"); +static const struct dimm_odt_config *odt_4rank_config __section(".data"); +static struct dimm_config *dimm_config_table __section(".data"); +static const struct dimm_odt_config *odt_config __section(".data"); +static const struct ddr3_custom_config *c_cfg __section(".data"); + +static int odt_idx __section(".data"); + +static ulong tclk_psecs __section(".data"); +static ulong eclk_psecs __section(".data"); + +static int row_bits __section(".data"); +static int col_bits __section(".data"); +static int num_banks __section(".data"); +static int num_ranks __section(".data"); +static int dram_width __section(".data"); +static int dimm_count __section(".data"); +/* Accumulate and report all the errors before giving up */ +static int fatal_error __section(".data"); +/* Flag that indicates safe DDR settings should be used */ +static int safe_ddr_flag __section(".data"); +/* Octeon II Default: 64bit interface width */ +static int if_64b __section(".data"); +static int if_bytemask __section(".data"); +static u32 mem_size_mbytes __section(".data"); +static unsigned int didx __section(".data"); +static int bank_bits __section(".data"); +static int bunk_enable __section(".data"); +static int rank_mask __section(".data"); +static int column_bits_start __section(".data"); +static int row_lsb __section(".data"); +static int pbank_lsb __section(".data"); +static int use_ecc __section(".data"); +static int mtb_psec __section(".data"); +static short ftb_dividend __section(".data"); +static short ftb_divisor __section(".data"); +static int taamin __section(".data"); +static int tckmin __section(".data"); +static int cl __section(".data"); +static int min_cas_latency __section(".data"); +static int max_cas_latency __section(".data"); +static int override_cas_latency __section(".data"); +static int ddr_rtt_nom_auto __section(".data"); +static int ddr_rodt_ctl_auto __section(".data"); + +static int spd_addr __section(".data"); +static int spd_org __section(".data"); +static int spd_banks __section(".data"); +static int spd_rdimm __section(".data"); +static int spd_dimm_type __section(".data"); +static int spd_ecc __section(".data"); +static u32 spd_cas_latency __section(".data"); +static int spd_mtb_dividend __section(".data"); +static int spd_mtb_divisor __section(".data"); +static int spd_tck_min __section(".data"); +static int spd_taa_min __section(".data"); +static int spd_twr __section(".data"); +static int spd_trcd __section(".data"); +static int spd_trrd __section(".data"); +static int spd_trp __section(".data"); +static int spd_tras __section(".data"); +static int spd_trc __section(".data"); +static int spd_trfc __section(".data"); +static int spd_twtr __section(".data"); +static int spd_trtp __section(".data"); +static int spd_tfaw __section(".data"); +static int spd_addr_mirror __section(".data"); +static int spd_package __section(".data"); +static int spd_rawcard __section(".data"); +static int spd_rawcard_aorb __section(".data"); +static int spd_rdimm_registers __section(".data"); +static int spd_thermal_sensor __section(".data"); + +static int is_stacked_die __section(".data"); +static int is_3ds_dimm __section(".data"); +// 3DS: logical ranks per package rank +static int lranks_per_prank __section(".data"); +// 3DS: logical ranks bits +static int lranks_bits __section(".data"); +// in Mbits; only used for 3DS +static int die_capacity __section(".data"); + +static enum ddr_type ddr_type __section(".data"); + +static int twr __section(".data"); +static int trcd __section(".data"); +static int trrd __section(".data"); +static int trp __section(".data"); +static int tras __section(".data"); +static int trc __section(".data"); +static int trfc __section(".data"); +static int twtr __section(".data"); +static int trtp __section(".data"); +static int tfaw __section(".data"); + +static int ddr4_tckavgmin __section(".data"); +static int ddr4_tckavgmax __section(".data"); +static int ddr4_trdcmin __section(".data"); +static int ddr4_trpmin __section(".data"); +static int ddr4_trasmin __section(".data"); +static int ddr4_trcmin __section(".data"); +static int ddr4_trfc1min __section(".data"); +static int ddr4_trfc2min __section(".data"); +static int ddr4_trfc4min __section(".data"); +static int ddr4_tfawmin __section(".data"); +static int ddr4_trrd_smin __section(".data"); +static int ddr4_trrd_lmin __section(".data"); +static int ddr4_tccd_lmin __section(".data"); + +static int wl_mask_err __section(".data"); +static int wl_loops __section(".data"); +static int default_rtt_nom[4] __section(".data"); +static int dyn_rtt_nom_mask __section(".data"); +static struct impedence_values *imp_val __section(".data"); +static char default_rodt_ctl __section(".data"); +// default to disabled (ie, try LMC restart, not chip reset) +static int ddr_disable_chip_reset __section(".data"); +static const char *dimm_type_name __section(".data"); +static int match_wl_rtt_nom __section(".data"); + +struct hwl_alt_by_rank { + u16 hwl_alt_mask; // mask of bytelanes with alternate + u16 hwl_alt_delay[9]; // bytelane alternate avail if mask=1 +}; + +static struct hwl_alt_by_rank hwl_alts[4] __section(".data"); + +#define DEFAULT_INTERNAL_VREF_TRAINING_LIMIT 3 // was: 5 +static int internal_retries __section(".data"); + +static int deskew_training_errors __section(".data"); +static struct deskew_counts deskew_training_results __section(".data"); +static int disable_deskew_training __section(".data"); +static int restart_if_dsk_incomplete __section(".data"); +static int dac_eval_retries __section(".data"); +static int dac_settings[9] __section(".data"); +static int num_samples __section(".data"); +static int sample __section(".data"); +static int lane __section(".data"); +static int last_lane __section(".data"); +static int total_dac_eval_retries __section(".data"); +static int dac_eval_exhausted __section(".data"); + +#define DEFAULT_DAC_SAMPLES 7 // originally was 5 +#define DAC_RETRIES_LIMIT 2 + +struct bytelane_sample { + s16 bytes[DEFAULT_DAC_SAMPLES]; +}; + +static struct bytelane_sample lanes[9] __section(".data"); + +static char disable_sequential_delay_check __section(".data"); +static int wl_print __section(".data"); + +static int enable_by_rank_init __section(".data"); +static int saved_rank_mask __section(".data"); +static int by_rank __section(".data"); +static struct deskew_data rank_dsk[4] __section(".data"); +static struct dac_data rank_dac[4] __section(".data"); + +// todo: perhaps remove node at some time completely? +static int node __section(".data"); +static int base_cl __section(".data"); + +/* Parameters from DDR3 Specifications */ +#define DDR3_TREFI 7800000 /* 7.8 us */ +#define DDR3_ZQCS 80000ull /* 80 ns */ +#define DDR3_ZQCS_INTERNAL 1280000000ull /* 128ms/100 */ +#define DDR3_TCKE 5000 /* 5 ns */ +#define DDR3_TMRD 4 /* 4 nCK */ +#define DDR3_TDLLK 512 /* 512 nCK */ +#define DDR3_TMPRR 1 /* 1 nCK */ +#define DDR3_TWLMRD 40 /* 40 nCK */ +#define DDR3_TWLDQSEN 25 /* 25 nCK */ + +/* Parameters from DDR4 Specifications */ +#define DDR4_TMRD 8 /* 8 nCK */ +#define DDR4_TDLLK 768 /* 768 nCK */ + +static void lmc_config(struct ddr_priv *priv) +{ + union cvmx_lmcx_config cfg; + char *s; + + cfg.u64 = 0; + + cfg.cn78xx.ecc_ena = use_ecc; + cfg.cn78xx.row_lsb = encode_row_lsb_ddr3(row_lsb); + cfg.cn78xx.pbank_lsb = encode_pbank_lsb_ddr3(pbank_lsb); + + cfg.cn78xx.idlepower = 0; /* Disabled */ + + s = lookup_env(priv, "ddr_idlepower"); + if (s) + cfg.cn78xx.idlepower = simple_strtoul(s, NULL, 0); + + cfg.cn78xx.forcewrite = 0; /* Disabled */ + /* Include memory reference address in the ECC */ + cfg.cn78xx.ecc_adr = 1; + + s = lookup_env(priv, "ddr_ecc_adr"); + if (s) + cfg.cn78xx.ecc_adr = simple_strtoul(s, NULL, 0); + + cfg.cn78xx.reset = 0; + + /* + * Program LMC0_CONFIG[24:18], ref_zqcs_int(6:0) to + * RND-DN(tREFI/clkPeriod/512) Program LMC0_CONFIG[36:25], + * ref_zqcs_int(18:7) to + * RND-DN(ZQCS_Interval/clkPeriod/(512*128)). Note that this + * value should always be greater than 32, to account for + * resistor calibration delays. + */ + + cfg.cn78xx.ref_zqcs_int = ((DDR3_TREFI / tclk_psecs / 512) & 0x7f); + cfg.cn78xx.ref_zqcs_int |= + ((max(33ull, (DDR3_ZQCS_INTERNAL / (tclk_psecs / 100) / + (512 * 128))) & 0xfff) << 7); + + cfg.cn78xx.early_dqx = 1; /* Default to enabled */ + + s = lookup_env(priv, "ddr_early_dqx"); + if (!s) + s = lookup_env(priv, "ddr%d_early_dqx", if_num); + + if (s) + cfg.cn78xx.early_dqx = simple_strtoul(s, NULL, 0); + + cfg.cn78xx.sref_with_dll = 0; + + cfg.cn78xx.rank_ena = bunk_enable; + cfg.cn78xx.rankmask = rank_mask; /* Set later */ + cfg.cn78xx.mirrmask = (spd_addr_mirror << 1 | spd_addr_mirror << 3) & + rank_mask; + /* Set once and don't change it. */ + cfg.cn78xx.init_status = rank_mask; + cfg.cn78xx.early_unload_d0_r0 = 0; + cfg.cn78xx.early_unload_d0_r1 = 0; + cfg.cn78xx.early_unload_d1_r0 = 0; + cfg.cn78xx.early_unload_d1_r1 = 0; + cfg.cn78xx.scrz = 0; + if (octeon_is_cpuid(OCTEON_CN70XX)) + cfg.cn78xx.mode32b = 1; /* Read-only. Always 1. */ + cfg.cn78xx.mode_x4dev = (dram_width == 4) ? 1 : 0; + cfg.cn78xx.bg2_enable = ((ddr_type == DDR4_DRAM) && + (dram_width == 16)) ? 0 : 1; + + s = lookup_env_ull(priv, "ddr_config"); + if (s) + cfg.u64 = simple_strtoull(s, NULL, 0); + debug("LMC_CONFIG : 0x%016llx\n", + cfg.u64); + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), cfg.u64); +} + +static void lmc_control(struct ddr_priv *priv) +{ + union cvmx_lmcx_control ctrl; + char *s; + + ctrl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + ctrl.s.rdimm_ena = spd_rdimm; + ctrl.s.bwcnt = 0; /* Clear counter later */ + if (spd_rdimm) + ctrl.s.ddr2t = (safe_ddr_flag ? 1 : c_cfg->ddr2t_rdimm); + else + ctrl.s.ddr2t = (safe_ddr_flag ? 1 : c_cfg->ddr2t_udimm); + ctrl.s.pocas = 0; + ctrl.s.fprch2 = (safe_ddr_flag ? 2 : c_cfg->fprch2); + ctrl.s.throttle_rd = safe_ddr_flag ? 1 : 0; + ctrl.s.throttle_wr = safe_ddr_flag ? 1 : 0; + ctrl.s.inorder_rd = safe_ddr_flag ? 1 : 0; + ctrl.s.inorder_wr = safe_ddr_flag ? 1 : 0; + ctrl.s.elev_prio_dis = safe_ddr_flag ? 1 : 0; + /* discards writes to addresses that don't exist in the DRAM */ + ctrl.s.nxm_write_en = 0; + ctrl.s.max_write_batch = 8; + ctrl.s.xor_bank = 1; + ctrl.s.auto_dclkdis = 1; + ctrl.s.int_zqcs_dis = 0; + ctrl.s.ext_zqcs_dis = 0; + ctrl.s.bprch = 1; + ctrl.s.wodt_bprch = 1; + ctrl.s.rodt_bprch = 1; + + s = lookup_env(priv, "ddr_xor_bank"); + if (s) + ctrl.s.xor_bank = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_2t"); + if (s) + ctrl.s.ddr2t = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_fprch2"); + if (s) + ctrl.s.fprch2 = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_bprch"); + if (s) + ctrl.s.bprch = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_wodt_bprch"); + if (s) + ctrl.s.wodt_bprch = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rodt_bprch"); + if (s) + ctrl.s.rodt_bprch = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_int_zqcs_dis"); + if (s) + ctrl.s.int_zqcs_dis = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_ext_zqcs_dis"); + if (s) + ctrl.s.ext_zqcs_dis = simple_strtoul(s, NULL, 0); + + s = lookup_env_ull(priv, "ddr_control"); + if (s) + ctrl.u64 = simple_strtoull(s, NULL, 0); + + debug("LMC_CONTROL : 0x%016llx\n", + ctrl.u64); + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctrl.u64); +} + +static void lmc_timing_params0(struct ddr_priv *priv) +{ + union cvmx_lmcx_timing_params0 tp0; + unsigned int trp_value; + char *s; + + tp0.u64 = lmc_rd(priv, CVMX_LMCX_TIMING_PARAMS0(if_num)); + + trp_value = divide_roundup(trp, tclk_psecs) - 1; + debug("TIMING_PARAMS0[TRP]: NEW 0x%x, OLD 0x%x\n", trp_value, + trp_value + + (unsigned int)(divide_roundup(max(4ull * tclk_psecs, 7500ull), + tclk_psecs)) - 4); + s = lookup_env_ull(priv, "ddr_use_old_trp"); + if (s) { + if (!!simple_strtoull(s, NULL, 0)) { + trp_value += + divide_roundup(max(4ull * tclk_psecs, 7500ull), + tclk_psecs) - 4; + debug("TIMING_PARAMS0[trp]: USING OLD 0x%x\n", + trp_value); + } + } + + tp0.cn78xx.txpr = + divide_roundup(max(5ull * tclk_psecs, trfc + 10000ull), + 16 * tclk_psecs); + tp0.cn78xx.trp = trp_value & 0x1f; + tp0.cn78xx.tcksre = + divide_roundup(max(5ull * tclk_psecs, 10000ull), tclk_psecs) - 1; + + if (ddr_type == DDR4_DRAM) { + int tzqinit = 4; // Default to 4, for all DDR4 speed bins + + s = lookup_env(priv, "ddr_tzqinit"); + if (s) + tzqinit = simple_strtoul(s, NULL, 0); + + tp0.cn78xx.tzqinit = tzqinit; + /* Always 8. */ + tp0.cn78xx.tzqcs = divide_roundup(128 * tclk_psecs, + (16 * tclk_psecs)); + tp0.cn78xx.tcke = + divide_roundup(max(3 * tclk_psecs, (ulong)DDR3_TCKE), + tclk_psecs) - 1; + tp0.cn78xx.tmrd = + divide_roundup((DDR4_TMRD * tclk_psecs), tclk_psecs) - 1; + tp0.cn78xx.tmod = 25; /* 25 is the max allowed */ + tp0.cn78xx.tdllk = divide_roundup(DDR4_TDLLK, 256); + } else { + tp0.cn78xx.tzqinit = + divide_roundup(max(512ull * tclk_psecs, 640000ull), + (256 * tclk_psecs)); + tp0.cn78xx.tzqcs = + divide_roundup(max(64ull * tclk_psecs, DDR3_ZQCS), + (16 * tclk_psecs)); + tp0.cn78xx.tcke = divide_roundup(DDR3_TCKE, tclk_psecs) - 1; + tp0.cn78xx.tmrd = + divide_roundup((DDR3_TMRD * tclk_psecs), tclk_psecs) - 1; + tp0.cn78xx.tmod = + divide_roundup(max(12ull * tclk_psecs, 15000ull), + tclk_psecs) - 1; + tp0.cn78xx.tdllk = divide_roundup(DDR3_TDLLK, 256); + } + + s = lookup_env_ull(priv, "ddr_timing_params0"); + if (s) + tp0.u64 = simple_strtoull(s, NULL, 0); + debug("TIMING_PARAMS0 : 0x%016llx\n", + tp0.u64); + lmc_wr(priv, CVMX_LMCX_TIMING_PARAMS0(if_num), tp0.u64); +} + +static void lmc_timing_params1(struct ddr_priv *priv) +{ + union cvmx_lmcx_timing_params1 tp1; + unsigned int txp, temp_trcd, trfc_dlr; + char *s; + + tp1.u64 = lmc_rd(priv, CVMX_LMCX_TIMING_PARAMS1(if_num)); + + /* .cn70xx. */ + tp1.s.tmprr = divide_roundup(DDR3_TMPRR * tclk_psecs, tclk_psecs) - 1; + + tp1.cn78xx.tras = divide_roundup(tras, tclk_psecs) - 1; + + temp_trcd = divide_roundup(trcd, tclk_psecs); + if (temp_trcd > 15) { + debug("TIMING_PARAMS1[trcd]: need extension bit for 0x%x\n", + temp_trcd); + } + if (octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) && temp_trcd > 15) { + /* + * Let .trcd=0 serve as a flag that the field has + * overflowed. Must use Additive Latency mode as a + * workaround. + */ + temp_trcd = 0; + } + tp1.cn78xx.trcd = (temp_trcd >> 0) & 0xf; + tp1.cn78xx.trcd_ext = (temp_trcd >> 4) & 0x1; + + tp1.cn78xx.twtr = divide_roundup(twtr, tclk_psecs) - 1; + tp1.cn78xx.trfc = divide_roundup(trfc, 8 * tclk_psecs); + + if (ddr_type == DDR4_DRAM) { + /* Workaround bug 24006. Use Trrd_l. */ + tp1.cn78xx.trrd = + divide_roundup(ddr4_trrd_lmin, tclk_psecs) - 2; + } else { + tp1.cn78xx.trrd = divide_roundup(trrd, tclk_psecs) - 2; + } + + /* + * tXP = max( 3nCK, 7.5 ns) DDR3-800 tCLK = 2500 psec + * tXP = max( 3nCK, 7.5 ns) DDR3-1066 tCLK = 1875 psec + * tXP = max( 3nCK, 6.0 ns) DDR3-1333 tCLK = 1500 psec + * tXP = max( 3nCK, 6.0 ns) DDR3-1600 tCLK = 1250 psec + * tXP = max( 3nCK, 6.0 ns) DDR3-1866 tCLK = 1071 psec + * tXP = max( 3nCK, 6.0 ns) DDR3-2133 tCLK = 937 psec + */ + txp = (tclk_psecs < 1875) ? 6000 : 7500; + txp = divide_roundup(max((unsigned int)(3 * tclk_psecs), txp), + tclk_psecs) - 1; + if (txp > 7) { + debug("TIMING_PARAMS1[txp]: need extension bit for 0x%x\n", + txp); + } + if (octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) && txp > 7) + txp = 7; // max it out + tp1.cn78xx.txp = (txp >> 0) & 7; + tp1.cn78xx.txp_ext = (txp >> 3) & 1; + + tp1.cn78xx.twlmrd = divide_roundup(DDR3_TWLMRD * tclk_psecs, + 4 * tclk_psecs); + tp1.cn78xx.twldqsen = divide_roundup(DDR3_TWLDQSEN * tclk_psecs, + 4 * tclk_psecs); + tp1.cn78xx.tfaw = divide_roundup(tfaw, 4 * tclk_psecs); + tp1.cn78xx.txpdll = divide_roundup(max(10ull * tclk_psecs, 24000ull), + tclk_psecs) - 1; + + if (ddr_type == DDR4_DRAM && is_3ds_dimm) { + /* + * 4 Gb: tRFC_DLR = 90 ns + * 8 Gb: tRFC_DLR = 120 ns + * 16 Gb: tRFC_DLR = 190 ns FIXME? + */ + if (die_capacity == 0x1000) // 4 Gbit + trfc_dlr = 90; + else if (die_capacity == 0x2000) // 8 Gbit + trfc_dlr = 120; + else if (die_capacity == 0x4000) // 16 Gbit + trfc_dlr = 190; + else + trfc_dlr = 0; + + if (trfc_dlr == 0) { + debug("N%d.LMC%d: ERROR: tRFC_DLR: die_capacity %u Mbit is illegal\n", + node, if_num, die_capacity); + } else { + tp1.cn78xx.trfc_dlr = + divide_roundup(trfc_dlr * 1000UL, 8 * tclk_psecs); + debug("N%d.LMC%d: TIMING_PARAMS1[trfc_dlr] set to %u\n", + node, if_num, tp1.cn78xx.trfc_dlr); + } + } + + s = lookup_env_ull(priv, "ddr_timing_params1"); + if (s) + tp1.u64 = simple_strtoull(s, NULL, 0); + + debug("TIMING_PARAMS1 : 0x%016llx\n", + tp1.u64); + lmc_wr(priv, CVMX_LMCX_TIMING_PARAMS1(if_num), tp1.u64); +} + +static void lmc_timing_params2(struct ddr_priv *priv) +{ + if (ddr_type == DDR4_DRAM) { + union cvmx_lmcx_timing_params1 tp1; + union cvmx_lmcx_timing_params2 tp2; + int temp_trrd_l; + + tp1.u64 = lmc_rd(priv, CVMX_LMCX_TIMING_PARAMS1(if_num)); + tp2.u64 = lmc_rd(priv, CVMX_LMCX_TIMING_PARAMS2(if_num)); + debug("TIMING_PARAMS2 : 0x%016llx\n", + tp2.u64); + + temp_trrd_l = divide_roundup(ddr4_trrd_lmin, tclk_psecs) - 2; + if (temp_trrd_l > 7) + debug("TIMING_PARAMS2[trrd_l]: need extension bit for 0x%x\n", + temp_trrd_l); + if (octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) && temp_trrd_l > 7) + temp_trrd_l = 7; // max it out + tp2.cn78xx.trrd_l = (temp_trrd_l >> 0) & 7; + tp2.cn78xx.trrd_l_ext = (temp_trrd_l >> 3) & 1; + + // correct for 1600-2400 + tp2.s.twtr_l = divide_nint(max(4ull * tclk_psecs, 7500ull), + tclk_psecs) - 1; + tp2.s.t_rw_op_max = 7; + tp2.s.trtp = divide_roundup(max(4ull * tclk_psecs, 7500ull), + tclk_psecs) - 1; + + debug("TIMING_PARAMS2 : 0x%016llx\n", + tp2.u64); + lmc_wr(priv, CVMX_LMCX_TIMING_PARAMS2(if_num), tp2.u64); + + /* + * Workaround Errata 25823 - LMC: Possible DDR4 tWTR_L not met + * for Write-to-Read operations to the same Bank Group + */ + if (tp1.cn78xx.twtr < (tp2.s.twtr_l - 4)) { + tp1.cn78xx.twtr = tp2.s.twtr_l - 4; + debug("ERRATA 25823: NEW: TWTR: %d, TWTR_L: %d\n", + tp1.cn78xx.twtr, tp2.s.twtr_l); + debug("TIMING_PARAMS1 : 0x%016llx\n", + tp1.u64); + lmc_wr(priv, CVMX_LMCX_TIMING_PARAMS1(if_num), tp1.u64); + } + } +} + +static void lmc_modereg_params0(struct ddr_priv *priv) +{ + union cvmx_lmcx_modereg_params0 mp0; + int param; + char *s; + + mp0.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num)); + + if (ddr_type == DDR4_DRAM) { + mp0.s.cwl = 0; /* 1600 (1250ps) */ + if (tclk_psecs < 1250) + mp0.s.cwl = 1; /* 1866 (1072ps) */ + if (tclk_psecs < 1072) + mp0.s.cwl = 2; /* 2133 (938ps) */ + if (tclk_psecs < 938) + mp0.s.cwl = 3; /* 2400 (833ps) */ + if (tclk_psecs < 833) + mp0.s.cwl = 4; /* 2666 (750ps) */ + if (tclk_psecs < 750) + mp0.s.cwl = 5; /* 3200 (625ps) */ + } else { + /* + ** CSR CWL CAS write Latency + ** === === ================================= + ** 0 5 ( tCK(avg) >= 2.5 ns) + ** 1 6 (2.5 ns > tCK(avg) >= 1.875 ns) + ** 2 7 (1.875 ns > tCK(avg) >= 1.5 ns) + ** 3 8 (1.5 ns > tCK(avg) >= 1.25 ns) + ** 4 9 (1.25 ns > tCK(avg) >= 1.07 ns) + ** 5 10 (1.07 ns > tCK(avg) >= 0.935 ns) + ** 6 11 (0.935 ns > tCK(avg) >= 0.833 ns) + ** 7 12 (0.833 ns > tCK(avg) >= 0.75 ns) + */ + + mp0.s.cwl = 0; + if (tclk_psecs < 2500) + mp0.s.cwl = 1; + if (tclk_psecs < 1875) + mp0.s.cwl = 2; + if (tclk_psecs < 1500) + mp0.s.cwl = 3; + if (tclk_psecs < 1250) + mp0.s.cwl = 4; + if (tclk_psecs < 1070) + mp0.s.cwl = 5; + if (tclk_psecs < 935) + mp0.s.cwl = 6; + if (tclk_psecs < 833) + mp0.s.cwl = 7; + } + + s = lookup_env(priv, "ddr_cwl"); + if (s) + mp0.s.cwl = simple_strtoul(s, NULL, 0) - 5; + + if (ddr_type == DDR4_DRAM) { + debug("%-45s : %d, [0x%x]\n", "CAS Write Latency CWL, [CSR]", + mp0.s.cwl + 9 + + ((mp0.s.cwl > 2) ? (mp0.s.cwl - 3) * 2 : 0), mp0.s.cwl); + } else { + debug("%-45s : %d, [0x%x]\n", "CAS Write Latency CWL, [CSR]", + mp0.s.cwl + 5, mp0.s.cwl); + } + + mp0.s.mprloc = 0; + mp0.s.mpr = 0; + mp0.s.dll = (ddr_type == DDR4_DRAM); /* 0 for DDR3 and 1 for DDR4 */ + mp0.s.al = 0; + mp0.s.wlev = 0; /* Read Only */ + if (octeon_is_cpuid(OCTEON_CN70XX) || ddr_type == DDR4_DRAM) + mp0.s.tdqs = 0; + else + mp0.s.tdqs = 1; + mp0.s.qoff = 0; + + s = lookup_env(priv, "ddr_cl"); + if (s) { + cl = simple_strtoul(s, NULL, 0); + debug("CAS Latency : %6d\n", + cl); + } + + if (ddr_type == DDR4_DRAM) { + mp0.s.cl = 0x0; + if (cl > 9) + mp0.s.cl = 0x1; + if (cl > 10) + mp0.s.cl = 0x2; + if (cl > 11) + mp0.s.cl = 0x3; + if (cl > 12) + mp0.s.cl = 0x4; + if (cl > 13) + mp0.s.cl = 0x5; + if (cl > 14) + mp0.s.cl = 0x6; + if (cl > 15) + mp0.s.cl = 0x7; + if (cl > 16) + mp0.s.cl = 0x8; + if (cl > 18) + mp0.s.cl = 0x9; + if (cl > 20) + mp0.s.cl = 0xA; + if (cl > 24) + mp0.s.cl = 0xB; + } else { + mp0.s.cl = 0x2; + if (cl > 5) + mp0.s.cl = 0x4; + if (cl > 6) + mp0.s.cl = 0x6; + if (cl > 7) + mp0.s.cl = 0x8; + if (cl > 8) + mp0.s.cl = 0xA; + if (cl > 9) + mp0.s.cl = 0xC; + if (cl > 10) + mp0.s.cl = 0xE; + if (cl > 11) + mp0.s.cl = 0x1; + if (cl > 12) + mp0.s.cl = 0x3; + if (cl > 13) + mp0.s.cl = 0x5; + if (cl > 14) + mp0.s.cl = 0x7; + if (cl > 15) + mp0.s.cl = 0x9; + } + + mp0.s.rbt = 0; /* Read Only. */ + mp0.s.tm = 0; + mp0.s.dllr = 0; + + param = divide_roundup(twr, tclk_psecs); + + if (ddr_type == DDR4_DRAM) { /* DDR4 */ + mp0.s.wrp = 1; + if (param > 12) + mp0.s.wrp = 2; + if (param > 14) + mp0.s.wrp = 3; + if (param > 16) + mp0.s.wrp = 4; + if (param > 18) + mp0.s.wrp = 5; + if (param > 20) + mp0.s.wrp = 6; + if (param > 24) /* RESERVED in DDR4 spec */ + mp0.s.wrp = 7; + } else { /* DDR3 */ + mp0.s.wrp = 1; + if (param > 5) + mp0.s.wrp = 2; + if (param > 6) + mp0.s.wrp = 3; + if (param > 7) + mp0.s.wrp = 4; + if (param > 8) + mp0.s.wrp = 5; + if (param > 10) + mp0.s.wrp = 6; + if (param > 12) + mp0.s.wrp = 7; + } + + mp0.s.ppd = 0; + + s = lookup_env(priv, "ddr_wrp"); + if (s) + mp0.s.wrp = simple_strtoul(s, NULL, 0); + + debug("%-45s : %d, [0x%x]\n", + "Write recovery for auto precharge WRP, [CSR]", param, mp0.s.wrp); + + s = lookup_env_ull(priv, "ddr_modereg_params0"); + if (s) + mp0.u64 = simple_strtoull(s, NULL, 0); + + debug("MODEREG_PARAMS0 : 0x%016llx\n", + mp0.u64); + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num), mp0.u64); +} + +static void lmc_modereg_params1(struct ddr_priv *priv) +{ + union cvmx_lmcx_modereg_params1 mp1; + char *s; + int i; + + mp1.u64 = odt_config[odt_idx].modereg_params1.u64; + + /* + * Special request: mismatched DIMM support. Slot 0: 2-Rank, + * Slot 1: 1-Rank + */ + if (rank_mask == 0x7) { /* 2-Rank, 1-Rank */ + mp1.s.rtt_nom_00 = 0; + mp1.s.rtt_nom_01 = 3; /* rttnom_40ohm */ + mp1.s.rtt_nom_10 = 3; /* rttnom_40ohm */ + mp1.s.rtt_nom_11 = 0; + dyn_rtt_nom_mask = 0x6; + } + + s = lookup_env(priv, "ddr_rtt_nom_mask"); + if (s) + dyn_rtt_nom_mask = simple_strtoul(s, NULL, 0); + + /* + * Save the original rtt_nom settings before sweeping through + * settings. + */ + default_rtt_nom[0] = mp1.s.rtt_nom_00; + default_rtt_nom[1] = mp1.s.rtt_nom_01; + default_rtt_nom[2] = mp1.s.rtt_nom_10; + default_rtt_nom[3] = mp1.s.rtt_nom_11; + + ddr_rtt_nom_auto = c_cfg->ddr_rtt_nom_auto; + + for (i = 0; i < 4; ++i) { + u64 value; + + s = lookup_env(priv, "ddr_rtt_nom_%1d%1d", !!(i & 2), + !!(i & 1)); + if (!s) + s = lookup_env(priv, "ddr%d_rtt_nom_%1d%1d", if_num, + !!(i & 2), !!(i & 1)); + if (s) { + value = simple_strtoul(s, NULL, 0); + mp1.u64 &= ~((u64)0x7 << (i * 12 + 9)); + mp1.u64 |= ((value & 0x7) << (i * 12 + 9)); + default_rtt_nom[i] = value; + ddr_rtt_nom_auto = 0; + } + } + + s = lookup_env(priv, "ddr_rtt_nom"); + if (!s) + s = lookup_env(priv, "ddr%d_rtt_nom", if_num); + if (s) { + u64 value; + + value = simple_strtoul(s, NULL, 0); + + if (dyn_rtt_nom_mask & 1) { + default_rtt_nom[0] = value; + mp1.s.rtt_nom_00 = value; + } + if (dyn_rtt_nom_mask & 2) { + default_rtt_nom[1] = value; + mp1.s.rtt_nom_01 = value; + } + if (dyn_rtt_nom_mask & 4) { + default_rtt_nom[2] = value; + mp1.s.rtt_nom_10 = value; + } + if (dyn_rtt_nom_mask & 8) { + default_rtt_nom[3] = value; + mp1.s.rtt_nom_11 = value; + } + + ddr_rtt_nom_auto = 0; + } + + for (i = 0; i < 4; ++i) { + u64 value; + + s = lookup_env(priv, "ddr_rtt_wr_%1d%1d", !!(i & 2), !!(i & 1)); + if (!s) + s = lookup_env(priv, "ddr%d_rtt_wr_%1d%1d", if_num, + !!(i & 2), !!(i & 1)); + if (s) { + value = simple_strtoul(s, NULL, 0); + insrt_wr(&mp1.u64, i, value); + } + } + + // Make sure 78XX pass 1 has valid RTT_WR settings, because + // configuration files may be set-up for later chips, and + // 78XX pass 1 supports no RTT_WR extension bits + if (octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) { + for (i = 0; i < 4; ++i) { + // if 80 or undefined + if (extr_wr(mp1.u64, i) > 3) { + // FIXME? always insert 120 + insrt_wr(&mp1.u64, i, 1); + debug("RTT_WR_%d%d set to 120 for CN78XX pass 1\n", + !!(i & 2), i & 1); + } + } + } + + s = lookup_env(priv, "ddr_dic"); + if (s) { + u64 value = simple_strtoul(s, NULL, 0); + + for (i = 0; i < 4; ++i) { + mp1.u64 &= ~((u64)0x3 << (i * 12 + 7)); + mp1.u64 |= ((value & 0x3) << (i * 12 + 7)); + } + } + + for (i = 0; i < 4; ++i) { + u64 value; + + s = lookup_env(priv, "ddr_dic_%1d%1d", !!(i & 2), !!(i & 1)); + if (s) { + value = simple_strtoul(s, NULL, 0); + mp1.u64 &= ~((u64)0x3 << (i * 12 + 7)); + mp1.u64 |= ((value & 0x3) << (i * 12 + 7)); + } + } + + s = lookup_env_ull(priv, "ddr_modereg_params1"); + if (s) + mp1.u64 = simple_strtoull(s, NULL, 0); + + debug("RTT_NOM %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_11], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_10], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_01], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_00], + mp1.s.rtt_nom_11, + mp1.s.rtt_nom_10, mp1.s.rtt_nom_01, mp1.s.rtt_nom_00); + + debug("RTT_WR %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 3)], + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 2)], + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 1)], + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 0)], + extr_wr(mp1.u64, 3), + extr_wr(mp1.u64, 2), extr_wr(mp1.u64, 1), extr_wr(mp1.u64, 0)); + + debug("DIC %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->dic_ohms[mp1.s.dic_11], + imp_val->dic_ohms[mp1.s.dic_10], + imp_val->dic_ohms[mp1.s.dic_01], + imp_val->dic_ohms[mp1.s.dic_00], + mp1.s.dic_11, mp1.s.dic_10, mp1.s.dic_01, mp1.s.dic_00); + + debug("MODEREG_PARAMS1 : 0x%016llx\n", + mp1.u64); + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS1(if_num), mp1.u64); +} + +static void lmc_modereg_params2(struct ddr_priv *priv) +{ + char *s; + int i; + + if (ddr_type == DDR4_DRAM) { + union cvmx_lmcx_modereg_params2 mp2; + + mp2.u64 = odt_config[odt_idx].modereg_params2.u64; + + s = lookup_env(priv, "ddr_rtt_park"); + if (s) { + u64 value = simple_strtoul(s, NULL, 0); + + for (i = 0; i < 4; ++i) { + mp2.u64 &= ~((u64)0x7 << (i * 10 + 0)); + mp2.u64 |= ((value & 0x7) << (i * 10 + 0)); + } + } + + for (i = 0; i < 4; ++i) { + u64 value; + + s = lookup_env(priv, "ddr_rtt_park_%1d%1d", !!(i & 2), + !!(i & 1)); + if (s) { + value = simple_strtoul(s, NULL, 0); + mp2.u64 &= ~((u64)0x7 << (i * 10 + 0)); + mp2.u64 |= ((value & 0x7) << (i * 10 + 0)); + } + } + + s = lookup_env_ull(priv, "ddr_modereg_params2"); + if (s) + mp2.u64 = simple_strtoull(s, NULL, 0); + + debug("RTT_PARK %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->rtt_nom_ohms[mp2.s.rtt_park_11], + imp_val->rtt_nom_ohms[mp2.s.rtt_park_10], + imp_val->rtt_nom_ohms[mp2.s.rtt_park_01], + imp_val->rtt_nom_ohms[mp2.s.rtt_park_00], + mp2.s.rtt_park_11, mp2.s.rtt_park_10, mp2.s.rtt_park_01, + mp2.s.rtt_park_00); + + debug("%-45s : 0x%x,0x%x,0x%x,0x%x\n", "VREF_RANGE", + mp2.s.vref_range_11, + mp2.s.vref_range_10, + mp2.s.vref_range_01, mp2.s.vref_range_00); + + debug("%-45s : 0x%x,0x%x,0x%x,0x%x\n", "VREF_VALUE", + mp2.s.vref_value_11, + mp2.s.vref_value_10, + mp2.s.vref_value_01, mp2.s.vref_value_00); + + debug("MODEREG_PARAMS2 : 0x%016llx\n", + mp2.u64); + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS2(if_num), mp2.u64); + } +} + +static void lmc_modereg_params3(struct ddr_priv *priv) +{ + char *s; + + if (ddr_type == DDR4_DRAM) { + union cvmx_lmcx_modereg_params3 mp3; + + mp3.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS3(if_num)); + /* Disable as workaround to Errata 20547 */ + mp3.s.rd_dbi = 0; + mp3.s.tccd_l = max(divide_roundup(ddr4_tccd_lmin, tclk_psecs), + 5ull) - 4; + + s = lookup_env(priv, "ddr_rd_preamble"); + if (s) + mp3.s.rd_preamble = !!simple_strtoul(s, NULL, 0); + + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) { + int delay = 0; + + if (lranks_per_prank == 4 && ddr_hertz >= 1000000000) + delay = 1; + + mp3.s.xrank_add_tccd_l = delay; + mp3.s.xrank_add_tccd_s = delay; + } + + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS3(if_num), mp3.u64); + debug("MODEREG_PARAMS3 : 0x%016llx\n", + mp3.u64); + } +} + +static void lmc_nxm(struct ddr_priv *priv) +{ + union cvmx_lmcx_nxm lmc_nxm; + int num_bits = row_lsb + row_bits + lranks_bits - 26; + char *s; + + lmc_nxm.u64 = lmc_rd(priv, CVMX_LMCX_NXM(if_num)); + + /* .cn78xx. */ + if (rank_mask & 0x1) + lmc_nxm.cn78xx.mem_msb_d0_r0 = num_bits; + if (rank_mask & 0x2) + lmc_nxm.cn78xx.mem_msb_d0_r1 = num_bits; + if (rank_mask & 0x4) + lmc_nxm.cn78xx.mem_msb_d1_r0 = num_bits; + if (rank_mask & 0x8) + lmc_nxm.cn78xx.mem_msb_d1_r1 = num_bits; + + /* Set the mask for non-existent ranks. */ + lmc_nxm.cn78xx.cs_mask = ~rank_mask & 0xff; + + s = lookup_env_ull(priv, "ddr_nxm"); + if (s) + lmc_nxm.u64 = simple_strtoull(s, NULL, 0); + + debug("LMC_NXM : 0x%016llx\n", + lmc_nxm.u64); + lmc_wr(priv, CVMX_LMCX_NXM(if_num), lmc_nxm.u64); +} + +static void lmc_wodt_mask(struct ddr_priv *priv) +{ + union cvmx_lmcx_wodt_mask wodt_mask; + char *s; + + wodt_mask.u64 = odt_config[odt_idx].odt_mask; + + s = lookup_env_ull(priv, "ddr_wodt_mask"); + if (s) + wodt_mask.u64 = simple_strtoull(s, NULL, 0); + + debug("WODT_MASK : 0x%016llx\n", + wodt_mask.u64); + lmc_wr(priv, CVMX_LMCX_WODT_MASK(if_num), wodt_mask.u64); +} + +static void lmc_rodt_mask(struct ddr_priv *priv) +{ + union cvmx_lmcx_rodt_mask rodt_mask; + int rankx; + char *s; + + rodt_mask.u64 = odt_config[odt_idx].rodt_ctl; + + s = lookup_env_ull(priv, "ddr_rodt_mask"); + if (s) + rodt_mask.u64 = simple_strtoull(s, NULL, 0); + + debug("%-45s : 0x%016llx\n", "RODT_MASK", rodt_mask.u64); + lmc_wr(priv, CVMX_LMCX_RODT_MASK(if_num), rodt_mask.u64); + + dyn_rtt_nom_mask = 0; + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + dyn_rtt_nom_mask |= ((rodt_mask.u64 >> (8 * rankx)) & 0xff); + } + if (num_ranks == 4) { + /* + * Normally ODT1 is wired to rank 1. For quad-ranked DIMMs + * ODT1 is wired to the third rank (rank 2). The mask, + * dyn_rtt_nom_mask, is used to indicate for which ranks + * to sweep RTT_NOM during read-leveling. Shift the bit + * from the ODT1 position over to the "ODT2" position so + * that the read-leveling analysis comes out right. + */ + int odt1_bit = dyn_rtt_nom_mask & 2; + + dyn_rtt_nom_mask &= ~2; + dyn_rtt_nom_mask |= odt1_bit << 1; + } + debug("%-45s : 0x%02x\n", "DYN_RTT_NOM_MASK", dyn_rtt_nom_mask); +} + +static void lmc_comp_ctl2(struct ddr_priv *priv) +{ + union cvmx_lmcx_comp_ctl2 cc2; + char *s; + + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + + cc2.cn78xx.dqx_ctl = odt_config[odt_idx].odt_ena; + /* Default 4=34.3 ohm */ + cc2.cn78xx.ck_ctl = (c_cfg->ck_ctl == 0) ? 4 : c_cfg->ck_ctl; + /* Default 4=34.3 ohm */ + cc2.cn78xx.cmd_ctl = (c_cfg->cmd_ctl == 0) ? 4 : c_cfg->cmd_ctl; + /* Default 4=34.3 ohm */ + cc2.cn78xx.control_ctl = (c_cfg->ctl_ctl == 0) ? 4 : c_cfg->ctl_ctl; + + ddr_rodt_ctl_auto = c_cfg->ddr_rodt_ctl_auto; + s = lookup_env(priv, "ddr_rodt_ctl_auto"); + if (s) + ddr_rodt_ctl_auto = !!simple_strtoul(s, NULL, 0); + + default_rodt_ctl = odt_config[odt_idx].qs_dic; + s = lookup_env(priv, "ddr_rodt_ctl"); + if (!s) + s = lookup_env(priv, "ddr%d_rodt_ctl", if_num); + if (s) { + default_rodt_ctl = simple_strtoul(s, NULL, 0); + ddr_rodt_ctl_auto = 0; + } + + cc2.cn70xx.rodt_ctl = default_rodt_ctl; + + // if DDR4, force CK_CTL to 26 ohms if it is currently 34 ohms, + // and DCLK speed is 1 GHz or more... + if (ddr_type == DDR4_DRAM && cc2.s.ck_ctl == ddr4_driver_34_ohm && + ddr_hertz >= 1000000000) { + // lowest for DDR4 is 26 ohms + cc2.s.ck_ctl = ddr4_driver_26_ohm; + debug("N%d.LMC%d: Forcing DDR4 COMP_CTL2[CK_CTL] to %d, %d ohms\n", + node, if_num, cc2.s.ck_ctl, + imp_val->drive_strength[cc2.s.ck_ctl]); + } + + // if DDR4, 2DPC, UDIMM, force CONTROL_CTL and CMD_CTL to 26 ohms, + // if DCLK speed is 1 GHz or more... + if (ddr_type == DDR4_DRAM && dimm_count == 2 && + (spd_dimm_type == 2 || spd_dimm_type == 6) && + ddr_hertz >= 1000000000) { + // lowest for DDR4 is 26 ohms + cc2.cn78xx.control_ctl = ddr4_driver_26_ohm; + // lowest for DDR4 is 26 ohms + cc2.cn78xx.cmd_ctl = ddr4_driver_26_ohm; + debug("N%d.LMC%d: Forcing DDR4 COMP_CTL2[CONTROL_CTL,CMD_CTL] to %d, %d ohms\n", + node, if_num, ddr4_driver_26_ohm, + imp_val->drive_strength[ddr4_driver_26_ohm]); + } + + s = lookup_env(priv, "ddr_ck_ctl"); + if (s) + cc2.cn78xx.ck_ctl = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_cmd_ctl"); + if (s) + cc2.cn78xx.cmd_ctl = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_control_ctl"); + if (s) + cc2.cn70xx.control_ctl = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_dqx_ctl"); + if (s) + cc2.cn78xx.dqx_ctl = simple_strtoul(s, NULL, 0); + + debug("%-45s : %d, %d ohms\n", "DQX_CTL ", cc2.cn78xx.dqx_ctl, + imp_val->drive_strength[cc2.cn78xx.dqx_ctl]); + debug("%-45s : %d, %d ohms\n", "CK_CTL ", cc2.cn78xx.ck_ctl, + imp_val->drive_strength[cc2.cn78xx.ck_ctl]); + debug("%-45s : %d, %d ohms\n", "CMD_CTL ", cc2.cn78xx.cmd_ctl, + imp_val->drive_strength[cc2.cn78xx.cmd_ctl]); + debug("%-45s : %d, %d ohms\n", "CONTROL_CTL ", + cc2.cn78xx.control_ctl, + imp_val->drive_strength[cc2.cn78xx.control_ctl]); + debug("Read ODT_CTL : 0x%x (%d ohms)\n", + cc2.cn78xx.rodt_ctl, imp_val->rodt_ohms[cc2.cn78xx.rodt_ctl]); + + debug("%-45s : 0x%016llx\n", "COMP_CTL2", cc2.u64); + lmc_wr(priv, CVMX_LMCX_COMP_CTL2(if_num), cc2.u64); +} + +static void lmc_phy_ctl(struct ddr_priv *priv) +{ + union cvmx_lmcx_phy_ctl phy_ctl; + + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.ts_stagger = 0; + // FIXME: are there others TBD? + phy_ctl.s.dsk_dbg_overwrt_ena = 0; + + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) && lranks_per_prank > 1) { + // C0 is TEN, C1 is A17 + phy_ctl.s.c0_sel = 2; + phy_ctl.s.c1_sel = 2; + debug("N%d.LMC%d: 3DS: setting PHY_CTL[cx_csel] = %d\n", + node, if_num, phy_ctl.s.c1_sel); + } + + debug("PHY_CTL : 0x%016llx\n", + phy_ctl.u64); + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); +} + +static void lmc_ext_config(struct ddr_priv *priv) +{ + union cvmx_lmcx_ext_config ext_cfg; + char *s; + + ext_cfg.u64 = lmc_rd(priv, CVMX_LMCX_EXT_CONFIG(if_num)); + ext_cfg.s.vrefint_seq_deskew = 0; + ext_cfg.s.read_ena_bprch = 1; + ext_cfg.s.read_ena_fprch = 1; + ext_cfg.s.drive_ena_fprch = 1; + ext_cfg.s.drive_ena_bprch = 1; + // make sure this is OFF for all current chips + ext_cfg.s.invert_data = 0; + + s = lookup_env(priv, "ddr_read_fprch"); + if (s) + ext_cfg.s.read_ena_fprch = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_read_bprch"); + if (s) + ext_cfg.s.read_ena_bprch = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_drive_fprch"); + if (s) + ext_cfg.s.drive_ena_fprch = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_drive_bprch"); + if (s) + ext_cfg.s.drive_ena_bprch = strtoul(s, NULL, 0); + + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) && lranks_per_prank > 1) { + ext_cfg.s.dimm0_cid = lranks_bits; + ext_cfg.s.dimm1_cid = lranks_bits; + debug("N%d.LMC%d: 3DS: setting EXT_CONFIG[dimmx_cid] = %d\n", + node, if_num, ext_cfg.s.dimm0_cid); + } + + lmc_wr(priv, CVMX_LMCX_EXT_CONFIG(if_num), ext_cfg.u64); + debug("%-45s : 0x%016llx\n", "EXT_CONFIG", ext_cfg.u64); +} + +static void lmc_ext_config2(struct ddr_priv *priv) +{ + char *s; + + // NOTE: all chips have this register, but not necessarily the + // fields we modify... + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) && + !octeon_is_cpuid(OCTEON_CN73XX)) { + union cvmx_lmcx_ext_config2 ext_cfg2; + int value = 1; // default to 1 + + ext_cfg2.u64 = lmc_rd(priv, CVMX_LMCX_EXT_CONFIG2(if_num)); + + s = lookup_env(priv, "ddr_ext2_delay_unload"); + if (s) + value = !!simple_strtoul(s, NULL, 0); + + ext_cfg2.s.delay_unload_r0 = value; + ext_cfg2.s.delay_unload_r1 = value; + ext_cfg2.s.delay_unload_r2 = value; + ext_cfg2.s.delay_unload_r3 = value; + + lmc_wr(priv, CVMX_LMCX_EXT_CONFIG2(if_num), ext_cfg2.u64); + debug("%-45s : 0x%016llx\n", "EXT_CONFIG2", ext_cfg2.u64); + } +} + +static void lmc_dimm01_params_loop(struct ddr_priv *priv) +{ + union cvmx_lmcx_dimmx_params dimm_p; + int dimmx = didx; + char *s; + int rc; + int i; + + dimm_p.u64 = lmc_rd(priv, CVMX_LMCX_DIMMX_PARAMS(dimmx, if_num)); + + if (ddr_type == DDR4_DRAM) { + union cvmx_lmcx_dimmx_ddr4_params0 ddr4_p0; + union cvmx_lmcx_dimmx_ddr4_params1 ddr4_p1; + union cvmx_lmcx_ddr4_dimm_ctl ddr4_ctl; + + dimm_p.s.rc0 = 0; + dimm_p.s.rc1 = 0; + dimm_p.s.rc2 = 0; + + rc = read_spd(&dimm_config_table[didx], 0, + DDR4_SPD_RDIMM_REGISTER_DRIVE_STRENGTH_CTL); + dimm_p.s.rc3 = (rc >> 4) & 0xf; + dimm_p.s.rc4 = ((rc >> 0) & 0x3) << 2; + dimm_p.s.rc4 |= ((rc >> 2) & 0x3) << 0; + + rc = read_spd(&dimm_config_table[didx], 0, + DDR4_SPD_RDIMM_REGISTER_DRIVE_STRENGTH_CK); + dimm_p.s.rc5 = ((rc >> 0) & 0x3) << 2; + dimm_p.s.rc5 |= ((rc >> 2) & 0x3) << 0; + + dimm_p.s.rc6 = 0; + dimm_p.s.rc7 = 0; + dimm_p.s.rc8 = 0; + dimm_p.s.rc9 = 0; + + /* + * rc10 DDR4 RDIMM Operating Speed + * === =================================================== + * 0 tclk_psecs >= 1250 psec DDR4-1600 (1250 ps) + * 1 1250 psec > tclk_psecs >= 1071 psec DDR4-1866 (1071 ps) + * 2 1071 psec > tclk_psecs >= 938 psec DDR4-2133 ( 938 ps) + * 3 938 psec > tclk_psecs >= 833 psec DDR4-2400 ( 833 ps) + * 4 833 psec > tclk_psecs >= 750 psec DDR4-2666 ( 750 ps) + * 5 750 psec > tclk_psecs >= 625 psec DDR4-3200 ( 625 ps) + */ + dimm_p.s.rc10 = 0; + if (tclk_psecs < 1250) + dimm_p.s.rc10 = 1; + if (tclk_psecs < 1071) + dimm_p.s.rc10 = 2; + if (tclk_psecs < 938) + dimm_p.s.rc10 = 3; + if (tclk_psecs < 833) + dimm_p.s.rc10 = 4; + if (tclk_psecs < 750) + dimm_p.s.rc10 = 5; + + dimm_p.s.rc11 = 0; + dimm_p.s.rc12 = 0; + /* 0=LRDIMM, 1=RDIMM */ + dimm_p.s.rc13 = (spd_dimm_type == 4) ? 0 : 4; + dimm_p.s.rc13 |= (ddr_type == DDR4_DRAM) ? + (spd_addr_mirror << 3) : 0; + dimm_p.s.rc14 = 0; + dimm_p.s.rc15 = 0; /* 1 nCK latency adder */ + + ddr4_p0.u64 = 0; + + ddr4_p0.s.rc8x = 0; + ddr4_p0.s.rc7x = 0; + ddr4_p0.s.rc6x = 0; + ddr4_p0.s.rc5x = 0; + ddr4_p0.s.rc4x = 0; + + ddr4_p0.s.rc3x = compute_rc3x(tclk_psecs); + + ddr4_p0.s.rc2x = 0; + ddr4_p0.s.rc1x = 0; + + ddr4_p1.u64 = 0; + + ddr4_p1.s.rcbx = 0; + ddr4_p1.s.rcax = 0; + ddr4_p1.s.rc9x = 0; + + ddr4_ctl.u64 = 0; + ddr4_ctl.cn70xx.ddr4_dimm0_wmask = 0x004; + ddr4_ctl.cn70xx.ddr4_dimm1_wmask = + (dimm_count > 1) ? 0x004 : 0x0000; + + /* + * Handle any overrides from envvars here... + */ + s = lookup_env(priv, "ddr_ddr4_params0"); + if (s) + ddr4_p0.u64 = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_ddr4_params1"); + if (s) + ddr4_p1.u64 = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_ddr4_dimm_ctl"); + if (s) + ddr4_ctl.u64 = simple_strtoul(s, NULL, 0); + + for (i = 0; i < 11; ++i) { + u64 value; + + s = lookup_env(priv, "ddr_ddr4_rc%1xx", i + 1); + if (s) { + value = simple_strtoul(s, NULL, 0); + if (i < 8) { + ddr4_p0.u64 &= ~((u64)0xff << (i * 8)); + ddr4_p0.u64 |= (value << (i * 8)); + } else { + ddr4_p1.u64 &= + ~((u64)0xff << ((i - 8) * 8)); + ddr4_p1.u64 |= (value << ((i - 8) * 8)); + } + } + } + + /* + * write the final CSR values + */ + lmc_wr(priv, CVMX_LMCX_DIMMX_DDR4_PARAMS0(dimmx, if_num), + ddr4_p0.u64); + + lmc_wr(priv, CVMX_LMCX_DDR4_DIMM_CTL(if_num), ddr4_ctl.u64); + + lmc_wr(priv, CVMX_LMCX_DIMMX_DDR4_PARAMS1(dimmx, if_num), + ddr4_p1.u64); + + debug("DIMM%d Register Control Words RCBx:RC1x : %x %x %x %x %x %x %x %x %x %x %x\n", + dimmx, ddr4_p1.s.rcbx, ddr4_p1.s.rcax, + ddr4_p1.s.rc9x, ddr4_p0.s.rc8x, + ddr4_p0.s.rc7x, ddr4_p0.s.rc6x, + ddr4_p0.s.rc5x, ddr4_p0.s.rc4x, + ddr4_p0.s.rc3x, ddr4_p0.s.rc2x, ddr4_p0.s.rc1x); + + } else { + rc = read_spd(&dimm_config_table[didx], 0, 69); + dimm_p.s.rc0 = (rc >> 0) & 0xf; + dimm_p.s.rc1 = (rc >> 4) & 0xf; + + rc = read_spd(&dimm_config_table[didx], 0, 70); + dimm_p.s.rc2 = (rc >> 0) & 0xf; + dimm_p.s.rc3 = (rc >> 4) & 0xf; + + rc = read_spd(&dimm_config_table[didx], 0, 71); + dimm_p.s.rc4 = (rc >> 0) & 0xf; + dimm_p.s.rc5 = (rc >> 4) & 0xf; + + rc = read_spd(&dimm_config_table[didx], 0, 72); + dimm_p.s.rc6 = (rc >> 0) & 0xf; + dimm_p.s.rc7 = (rc >> 4) & 0xf; + + rc = read_spd(&dimm_config_table[didx], 0, 73); + dimm_p.s.rc8 = (rc >> 0) & 0xf; + dimm_p.s.rc9 = (rc >> 4) & 0xf; + + rc = read_spd(&dimm_config_table[didx], 0, 74); + dimm_p.s.rc10 = (rc >> 0) & 0xf; + dimm_p.s.rc11 = (rc >> 4) & 0xf; + + rc = read_spd(&dimm_config_table[didx], 0, 75); + dimm_p.s.rc12 = (rc >> 0) & 0xf; + dimm_p.s.rc13 = (rc >> 4) & 0xf; + + rc = read_spd(&dimm_config_table[didx], 0, 76); + dimm_p.s.rc14 = (rc >> 0) & 0xf; + dimm_p.s.rc15 = (rc >> 4) & 0xf; + + s = ddr_getenv_debug(priv, "ddr_clk_drive"); + if (s) { + if (strcmp(s, "light") == 0) + dimm_p.s.rc5 = 0x0; /* Light Drive */ + if (strcmp(s, "moderate") == 0) + dimm_p.s.rc5 = 0x5; /* Moderate Drive */ + if (strcmp(s, "strong") == 0) + dimm_p.s.rc5 = 0xA; /* Strong Drive */ + printf("Parameter found in environment. ddr_clk_drive = %s\n", + s); + } + + s = ddr_getenv_debug(priv, "ddr_cmd_drive"); + if (s) { + if (strcmp(s, "light") == 0) + dimm_p.s.rc3 = 0x0; /* Light Drive */ + if (strcmp(s, "moderate") == 0) + dimm_p.s.rc3 = 0x5; /* Moderate Drive */ + if (strcmp(s, "strong") == 0) + dimm_p.s.rc3 = 0xA; /* Strong Drive */ + printf("Parameter found in environment. ddr_cmd_drive = %s\n", + s); + } + + s = ddr_getenv_debug(priv, "ddr_ctl_drive"); + if (s) { + if (strcmp(s, "light") == 0) + dimm_p.s.rc4 = 0x0; /* Light Drive */ + if (strcmp(s, "moderate") == 0) + dimm_p.s.rc4 = 0x5; /* Moderate Drive */ + printf("Parameter found in environment. ddr_ctl_drive = %s\n", + s); + } + + /* + * rc10 DDR3 RDIMM Operating Speed + * == ===================================================== + * 0 tclk_psecs >= 2500 psec DDR3/DDR3L-800 def + * 1 2500 psec > tclk_psecs >= 1875 psec DDR3/DDR3L-1066 + * 2 1875 psec > tclk_psecs >= 1500 psec DDR3/DDR3L-1333 + * 3 1500 psec > tclk_psecs >= 1250 psec DDR3/DDR3L-1600 + * 4 1250 psec > tclk_psecs >= 1071 psec DDR3-1866 + */ + dimm_p.s.rc10 = 0; + if (tclk_psecs < 2500) + dimm_p.s.rc10 = 1; + if (tclk_psecs < 1875) + dimm_p.s.rc10 = 2; + if (tclk_psecs < 1500) + dimm_p.s.rc10 = 3; + if (tclk_psecs < 1250) + dimm_p.s.rc10 = 4; + } + + s = lookup_env(priv, "ddr_dimmx_params", i); + if (s) + dimm_p.u64 = simple_strtoul(s, NULL, 0); + + for (i = 0; i < 16; ++i) { + u64 value; + + s = lookup_env(priv, "ddr_rc%d", i); + if (s) { + value = simple_strtoul(s, NULL, 0); + dimm_p.u64 &= ~((u64)0xf << (i * 4)); + dimm_p.u64 |= (value << (i * 4)); + } + } + + lmc_wr(priv, CVMX_LMCX_DIMMX_PARAMS(dimmx, if_num), dimm_p.u64); + + debug("DIMM%d Register Control Words RC15:RC0 : %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n", + dimmx, dimm_p.s.rc15, dimm_p.s.rc14, dimm_p.s.rc13, + dimm_p.s.rc12, dimm_p.s.rc11, dimm_p.s.rc10, + dimm_p.s.rc9, dimm_p.s.rc8, dimm_p.s.rc7, + dimm_p.s.rc6, dimm_p.s.rc5, dimm_p.s.rc4, + dimm_p.s.rc3, dimm_p.s.rc2, dimm_p.s.rc1, dimm_p.s.rc0); + + // FIXME: recognize a DDR3 RDIMM with 4 ranks and 2 registers, + // and treat it specially + if (ddr_type == DDR3_DRAM && num_ranks == 4 && + spd_rdimm_registers == 2 && dimmx == 0) { + debug("DDR3: Copying DIMM0_PARAMS to DIMM1_PARAMS for pseudo-DIMM #1...\n"); + lmc_wr(priv, CVMX_LMCX_DIMMX_PARAMS(1, if_num), dimm_p.u64); + } +} + +static void lmc_dimm01_params(struct ddr_priv *priv) +{ + union cvmx_lmcx_dimm_ctl dimm_ctl; + char *s; + + if (spd_rdimm) { + for (didx = 0; didx < (unsigned int)dimm_count; ++didx) + lmc_dimm01_params_loop(priv); + + if (ddr_type == DDR4_DRAM) { + /* LMC0_DIMM_CTL */ + dimm_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DIMM_CTL(if_num)); + dimm_ctl.s.dimm0_wmask = 0xdf3f; + dimm_ctl.s.dimm1_wmask = + (dimm_count > 1) ? 0xdf3f : 0x0000; + dimm_ctl.s.tcws = 0x4e0; + dimm_ctl.s.parity = c_cfg->parity; + + s = lookup_env(priv, "ddr_dimm0_wmask"); + if (s) { + dimm_ctl.s.dimm0_wmask = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_dimm1_wmask"); + if (s) { + dimm_ctl.s.dimm1_wmask = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_dimm_ctl_parity"); + if (s) + dimm_ctl.s.parity = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_dimm_ctl_tcws"); + if (s) + dimm_ctl.s.tcws = simple_strtoul(s, NULL, 0); + + debug("LMC DIMM_CTL : 0x%016llx\n", + dimm_ctl.u64); + lmc_wr(priv, CVMX_LMCX_DIMM_CTL(if_num), dimm_ctl.u64); + + /* Init RCW */ + oct3_ddr3_seq(priv, rank_mask, if_num, 0x7); + + /* Write RC0D last */ + dimm_ctl.s.dimm0_wmask = 0x2000; + dimm_ctl.s.dimm1_wmask = (dimm_count > 1) ? + 0x2000 : 0x0000; + debug("LMC DIMM_CTL : 0x%016llx\n", + dimm_ctl.u64); + lmc_wr(priv, CVMX_LMCX_DIMM_CTL(if_num), dimm_ctl.u64); + + /* + * Don't write any extended registers the second time + */ + lmc_wr(priv, CVMX_LMCX_DDR4_DIMM_CTL(if_num), 0); + + /* Init RCW */ + oct3_ddr3_seq(priv, rank_mask, if_num, 0x7); + } else { + /* LMC0_DIMM_CTL */ + dimm_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DIMM_CTL(if_num)); + dimm_ctl.s.dimm0_wmask = 0xffff; + // FIXME: recognize a DDR3 RDIMM with 4 ranks and 2 + // registers, and treat it specially + if (num_ranks == 4 && spd_rdimm_registers == 2) { + debug("DDR3: Activating DIMM_CTL[dimm1_mask] bits...\n"); + dimm_ctl.s.dimm1_wmask = 0xffff; + } else { + dimm_ctl.s.dimm1_wmask = + (dimm_count > 1) ? 0xffff : 0x0000; + } + dimm_ctl.s.tcws = 0x4e0; + dimm_ctl.s.parity = c_cfg->parity; + + s = lookup_env(priv, "ddr_dimm0_wmask"); + if (s) { + dimm_ctl.s.dimm0_wmask = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_dimm1_wmask"); + if (s) { + dimm_ctl.s.dimm1_wmask = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_dimm_ctl_parity"); + if (s) + dimm_ctl.s.parity = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_dimm_ctl_tcws"); + if (s) + dimm_ctl.s.tcws = simple_strtoul(s, NULL, 0); + + debug("LMC DIMM_CTL : 0x%016llx\n", + dimm_ctl.u64); + lmc_wr(priv, CVMX_LMCX_DIMM_CTL(if_num), dimm_ctl.u64); + + /* Init RCW */ + oct3_ddr3_seq(priv, rank_mask, if_num, 0x7); + } + + } else { + /* Disable register control writes for unbuffered */ + union cvmx_lmcx_dimm_ctl dimm_ctl; + + dimm_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DIMM_CTL(if_num)); + dimm_ctl.s.dimm0_wmask = 0; + dimm_ctl.s.dimm1_wmask = 0; + lmc_wr(priv, CVMX_LMCX_DIMM_CTL(if_num), dimm_ctl.u64); + } +} + +static int lmc_rank_init(struct ddr_priv *priv) +{ + char *s; + + if (enable_by_rank_init) { + by_rank = 3; + saved_rank_mask = rank_mask; + } + +start_by_rank_init: + + if (enable_by_rank_init) { + rank_mask = (1 << by_rank); + if (!(rank_mask & saved_rank_mask)) + goto end_by_rank_init; + if (by_rank == 0) + rank_mask = saved_rank_mask; + + debug("\n>>>>> BY_RANK: starting rank %d with mask 0x%02x\n\n", + by_rank, rank_mask); + } + + /* + * Comments (steps 3 through 5) continue in oct3_ddr3_seq() + */ + union cvmx_lmcx_modereg_params0 mp0; + + if (ddr_memory_preserved(priv)) { + /* + * Contents are being preserved. Take DRAM out of self-refresh + * first. Then init steps can procede normally + */ + /* self-refresh exit */ + oct3_ddr3_seq(priv, rank_mask, if_num, 3); + } + + mp0.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num)); + mp0.s.dllr = 1; /* Set during first init sequence */ + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num), mp0.u64); + + ddr_init_seq(priv, rank_mask, if_num); + + mp0.s.dllr = 0; /* Clear for normal operation */ + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num), mp0.u64); + + if (spd_rdimm && ddr_type == DDR4_DRAM && + octeon_is_cpuid(OCTEON_CN7XXX)) { + debug("Running init sequence 1\n"); + change_rdimm_mpr_pattern(priv, rank_mask, if_num, dimm_count); + } + + memset(lanes, 0, sizeof(lanes)); + for (lane = 0; lane < last_lane; lane++) { + // init all lanes to reset value + dac_settings[lane] = 127; + } + + // FIXME: disable internal VREF if deskew is disabled? + if (disable_deskew_training) { + debug("N%d.LMC%d: internal VREF Training disabled, leaving them in RESET.\n", + node, if_num); + num_samples = 0; + } else if (ddr_type == DDR4_DRAM && + !octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) { + num_samples = DEFAULT_DAC_SAMPLES; + } else { + // if DDR3 or no ability to write DAC values + num_samples = 1; + } + +perform_internal_vref_training: + + total_dac_eval_retries = 0; + dac_eval_exhausted = 0; + + for (sample = 0; sample < num_samples; sample++) { + dac_eval_retries = 0; + + // make offset and internal vref training repeatable + do { + /* + * 6.9.8 LMC Offset Training + * LMC requires input-receiver offset training. + */ + perform_offset_training(priv, rank_mask, if_num); + + /* + * 6.9.9 LMC Internal vref Training + * LMC requires input-reference-voltage training. + */ + perform_internal_vref_training(priv, rank_mask, if_num); + + // read and maybe display the DAC values for a sample + read_dac_dbi_settings(priv, if_num, /*DAC*/ 1, + dac_settings); + if (num_samples == 1 || ddr_verbose(priv)) { + display_dac_dbi_settings(if_num, /*DAC*/ 1, + use_ecc, dac_settings, + "Internal VREF"); + } + + // for DDR4, evaluate the DAC settings and retry + // if any issues + if (ddr_type == DDR4_DRAM) { + if (evaluate_dac_settings + (if_64b, use_ecc, dac_settings)) { + dac_eval_retries += 1; + if (dac_eval_retries > + DAC_RETRIES_LIMIT) { + debug("N%d.LMC%d: DDR4 internal VREF DAC settings: retries exhausted; continuing...\n", + node, if_num); + dac_eval_exhausted += 1; + } else { + debug("N%d.LMC%d: DDR4 internal VREF DAC settings inconsistent; retrying....\n", + node, if_num); + total_dac_eval_retries += 1; + // try another sample + continue; + } + } + + // taking multiple samples, otherwise do nothing + if (num_samples > 1) { + // good sample or exhausted retries, + // record it + for (lane = 0; lane < last_lane; + lane++) { + lanes[lane].bytes[sample] = + dac_settings[lane]; + } + } + } + // done if DDR3, or good sample, or exhausted retries + break; + } while (1); + } + + if (ddr_type == DDR4_DRAM && dac_eval_exhausted > 0) { + debug("N%d.LMC%d: DDR internal VREF DAC settings: total retries %d, exhausted %d\n", + node, if_num, total_dac_eval_retries, dac_eval_exhausted); + } + + if (num_samples > 1) { + debug("N%d.LMC%d: DDR4 internal VREF DAC settings: processing multiple samples...\n", + node, if_num); + + for (lane = 0; lane < last_lane; lane++) { + dac_settings[lane] = + process_samples_average(&lanes[lane].bytes[0], + num_samples, if_num, lane); + } + display_dac_dbi_settings(if_num, /*DAC*/ 1, use_ecc, + dac_settings, "Averaged VREF"); + + // finally, write the final DAC values + for (lane = 0; lane < last_lane; lane++) { + load_dac_override(priv, if_num, dac_settings[lane], + lane); + } + } + + // allow override of any byte-lane internal VREF + int overrode_vref_dac = 0; + + for (lane = 0; lane < last_lane; lane++) { + s = lookup_env(priv, "ddr%d_vref_dac_byte%d", if_num, lane); + if (s) { + dac_settings[lane] = simple_strtoul(s, NULL, 0); + overrode_vref_dac = 1; + // finally, write the new DAC value + load_dac_override(priv, if_num, dac_settings[lane], + lane); + } + } + if (overrode_vref_dac) { + display_dac_dbi_settings(if_num, /*DAC*/ 1, use_ecc, + dac_settings, "Override VREF"); + } + + // as a second step, after internal VREF training, before starting + // deskew training: + // for DDR3 and OCTEON3 not O78 pass 1.x, override the DAC setting + // to 127 + if (ddr_type == DDR3_DRAM && !octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) && + !disable_deskew_training) { + load_dac_override(priv, if_num, 127, /* all */ 0x0A); + debug("N%d.LMC%d: Overriding DDR3 internal VREF DAC settings to 127.\n", + node, if_num); + } + + /* + * 4.8.8 LMC Deskew Training + * + * LMC requires input-read-data deskew training. + */ + if (!disable_deskew_training) { + deskew_training_errors = + perform_deskew_training(priv, rank_mask, if_num, + spd_rawcard_aorb); + + // All the Deskew lock and saturation retries (may) have + // been done, but we ended up with nibble errors; so, + // as a last ditch effort, try the Internal vref + // Training again... + if (deskew_training_errors) { + if (internal_retries < + DEFAULT_INTERNAL_VREF_TRAINING_LIMIT) { + internal_retries++; + debug("N%d.LMC%d: Deskew training results still unsettled - retrying internal vref training (%d)\n", + node, if_num, internal_retries); + goto perform_internal_vref_training; + } else { + if (restart_if_dsk_incomplete) { + debug("N%d.LMC%d: INFO: Deskew training incomplete - %d retries exhausted, Restarting LMC init...\n", + node, if_num, internal_retries); + return -EAGAIN; + } + debug("N%d.LMC%d: Deskew training incomplete - %d retries exhausted, but continuing...\n", + node, if_num, internal_retries); + } + } /* if (deskew_training_errors) */ + + // FIXME: treat this as the final DSK print from now on, + // and print if VBL_NORM or above also, save the results + // of the original training in case we want them later + validate_deskew_training(priv, rank_mask, if_num, + &deskew_training_results, 1); + } else { /* if (! disable_deskew_training) */ + debug("N%d.LMC%d: Deskew Training disabled, printing settings before HWL.\n", + node, if_num); + validate_deskew_training(priv, rank_mask, if_num, + &deskew_training_results, 1); + } /* if (! disable_deskew_training) */ + + if (enable_by_rank_init) { + read_dac_dbi_settings(priv, if_num, /*dac */ 1, + &rank_dac[by_rank].bytes[0]); + get_deskew_settings(priv, if_num, &rank_dsk[by_rank]); + debug("\n>>>>> BY_RANK: ending rank %d\n\n", by_rank); + } + +end_by_rank_init: + + if (enable_by_rank_init) { + //debug("\n>>>>> BY_RANK: ending rank %d\n\n", by_rank); + + by_rank--; + if (by_rank >= 0) + goto start_by_rank_init; + + rank_mask = saved_rank_mask; + ddr_init_seq(priv, rank_mask, if_num); + + process_by_rank_dac(priv, if_num, rank_mask, rank_dac); + process_by_rank_dsk(priv, if_num, rank_mask, rank_dsk); + + // FIXME: set this to prevent later checking!!! + disable_deskew_training = 1; + + debug("\n>>>>> BY_RANK: FINISHED!!\n\n"); + } + + return 0; +} + +static void lmc_config_2(struct ddr_priv *priv) +{ + union cvmx_lmcx_config lmc_config; + int save_ref_zqcs_int; + u64 temp_delay_usecs; + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + + /* + * Temporarily select the minimum ZQCS interval and wait + * long enough for a few ZQCS calibrations to occur. This + * should ensure that the calibration circuitry is + * stabilized before read/write leveling occurs. + */ + if (octeon_is_cpuid(OCTEON_CN7XXX)) { + save_ref_zqcs_int = lmc_config.cn78xx.ref_zqcs_int; + /* set smallest interval */ + lmc_config.cn78xx.ref_zqcs_int = 1 | (32 << 7); + } else { + save_ref_zqcs_int = lmc_config.cn63xx.ref_zqcs_int; + /* set smallest interval */ + lmc_config.cn63xx.ref_zqcs_int = 1 | (32 << 7); + } + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), lmc_config.u64); + lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + + /* + * Compute an appropriate delay based on the current ZQCS + * interval. The delay should be long enough for the + * current ZQCS delay counter to expire plus ten of the + * minimum intarvals to ensure that some calibrations + * occur. + */ + temp_delay_usecs = (((u64)save_ref_zqcs_int >> 7) * tclk_psecs * + 100 * 512 * 128) / (10000 * 10000) + 10 * + ((u64)32 * tclk_psecs * 100 * 512 * 128) / (10000 * 10000); + + debug("Waiting %lld usecs for ZQCS calibrations to start\n", + temp_delay_usecs); + udelay(temp_delay_usecs); + + if (octeon_is_cpuid(OCTEON_CN7XXX)) { + /* Restore computed interval */ + lmc_config.cn78xx.ref_zqcs_int = save_ref_zqcs_int; + } else { + /* Restore computed interval */ + lmc_config.cn63xx.ref_zqcs_int = save_ref_zqcs_int; + } + + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), lmc_config.u64); + lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); +} + +static union cvmx_lmcx_wlevel_ctl wl_ctl __section(".data"); +static union cvmx_lmcx_wlevel_rankx wl_rank __section(".data"); +static union cvmx_lmcx_modereg_params1 mp1 __section(".data"); + +static int wl_mask[9] __section(".data"); +static int byte_idx __section(".data"); +static int ecc_ena __section(".data"); +static int wl_roundup __section(".data"); +static int save_mode32b __section(".data"); +static int disable_hwl_validity __section(".data"); +static int default_wl_rtt_nom __section(".data"); +static int wl_pbm_pump __section(".data"); + +static void lmc_write_leveling_loop(struct ddr_priv *priv, int rankx) +{ + int wloop = 0; + // retries per sample for HW-related issues with bitmasks or values + int wloop_retries = 0; + int wloop_retries_total = 0; + int wloop_retries_exhausted = 0; +#define WLOOP_RETRIES_DEFAULT 5 + int wl_val_err; + int wl_mask_err_rank = 0; + int wl_val_err_rank = 0; + // array to collect counts of byte-lane values + // assume low-order 3 bits and even, so really only 2-bit values + struct wlevel_bitcnt wl_bytes[9], wl_bytes_extra[9]; + int extra_bumps, extra_mask; + int rank_nom = 0; + + if (!(rank_mask & (1 << rankx))) + return; + + if (match_wl_rtt_nom) { + if (rankx == 0) + rank_nom = mp1.s.rtt_nom_00; + if (rankx == 1) + rank_nom = mp1.s.rtt_nom_01; + if (rankx == 2) + rank_nom = mp1.s.rtt_nom_10; + if (rankx == 3) + rank_nom = mp1.s.rtt_nom_11; + + debug("N%d.LMC%d.R%d: Setting WLEVEL_CTL[rtt_nom] to %d (%d)\n", + node, if_num, rankx, rank_nom, + imp_val->rtt_nom_ohms[rank_nom]); + } + + memset(wl_bytes, 0, sizeof(wl_bytes)); + memset(wl_bytes_extra, 0, sizeof(wl_bytes_extra)); + + // restructure the looping so we can keep trying until we get the + // samples we want + while (wloop < wl_loops) { + wl_ctl.u64 = lmc_rd(priv, CVMX_LMCX_WLEVEL_CTL(if_num)); + + wl_ctl.cn78xx.rtt_nom = + (default_wl_rtt_nom > 0) ? (default_wl_rtt_nom - 1) : 7; + + if (match_wl_rtt_nom) { + wl_ctl.cn78xx.rtt_nom = + (rank_nom > 0) ? (rank_nom - 1) : 7; + } + + /* Clear write-level delays */ + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), 0); + + wl_mask_err = 0; /* Reset error counters */ + wl_val_err = 0; + + for (byte_idx = 0; byte_idx < 9; ++byte_idx) + wl_mask[byte_idx] = 0; /* Reset bitmasks */ + + // do all the byte-lanes at the same time + wl_ctl.cn78xx.lanemask = 0x1ff; + + lmc_wr(priv, CVMX_LMCX_WLEVEL_CTL(if_num), wl_ctl.u64); + + /* + * Read and write values back in order to update the + * status field. This insures that we read the updated + * values after write-leveling has completed. + */ + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), + lmc_rd(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num))); + + /* write-leveling */ + oct3_ddr3_seq(priv, 1 << rankx, if_num, 6); + + do { + wl_rank.u64 = lmc_rd(priv, + CVMX_LMCX_WLEVEL_RANKX(rankx, + if_num)); + } while (wl_rank.cn78xx.status != 3); + + wl_rank.u64 = lmc_rd(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, + if_num)); + + for (byte_idx = 0; byte_idx < (8 + ecc_ena); ++byte_idx) { + wl_mask[byte_idx] = lmc_ddr3_wl_dbg_read(priv, + if_num, + byte_idx); + if (wl_mask[byte_idx] == 0) + ++wl_mask_err; + } + + // check validity only if no bitmask errors + if (wl_mask_err == 0) { + if ((spd_dimm_type == 1 || spd_dimm_type == 2) && + dram_width != 16 && if_64b && + !disable_hwl_validity) { + // bypass if [mini|SO]-[RU]DIMM or x16 or + // 32-bit + wl_val_err = + validate_hw_wl_settings(if_num, + &wl_rank, + spd_rdimm, ecc_ena); + wl_val_err_rank += (wl_val_err != 0); + } + } else { + wl_mask_err_rank++; + } + + // before we print, if we had bitmask or validity errors, + // do a retry... + if (wl_mask_err != 0 || wl_val_err != 0) { + if (wloop_retries < WLOOP_RETRIES_DEFAULT) { + wloop_retries++; + wloop_retries_total++; + // this printout is per-retry: only when VBL + // is high enough (DEV?) + // FIXME: do we want to show the bad bitmaps + // or delays here also? + debug("N%d.LMC%d.R%d: H/W Write-Leveling had %s errors - retrying...\n", + node, if_num, rankx, + (wl_mask_err) ? "Bitmask" : "Validity"); + // this takes us back to the top without + // counting a sample + return; + } + + // retries exhausted, do not print at normal VBL + debug("N%d.LMC%d.R%d: H/W Write-Leveling issues: %s errors\n", + node, if_num, rankx, + (wl_mask_err) ? "Bitmask" : "Validity"); + wloop_retries_exhausted++; + } + // no errors or exhausted retries, use this sample + wloop_retries = 0; //reset for next sample + + // when only 1 sample or forced, print the bitmasks then + // current HW WL + if (wl_loops == 1 || wl_print) { + if (wl_print > 1) + display_wl_bm(if_num, rankx, wl_mask); + display_wl(if_num, wl_rank, rankx); + } + + if (wl_roundup) { /* Round up odd bitmask delays */ + for (byte_idx = 0; byte_idx < (8 + ecc_ena); + ++byte_idx) { + if (!(if_bytemask & (1 << byte_idx))) + return; + upd_wl_rank(&wl_rank, byte_idx, + roundup_ddr3_wlevel_bitmask + (wl_mask[byte_idx])); + } + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), + wl_rank.u64); + display_wl(if_num, wl_rank, rankx); + } + + // OK, we have a decent sample, no bitmask or validity errors + extra_bumps = 0; + extra_mask = 0; + for (byte_idx = 0; byte_idx < (8 + ecc_ena); ++byte_idx) { + int ix; + + if (!(if_bytemask & (1 << byte_idx))) + return; + + // increment count of byte-lane value + // only 4 values + ix = (get_wl_rank(&wl_rank, byte_idx) >> 1) & 3; + wl_bytes[byte_idx].bitcnt[ix]++; + wl_bytes_extra[byte_idx].bitcnt[ix]++; + // if perfect... + if (__builtin_popcount(wl_mask[byte_idx]) == 4) { + wl_bytes_extra[byte_idx].bitcnt[ix] += + wl_pbm_pump; + extra_bumps++; + extra_mask |= 1 << byte_idx; + } + } + + if (extra_bumps) { + if (wl_print > 1) { + debug("N%d.LMC%d.R%d: HWL sample had %d bumps (0x%02x).\n", + node, if_num, rankx, extra_bumps, + extra_mask); + } + } + + // if we get here, we have taken a decent sample + wloop++; + + } /* while (wloop < wl_loops) */ + + // if we did sample more than once, try to pick a majority vote + if (wl_loops > 1) { + // look for the majority in each byte-lane + for (byte_idx = 0; byte_idx < (8 + ecc_ena); ++byte_idx) { + int mx, mc, xc, cc; + int ix, alts; + int maj, xmaj, xmx, xmc, xxc, xcc; + + if (!(if_bytemask & (1 << byte_idx))) + return; + maj = find_wl_majority(&wl_bytes[byte_idx], &mx, + &mc, &xc, &cc); + xmaj = find_wl_majority(&wl_bytes_extra[byte_idx], + &xmx, &xmc, &xxc, &xcc); + if (maj != xmaj) { + if (wl_print) { + debug("N%d.LMC%d.R%d: Byte %d: HWL maj %d(%d), USING xmaj %d(%d)\n", + node, if_num, rankx, + byte_idx, maj, xc, xmaj, xxc); + } + mx = xmx; + mc = xmc; + xc = xxc; + cc = xcc; + } + + // see if there was an alternate + // take out the majority choice + alts = (mc & ~(1 << mx)); + if (alts != 0) { + for (ix = 0; ix < 4; ix++) { + // FIXME: could be done multiple times? + // bad if so + if (alts & (1 << ix)) { + // set the mask + hwl_alts[rankx].hwl_alt_mask |= + (1 << byte_idx); + // record the value + hwl_alts[rankx].hwl_alt_delay[byte_idx] = + ix << 1; + if (wl_print > 1) { + debug("N%d.LMC%d.R%d: SWL_TRY_HWL_ALT: Byte %d maj %d (%d) alt %d (%d).\n", + node, + if_num, + rankx, + byte_idx, + mx << 1, + xc, + ix << 1, + wl_bytes + [byte_idx].bitcnt + [ix]); + } + } + } + } + + if (cc > 2) { // unlikely, but... + // assume: counts for 3 indices are all 1 + // possiblities are: 0/2/4, 2/4/6, 0/4/6, 0/2/6 + // and the desired?: 2 , 4 , 6, 0 + // we choose the middle, assuming one of the + // outliers is bad + // NOTE: this is an ugly hack at the moment; + // there must be a better way + switch (mc) { + case 0x7: + mx = 1; + break; // was 0/2/4, choose 2 + case 0xb: + mx = 0; + break; // was 0/2/6, choose 0 + case 0xd: + mx = 3; + break; // was 0/4/6, choose 6 + case 0xe: + mx = 2; + break; // was 2/4/6, choose 4 + default: + case 0xf: + mx = 1; + break; // was 0/2/4/6, choose 2? + } + printf("N%d.LMC%d.R%d: HW WL MAJORITY: bad byte-lane %d (0x%x), using %d.\n", + node, if_num, rankx, byte_idx, mc, + mx << 1); + } + upd_wl_rank(&wl_rank, byte_idx, mx << 1); + } + + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), + wl_rank.u64); + display_wl_with_final(if_num, wl_rank, rankx); + + // FIXME: does this help make the output a little easier + // to focus? + if (wl_print > 0) + debug("-----------\n"); + + } /* if (wl_loops > 1) */ + + // maybe print an error summary for the rank + if (wl_mask_err_rank != 0 || wl_val_err_rank != 0) { + debug("N%d.LMC%d.R%d: H/W Write-Leveling errors - %d bitmask, %d validity, %d retries, %d exhausted\n", + node, if_num, rankx, wl_mask_err_rank, + wl_val_err_rank, wloop_retries_total, + wloop_retries_exhausted); + } +} + +static void lmc_write_leveling(struct ddr_priv *priv) +{ + union cvmx_lmcx_config cfg; + int rankx; + char *s; + + /* + * 4.8.9 LMC Write Leveling + * + * LMC supports an automatic write leveling like that described in the + * JEDEC DDR3 specifications separately per byte-lane. + * + * All of DDR PLL, LMC CK, LMC DRESET, and early LMC initializations + * must be completed prior to starting this LMC write-leveling sequence. + * + * There are many possible procedures that will write-level all the + * attached DDR3 DRAM parts. One possibility is for software to simply + * write the desired values into LMC(0)_WLEVEL_RANK(0..3). This section + * describes one possible sequence that uses LMC's autowrite-leveling + * capabilities. + * + * 1. If the DQS/DQ delays on the board may be more than the ADD/CMD + * delays, then ensure that LMC(0)_CONFIG[EARLY_DQX] is set at this + * point. + * + * Do the remaining steps 2-7 separately for each rank i with attached + * DRAM. + * + * 2. Write LMC(0)_WLEVEL_RANKi = 0. + * + * 3. For x8 parts: + * + * Without changing any other fields in LMC(0)_WLEVEL_CTL, write + * LMC(0)_WLEVEL_CTL[LANEMASK] to select all byte lanes with attached + * DRAM. + * + * For x16 parts: + * + * Without changing any other fields in LMC(0)_WLEVEL_CTL, write + * LMC(0)_WLEVEL_CTL[LANEMASK] to select all even byte lanes with + * attached DRAM. + * + * 4. Without changing any other fields in LMC(0)_CONFIG, + * + * o write LMC(0)_SEQ_CTL[SEQ_SEL] to select write-leveling + * + * o write LMC(0)_CONFIG[RANKMASK] = (1 << i) + * + * o write LMC(0)_SEQ_CTL[INIT_START] = 1 + * + * LMC will initiate write-leveling at this point. Assuming + * LMC(0)_WLEVEL_CTL [SSET] = 0, LMC first enables write-leveling on + * the selected DRAM rank via a DDR3 MR1 write, then sequences + * through + * and accumulates write-leveling results for eight different delay + * settings twice, starting at a delay of zero in this case since + * LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] = 0, increasing by 1/8 CK each + * setting, covering a total distance of one CK, then disables the + * write-leveling via another DDR3 MR1 write. + * + * After the sequence through 16 delay settings is complete: + * + * o LMC sets LMC(0)_WLEVEL_RANKi[STATUS] = 3 + * + * o LMC sets LMC(0)_WLEVEL_RANKi[BYTE*<2:0>] (for all ranks selected + * by LMC(0)_WLEVEL_CTL[LANEMASK]) to indicate the first write + * leveling result of 1 that followed result of 0 during the + * sequence, except that the LMC always writes + * LMC(0)_WLEVEL_RANKi[BYTE*<0>]=0. + * + * o Software can read the eight write-leveling results from the + * first pass through the delay settings by reading + * LMC(0)_WLEVEL_DBG[BITMASK] (after writing + * LMC(0)_WLEVEL_DBG[BYTE]). (LMC does not retain the writeleveling + * results from the second pass through the eight delay + * settings. They should often be identical to the + * LMC(0)_WLEVEL_DBG[BITMASK] results, though.) + * + * 5. Wait until LMC(0)_WLEVEL_RANKi[STATUS] != 2. + * + * LMC will have updated LMC(0)_WLEVEL_RANKi[BYTE*<2:0>] for all byte + * lanes selected by LMC(0)_WLEVEL_CTL[LANEMASK] at this point. + * LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] will still be the value that + * software wrote in substep 2 above, which is 0. + * + * 6. For x16 parts: + * + * Without changing any other fields in LMC(0)_WLEVEL_CTL, write + * LMC(0)_WLEVEL_CTL[LANEMASK] to select all odd byte lanes with + * attached DRAM. + * + * Repeat substeps 4 and 5 with this new LMC(0)_WLEVEL_CTL[LANEMASK] + * setting. Skip to substep 7 if this has already been done. + * + * For x8 parts: + * + * Skip this substep. Go to substep 7. + * + * 7. Calculate LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] settings for all byte + * lanes on all ranks with attached DRAM. + * + * At this point, all byte lanes on rank i with attached DRAM should + * have been write-leveled, and LMC(0)_WLEVEL_RANKi[BYTE*<2:0>] has + * the result for each byte lane. + * + * But note that the DDR3 write-leveling sequence will only determine + * the delay modulo the CK cycle time, and cannot determine how many + * additional CK cycles of delay are present. Software must calculate + * the number of CK cycles, or equivalently, the + * LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] settings. + * + * This BYTE*<4:3> calculation is system/board specific. + * + * Many techniques can be used to calculate write-leveling BYTE*<4:3> + * values, including: + * + * o Known values for some byte lanes. + * + * o Relative values for some byte lanes relative to others. + * + * For example, suppose lane X is likely to require a larger + * write-leveling delay than lane Y. A BYTEX<2:0> value that is much + * smaller than the BYTEY<2:0> value may then indicate that the + * required lane X delay wrapped into the next CK, so BYTEX<4:3> + * should be set to BYTEY<4:3>+1. + * + * When ECC DRAM is not present (i.e. when DRAM is not attached to + * the DDR_CBS_0_* and DDR_CB<7:0> chip signals, or the + * DDR_DQS_<4>_* and DDR_DQ<35:32> chip signals), write + * LMC(0)_WLEVEL_RANK*[BYTE8] = LMC(0)_WLEVEL_RANK*[BYTE0], + * using the final calculated BYTE0 value. + * Write LMC(0)_WLEVEL_RANK*[BYTE4] = LMC(0)_WLEVEL_RANK*[BYTE0], + * using the final calculated BYTE0 value. + * + * 8. Initialize LMC(0)_WLEVEL_RANK* values for all unused ranks. + * + * Let rank i be a rank with attached DRAM. + * + * For all ranks j that do not have attached DRAM, set + * LMC(0)_WLEVEL_RANKj = LMC(0)_WLEVEL_RANKi. + */ + + rankx = 0; + wl_roundup = 0; + disable_hwl_validity = 0; + + // wl_pbm_pump: weight for write-leveling PBMs... + // 0 causes original behavior + // 1 allows a minority of 2 pbms to outscore a majority of 3 non-pbms + // 4 would allow a minority of 1 pbm to outscore a majority of 4 + // non-pbms + wl_pbm_pump = 4; // FIXME: is 4 too much? + + if (wl_loops) { + debug("N%d.LMC%d: Performing Hardware Write-Leveling\n", node, + if_num); + } else { + /* Force software write-leveling to run */ + wl_mask_err = 1; + debug("N%d.LMC%d: Forcing software Write-Leveling\n", node, + if_num); + } + + default_wl_rtt_nom = (ddr_type == DDR3_DRAM) ? + rttnom_20ohm : ddr4_rttnom_40ohm; + + cfg.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + ecc_ena = cfg.s.ecc_ena; + save_mode32b = cfg.cn78xx.mode32b; + cfg.cn78xx.mode32b = (!if_64b); + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), cfg.u64); + debug("%-45s : %d\n", "MODE32B", cfg.cn78xx.mode32b); + + s = lookup_env(priv, "ddr_wlevel_roundup"); + if (s) + wl_roundup = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_wlevel_printall"); + if (s) + wl_print = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_wlevel_pbm_bump"); + if (s) + wl_pbm_pump = strtoul(s, NULL, 0); + + // default to disable when RL sequential delay check is disabled + disable_hwl_validity = disable_sequential_delay_check; + s = lookup_env(priv, "ddr_disable_hwl_validity"); + if (s) + disable_hwl_validity = !!strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_wl_rtt_nom"); + if (s) + default_wl_rtt_nom = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_match_wl_rtt_nom"); + if (s) + match_wl_rtt_nom = !!simple_strtoul(s, NULL, 0); + + if (match_wl_rtt_nom) + mp1.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS1(if_num)); + + // For DDR3, we do not touch WLEVEL_CTL fields OR_DIS or BITMASK + // For DDR4, we touch WLEVEL_CTL fields OR_DIS or BITMASK here + if (ddr_type == DDR4_DRAM) { + int default_or_dis = 1; + int default_bitmask = 0xff; + + // when x4, use only the lower nibble + if (dram_width == 4) { + default_bitmask = 0x0f; + if (wl_print) { + debug("N%d.LMC%d: WLEVEL_CTL: default bitmask is 0x%02x for DDR4 x4\n", + node, if_num, default_bitmask); + } + } + + wl_ctl.u64 = lmc_rd(priv, CVMX_LMCX_WLEVEL_CTL(if_num)); + wl_ctl.s.or_dis = default_or_dis; + wl_ctl.s.bitmask = default_bitmask; + + // allow overrides + s = lookup_env(priv, "ddr_wlevel_ctl_or_dis"); + if (s) + wl_ctl.s.or_dis = !!strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_wlevel_ctl_bitmask"); + if (s) + wl_ctl.s.bitmask = simple_strtoul(s, NULL, 0); + + // print only if not defaults + if (wl_ctl.s.or_dis != default_or_dis || + wl_ctl.s.bitmask != default_bitmask) { + debug("N%d.LMC%d: WLEVEL_CTL: or_dis=%d, bitmask=0x%02x\n", + node, if_num, wl_ctl.s.or_dis, wl_ctl.s.bitmask); + } + + // always write + lmc_wr(priv, CVMX_LMCX_WLEVEL_CTL(if_num), wl_ctl.u64); + } + + // Start the hardware write-leveling loop per rank + for (rankx = 0; rankx < dimm_count * 4; rankx++) + lmc_write_leveling_loop(priv, rankx); + + cfg.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + cfg.cn78xx.mode32b = save_mode32b; + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), cfg.u64); + debug("%-45s : %d\n", "MODE32B", cfg.cn78xx.mode32b); + + // At the end of HW Write Leveling, check on some DESKEW things... + if (!disable_deskew_training) { + struct deskew_counts dsk_counts; + int retry_count = 0; + + debug("N%d.LMC%d: Check Deskew Settings before Read-Leveling.\n", + node, if_num); + + do { + validate_deskew_training(priv, rank_mask, if_num, + &dsk_counts, 1); + + // only RAWCARD A or B will not benefit from + // retraining if there's only saturation + // or any rawcard if there is a nibble error + if ((!spd_rawcard_aorb && dsk_counts.saturated > 0) || + (dsk_counts.nibrng_errs != 0 || + dsk_counts.nibunl_errs != 0)) { + retry_count++; + debug("N%d.LMC%d: Deskew Status indicates saturation or nibble errors - retry %d Training.\n", + node, if_num, retry_count); + perform_deskew_training(priv, rank_mask, if_num, + spd_rawcard_aorb); + } else { + break; + } + } while (retry_count < 5); + } +} + +static void lmc_workaround(struct ddr_priv *priv) +{ + /* Workaround Trcd overflow by using Additive latency. */ + if (octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) { + union cvmx_lmcx_modereg_params0 mp0; + union cvmx_lmcx_timing_params1 tp1; + union cvmx_lmcx_control ctrl; + int rankx; + + tp1.u64 = lmc_rd(priv, CVMX_LMCX_TIMING_PARAMS1(if_num)); + mp0.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num)); + ctrl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + + if (tp1.cn78xx.trcd == 0) { + debug("Workaround Trcd overflow by using Additive latency.\n"); + /* Hard code this to 12 and enable additive latency */ + tp1.cn78xx.trcd = 12; + mp0.s.al = 2; /* CL-2 */ + ctrl.s.pocas = 1; + + debug("MODEREG_PARAMS0 : 0x%016llx\n", + mp0.u64); + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num), + mp0.u64); + debug("TIMING_PARAMS1 : 0x%016llx\n", + tp1.u64); + lmc_wr(priv, CVMX_LMCX_TIMING_PARAMS1(if_num), tp1.u64); + + debug("LMC_CONTROL : 0x%016llx\n", + ctrl.u64); + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctrl.u64); + + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + /* MR1 */ + ddr4_mrw(priv, if_num, rankx, -1, 1, 0); + } + } + } + + // this is here just for output, to allow check of the Deskew + // settings one last time... + if (!disable_deskew_training) { + struct deskew_counts dsk_counts; + + debug("N%d.LMC%d: Check Deskew Settings before software Write-Leveling.\n", + node, if_num); + validate_deskew_training(priv, rank_mask, if_num, &dsk_counts, + 3); + } + + /* + * Workaround Errata 26304 (T88@2.0, O75@1.x, O78@2.x) + * + * When the CSRs LMCX_DLL_CTL3[WR_DESKEW_ENA] = 1 AND + * LMCX_PHY_CTL2[DQS[0..8]_DSK_ADJ] > 4, set + * LMCX_EXT_CONFIG[DRIVE_ENA_BPRCH] = 1. + */ + if (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X) || + octeon_is_cpuid(OCTEON_CNF75XX_PASS1_X)) { + union cvmx_lmcx_dll_ctl3 dll_ctl3; + union cvmx_lmcx_phy_ctl2 phy_ctl2; + union cvmx_lmcx_ext_config ext_cfg; + int increased_dsk_adj = 0; + int byte; + + phy_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL2(if_num)); + ext_cfg.u64 = lmc_rd(priv, CVMX_LMCX_EXT_CONFIG(if_num)); + dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + + for (byte = 0; byte < 8; ++byte) { + if (!(if_bytemask & (1 << byte))) + continue; + increased_dsk_adj |= + (((phy_ctl2.u64 >> (byte * 3)) & 0x7) > 4); + } + + if (dll_ctl3.s.wr_deskew_ena == 1 && increased_dsk_adj) { + ext_cfg.s.drive_ena_bprch = 1; + lmc_wr(priv, CVMX_LMCX_EXT_CONFIG(if_num), ext_cfg.u64); + debug("LMC%d: Forcing DRIVE_ENA_BPRCH for Workaround Errata 26304.\n", + if_num); + } + } +} + +// Software Write-Leveling block + +#define VREF_RANGE1_LIMIT 0x33 // range1 is valid for 0x00 - 0x32 +#define VREF_RANGE2_LIMIT 0x18 // range2 is valid for 0x00 - 0x17 +// full window is valid for 0x00 to 0x4A +// let 0x00 - 0x17 be range2, 0x18 - 0x4a be range 1 +#define VREF_LIMIT (VREF_RANGE1_LIMIT + VREF_RANGE2_LIMIT) +#define VREF_FINAL (VREF_LIMIT - 1) + +enum sw_wl_status { + WL_ESTIMATED = 0, /* HW/SW wleveling failed. Reslt estimated */ + WL_HARDWARE = 1, /* H/W wleveling succeeded */ + WL_SOFTWARE = 2, /* S/W wleveling passed 2 contiguous setting */ + WL_SOFTWARE1 = 3, /* S/W wleveling passed 1 marginal setting */ +}; + +static u64 rank_addr __section(".data"); +static int vref_val __section(".data"); +static int final_vref_val __section(".data"); +static int final_vref_range __section(".data"); +static int start_vref_val __section(".data"); +static int computed_final_vref_val __section(".data"); +static char best_vref_val_count __section(".data"); +static char vref_val_count __section(".data"); +static char best_vref_val_start __section(".data"); +static char vref_val_start __section(".data"); +static int bytes_failed __section(".data"); +static enum sw_wl_status byte_test_status[9] __section(".data"); +static enum sw_wl_status sw_wl_rank_status __section(".data"); +static int sw_wl_failed __section(".data"); +static int sw_wl_hw __section(".data"); +static int measured_vref_flag __section(".data"); + +static void ddr4_vref_loop(struct ddr_priv *priv, int rankx) +{ + char *s; + + if (vref_val < VREF_FINAL) { + int vrange, vvalue; + + if (vref_val < VREF_RANGE2_LIMIT) { + vrange = 1; + vvalue = vref_val; + } else { + vrange = 0; + vvalue = vref_val - VREF_RANGE2_LIMIT; + } + + set_vref(priv, if_num, rankx, vrange, vvalue); + } else { /* if (vref_val < VREF_FINAL) */ + /* Print the final vref value first. */ + + /* Always print the computed first if its valid */ + if (computed_final_vref_val >= 0) { + debug("N%d.LMC%d.R%d: vref Computed Summary : %2d (0x%02x)\n", + node, if_num, rankx, + computed_final_vref_val, computed_final_vref_val); + } + + if (!measured_vref_flag) { // setup to use the computed + best_vref_val_count = 1; + final_vref_val = computed_final_vref_val; + } else { // setup to use the measured + if (best_vref_val_count > 0) { + best_vref_val_count = + max(best_vref_val_count, (char)2); + final_vref_val = best_vref_val_start + + divide_nint(best_vref_val_count - 1, 2); + + if (final_vref_val < VREF_RANGE2_LIMIT) { + final_vref_range = 1; + } else { + final_vref_range = 0; + final_vref_val -= VREF_RANGE2_LIMIT; + } + + int vvlo = best_vref_val_start; + int vrlo; + int vvhi = best_vref_val_start + + best_vref_val_count - 1; + int vrhi; + + if (vvlo < VREF_RANGE2_LIMIT) { + vrlo = 2; + } else { + vrlo = 1; + vvlo -= VREF_RANGE2_LIMIT; + } + + if (vvhi < VREF_RANGE2_LIMIT) { + vrhi = 2; + } else { + vrhi = 1; + vvhi -= VREF_RANGE2_LIMIT; + } + debug("N%d.LMC%d.R%d: vref Training Summary : 0x%02x/%1d <----- 0x%02x/%1d -----> 0x%02x/%1d, range: %2d\n", + node, if_num, rankx, vvlo, vrlo, + final_vref_val, + final_vref_range + 1, vvhi, vrhi, + best_vref_val_count - 1); + + } else { + /* + * If nothing passed use the default vref + * value for this rank + */ + union cvmx_lmcx_modereg_params2 mp2; + + mp2.u64 = + lmc_rd(priv, + CVMX_LMCX_MODEREG_PARAMS2(if_num)); + final_vref_val = (mp2.u64 >> + (rankx * 10 + 3)) & 0x3f; + final_vref_range = (mp2.u64 >> + (rankx * 10 + 9)) & 0x01; + + debug("N%d.LMC%d.R%d: vref Using Default : %2d <----- %2d (0x%02x) -----> %2d, range%1d\n", + node, if_num, rankx, final_vref_val, + final_vref_val, final_vref_val, + final_vref_val, final_vref_range + 1); + } + } + + // allow override + s = lookup_env(priv, "ddr%d_vref_val_%1d%1d", + if_num, !!(rankx & 2), !!(rankx & 1)); + if (s) + final_vref_val = strtoul(s, NULL, 0); + + set_vref(priv, if_num, rankx, final_vref_range, final_vref_val); + } +} + +#define WL_MIN_NO_ERRORS_COUNT 3 // FIXME? three passes without errors + +static int errors __section(".data"); +static int byte_delay[9] __section(".data"); +static u64 bytemask __section(".data"); +static int bytes_todo __section(".data"); +static int no_errors_count __section(".data"); +static u64 bad_bits[2] __section(".data"); +static u64 sum_dram_dclk __section(".data"); +static u64 sum_dram_ops __section(".data"); +static u64 start_dram_dclk __section(".data"); +static u64 stop_dram_dclk __section(".data"); +static u64 start_dram_ops __section(".data"); +static u64 stop_dram_ops __section(".data"); + +static void lmc_sw_write_leveling_loop(struct ddr_priv *priv, int rankx) +{ + int delay; + int b; + + // write the current set of WL delays + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), wl_rank.u64); + wl_rank.u64 = lmc_rd(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num)); + + // do the test + if (sw_wl_hw) { + errors = run_best_hw_patterns(priv, if_num, rank_addr, + DBTRAIN_TEST, bad_bits); + errors &= bytes_todo; // keep only the ones we are still doing + } else { + start_dram_dclk = lmc_rd(priv, CVMX_LMCX_DCLK_CNT(if_num)); + start_dram_ops = lmc_rd(priv, CVMX_LMCX_OPS_CNT(if_num)); + errors = test_dram_byte64(priv, if_num, rank_addr, bytemask, + bad_bits); + + stop_dram_dclk = lmc_rd(priv, CVMX_LMCX_DCLK_CNT(if_num)); + stop_dram_ops = lmc_rd(priv, CVMX_LMCX_OPS_CNT(if_num)); + sum_dram_dclk += stop_dram_dclk - start_dram_dclk; + sum_dram_ops += stop_dram_ops - start_dram_ops; + } + + debug("WL pass1: test_dram_byte returned 0x%x\n", errors); + + // remember, errors will not be returned for byte-lanes that have + // maxxed out... + if (errors == 0) { + no_errors_count++; // bump + // bypass check/update completely + if (no_errors_count > 1) + return; // to end of do-while + } else { + no_errors_count = 0; // reset + } + + // check errors by byte + for (b = 0; b < 9; ++b) { + if (!(bytes_todo & (1 << b))) + continue; + + delay = byte_delay[b]; + // yes, an error in this byte lane + if (errors & (1 << b)) { + debug(" byte %d delay %2d Errors\n", b, delay); + // since this byte had an error, we move to the next + // delay value, unless done with it + delay += 8; // incr by 8 to do delay high-order bits + if (delay < 32) { + upd_wl_rank(&wl_rank, b, delay); + debug(" byte %d delay %2d New\n", + b, delay); + byte_delay[b] = delay; + } else { + // reached max delay, maybe really done with + // this byte + // consider an alt only for computed VREF and + if (!measured_vref_flag && + (hwl_alts[rankx].hwl_alt_mask & (1 << b))) { + // if an alt exists... + // just orig low-3 bits + int bad_delay = delay & 0x6; + + // yes, use it + delay = hwl_alts[rankx].hwl_alt_delay[b]; + // clear that flag + hwl_alts[rankx].hwl_alt_mask &= + ~(1 << b); + upd_wl_rank(&wl_rank, b, delay); + byte_delay[b] = delay; + debug(" byte %d delay %2d ALTERNATE\n", + b, delay); + debug("N%d.LMC%d.R%d: SWL: Byte %d: %d FAIL, trying ALTERNATE %d\n", + node, if_num, + rankx, b, bad_delay, delay); + + } else { + unsigned int bits_bad; + + if (b < 8) { + // test no longer, remove from + // byte mask + bytemask &= + ~(0xffULL << (8 * b)); + bits_bad = (unsigned int) + ((bad_bits[0] >> + (8 * b)) & 0xffUL); + } else { + bits_bad = (unsigned int) + (bad_bits[1] & 0xffUL); + } + + // remove from bytes to do + bytes_todo &= ~(1 << b); + // make sure this is set for this case + byte_test_status[b] = WL_ESTIMATED; + debug(" byte %d delay %2d Exhausted\n", + b, delay); + if (!measured_vref_flag) { + // this is too noisy when doing + // measured VREF + debug("N%d.LMC%d.R%d: SWL: Byte %d (0x%02x): delay %d EXHAUSTED\n", + node, if_num, rankx, + b, bits_bad, delay); + } + } + } + } else { + // no error, stay with current delay, but keep testing + // it... + debug(" byte %d delay %2d Passed\n", b, delay); + byte_test_status[b] = WL_HARDWARE; // change status + } + } /* for (b = 0; b < 9; ++b) */ +} + +static void sw_write_lvl_use_ecc(struct ddr_priv *priv, int rankx) +{ + int save_byte8 = wl_rank.s.byte8; + + byte_test_status[8] = WL_HARDWARE; /* H/W delay value */ + + if (save_byte8 != wl_rank.s.byte3 && + save_byte8 != wl_rank.s.byte4) { + int test_byte8 = save_byte8; + int test_byte8_error; + int byte8_error = 0x1f; + int adder; + int avg_bytes = divide_nint(wl_rank.s.byte3 + wl_rank.s.byte4, + 2); + + for (adder = 0; adder <= 32; adder += 8) { + test_byte8_error = abs((adder + save_byte8) - + avg_bytes); + if (test_byte8_error < byte8_error) { + byte8_error = test_byte8_error; + test_byte8 = save_byte8 + adder; + } + } + + // only do the check if we are not using measured VREF + if (!measured_vref_flag) { + /* Use only even settings, rounding down... */ + test_byte8 &= ~1; + + // do validity check on the calculated ECC delay value + // this depends on the DIMM type + if (spd_rdimm) { // RDIMM + // but not mini-RDIMM + if (spd_dimm_type != 5) { + // it can be > byte4, but should never + // be > byte3 + if (test_byte8 > wl_rank.s.byte3) { + /* say it is still estimated */ + byte_test_status[8] = + WL_ESTIMATED; + } + } + } else { // UDIMM + if (test_byte8 < wl_rank.s.byte3 || + test_byte8 > wl_rank.s.byte4) { + // should never be outside the + // byte 3-4 range + /* say it is still estimated */ + byte_test_status[8] = WL_ESTIMATED; + } + } + /* + * Report whenever the calculation appears bad. + * This happens if some of the original values were off, + * or unexpected geometry from DIMM type, or custom + * circuitry (NIC225E, I am looking at you!). + * We will trust the calculated value, and depend on + * later testing to catch any instances when that + * value is truly bad. + */ + // ESTIMATED means there may be an issue + if (byte_test_status[8] == WL_ESTIMATED) { + debug("N%d.LMC%d.R%d: SWL: (%cDIMM): calculated ECC delay unexpected (%d/%d/%d)\n", + node, if_num, rankx, + (spd_rdimm ? 'R' : 'U'), wl_rank.s.byte4, + test_byte8, wl_rank.s.byte3); + byte_test_status[8] = WL_HARDWARE; + } + } + /* Use only even settings */ + wl_rank.s.byte8 = test_byte8 & ~1; + } + + if (wl_rank.s.byte8 != save_byte8) { + /* Change the status if s/w adjusted the delay */ + byte_test_status[8] = WL_SOFTWARE; /* Estimated delay */ + } +} + +static __maybe_unused void parallel_wl_block_delay(struct ddr_priv *priv, + int rankx) +{ + int errors; + int byte_delay[8]; + int byte_passed[8]; + u64 bytemask; + u64 bitmask; + int wl_offset; + int bytes_todo; + int sw_wl_offset = 1; + int delay; + int b; + + for (b = 0; b < 8; ++b) + byte_passed[b] = 0; + + bytes_todo = if_bytemask; + + for (wl_offset = sw_wl_offset; wl_offset >= 0; --wl_offset) { + debug("Starting wl_offset for-loop: %d\n", wl_offset); + + bytemask = 0; + + for (b = 0; b < 8; ++b) { + byte_delay[b] = 0; + // this does not contain fully passed bytes + if (!(bytes_todo & (1 << b))) + continue; + + // reset across passes if not fully passed + byte_passed[b] = 0; + upd_wl_rank(&wl_rank, b, 0); // all delays start at 0 + bitmask = ((!if_64b) && (b == 4)) ? 0x0f : 0xff; + // set the bytes bits in the bytemask + bytemask |= bitmask << (8 * b); + } /* for (b = 0; b < 8; ++b) */ + + // start a pass if there is any byte lane to test + while (bytemask != 0) { + debug("Starting bytemask while-loop: 0x%llx\n", + bytemask); + + // write this set of WL delays + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), + wl_rank.u64); + wl_rank.u64 = lmc_rd(priv, + CVMX_LMCX_WLEVEL_RANKX(rankx, + if_num)); + + // do the test + if (sw_wl_hw) { + errors = run_best_hw_patterns(priv, if_num, + rank_addr, + DBTRAIN_TEST, + NULL) & 0xff; + } else { + errors = test_dram_byte64(priv, if_num, + rank_addr, bytemask, + NULL); + } + + debug("test_dram_byte returned 0x%x\n", errors); + + // check errors by byte + for (b = 0; b < 8; ++b) { + if (!(bytes_todo & (1 << b))) + continue; + + delay = byte_delay[b]; + if (errors & (1 << b)) { // yes, an error + debug(" byte %d delay %2d Errors\n", + b, delay); + byte_passed[b] = 0; + } else { // no error + byte_passed[b] += 1; + // Look for consecutive working settings + if (byte_passed[b] == (1 + wl_offset)) { + debug(" byte %d delay %2d FULLY Passed\n", + b, delay); + if (wl_offset == 1) { + byte_test_status[b] = + WL_SOFTWARE; + } else if (wl_offset == 0) { + byte_test_status[b] = + WL_SOFTWARE1; + } + + // test no longer, remove + // from byte mask this pass + bytemask &= ~(0xffULL << + (8 * b)); + // remove completely from + // concern + bytes_todo &= ~(1 << b); + // on to the next byte, bypass + // delay updating!! + continue; + } else { + debug(" byte %d delay %2d Passed\n", + b, delay); + } + } + + // error or no, here we move to the next delay + // value for this byte, unless done all delays + // only a byte that has "fully passed" will + // bypass around this, + delay += 2; + if (delay < 32) { + upd_wl_rank(&wl_rank, b, delay); + debug(" byte %d delay %2d New\n", + b, delay); + byte_delay[b] = delay; + } else { + // reached max delay, done with this + // byte + debug(" byte %d delay %2d Exhausted\n", + b, delay); + // test no longer, remove from byte + // mask this pass + bytemask &= ~(0xffULL << (8 * b)); + } + } /* for (b = 0; b < 8; ++b) */ + debug("End of for-loop: bytemask 0x%llx\n", bytemask); + } /* while (bytemask != 0) */ + } + + for (b = 0; b < 8; ++b) { + // any bytes left in bytes_todo did not pass + if (bytes_todo & (1 << b)) { + union cvmx_lmcx_rlevel_rankx lmc_rlevel_rank; + + /* + * Last resort. Use Rlevel settings to estimate + * Wlevel if software write-leveling fails + */ + debug("Using RLEVEL as WLEVEL estimate for byte %d\n", + b); + lmc_rlevel_rank.u64 = + lmc_rd(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + rlevel_to_wlevel(&lmc_rlevel_rank, &wl_rank, b); + } + } /* for (b = 0; b < 8; ++b) */ +} + +static int lmc_sw_write_leveling(struct ddr_priv *priv) +{ + /* Try to determine/optimize write-level delays experimentally. */ + union cvmx_lmcx_wlevel_rankx wl_rank_hw_res; + union cvmx_lmcx_config cfg; + int rankx; + int byte; + char *s; + int i; + + int active_rank; + int sw_wl_enable = 1; /* FIX... Should be customizable. */ + int interfaces; + + static const char * const wl_status_strings[] = { + "(e)", + " ", + " ", + "(1)" + }; + + // FIXME: make HW-assist the default now? + int sw_wl_hw_default = SW_WLEVEL_HW_DEFAULT; + int dram_connection = c_cfg->dram_connection; + + s = lookup_env(priv, "ddr_sw_wlevel_hw"); + if (s) + sw_wl_hw_default = !!strtoul(s, NULL, 0); + if (!if_64b) // must use SW algo if 32-bit mode + sw_wl_hw_default = 0; + + // can never use hw-assist + if (octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) + sw_wl_hw_default = 0; + + s = lookup_env(priv, "ddr_software_wlevel"); + if (s) + sw_wl_enable = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr%d_dram_connection", if_num); + if (s) + dram_connection = !!strtoul(s, NULL, 0); + + cvmx_rng_enable(); + + /* + * Get the measured_vref setting from the config, check for an + * override... + */ + /* NOTE: measured_vref=1 (ON) means force use of MEASURED vref... */ + // NOTE: measured VREF can only be done for DDR4 + if (ddr_type == DDR4_DRAM) { + measured_vref_flag = c_cfg->measured_vref; + s = lookup_env(priv, "ddr_measured_vref"); + if (s) + measured_vref_flag = !!strtoul(s, NULL, 0); + } else { + measured_vref_flag = 0; // OFF for DDR3 + } + + /* + * Ensure disabled ECC for DRAM tests using the SW algo, else leave + * it untouched + */ + if (!sw_wl_hw_default) { + cfg.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + cfg.cn78xx.ecc_ena = 0; + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), cfg.u64); + } + + /* + * We need to track absolute rank number, as well as how many + * active ranks we have. Two single rank DIMMs show up as + * ranks 0 and 2, but only 2 ranks are active. + */ + active_rank = 0; + + interfaces = __builtin_popcount(if_mask); + + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + final_vref_range = 0; + start_vref_val = 0; + computed_final_vref_val = -1; + sw_wl_rank_status = WL_HARDWARE; + sw_wl_failed = 0; + sw_wl_hw = sw_wl_hw_default; + + if (!sw_wl_enable) + break; + + if (!(rank_mask & (1 << rankx))) + continue; + + debug("N%d.LMC%d.R%d: Performing Software Write-Leveling %s\n", + node, if_num, rankx, + (sw_wl_hw) ? "with H/W assist" : + "with S/W algorithm"); + + if (ddr_type == DDR4_DRAM && num_ranks != 4) { + // always compute when we can... + computed_final_vref_val = + compute_vref_val(priv, if_num, rankx, dimm_count, + num_ranks, imp_val, + is_stacked_die, dram_connection); + + // but only use it if allowed + if (!measured_vref_flag) { + // skip all the measured vref processing, + // just the final setting + start_vref_val = VREF_FINAL; + } + } + + /* Save off the h/w wl results */ + wl_rank_hw_res.u64 = lmc_rd(priv, + CVMX_LMCX_WLEVEL_RANKX(rankx, + if_num)); + + vref_val_count = 0; + vref_val_start = 0; + best_vref_val_count = 0; + best_vref_val_start = 0; + + /* Loop one extra time using the Final vref value. */ + for (vref_val = start_vref_val; vref_val < VREF_LIMIT; + ++vref_val) { + if (ddr_type == DDR4_DRAM) + ddr4_vref_loop(priv, rankx); + + /* Restore the saved value */ + wl_rank.u64 = wl_rank_hw_res.u64; + + for (byte = 0; byte < 9; ++byte) + byte_test_status[byte] = WL_ESTIMATED; + + if (wl_mask_err == 0) { + /* + * Determine address of DRAM to test for + * pass 1 of software write leveling. + */ + rank_addr = active_rank * + (1ull << (pbank_lsb - bunk_enable + + (interfaces / 2))); + + /* + * Adjust address for boot bus hole in memory + * map. + */ + if (rank_addr > 0x10000000) + rank_addr += 0x10000000; + + debug("N%d.LMC%d.R%d: Active Rank %d Address: 0x%llx\n", + node, if_num, rankx, active_rank, + rank_addr); + + // start parallel write-leveling block for + // delay high-order bits + errors = 0; + no_errors_count = 0; + sum_dram_dclk = 0; + sum_dram_ops = 0; + + if (if_64b) { + bytes_todo = (sw_wl_hw) ? + if_bytemask : 0xFF; + bytemask = ~0ULL; + } else { + // 32-bit, must be using SW algo, + // only data bytes + bytes_todo = 0x0f; + bytemask = 0x00000000ffffffffULL; + } + + for (byte = 0; byte < 9; ++byte) { + if (!(bytes_todo & (1 << byte))) { + byte_delay[byte] = 0; + } else { + byte_delay[byte] = + get_wl_rank(&wl_rank, byte); + } + } /* for (byte = 0; byte < 9; ++byte) */ + + do { + lmc_sw_write_leveling_loop(priv, rankx); + } while (no_errors_count < + WL_MIN_NO_ERRORS_COUNT); + + if (!sw_wl_hw) { + u64 percent_x10; + + if (sum_dram_dclk == 0) + sum_dram_dclk = 1; + percent_x10 = sum_dram_ops * 1000 / + sum_dram_dclk; + debug("N%d.LMC%d.R%d: ops %llu, cycles %llu, used %llu.%llu%%\n", + node, if_num, rankx, sum_dram_ops, + sum_dram_dclk, percent_x10 / 10, + percent_x10 % 10); + } + if (errors) { + debug("End WLEV_64 while loop: vref_val %d(0x%x), errors 0x%02x\n", + vref_val, vref_val, errors); + } + // end parallel write-leveling block for + // delay high-order bits + + // if we used HW-assist, we did the ECC byte + // when approp. + if (sw_wl_hw) { + if (wl_print) { + debug("N%d.LMC%d.R%d: HW-assisted SWL - ECC estimate not needed.\n", + node, if_num, rankx); + } + goto no_ecc_estimate; + } + + if ((if_bytemask & 0xff) == 0xff) { + if (use_ecc) { + sw_write_lvl_use_ecc(priv, + rankx); + } else { + /* H/W delay value */ + byte_test_status[8] = + WL_HARDWARE; + /* ECC is not used */ + wl_rank.s.byte8 = + wl_rank.s.byte0; + } + } else { + if (use_ecc) { + /* Estimate the ECC byte dly */ + // add hi-order to b4 + wl_rank.s.byte4 |= + (wl_rank.s.byte3 & + 0x38); + if ((wl_rank.s.byte4 & 0x06) < + (wl_rank.s.byte3 & 0x06)) { + // must be next clock + wl_rank.s.byte4 += 8; + } + } else { + /* ECC is not used */ + wl_rank.s.byte4 = + wl_rank.s.byte0; + } + + /* + * Change the status if s/w adjusted + * the delay + */ + /* Estimated delay */ + byte_test_status[4] = WL_SOFTWARE; + } /* if ((if_bytemask & 0xff) == 0xff) */ + } /* if (wl_mask_err == 0) */ + +no_ecc_estimate: + + bytes_failed = 0; + for (byte = 0; byte < 9; ++byte) { + /* Don't accumulate errors for untested bytes */ + if (!(if_bytemask & (1 << byte))) + continue; + bytes_failed += + (byte_test_status[byte] == WL_ESTIMATED); + } + + /* vref training loop is only used for DDR4 */ + if (ddr_type != DDR4_DRAM) + break; + + if (bytes_failed == 0) { + if (vref_val_count == 0) + vref_val_start = vref_val; + + ++vref_val_count; + if (vref_val_count > best_vref_val_count) { + best_vref_val_count = vref_val_count; + best_vref_val_start = vref_val_start; + debug("N%d.LMC%d.R%d: vref Training (%2d) : 0x%02x <----- ???? -----> 0x%02x\n", + node, if_num, rankx, vref_val, + best_vref_val_start, + best_vref_val_start + + best_vref_val_count - 1); + } + } else { + vref_val_count = 0; + debug("N%d.LMC%d.R%d: vref Training (%2d) : failed\n", + node, if_num, rankx, vref_val); + } + } + + /* + * Determine address of DRAM to test for software write + * leveling. + */ + rank_addr = active_rank * (1ull << (pbank_lsb - bunk_enable + + (interfaces / 2))); + /* Adjust address for boot bus hole in memory map. */ + if (rank_addr > 0x10000000) + rank_addr += 0x10000000; + + debug("Rank Address: 0x%llx\n", rank_addr); + + if (bytes_failed) { + // FIXME? the big hammer, did not even try SW WL pass2, + // assume only chip reset will help + debug("N%d.LMC%d.R%d: S/W write-leveling pass 1 failed\n", + node, if_num, rankx); + sw_wl_failed = 1; + } else { /* if (bytes_failed) */ + // SW WL pass 1 was OK, write the settings + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), + wl_rank.u64); + wl_rank.u64 = lmc_rd(priv, + CVMX_LMCX_WLEVEL_RANKX(rankx, + if_num)); + + // do validity check on the delay values by running + // the test 1 more time... + // FIXME: we really need to check the ECC byte setting + // here as well, so we need to enable ECC for this test! + // if there are any errors, claim SW WL failure + u64 datamask = (if_64b) ? 0xffffffffffffffffULL : + 0x00000000ffffffffULL; + int errors; + + // do the test + if (sw_wl_hw) { + errors = run_best_hw_patterns(priv, if_num, + rank_addr, + DBTRAIN_TEST, + NULL) & 0xff; + } else { + errors = test_dram_byte64(priv, if_num, + rank_addr, datamask, + NULL); + } + + if (errors) { + debug("N%d.LMC%d.R%d: Wlevel Rank Final Test errors 0x%03x\n", + node, if_num, rankx, errors); + sw_wl_failed = 1; + } + } /* if (bytes_failed) */ + + // FIXME? dump the WL settings, so we get more of a clue + // as to what happened where + debug("N%d.LMC%d.R%d: Wlevel Rank %#4x, 0x%016llX : %2d%3s %2d%3s %2d%3s %2d%3s %2d%3s %2d%3s %2d%3s %2d%3s %2d%3s %s\n", + node, if_num, rankx, wl_rank.s.status, wl_rank.u64, + wl_rank.s.byte8, wl_status_strings[byte_test_status[8]], + wl_rank.s.byte7, wl_status_strings[byte_test_status[7]], + wl_rank.s.byte6, wl_status_strings[byte_test_status[6]], + wl_rank.s.byte5, wl_status_strings[byte_test_status[5]], + wl_rank.s.byte4, wl_status_strings[byte_test_status[4]], + wl_rank.s.byte3, wl_status_strings[byte_test_status[3]], + wl_rank.s.byte2, wl_status_strings[byte_test_status[2]], + wl_rank.s.byte1, wl_status_strings[byte_test_status[1]], + wl_rank.s.byte0, wl_status_strings[byte_test_status[0]], + (sw_wl_rank_status == WL_HARDWARE) ? "" : "(s)"); + + // finally, check for fatal conditions: either chip reset + // right here, or return error flag + if ((ddr_type == DDR4_DRAM && best_vref_val_count == 0) || + sw_wl_failed) { + if (!ddr_disable_chip_reset) { // do chip RESET + printf("N%d.LMC%d.R%d: INFO: Short memory test indicates a retry is needed. Resetting node...\n", + node, if_num, rankx); + mdelay(500); + do_reset(NULL, 0, 0, NULL); + } else { + // return error flag so LMC init can be retried. + debug("N%d.LMC%d.R%d: INFO: Short memory test indicates a retry is needed. Restarting LMC init...\n", + node, if_num, rankx); + return -EAGAIN; // 0 indicates restart possible. + } + } + active_rank++; + } + + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + int parameter_set = 0; + u64 value; + + if (!(rank_mask & (1 << rankx))) + continue; + + wl_rank.u64 = lmc_rd(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, + if_num)); + + for (i = 0; i < 9; ++i) { + s = lookup_env(priv, "ddr%d_wlevel_rank%d_byte%d", + if_num, rankx, i); + if (s) { + parameter_set |= 1; + value = strtoul(s, NULL, 0); + + upd_wl_rank(&wl_rank, i, value); + } + } + + s = lookup_env_ull(priv, "ddr%d_wlevel_rank%d", if_num, rankx); + if (s) { + parameter_set |= 1; + value = strtoull(s, NULL, 0); + wl_rank.u64 = value; + } + + if (parameter_set) { + lmc_wr(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num), + wl_rank.u64); + wl_rank.u64 = + lmc_rd(priv, CVMX_LMCX_WLEVEL_RANKX(rankx, if_num)); + display_wl(if_num, wl_rank, rankx); + } + // if there are unused entries to be filled + if ((rank_mask & 0x0F) != 0x0F) { + if (rankx < 3) { + debug("N%d.LMC%d.R%d: checking for WLEVEL_RANK unused entries.\n", + node, if_num, rankx); + + // if rank 0, write ranks 1 and 2 here if empty + if (rankx == 0) { + // check that rank 1 is empty + if (!(rank_mask & (1 << 1))) { + debug("N%d.LMC%d.R%d: writing WLEVEL_RANK unused entry R%d.\n", + node, if_num, rankx, 1); + lmc_wr(priv, + CVMX_LMCX_WLEVEL_RANKX(1, + if_num), + wl_rank.u64); + } + + // check that rank 2 is empty + if (!(rank_mask & (1 << 2))) { + debug("N%d.LMC%d.R%d: writing WLEVEL_RANK unused entry R%d.\n", + node, if_num, rankx, 2); + lmc_wr(priv, + CVMX_LMCX_WLEVEL_RANKX(2, + if_num), + wl_rank.u64); + } + } + + // if rank 0, 1 or 2, write rank 3 here if empty + // check that rank 3 is empty + if (!(rank_mask & (1 << 3))) { + debug("N%d.LMC%d.R%d: writing WLEVEL_RANK unused entry R%d.\n", + node, if_num, rankx, 3); + lmc_wr(priv, + CVMX_LMCX_WLEVEL_RANKX(3, + if_num), + wl_rank.u64); + } + } + } + } + + /* Enable 32-bit mode if required. */ + cfg.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + cfg.cn78xx.mode32b = (!if_64b); + debug("%-45s : %d\n", "MODE32B", cfg.cn78xx.mode32b); + + /* Restore the ECC configuration */ + if (!sw_wl_hw_default) + cfg.cn78xx.ecc_ena = use_ecc; + + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), cfg.u64); + + return 0; +} + +static void lmc_dll(struct ddr_priv *priv) +{ + union cvmx_lmcx_dll_ctl3 ddr_dll_ctl3; + int setting[9]; + int i; + + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + + for (i = 0; i < 9; ++i) { + SET_DDR_DLL_CTL3(dll90_byte_sel, ENCODE_DLL90_BYTE_SEL(i)); + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + setting[i] = GET_DDR_DLL_CTL3(dll90_setting); + debug("%d. LMC%d_DLL_CTL3[%d] = %016llx %d\n", i, if_num, + GET_DDR_DLL_CTL3(dll90_byte_sel), ddr_dll_ctl3.u64, + setting[i]); + } + + debug("N%d.LMC%d: %-36s : %5d %5d %5d %5d %5d %5d %5d %5d %5d\n", + node, if_num, "DLL90 Setting 8:0", + setting[8], setting[7], setting[6], setting[5], setting[4], + setting[3], setting[2], setting[1], setting[0]); + + process_custom_dll_offsets(priv, if_num, "ddr_dll_write_offset", + c_cfg->dll_write_offset, + "ddr%d_dll_write_offset_byte%d", 1); + process_custom_dll_offsets(priv, if_num, "ddr_dll_read_offset", + c_cfg->dll_read_offset, + "ddr%d_dll_read_offset_byte%d", 2); +} + +#define SLOT_CTL_INCR(csr, chip, field, incr) \ + csr.chip.field = (csr.chip.field < (64 - incr)) ? \ + (csr.chip.field + incr) : 63 + +#define INCR(csr, chip, field, incr) \ + csr.chip.field = (csr.chip.field < (64 - incr)) ? \ + (csr.chip.field + incr) : 63 + +static void lmc_workaround_2(struct ddr_priv *priv) +{ + /* Workaround Errata 21063 */ + if (octeon_is_cpuid(OCTEON_CN78XX) || + octeon_is_cpuid(OCTEON_CN70XX_PASS1_X)) { + union cvmx_lmcx_slot_ctl0 slot_ctl0; + union cvmx_lmcx_slot_ctl1 slot_ctl1; + union cvmx_lmcx_slot_ctl2 slot_ctl2; + union cvmx_lmcx_ext_config ext_cfg; + + slot_ctl0.u64 = lmc_rd(priv, CVMX_LMCX_SLOT_CTL0(if_num)); + slot_ctl1.u64 = lmc_rd(priv, CVMX_LMCX_SLOT_CTL1(if_num)); + slot_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_SLOT_CTL2(if_num)); + + ext_cfg.u64 = lmc_rd(priv, CVMX_LMCX_EXT_CONFIG(if_num)); + + /* When ext_cfg.s.read_ena_bprch is set add 1 */ + if (ext_cfg.s.read_ena_bprch) { + SLOT_CTL_INCR(slot_ctl0, cn78xx, r2w_init, 1); + SLOT_CTL_INCR(slot_ctl0, cn78xx, r2w_l_init, 1); + SLOT_CTL_INCR(slot_ctl1, cn78xx, r2w_xrank_init, 1); + SLOT_CTL_INCR(slot_ctl2, cn78xx, r2w_xdimm_init, 1); + } + + /* Always add 2 */ + SLOT_CTL_INCR(slot_ctl1, cn78xx, w2r_xrank_init, 2); + SLOT_CTL_INCR(slot_ctl2, cn78xx, w2r_xdimm_init, 2); + + lmc_wr(priv, CVMX_LMCX_SLOT_CTL0(if_num), slot_ctl0.u64); + lmc_wr(priv, CVMX_LMCX_SLOT_CTL1(if_num), slot_ctl1.u64); + lmc_wr(priv, CVMX_LMCX_SLOT_CTL2(if_num), slot_ctl2.u64); + } + + /* Workaround Errata 21216 */ + if (octeon_is_cpuid(OCTEON_CN78XX_PASS1_X) || + octeon_is_cpuid(OCTEON_CN70XX_PASS1_X)) { + union cvmx_lmcx_slot_ctl1 slot_ctl1; + union cvmx_lmcx_slot_ctl2 slot_ctl2; + + slot_ctl1.u64 = lmc_rd(priv, CVMX_LMCX_SLOT_CTL1(if_num)); + slot_ctl1.cn78xx.w2w_xrank_init = + max(10, (int)slot_ctl1.cn78xx.w2w_xrank_init); + lmc_wr(priv, CVMX_LMCX_SLOT_CTL1(if_num), slot_ctl1.u64); + + slot_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_SLOT_CTL2(if_num)); + slot_ctl2.cn78xx.w2w_xdimm_init = + max(10, (int)slot_ctl2.cn78xx.w2w_xdimm_init); + lmc_wr(priv, CVMX_LMCX_SLOT_CTL2(if_num), slot_ctl2.u64); + } +} + +static void lmc_final(struct ddr_priv *priv) +{ + /* + * 4.8.11 Final LMC Initialization + * + * Early LMC initialization, LMC write-leveling, and LMC read-leveling + * must be completed prior to starting this final LMC initialization. + * + * LMC hardware updates the LMC(0)_SLOT_CTL0, LMC(0)_SLOT_CTL1, + * LMC(0)_SLOT_CTL2 CSRs with minimum values based on the selected + * readleveling and write-leveling settings. Software should not write + * the final LMC(0)_SLOT_CTL0, LMC(0)_SLOT_CTL1, and LMC(0)_SLOT_CTL2 + * values until after the final read-leveling and write-leveling + * settings are written. + * + * Software must ensure the LMC(0)_SLOT_CTL0, LMC(0)_SLOT_CTL1, and + * LMC(0)_SLOT_CTL2 CSR values are appropriate for this step. These CSRs + * select the minimum gaps between read operations and write operations + * of various types. + * + * Software must not reduce the values in these CSR fields below the + * values previously selected by the LMC hardware (during write-leveling + * and read-leveling steps above). + * + * All sections in this chapter may be used to derive proper settings + * for these registers. + * + * For minimal read latency, L2C_CTL[EF_ENA,EF_CNT] should be programmed + * properly. This should be done prior to the first read. + */ + + /* Clear any residual ECC errors */ + int num_tads = 1; + int tad; + int num_mcis = 1; + int mci; + + if (octeon_is_cpuid(OCTEON_CN78XX)) { + num_tads = 8; + num_mcis = 4; + } else if (octeon_is_cpuid(OCTEON_CN70XX)) { + num_tads = 1; + num_mcis = 1; + } else if (octeon_is_cpuid(OCTEON_CN73XX) || + octeon_is_cpuid(OCTEON_CNF75XX)) { + num_tads = 4; + num_mcis = 3; + } + + lmc_wr(priv, CVMX_LMCX_INT(if_num), -1ULL); + lmc_rd(priv, CVMX_LMCX_INT(if_num)); + + for (tad = 0; tad < num_tads; tad++) { + l2c_wr(priv, CVMX_L2C_TADX_INT_REL(tad), + l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad))); + debug("%-45s : (%d) 0x%08llx\n", "CVMX_L2C_TAD_INT", tad, + l2c_rd(priv, CVMX_L2C_TADX_INT_REL(tad))); + } + + for (mci = 0; mci < num_mcis; mci++) { + l2c_wr(priv, CVMX_L2C_MCIX_INT_REL(mci), + l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci))); + debug("%-45s : (%d) 0x%08llx\n", "L2C_MCI_INT", mci, + l2c_rd(priv, CVMX_L2C_MCIX_INT_REL(mci))); + } + + debug("%-45s : 0x%08llx\n", "LMC_INT", + lmc_rd(priv, CVMX_LMCX_INT(if_num))); +} + +static void lmc_scrambling(struct ddr_priv *priv) +{ + // Make sure scrambling is disabled during init... + union cvmx_lmcx_control ctrl; + union cvmx_lmcx_scramble_cfg0 lmc_scramble_cfg0; + union cvmx_lmcx_scramble_cfg1 lmc_scramble_cfg1; + union cvmx_lmcx_scramble_cfg2 lmc_scramble_cfg2; + union cvmx_lmcx_ns_ctl lmc_ns_ctl; + int use_scramble = 0; // default OFF + char *s; + + ctrl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + lmc_scramble_cfg0.u64 = lmc_rd(priv, CVMX_LMCX_SCRAMBLE_CFG0(if_num)); + lmc_scramble_cfg1.u64 = lmc_rd(priv, CVMX_LMCX_SCRAMBLE_CFG1(if_num)); + lmc_scramble_cfg2.u64 = 0; // quiet compiler + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) { + lmc_scramble_cfg2.u64 = + lmc_rd(priv, CVMX_LMCX_SCRAMBLE_CFG2(if_num)); + } + lmc_ns_ctl.u64 = lmc_rd(priv, CVMX_LMCX_NS_CTL(if_num)); + + s = lookup_env_ull(priv, "ddr_use_scramble"); + if (s) + use_scramble = simple_strtoull(s, NULL, 0); + + /* Generate random values if scrambling is needed */ + if (use_scramble) { + lmc_scramble_cfg0.u64 = cvmx_rng_get_random64(); + lmc_scramble_cfg1.u64 = cvmx_rng_get_random64(); + lmc_scramble_cfg2.u64 = cvmx_rng_get_random64(); + lmc_ns_ctl.s.ns_scramble_dis = 0; + lmc_ns_ctl.s.adr_offset = 0; + ctrl.s.scramble_ena = 1; + } + + s = lookup_env_ull(priv, "ddr_scramble_cfg0"); + if (s) { + lmc_scramble_cfg0.u64 = simple_strtoull(s, NULL, 0); + ctrl.s.scramble_ena = 1; + } + debug("%-45s : 0x%016llx\n", "LMC_SCRAMBLE_CFG0", + lmc_scramble_cfg0.u64); + + lmc_wr(priv, CVMX_LMCX_SCRAMBLE_CFG0(if_num), lmc_scramble_cfg0.u64); + + s = lookup_env_ull(priv, "ddr_scramble_cfg1"); + if (s) { + lmc_scramble_cfg1.u64 = simple_strtoull(s, NULL, 0); + ctrl.s.scramble_ena = 1; + } + debug("%-45s : 0x%016llx\n", "LMC_SCRAMBLE_CFG1", + lmc_scramble_cfg1.u64); + lmc_wr(priv, CVMX_LMCX_SCRAMBLE_CFG1(if_num), lmc_scramble_cfg1.u64); + + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) { + s = lookup_env_ull(priv, "ddr_scramble_cfg2"); + if (s) { + lmc_scramble_cfg2.u64 = simple_strtoull(s, NULL, 0); + ctrl.s.scramble_ena = 1; + } + debug("%-45s : 0x%016llx\n", "LMC_SCRAMBLE_CFG2", + lmc_scramble_cfg1.u64); + lmc_wr(priv, CVMX_LMCX_SCRAMBLE_CFG2(if_num), + lmc_scramble_cfg2.u64); + } + + s = lookup_env_ull(priv, "ddr_ns_ctl"); + if (s) + lmc_ns_ctl.u64 = simple_strtoull(s, NULL, 0); + debug("%-45s : 0x%016llx\n", "LMC_NS_CTL", lmc_ns_ctl.u64); + lmc_wr(priv, CVMX_LMCX_NS_CTL(if_num), lmc_ns_ctl.u64); + + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctrl.u64); +} + +struct rl_score { + u64 setting; + int score; +}; + +static union cvmx_lmcx_rlevel_rankx rl_rank __section(".data"); +static union cvmx_lmcx_rlevel_ctl rl_ctl __section(".data"); +static unsigned char rodt_ctl __section(".data"); + +static int rl_rodt_err __section(".data"); +static unsigned char rtt_nom __section(".data"); +static unsigned char rtt_idx __section(".data"); +static char min_rtt_nom_idx __section(".data"); +static char max_rtt_nom_idx __section(".data"); +static char min_rodt_ctl __section(".data"); +static char max_rodt_ctl __section(".data"); +static int rl_dbg_loops __section(".data"); +static unsigned char save_ddr2t __section(".data"); +static int rl_samples __section(".data"); +static char rl_compute __section(".data"); +static char saved_ddr__ptune __section(".data"); +static char saved_ddr__ntune __section(".data"); +static char rl_comp_offs __section(".data"); +static char saved_int_zqcs_dis __section(".data"); +static int max_adj_rl_del_inc __section(".data"); +static int print_nom_ohms __section(".data"); +static int rl_print __section(".data"); + +#ifdef ENABLE_HARDCODED_RLEVEL +static char part_number[21] __section(".data"); +#endif /* ENABLE_HARDCODED_RLEVEL */ + +struct perfect_counts { + u16 count[9][32]; // 8+ECC by 64 values + u32 mask[9]; // 8+ECC, bitmask of perfect delays +}; + +static struct perfect_counts rank_perf[4] __section(".data"); +static struct perfect_counts rodt_perfect_counts __section(".data"); +static int pbm_lowsum_limit __section(".data"); +// FIXME: PBM skip for RODT 240 and 34 +static u32 pbm_rodt_skip __section(".data"); + +// control rank majority processing +static int disable_rank_majority __section(".data"); + +// default to mask 11b ODDs for DDR4 (except 73xx), else DISABLE +// for DDR3 +static int enable_rldelay_bump __section(".data"); +static int rldelay_bump_incr __section(".data"); +static int disable_rlv_bump_this_byte __section(".data"); +static u64 value_mask __section(".data"); + +static struct rlevel_byte_data rl_byte[9] __section(".data"); +static int sample_loops __section(".data"); +static int max_samples __section(".data"); +static int rl_rank_errors __section(".data"); +static int rl_mask_err __section(".data"); +static int rl_nonseq_err __section(".data"); +static struct rlevel_bitmask rl_mask[9] __section(".data"); +static int rl_best_rank_score __section(".data"); + +static int rodt_row_skip_mask __section(".data"); + +static void rodt_loop(struct ddr_priv *priv, int rankx, struct rl_score + rl_score[RTT_NOM_OHMS_COUNT][RODT_OHMS_COUNT][4]) +{ + union cvmx_lmcx_comp_ctl2 cc2; + const int rl_separate_ab = 1; + int i; + + rl_best_rank_score = DEFAULT_BEST_RANK_SCORE; + rl_rodt_err = 0; + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + cc2.cn78xx.rodt_ctl = rodt_ctl; + lmc_wr(priv, CVMX_LMCX_COMP_CTL2(if_num), cc2.u64); + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + udelay(1); /* Give it a little time to take affect */ + if (rl_print > 1) { + debug("Read ODT_CTL : 0x%x (%d ohms)\n", + cc2.cn78xx.rodt_ctl, + imp_val->rodt_ohms[cc2.cn78xx.rodt_ctl]); + } + + memset(rl_byte, 0, sizeof(rl_byte)); + memset(&rodt_perfect_counts, 0, sizeof(rodt_perfect_counts)); + + // when iter RODT is the target RODT, take more samples... + max_samples = rl_samples; + if (rodt_ctl == default_rodt_ctl) + max_samples += rl_samples + 1; + + for (sample_loops = 0; sample_loops < max_samples; sample_loops++) { + int redoing_nonseq_errs = 0; + + rl_mask_err = 0; + + if (!(rl_separate_ab && spd_rdimm && + ddr_type == DDR4_DRAM)) { + /* Clear read-level delays */ + lmc_wr(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num), 0); + + /* read-leveling */ + oct3_ddr3_seq(priv, 1 << rankx, if_num, 1); + + do { + rl_rank.u64 = + lmc_rd(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + } while (rl_rank.cn78xx.status != 3); + } + + rl_rank.u64 = + lmc_rd(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num)); + + // start bitmask interpretation block + + memset(rl_mask, 0, sizeof(rl_mask)); + + if (rl_separate_ab && spd_rdimm && ddr_type == DDR4_DRAM) { + union cvmx_lmcx_rlevel_rankx rl_rank_aside; + union cvmx_lmcx_modereg_params0 mp0; + + /* A-side */ + mp0.u64 = + lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num)); + mp0.s.mprloc = 0; /* MPR Page 0 Location 0 */ + lmc_wr(priv, + CVMX_LMCX_MODEREG_PARAMS0(if_num), + mp0.u64); + + /* Clear read-level delays */ + lmc_wr(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num), 0); + + /* read-leveling */ + oct3_ddr3_seq(priv, 1 << rankx, if_num, 1); + + do { + rl_rank.u64 = + lmc_rd(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + } while (rl_rank.cn78xx.status != 3); + + rl_rank.u64 = + lmc_rd(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + + rl_rank_aside.u64 = rl_rank.u64; + + rl_mask[0].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 0); + rl_mask[1].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 1); + rl_mask[2].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 2); + rl_mask[3].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 3); + rl_mask[8].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 8); + /* A-side complete */ + + /* B-side */ + mp0.u64 = + lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num)); + mp0.s.mprloc = 3; /* MPR Page 0 Location 3 */ + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num), + mp0.u64); + + /* Clear read-level delays */ + lmc_wr(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num), 0); + + /* read-leveling */ + oct3_ddr3_seq(priv, 1 << rankx, if_num, 1); + + do { + rl_rank.u64 = + lmc_rd(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + } while (rl_rank.cn78xx.status != 3); + + rl_rank.u64 = + lmc_rd(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + + rl_mask[4].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 4); + rl_mask[5].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 5); + rl_mask[6].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 6); + rl_mask[7].bm = lmc_ddr3_rl_dbg_read(priv, if_num, 7); + /* B-side complete */ + + upd_rl_rank(&rl_rank, 0, rl_rank_aside.s.byte0); + upd_rl_rank(&rl_rank, 1, rl_rank_aside.s.byte1); + upd_rl_rank(&rl_rank, 2, rl_rank_aside.s.byte2); + upd_rl_rank(&rl_rank, 3, rl_rank_aside.s.byte3); + /* ECC A-side */ + upd_rl_rank(&rl_rank, 8, rl_rank_aside.s.byte8); + + mp0.u64 = + lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num)); + mp0.s.mprloc = 0; /* MPR Page 0 Location 0 */ + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS0(if_num), + mp0.u64); + } + + /* + * Evaluate the quality of the read-leveling delays from the + * bitmasks. Also save off a software computed read-leveling + * mask that may be used later to qualify the delay results + * from Octeon. + */ + for (i = 0; i < (8 + ecc_ena); ++i) { + int bmerr; + + if (!(if_bytemask & (1 << i))) + continue; + if (!(rl_separate_ab && spd_rdimm && + ddr_type == DDR4_DRAM)) { + rl_mask[i].bm = + lmc_ddr3_rl_dbg_read(priv, if_num, i); + } + bmerr = validate_ddr3_rlevel_bitmask(&rl_mask[i], + ddr_type); + rl_mask[i].errs = bmerr; + rl_mask_err += bmerr; + // count only the "perfect" bitmasks + if (ddr_type == DDR4_DRAM && !bmerr) { + int delay; + // FIXME: for now, simple filtering: + // do NOT count PBMs for RODTs in skip mask + if ((1U << rodt_ctl) & pbm_rodt_skip) + continue; + // FIXME: could optimize this a bit? + delay = get_rl_rank(&rl_rank, i); + rank_perf[rankx].count[i][delay] += 1; + rank_perf[rankx].mask[i] |= + (1ULL << delay); + rodt_perfect_counts.count[i][delay] += 1; + rodt_perfect_counts.mask[i] |= (1ULL << delay); + } + } + + /* Set delays for unused bytes to match byte 0. */ + for (i = 0; i < 9; ++i) { + if (if_bytemask & (1 << i)) + continue; + upd_rl_rank(&rl_rank, i, rl_rank.s.byte0); + } + + /* + * Save a copy of the byte delays in physical + * order for sequential evaluation. + */ + unpack_rlevel_settings(if_bytemask, ecc_ena, rl_byte, rl_rank); + + redo_nonseq_errs: + + rl_nonseq_err = 0; + if (!disable_sequential_delay_check) { + for (i = 0; i < 9; ++i) + rl_byte[i].sqerrs = 0; + + if ((if_bytemask & 0xff) == 0xff) { + /* + * Evaluate delay sequence across the whole + * range of bytes for standard dimms. + */ + /* 1=RDIMM, 5=Mini-RDIMM */ + if (spd_dimm_type == 1 || spd_dimm_type == 5) { + int reg_adj_del = abs(rl_byte[4].delay - + rl_byte[5].delay); + + /* + * Registered dimm topology routes + * from the center. + */ + rl_nonseq_err += + nonseq_del(rl_byte, 0, + 3 + ecc_ena, + max_adj_rl_del_inc); + rl_nonseq_err += + nonseq_del(rl_byte, 5, + 7 + ecc_ena, + max_adj_rl_del_inc); + // byte 5 sqerrs never gets cleared + // for RDIMMs + rl_byte[5].sqerrs = 0; + if (reg_adj_del > 1) { + /* + * Assess proximity of bytes on + * opposite sides of register + */ + rl_nonseq_err += (reg_adj_del - + 1) * + RLEVEL_ADJACENT_DELAY_ERROR; + // update byte 5 error + rl_byte[5].sqerrs += + (reg_adj_del - 1) * + RLEVEL_ADJACENT_DELAY_ERROR; + } + } + + /* 2=UDIMM, 6=Mini-UDIMM */ + if (spd_dimm_type == 2 || spd_dimm_type == 6) { + /* + * Unbuffered dimm topology routes + * from end to end. + */ + rl_nonseq_err += nonseq_del(rl_byte, 0, + 7 + ecc_ena, + max_adj_rl_del_inc); + } + } else { + rl_nonseq_err += nonseq_del(rl_byte, 0, + 3 + ecc_ena, + max_adj_rl_del_inc); + } + } /* if (! disable_sequential_delay_check) */ + + rl_rank_errors = rl_mask_err + rl_nonseq_err; + + // print original sample here only if we are not really + // averaging or picking best + // also do not print if we were redoing the NONSEQ score + // for using COMPUTED + if (!redoing_nonseq_errs && rl_samples < 2) { + if (rl_print > 1) { + display_rl_bm(if_num, rankx, rl_mask, ecc_ena); + display_rl_bm_scores(if_num, rankx, rl_mask, + ecc_ena); + display_rl_seq_scores(if_num, rankx, rl_byte, + ecc_ena); + } + display_rl_with_score(if_num, rl_rank, rankx, + rl_rank_errors); + } + + if (rl_compute) { + if (!redoing_nonseq_errs) { + /* Recompute the delays based on the bitmask */ + for (i = 0; i < (8 + ecc_ena); ++i) { + if (!(if_bytemask & (1 << i))) + continue; + + upd_rl_rank(&rl_rank, i, + compute_ddr3_rlevel_delay( + rl_mask[i].mstart, + rl_mask[i].width, + rl_ctl)); + } + + /* + * Override the copy of byte delays with the + * computed results. + */ + unpack_rlevel_settings(if_bytemask, ecc_ena, + rl_byte, rl_rank); + + redoing_nonseq_errs = 1; + goto redo_nonseq_errs; + + } else { + /* + * now print this if already printed the + * original sample + */ + if (rl_samples < 2 || rl_print) { + display_rl_with_computed(if_num, + rl_rank, rankx, + rl_rank_errors); + } + } + } /* if (rl_compute) */ + + // end bitmask interpretation block + + // if it is a better (lower) score, then keep it + if (rl_rank_errors < rl_best_rank_score) { + rl_best_rank_score = rl_rank_errors; + + // save the new best delays and best errors + for (i = 0; i < (8 + ecc_ena); ++i) { + rl_byte[i].best = rl_byte[i].delay; + rl_byte[i].bestsq = rl_byte[i].sqerrs; + // save bitmasks and their scores as well + // xlate UNPACKED index to PACKED index to + // get from rl_mask + rl_byte[i].bm = rl_mask[XUP(i, !!ecc_ena)].bm; + rl_byte[i].bmerrs = + rl_mask[XUP(i, !!ecc_ena)].errs; + } + } + + rl_rodt_err += rl_rank_errors; + } + + /* We recorded the best score across the averaging loops */ + rl_score[rtt_nom][rodt_ctl][rankx].score = rl_best_rank_score; + + /* + * Restore the delays from the best fields that go with the best + * score + */ + for (i = 0; i < 9; ++i) { + rl_byte[i].delay = rl_byte[i].best; + rl_byte[i].sqerrs = rl_byte[i].bestsq; + } + + rl_rank.u64 = lmc_rd(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num)); + + pack_rlevel_settings(if_bytemask, ecc_ena, rl_byte, &rl_rank); + + if (rl_samples > 1) { + // restore the "best" bitmasks and their scores for printing + for (i = 0; i < 9; ++i) { + if ((if_bytemask & (1 << i)) == 0) + continue; + // xlate PACKED index to UNPACKED index to get from + // rl_byte + rl_mask[i].bm = rl_byte[XPU(i, !!ecc_ena)].bm; + rl_mask[i].errs = rl_byte[XPU(i, !!ecc_ena)].bmerrs; + } + + // maybe print bitmasks/scores here + if (rl_print > 1) { + display_rl_bm(if_num, rankx, rl_mask, ecc_ena); + display_rl_bm_scores(if_num, rankx, rl_mask, ecc_ena); + display_rl_seq_scores(if_num, rankx, rl_byte, ecc_ena); + + display_rl_with_rodt(if_num, rl_rank, rankx, + rl_score[rtt_nom][rodt_ctl][rankx].score, + print_nom_ohms, + imp_val->rodt_ohms[rodt_ctl], + WITH_RODT_BESTSCORE); + + debug("-----------\n"); + } + } + + rl_score[rtt_nom][rodt_ctl][rankx].setting = rl_rank.u64; + + // print out the PBMs for the current RODT + if (ddr_type == DDR4_DRAM && rl_print > 1) { // verbosity? + // FIXME: change verbosity level after debug complete... + + for (i = 0; i < 9; i++) { + u64 temp_mask; + int num_values; + + // FIXME: PBM skip for RODTs in mask + if ((1U << rodt_ctl) & pbm_rodt_skip) + continue; + + temp_mask = rodt_perfect_counts.mask[i]; + num_values = __builtin_popcountll(temp_mask); + i = __builtin_ffsll(temp_mask) - 1; + + debug("N%d.LMC%d.R%d: PERFECT: RODT %3d: Byte %d: mask 0x%02llx (%d): ", + node, if_num, rankx, + imp_val->rodt_ohms[rodt_ctl], + i, temp_mask >> i, num_values); + + while (temp_mask != 0) { + i = __builtin_ffsll(temp_mask) - 1; + debug("%2d(%2d) ", i, + rodt_perfect_counts.count[i][i]); + temp_mask &= ~(1UL << i); + } /* while (temp_mask != 0) */ + debug("\n"); + } + } +} + +static void rank_major_loop(struct ddr_priv *priv, int rankx, struct rl_score + rl_score[RTT_NOM_OHMS_COUNT][RODT_OHMS_COUNT][4]) +{ + /* Start with an arbitrarily high score */ + int best_rank_score = DEFAULT_BEST_RANK_SCORE; + int best_rank_rtt_nom = 0; + int best_rank_ctl = 0; + int best_rank_ohms = 0; + int best_rankx = 0; + int dimm_rank_mask; + int max_rank_score; + union cvmx_lmcx_rlevel_rankx saved_rl_rank; + int next_ohms; + int orankx; + int next_score = 0; + int best_byte, new_byte, temp_byte, orig_best_byte; + int rank_best_bytes[9]; + int byte_sh; + int avg_byte; + int avg_diff; + int i; + + if (!(rank_mask & (1 << rankx))) + return; + + // some of the rank-related loops below need to operate only on + // the ranks of a single DIMM, + // so create a mask for their use here + if (num_ranks == 4) { + dimm_rank_mask = rank_mask; // should be 1111 + } else { + dimm_rank_mask = rank_mask & 3; // should be 01 or 11 + if (rankx >= 2) { + // doing a rank on the second DIMM, should be + // 0100 or 1100 + dimm_rank_mask <<= 2; + } + } + debug("DIMM rank mask: 0x%x, rank mask: 0x%x, rankx: %d\n", + dimm_rank_mask, rank_mask, rankx); + + // this is the start of the BEST ROW SCORE LOOP + + for (rtt_idx = min_rtt_nom_idx; rtt_idx <= max_rtt_nom_idx; ++rtt_idx) { + rtt_nom = imp_val->rtt_nom_table[rtt_idx]; + + debug("N%d.LMC%d.R%d: starting RTT_NOM %d (%d)\n", + node, if_num, rankx, rtt_nom, + imp_val->rtt_nom_ohms[rtt_nom]); + + for (rodt_ctl = max_rodt_ctl; rodt_ctl >= min_rodt_ctl; + --rodt_ctl) { + next_ohms = imp_val->rodt_ohms[rodt_ctl]; + + // skip RODT rows in mask, but *NOT* rows with too + // high a score; + // we will not use the skipped ones for printing or + // evaluating, but we need to allow all the + // non-skipped ones to be candidates for "best" + if (((1 << rodt_ctl) & rodt_row_skip_mask) != 0) { + debug("N%d.LMC%d.R%d: SKIPPING rodt:%d (%d) with rank_score:%d\n", + node, if_num, rankx, rodt_ctl, + next_ohms, next_score); + continue; + } + + // this is ROFFIX-0528 + for (orankx = 0; orankx < dimm_count * 4; orankx++) { + // stay on the same DIMM + if (!(dimm_rank_mask & (1 << orankx))) + continue; + + next_score = rl_score[rtt_nom][rodt_ctl][orankx].score; + + // always skip a higher score + if (next_score > best_rank_score) + continue; + + // if scores are equal + if (next_score == best_rank_score) { + // always skip lower ohms + if (next_ohms < best_rank_ohms) + continue; + + // if same ohms + if (next_ohms == best_rank_ohms) { + // always skip the other rank(s) + if (orankx != rankx) + continue; + } + // else next_ohms are greater, + // always choose it + } + // else next_score is less than current best, + // so always choose it + debug("N%d.LMC%d.R%d: new best score: rank %d, rodt %d(%3d), new best %d, previous best %d(%d)\n", + node, if_num, rankx, orankx, rodt_ctl, next_ohms, next_score, + best_rank_score, best_rank_ohms); + best_rank_score = next_score; + best_rank_rtt_nom = rtt_nom; + //best_rank_nom_ohms = rtt_nom_ohms; + best_rank_ctl = rodt_ctl; + best_rank_ohms = next_ohms; + best_rankx = orankx; + rl_rank.u64 = + rl_score[rtt_nom][rodt_ctl][orankx].setting; + } + } + } + + // this is the end of the BEST ROW SCORE LOOP + + // DANGER, Will Robinson!! Abort now if we did not find a best + // score at all... + if (best_rank_score == DEFAULT_BEST_RANK_SCORE) { + printf("N%d.LMC%d.R%d: WARNING: no best rank score found - resetting node...\n", + node, if_num, rankx); + mdelay(500); + do_reset(NULL, 0, 0, NULL); + } + + // FIXME: relative now, but still arbitrary... + max_rank_score = best_rank_score; + if (ddr_type == DDR4_DRAM) { + // halve the range if 2 DIMMs unless they are single rank... + max_rank_score += (MAX_RANK_SCORE_LIMIT / ((num_ranks > 1) ? + dimm_count : 1)); + } else { + // Since DDR3 typically has a wider score range, + // keep more of them always + max_rank_score += MAX_RANK_SCORE_LIMIT; + } + + if (!ecc_ena) { + /* ECC is not used */ + rl_rank.s.byte8 = rl_rank.s.byte0; + } + + // at the end, write the best row settings to the current rank + lmc_wr(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num), rl_rank.u64); + rl_rank.u64 = lmc_rd(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num)); + + saved_rl_rank.u64 = rl_rank.u64; + + // this is the start of the PRINT LOOP + int pass; + + // for pass==0, print current rank, pass==1 print other rank(s) + // this is done because we want to show each ranks RODT values + // together, not interlaced + // keep separates for ranks - pass=0 target rank, pass=1 other + // rank on DIMM + int mask_skipped[2] = {0, 0}; + int score_skipped[2] = {0, 0}; + int selected_rows[2] = {0, 0}; + int zero_scores[2] = {0, 0}; + for (pass = 0; pass < 2; pass++) { + for (orankx = 0; orankx < dimm_count * 4; orankx++) { + // stay on the same DIMM + if (!(dimm_rank_mask & (1 << orankx))) + continue; + + if ((pass == 0 && orankx != rankx) || + (pass != 0 && orankx == rankx)) + continue; + + for (rtt_idx = min_rtt_nom_idx; + rtt_idx <= max_rtt_nom_idx; ++rtt_idx) { + rtt_nom = imp_val->rtt_nom_table[rtt_idx]; + if (dyn_rtt_nom_mask == 0) { + print_nom_ohms = -1; + } else { + print_nom_ohms = + imp_val->rtt_nom_ohms[rtt_nom]; + } + + // cycle through all the RODT values... + for (rodt_ctl = max_rodt_ctl; + rodt_ctl >= min_rodt_ctl; --rodt_ctl) { + union cvmx_lmcx_rlevel_rankx + temp_rl_rank; + int temp_score = + rl_score[rtt_nom][rodt_ctl][orankx].score; + int skip_row; + + temp_rl_rank.u64 = + rl_score[rtt_nom][rodt_ctl][orankx].setting; + + // skip RODT rows in mask, or rows + // with too high a score; + // we will not use them for printing + // or evaluating... + if ((1 << rodt_ctl) & + rodt_row_skip_mask) { + skip_row = WITH_RODT_SKIPPING; + ++mask_skipped[pass]; + } else if (temp_score > + max_rank_score) { + skip_row = WITH_RODT_SKIPPING; + ++score_skipped[pass]; + } else { + skip_row = WITH_RODT_BLANK; + ++selected_rows[pass]; + if (temp_score == 0) + ++zero_scores[pass]; + } + + // identify and print the BEST ROW + // when it comes up + if (skip_row == WITH_RODT_BLANK && + best_rankx == orankx && + best_rank_rtt_nom == rtt_nom && + best_rank_ctl == rodt_ctl) + skip_row = WITH_RODT_BESTROW; + + if (rl_print) { + display_rl_with_rodt(if_num, + temp_rl_rank, orankx, temp_score, + print_nom_ohms, + imp_val->rodt_ohms[rodt_ctl], + skip_row); + } + } + } + } + } + debug("N%d.LMC%d.R%d: RLROWS: selected %d+%d, zero_scores %d+%d, mask_skipped %d+%d, score_skipped %d+%d\n", + node, if_num, rankx, selected_rows[0], selected_rows[1], + zero_scores[0], zero_scores[1], mask_skipped[0], mask_skipped[1], + score_skipped[0], score_skipped[1]); + // this is the end of the PRINT LOOP + + // now evaluate which bytes need adjusting + // collect the new byte values; first init with current best for + // neighbor use + for (i = 0, byte_sh = 0; i < 8 + ecc_ena; i++, byte_sh += 6) { + rank_best_bytes[i] = (int)(rl_rank.u64 >> byte_sh) & + RLEVEL_BYTE_MSK; + } + + // this is the start of the BEST BYTE LOOP + + for (i = 0, byte_sh = 0; i < 8 + ecc_ena; i++, byte_sh += 6) { + int sum = 0, count = 0; + int count_less = 0, count_same = 0, count_more = 0; + int count_byte; // save the value we counted around + // for rank majority use + int rank_less = 0, rank_same = 0, rank_more = 0; + int neighbor; + int neigh_byte; + + best_byte = rank_best_bytes[i]; + orig_best_byte = rank_best_bytes[i]; + + // this is the start of the BEST BYTE AVERAGING LOOP + + // validate the initial "best" byte by looking at the + // average of the unskipped byte-column entries + // we want to do this before we go further, so we can + // try to start with a better initial value + // this is the so-called "BESTBUY" patch set + + for (rtt_idx = min_rtt_nom_idx; rtt_idx <= max_rtt_nom_idx; + ++rtt_idx) { + rtt_nom = imp_val->rtt_nom_table[rtt_idx]; + + for (rodt_ctl = max_rodt_ctl; rodt_ctl >= min_rodt_ctl; + --rodt_ctl) { + union cvmx_lmcx_rlevel_rankx temp_rl_rank; + int temp_score; + + // average over all the ranks + for (orankx = 0; orankx < dimm_count * 4; + orankx++) { + // stay on the same DIMM + if (!(dimm_rank_mask & (1 << orankx))) + continue; + + temp_score = + rl_score[rtt_nom][rodt_ctl][orankx].score; + // skip RODT rows in mask, or rows with + // too high a score; + // we will not use them for printing or + // evaluating... + + if (!((1 << rodt_ctl) & + rodt_row_skip_mask) && + temp_score <= max_rank_score) { + temp_rl_rank.u64 = + rl_score[rtt_nom][rodt_ctl][orankx].setting; + temp_byte = + (int)(temp_rl_rank.u64 >> byte_sh) & + RLEVEL_BYTE_MSK; + sum += temp_byte; + count++; + } + } + } + } + + // this is the end of the BEST BYTE AVERAGING LOOP + + // FIXME: validate count and sum?? + avg_byte = (int)divide_nint(sum, count); + avg_diff = best_byte - avg_byte; + new_byte = best_byte; + if (avg_diff != 0) { + // bump best up/dn by 1, not necessarily all the + // way to avg + new_byte = best_byte + ((avg_diff > 0) ? -1 : 1); + } + + if (rl_print) { + debug("N%d.LMC%d.R%d: START: Byte %d: best %d is different by %d from average %d, using %d.\n", + node, if_num, rankx, + i, best_byte, avg_diff, avg_byte, new_byte); + } + best_byte = new_byte; + count_byte = new_byte; // save the value we will count around + + // At this point best_byte is either: + // 1. the original byte-column value from the best scoring + // RODT row, OR + // 2. that value bumped toward the average of all the + // byte-column values + // + // best_byte will not change from here on... + + // this is the start of the BEST BYTE COUNTING LOOP + + // NOTE: we do this next loop separately from above, because + // we count relative to "best_byte" + // which may have been modified by the above averaging + // operation... + + for (rtt_idx = min_rtt_nom_idx; rtt_idx <= max_rtt_nom_idx; + ++rtt_idx) { + rtt_nom = imp_val->rtt_nom_table[rtt_idx]; + + for (rodt_ctl = max_rodt_ctl; rodt_ctl >= min_rodt_ctl; + --rodt_ctl) { + union cvmx_lmcx_rlevel_rankx temp_rl_rank; + int temp_score; + + for (orankx = 0; orankx < dimm_count * 4; + orankx++) { // count over all the ranks + // stay on the same DIMM + if (!(dimm_rank_mask & (1 << orankx))) + continue; + + temp_score = + rl_score[rtt_nom][rodt_ctl][orankx].score; + // skip RODT rows in mask, or rows + // with too high a score; + // we will not use them for printing + // or evaluating... + if (((1 << rodt_ctl) & + rodt_row_skip_mask) || + temp_score > max_rank_score) + continue; + + temp_rl_rank.u64 = + rl_score[rtt_nom][rodt_ctl][orankx].setting; + temp_byte = (temp_rl_rank.u64 >> + byte_sh) & RLEVEL_BYTE_MSK; + + if (temp_byte == 0) + ; // do not count it if illegal + else if (temp_byte == best_byte) + count_same++; + else if (temp_byte == best_byte - 1) + count_less++; + else if (temp_byte == best_byte + 1) + count_more++; + // else do not count anything more + // than 1 away from the best + + // no rank counting if disabled + if (disable_rank_majority) + continue; + + // FIXME? count is relative to + // best_byte; should it be rank-based? + // rank counts only on main rank + if (orankx != rankx) + continue; + else if (temp_byte == best_byte) + rank_same++; + else if (temp_byte == best_byte - 1) + rank_less++; + else if (temp_byte == best_byte + 1) + rank_more++; + } + } + } + + if (rl_print) { + debug("N%d.LMC%d.R%d: COUNT: Byte %d: orig %d now %d, more %d same %d less %d (%d/%d/%d)\n", + node, if_num, rankx, + i, orig_best_byte, best_byte, + count_more, count_same, count_less, + rank_more, rank_same, rank_less); + } + + // this is the end of the BEST BYTE COUNTING LOOP + + // choose the new byte value + // we need to check that there is no gap greater than 2 + // between adjacent bytes (adjacency depends on DIMM type) + // use the neighbor value to help decide + // initially, the rank_best_bytes[] will contain values from + // the chosen lowest score rank + new_byte = 0; + + // neighbor is index-1 unless we are index 0 or index 8 (ECC) + neighbor = (i == 8) ? 3 : ((i == 0) ? 1 : i - 1); + neigh_byte = rank_best_bytes[neighbor]; + + // can go up or down or stay the same, so look at a numeric + // average to help + new_byte = (int)divide_nint(((count_more * (best_byte + 1)) + + (count_same * (best_byte + 0)) + + (count_less * (best_byte - 1))), + max(1, (count_more + count_same + + count_less))); + + // use neighbor to help choose with average + if (i > 0 && (abs(neigh_byte - new_byte) > 2) && + !disable_sequential_delay_check) { + // but not for byte 0 + int avg_pick = new_byte; + + if ((new_byte - best_byte) != 0) { + // back to best, average did not get better + new_byte = best_byte; + } else { + // avg was the same, still too far, now move + // it towards the neighbor + new_byte += (neigh_byte > new_byte) ? 1 : -1; + } + + if (rl_print) { + debug("N%d.LMC%d.R%d: AVERAGE: Byte %d: neighbor %d too different %d from average %d, picking %d.\n", + node, if_num, rankx, + i, neighbor, neigh_byte, avg_pick, + new_byte); + } + } else { + // NOTE: + // For now, we let the neighbor processing above trump + // the new simple majority processing here. + // This is mostly because we have seen no smoking gun + // for a neighbor bad choice (yet?). + // Also note that we will ALWAYS be using byte 0 + // majority, because of the if clause above. + + // majority is dependent on the counts, which are + // relative to best_byte, so start there + int maj_byte = best_byte; + int rank_maj; + int rank_sum; + + if (count_more > count_same && + count_more > count_less) { + maj_byte++; + } else if (count_less > count_same && + count_less > count_more) { + maj_byte--; + } + + if (maj_byte != new_byte) { + // print only when majority choice is + // different from average + if (rl_print) { + debug("N%d.LMC%d.R%d: MAJORTY: Byte %d: picking majority of %d over average %d.\n", + node, if_num, rankx, i, maj_byte, + new_byte); + } + new_byte = maj_byte; + } else { + if (rl_print) { + debug("N%d.LMC%d.R%d: AVERAGE: Byte %d: picking average of %d.\n", + node, if_num, rankx, i, new_byte); + } + } + + if (!disable_rank_majority) { + // rank majority is dependent on the rank + // counts, which are relative to best_byte, + // so start there, and adjust according to the + // rank counts majority + rank_maj = best_byte; + if (rank_more > rank_same && + rank_more > rank_less) { + rank_maj++; + } else if (rank_less > rank_same && + rank_less > rank_more) { + rank_maj--; + } + rank_sum = rank_more + rank_same + rank_less; + + // now, let rank majority possibly rule over + // the current new_byte however we got it + if (rank_maj != new_byte) { // only if different + // Here is where we decide whether to + // completely apply RANK_MAJORITY or not + // ignore if less than + if (rank_maj < new_byte) { + if (rl_print) { + debug("N%d.LMC%d.R%d: RANKMAJ: Byte %d: LESS: NOT using %d over %d.\n", + node, if_num, + rankx, i, + rank_maj, + new_byte); + } + } else { + // For the moment, we do it + // ONLY when running 2-slot + // configs + // OR when rank_sum is big + // enough + if (dimm_count > 1 || + rank_sum > 2) { + // print only when rank + // majority choice is + // selected + if (rl_print) { + debug("N%d.LMC%d.R%d: RANKMAJ: Byte %d: picking %d over %d.\n", + node, + if_num, + rankx, + i, + rank_maj, + new_byte); + } + new_byte = rank_maj; + } else { + // FIXME: print some + // info when we could + // have chosen RANKMAJ + // but did not + if (rl_print) { + debug("N%d.LMC%d.R%d: RANKMAJ: Byte %d: NOT using %d over %d (best=%d,sum=%d).\n", + node, + if_num, + rankx, + i, + rank_maj, + new_byte, + best_byte, + rank_sum); + } + } + } + } + } /* if (!disable_rank_majority) */ + } + // one last check: + // if new_byte is still count_byte, BUT there was no count + // for that value, DO SOMETHING!!! + // FIXME: go back to original best byte from the best row + if (new_byte == count_byte && count_same == 0) { + new_byte = orig_best_byte; + if (rl_print) { + debug("N%d.LMC%d.R%d: FAILSAF: Byte %d: going back to original %d.\n", + node, if_num, rankx, i, new_byte); + } + } + // Look at counts for "perfect" bitmasks (PBMs) if we had + // any for this byte-lane. + // Remember, we only counted for DDR4, so zero means none + // or DDR3, and we bypass this... + value_mask = rank_perf[rankx].mask[i]; + disable_rlv_bump_this_byte = 0; + + if (value_mask != 0 && rl_ctl.cn78xx.offset == 1) { + int i, delay_count, delay_max = 0, del_val = 0; + int num_values = __builtin_popcountll(value_mask); + int sum_counts = 0; + u64 temp_mask = value_mask; + + disable_rlv_bump_this_byte = 1; + i = __builtin_ffsll(temp_mask) - 1; + if (rl_print) + debug("N%d.LMC%d.R%d: PERFECT: Byte %d: OFF1: mask 0x%02llx (%d): ", + node, if_num, rankx, i, value_mask >> i, + num_values); + + while (temp_mask != 0) { + i = __builtin_ffsll(temp_mask) - 1; + delay_count = rank_perf[rankx].count[i][i]; + sum_counts += delay_count; + if (rl_print) + debug("%2d(%2d) ", i, delay_count); + if (delay_count >= delay_max) { + delay_max = delay_count; + del_val = i; + } + temp_mask &= ~(1UL << i); + } /* while (temp_mask != 0) */ + + // if sum_counts is small, just use NEW_BYTE + if (sum_counts < pbm_lowsum_limit) { + if (rl_print) + debug(": LOWSUM (%2d), choose ORIG ", + sum_counts); + del_val = new_byte; + delay_max = rank_perf[rankx].count[i][del_val]; + } + + // finish printing here... + if (rl_print) { + debug(": USING %2d (%2d) D%d\n", del_val, + delay_max, disable_rlv_bump_this_byte); + } + + new_byte = del_val; // override with best PBM choice + + } else if ((value_mask != 0) && (rl_ctl.cn78xx.offset == 2)) { + // if (value_mask != 0) { + int i, delay_count, del_val; + int num_values = __builtin_popcountll(value_mask); + int sum_counts = 0; + u64 temp_mask = value_mask; + + i = __builtin_ffsll(temp_mask) - 1; + if (rl_print) + debug("N%d.LMC%d.R%d: PERFECT: Byte %d: mask 0x%02llx (%d): ", + node, if_num, rankx, i, value_mask >> i, + num_values); + while (temp_mask != 0) { + i = __builtin_ffsll(temp_mask) - 1; + delay_count = rank_perf[rankx].count[i][i]; + sum_counts += delay_count; + if (rl_print) + debug("%2d(%2d) ", i, delay_count); + temp_mask &= ~(1UL << i); + } /* while (temp_mask != 0) */ + + del_val = __builtin_ffsll(value_mask) - 1; + delay_count = + rank_perf[rankx].count[i][del_val]; + + // overkill, normally only 1-4 bits + i = (value_mask >> del_val) & 0x1F; + + // if sum_counts is small, treat as special and use + // NEW_BYTE + if (sum_counts < pbm_lowsum_limit) { + if (rl_print) + debug(": LOWSUM (%2d), choose ORIG", + sum_counts); + i = 99; // SPECIAL case... + } + + switch (i) { + case 0x01 /* 00001b */: + // allow BUMP + break; + + case 0x13 /* 10011b */: + case 0x0B /* 01011b */: + case 0x03 /* 00011b */: + del_val += 1; // take the second + disable_rlv_bump_this_byte = 1; // allow no BUMP + break; + + case 0x0D /* 01101b */: + case 0x05 /* 00101b */: + // test count of lowest and all + if (delay_count >= 5 || sum_counts <= 5) + del_val += 1; // take the hole + else + del_val += 2; // take the next set + disable_rlv_bump_this_byte = 1; // allow no BUMP + break; + + case 0x0F /* 01111b */: + case 0x17 /* 10111b */: + case 0x07 /* 00111b */: + del_val += 1; // take the second + if (delay_count < 5) { // lowest count is small + int second = + rank_perf[rankx].count[i][del_val]; + int third = + rank_perf[rankx].count[i][del_val + 1]; + // test if middle is more than 1 OR + // top is more than 1; + // this means if they are BOTH 1, + // then we keep the second... + if (second > 1 || third > 1) { + // if middle is small OR top + // is large + if (second < 5 || + third > 1) { + // take the top + del_val += 1; + if (rl_print) + debug(": TOP7 "); + } + } + } + disable_rlv_bump_this_byte = 1; // allow no BUMP + break; + + default: // all others... + if (rl_print) + debug(": ABNORMAL, choose ORIG"); + + case 99: // special + // FIXME: choose original choice? + del_val = new_byte; + disable_rlv_bump_this_byte = 1; // allow no BUMP + break; + } + delay_count = + rank_perf[rankx].count[i][del_val]; + + // finish printing here... + if (rl_print) + debug(": USING %2d (%2d) D%d\n", del_val, + delay_count, disable_rlv_bump_this_byte); + new_byte = del_val; // override with best PBM choice + } else { + if (ddr_type == DDR4_DRAM) { // only report when DDR4 + // FIXME: remove or increase VBL for this + // output... + if (rl_print) + debug("N%d.LMC%d.R%d: PERFECT: Byte %d: ZERO PBMs, USING %d\n", + node, if_num, rankx, i, + new_byte); + // prevent ODD bump, rely on original + disable_rlv_bump_this_byte = 1; + } + } /* if (value_mask != 0) */ + + // optionally bump the delay value + if (enable_rldelay_bump && !disable_rlv_bump_this_byte) { + if ((new_byte & enable_rldelay_bump) == + enable_rldelay_bump) { + int bump_value = new_byte + rldelay_bump_incr; + + if (rl_print) { + debug("N%d.LMC%d.R%d: RLVBUMP: Byte %d: CHANGING %d to %d (%s)\n", + node, if_num, rankx, i, + new_byte, bump_value, + (value_mask & + (1 << bump_value)) ? + "PBM" : "NOPBM"); + } + new_byte = bump_value; + } + } + + // last checks for count-related purposes + if (new_byte == best_byte && count_more > 0 && + count_less == 0) { + // we really should take best_byte + 1 + if (rl_print) { + debug("N%d.LMC%d.R%d: CADJMOR: Byte %d: CHANGING %d to %d\n", + node, if_num, rankx, i, + new_byte, best_byte + 1); + new_byte = best_byte + 1; + } + } else if ((new_byte < best_byte) && (count_same > 0)) { + // we really should take best_byte + if (rl_print) { + debug("N%d.LMC%d.R%d: CADJSAM: Byte %d: CHANGING %d to %d\n", + node, if_num, rankx, i, + new_byte, best_byte); + new_byte = best_byte; + } + } else if (new_byte > best_byte) { + if ((new_byte == (best_byte + 1)) && + count_more == 0 && count_less > 0) { + // we really should take best_byte + if (rl_print) { + debug("N%d.LMC%d.R%d: CADJLE1: Byte %d: CHANGING %d to %d\n", + node, if_num, rankx, i, + new_byte, best_byte); + new_byte = best_byte; + } + } else if ((new_byte >= (best_byte + 2)) && + ((count_more > 0) || (count_same > 0))) { + if (rl_print) { + debug("N%d.LMC%d.R%d: CADJLE2: Byte %d: CHANGING %d to %d\n", + node, if_num, rankx, i, + new_byte, best_byte + 1); + new_byte = best_byte + 1; + } + } + } + + if (rl_print) { + debug("N%d.LMC%d.R%d: SUMMARY: Byte %d: orig %d now %d, more %d same %d less %d, using %d\n", + node, if_num, rankx, i, orig_best_byte, + best_byte, count_more, count_same, count_less, + new_byte); + } + + // update the byte with the new value (NOTE: orig value in + // the CSR may not be current "best") + upd_rl_rank(&rl_rank, i, new_byte); + + // save new best for neighbor use + rank_best_bytes[i] = new_byte; + } /* for (i = 0; i < 8+ecc_ena; i++) */ + + ////////////////// this is the end of the BEST BYTE LOOP + + if (saved_rl_rank.u64 != rl_rank.u64) { + lmc_wr(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, if_num), + rl_rank.u64); + rl_rank.u64 = lmc_rd(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, if_num)); + debug("Adjusting Read-Leveling per-RANK settings.\n"); + } else { + debug("Not Adjusting Read-Leveling per-RANK settings.\n"); + } + display_rl_with_final(if_num, rl_rank, rankx); + + // FIXME: does this help make the output a little easier to focus? + if (rl_print > 0) + debug("-----------\n"); + +#define RLEVEL_RANKX_EXTRAS_INCR 0 + // if there are unused entries to be filled + if ((rank_mask & 0x0f) != 0x0f) { + // copy the current rank + union cvmx_lmcx_rlevel_rankx temp_rl_rank = rl_rank; + + if (rankx < 3) { +#if RLEVEL_RANKX_EXTRAS_INCR > 0 + int byte, delay; + + // modify the copy in prep for writing to empty slot(s) + for (byte = 0; byte < 9; byte++) { + delay = get_rl_rank(&temp_rl_rank, byte) + + RLEVEL_RANKX_EXTRAS_INCR; + if (delay > RLEVEL_BYTE_MSK) + delay = RLEVEL_BYTE_MSK; + upd_rl_rank(&temp_rl_rank, byte, delay); + } +#endif + + // if rank 0, write rank 1 and rank 2 here if empty + if (rankx == 0) { + // check that rank 1 is empty + if (!(rank_mask & (1 << 1))) { + debug("N%d.LMC%d.R%d: writing RLEVEL_RANK unused entry R%d.\n", + node, if_num, rankx, 1); + lmc_wr(priv, + CVMX_LMCX_RLEVEL_RANKX(1, + if_num), + temp_rl_rank.u64); + } + + // check that rank 2 is empty + if (!(rank_mask & (1 << 2))) { + debug("N%d.LMC%d.R%d: writing RLEVEL_RANK unused entry R%d.\n", + node, if_num, rankx, 2); + lmc_wr(priv, + CVMX_LMCX_RLEVEL_RANKX(2, + if_num), + temp_rl_rank.u64); + } + } + + // if ranks 0, 1 or 2, write rank 3 here if empty + // check that rank 3 is empty + if (!(rank_mask & (1 << 3))) { + debug("N%d.LMC%d.R%d: writing RLEVEL_RANK unused entry R%d.\n", + node, if_num, rankx, 3); + lmc_wr(priv, CVMX_LMCX_RLEVEL_RANKX(3, if_num), + temp_rl_rank.u64); + } + } + } +} + +static void lmc_read_leveling(struct ddr_priv *priv) +{ + struct rl_score rl_score[RTT_NOM_OHMS_COUNT][RODT_OHMS_COUNT][4]; + union cvmx_lmcx_control ctl; + union cvmx_lmcx_config cfg; + int rankx; + char *s; + int i; + + /* + * 4.8.10 LMC Read Leveling + * + * LMC supports an automatic read-leveling separately per byte-lane + * using the DDR3 multipurpose register predefined pattern for system + * calibration defined in the JEDEC DDR3 specifications. + * + * All of DDR PLL, LMC CK, and LMC DRESET, and early LMC initializations + * must be completed prior to starting this LMC read-leveling sequence. + * + * Software could simply write the desired read-leveling values into + * LMC(0)_RLEVEL_RANK(0..3). This section describes a sequence that uses + * LMC's autoread-leveling capabilities. + * + * When LMC does the read-leveling sequence for a rank, it first enables + * the DDR3 multipurpose register predefined pattern for system + * calibration on the selected DRAM rank via a DDR3 MR3 write, then + * executes 64 RD operations at different internal delay settings, then + * disables the predefined pattern via another DDR3 MR3 write + * operation. LMC determines the pass or fail of each of the 64 settings + * independently for each byte lane, then writes appropriate + * LMC(0)_RLEVEL_RANK(0..3)[BYTE*] values for the rank. + * + * After read-leveling for a rank, software can read the 64 pass/fail + * indications for one byte lane via LMC(0)_RLEVEL_DBG[BITMASK]. + * Software can observe all pass/fail results for all byte lanes in a + * rank via separate read-leveling sequences on the rank with different + * LMC(0)_RLEVEL_CTL[BYTE] values. + * + * The 64 pass/fail results will typically have failures for the low + * delays, followed by a run of some passing settings, followed by more + * failures in the remaining high delays. LMC sets + * LMC(0)_RLEVEL_RANK(0..3)[BYTE*] to one of the passing settings. + * First, LMC selects the longest run of successes in the 64 results. + * (In the unlikely event that there is more than one longest run, LMC + * selects the first one.) Then if LMC(0)_RLEVEL_CTL[OFFSET_EN] = 1 and + * the selected run has more than LMC(0)_RLEVEL_CTL[OFFSET] successes, + * LMC selects the last passing setting in the run minus + * LMC(0)_RLEVEL_CTL[OFFSET]. Otherwise LMC selects the middle setting + * in the run (rounding earlier when necessary). We expect the + * read-leveling sequence to produce good results with the reset values + * LMC(0)_RLEVEL_CTL [OFFSET_EN]=1, LMC(0)_RLEVEL_CTL[OFFSET] = 2. + * + * The read-leveling sequence has the following steps: + * + * 1. Select desired LMC(0)_RLEVEL_CTL[OFFSET_EN,OFFSET,BYTE] settings. + * Do the remaining substeps 2-4 separately for each rank i with + * attached DRAM. + * + * 2. Without changing any other fields in LMC(0)_CONFIG, + * + * o write LMC(0)_SEQ_CTL[SEQ_SEL] to select read-leveling + * + * o write LMC(0)_CONFIG[RANKMASK] = (1 << i) + * + * o write LMC(0)_SEQ_CTL[INIT_START] = 1 + * + * This initiates the previously-described read-leveling. + * + * 3. Wait until LMC(0)_RLEVEL_RANKi[STATUS] != 2 + * + * LMC will have updated LMC(0)_RLEVEL_RANKi[BYTE*] for all byte + * lanes at this point. + * + * If ECC DRAM is not present (i.e. when DRAM is not attached to the + * DDR_CBS_0_* and DDR_CB<7:0> chip signals, or the DDR_DQS_<4>_* and + * DDR_DQ<35:32> chip signals), write LMC(0)_RLEVEL_RANK*[BYTE8] = + * LMC(0)_RLEVEL_RANK*[BYTE0]. Write LMC(0)_RLEVEL_RANK*[BYTE4] = + * LMC(0)_RLEVEL_RANK*[BYTE0]. + * + * 4. If desired, consult LMC(0)_RLEVEL_DBG[BITMASK] and compare to + * LMC(0)_RLEVEL_RANKi[BYTE*] for the lane selected by + * LMC(0)_RLEVEL_CTL[BYTE]. If desired, modify + * LMC(0)_RLEVEL_CTL[BYTE] to a new value and repeat so that all + * BITMASKs can be observed. + * + * 5. Initialize LMC(0)_RLEVEL_RANK* values for all unused ranks. + * + * Let rank i be a rank with attached DRAM. + * + * For all ranks j that do not have attached DRAM, set + * LMC(0)_RLEVEL_RANKj = LMC(0)_RLEVEL_RANKi. + * + * This read-leveling sequence can help select the proper CN70XX ODT + * resistance value (LMC(0)_COMP_CTL2[RODT_CTL]). A hardware-generated + * LMC(0)_RLEVEL_RANKi[BYTEj] value (for a used byte lane j) that is + * drastically different from a neighboring LMC(0)_RLEVEL_RANKi[BYTEk] + * (for a used byte lane k) can indicate that the CN70XX ODT value is + * bad. It is possible to simultaneously optimize both + * LMC(0)_COMP_CTL2[RODT_CTL] and LMC(0)_RLEVEL_RANKn[BYTE*] values by + * performing this read-leveling sequence for several + * LMC(0)_COMP_CTL2[RODT_CTL] values and selecting the one with the + * best LMC(0)_RLEVEL_RANKn[BYTE*] profile for the ranks. + */ + + rl_rodt_err = 0; + rl_dbg_loops = 1; + saved_int_zqcs_dis = 0; + max_adj_rl_del_inc = 0; + rl_print = RLEVEL_PRINTALL_DEFAULT; + +#ifdef ENABLE_HARDCODED_RLEVEL + part_number[21] = {0}; +#endif /* ENABLE_HARDCODED_RLEVEL */ + + pbm_lowsum_limit = 5; // FIXME: is this a good default? + // FIXME: PBM skip for RODT 240 and 34 + pbm_rodt_skip = (1U << ddr4_rodt_ctl_240_ohm) | + (1U << ddr4_rodt_ctl_34_ohm); + + disable_rank_majority = 0; // control rank majority processing + + // default to mask 11b ODDs for DDR4 (except 73xx), else DISABLE + // for DDR3 + rldelay_bump_incr = 0; + disable_rlv_bump_this_byte = 0; + + enable_rldelay_bump = (ddr_type == DDR4_DRAM) ? + ((octeon_is_cpuid(OCTEON_CN73XX)) ? 1 : 3) : 0; + + s = lookup_env(priv, "ddr_disable_rank_majority"); + if (s) + disable_rank_majority = !!simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_pbm_lowsum_limit"); + if (s) + pbm_lowsum_limit = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_pbm_rodt_skip"); + if (s) + pbm_rodt_skip = simple_strtoul(s, NULL, 0); + memset(rank_perf, 0, sizeof(rank_perf)); + + ctl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + save_ddr2t = ctl.cn78xx.ddr2t; + + cfg.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + ecc_ena = cfg.cn78xx.ecc_ena; + + s = lookup_env(priv, "ddr_rlevel_2t"); + if (s) + ctl.cn78xx.ddr2t = simple_strtoul(s, NULL, 0); + + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctl.u64); + + debug("LMC%d: Performing Read-Leveling\n", if_num); + + rl_ctl.u64 = lmc_rd(priv, CVMX_LMCX_RLEVEL_CTL(if_num)); + + rl_samples = c_cfg->rlevel_average_loops; + if (rl_samples == 0) { + rl_samples = RLEVEL_SAMPLES_DEFAULT; + // up the samples for these cases + if (dimm_count == 1 || num_ranks == 1) + rl_samples = rl_samples * 2 + 1; + } + + rl_compute = c_cfg->rlevel_compute; + rl_ctl.cn78xx.offset_en = c_cfg->offset_en; + rl_ctl.cn78xx.offset = spd_rdimm + ? c_cfg->offset_rdimm + : c_cfg->offset_udimm; + + int value = 1; // should ALWAYS be set + + s = lookup_env(priv, "ddr_rlevel_delay_unload"); + if (s) + value = !!simple_strtoul(s, NULL, 0); + rl_ctl.cn78xx.delay_unload_0 = value; + rl_ctl.cn78xx.delay_unload_1 = value; + rl_ctl.cn78xx.delay_unload_2 = value; + rl_ctl.cn78xx.delay_unload_3 = value; + + // use OR_DIS=1 to try for better results + rl_ctl.cn78xx.or_dis = 1; + + /* + * If we will be switching to 32bit mode level based on only + * four bits because there are only 4 ECC bits. + */ + rl_ctl.cn78xx.bitmask = (if_64b) ? 0xFF : 0x0F; + + // allow overrides + s = lookup_env(priv, "ddr_rlevel_ctl_or_dis"); + if (s) + rl_ctl.cn78xx.or_dis = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rlevel_ctl_bitmask"); + if (s) + rl_ctl.cn78xx.bitmask = simple_strtoul(s, NULL, 0); + + rl_comp_offs = spd_rdimm + ? c_cfg->rlevel_comp_offset_rdimm + : c_cfg->rlevel_comp_offset_udimm; + s = lookup_env(priv, "ddr_rlevel_comp_offset"); + if (s) + rl_comp_offs = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rlevel_offset"); + if (s) + rl_ctl.cn78xx.offset = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rlevel_offset_en"); + if (s) + rl_ctl.cn78xx.offset_en = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rlevel_ctl"); + if (s) + rl_ctl.u64 = simple_strtoul(s, NULL, 0); + + lmc_wr(priv, + CVMX_LMCX_RLEVEL_CTL(if_num), + rl_ctl.u64); + + // do this here so we can look at final RLEVEL_CTL[offset] setting... + s = lookup_env(priv, "ddr_enable_rldelay_bump"); + if (s) { + // also use as mask bits + enable_rldelay_bump = strtoul(s, NULL, 0); + } + + if (enable_rldelay_bump != 0) + rldelay_bump_incr = (rl_ctl.cn78xx.offset == 1) ? -1 : 1; + + s = lookup_env(priv, "ddr%d_rlevel_debug_loops", if_num); + if (s) + rl_dbg_loops = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rtt_nom_auto"); + if (s) + ddr_rtt_nom_auto = !!simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rlevel_average"); + if (s) + rl_samples = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rlevel_compute"); + if (s) + rl_compute = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_rlevel_printall"); + if (s) + rl_print = simple_strtoul(s, NULL, 0); + + debug("RLEVEL_CTL : 0x%016llx\n", + rl_ctl.u64); + debug("RLEVEL_OFFSET : %6d\n", + rl_ctl.cn78xx.offset); + debug("RLEVEL_OFFSET_EN : %6d\n", + rl_ctl.cn78xx.offset_en); + + /* + * The purpose for the indexed table is to sort the settings + * by the ohm value to simplify the testing when incrementing + * through the settings. (index => ohms) 1=120, 2=60, 3=40, + * 4=30, 5=20 + */ + min_rtt_nom_idx = (c_cfg->min_rtt_nom_idx == 0) ? + 1 : c_cfg->min_rtt_nom_idx; + max_rtt_nom_idx = (c_cfg->max_rtt_nom_idx == 0) ? + 5 : c_cfg->max_rtt_nom_idx; + + min_rodt_ctl = (c_cfg->min_rodt_ctl == 0) ? 1 : c_cfg->min_rodt_ctl; + max_rodt_ctl = (c_cfg->max_rodt_ctl == 0) ? 5 : c_cfg->max_rodt_ctl; + + s = lookup_env(priv, "ddr_min_rodt_ctl"); + if (s) + min_rodt_ctl = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_max_rodt_ctl"); + if (s) + max_rodt_ctl = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_min_rtt_nom_idx"); + if (s) + min_rtt_nom_idx = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_max_rtt_nom_idx"); + if (s) + max_rtt_nom_idx = simple_strtoul(s, NULL, 0); + +#ifdef ENABLE_HARDCODED_RLEVEL + if (c_cfg->rl_tbl) { + /* Check for hard-coded read-leveling settings */ + get_dimm_part_number(part_number, &dimm_config_table[0], + 0, ddr_type); + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + rl_rank.u64 = lmc_rd(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + + i = 0; + while (c_cfg->rl_tbl[i].part) { + debug("DIMM part number:\"%s\", SPD: \"%s\"\n", + c_cfg->rl_tbl[i].part, part_number); + if ((strcmp(part_number, + c_cfg->rl_tbl[i].part) == 0) && + (abs(c_cfg->rl_tbl[i].speed - + 2 * ddr_hertz / (1000 * 1000)) < 10)) { + debug("Using hard-coded read leveling for DIMM part number: \"%s\"\n", + part_number); + rl_rank.u64 = + c_cfg->rl_tbl[i].rl_rank[if_num][rankx]; + lmc_wr(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num), + rl_rank.u64); + rl_rank.u64 = + lmc_rd(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + display_rl(if_num, rl_rank, rankx); + /* Disable h/w read-leveling */ + rl_dbg_loops = 0; + break; + } + ++i; + } + } + } +#endif /* ENABLE_HARDCODED_RLEVEL */ + + max_adj_rl_del_inc = c_cfg->maximum_adjacent_rlevel_delay_increment; + s = lookup_env(priv, "ddr_maximum_adjacent_rlevel_delay_increment"); + if (s) + max_adj_rl_del_inc = strtoul(s, NULL, 0); + + while (rl_dbg_loops--) { + union cvmx_lmcx_modereg_params1 mp1; + union cvmx_lmcx_comp_ctl2 cc2; + + /* Initialize the error scoreboard */ + memset(rl_score, 0, sizeof(rl_score)); + + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + saved_ddr__ptune = cc2.cn78xx.ddr__ptune; + saved_ddr__ntune = cc2.cn78xx.ddr__ntune; + + /* Disable dynamic compensation settings */ + if (rl_comp_offs != 0) { + cc2.cn78xx.ptune = saved_ddr__ptune; + cc2.cn78xx.ntune = saved_ddr__ntune; + + /* + * Round up the ptune calculation to bias the odd + * cases toward ptune + */ + cc2.cn78xx.ptune += divide_roundup(rl_comp_offs, 2); + cc2.cn78xx.ntune -= rl_comp_offs / 2; + + ctl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + saved_int_zqcs_dis = ctl.s.int_zqcs_dis; + /* Disable ZQCS while in bypass. */ + ctl.s.int_zqcs_dis = 1; + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctl.u64); + + cc2.cn78xx.byp = 1; /* Enable bypass mode */ + lmc_wr(priv, CVMX_LMCX_COMP_CTL2(if_num), cc2.u64); + lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + /* Read again */ + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + debug("DDR__PTUNE/DDR__NTUNE : %d/%d\n", + cc2.cn78xx.ddr__ptune, cc2.cn78xx.ddr__ntune); + } + + mp1.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS1(if_num)); + + for (rtt_idx = min_rtt_nom_idx; rtt_idx <= max_rtt_nom_idx; + ++rtt_idx) { + rtt_nom = imp_val->rtt_nom_table[rtt_idx]; + + /* + * When the read ODT mask is zero the dyn_rtt_nom_mask + * is zero than RTT_NOM will not be changing during + * read-leveling. Since the value is fixed we only need + * to test it once. + */ + if (dyn_rtt_nom_mask == 0) { + // flag not to print NOM ohms + print_nom_ohms = -1; + } else { + if (dyn_rtt_nom_mask & 1) + mp1.s.rtt_nom_00 = rtt_nom; + if (dyn_rtt_nom_mask & 2) + mp1.s.rtt_nom_01 = rtt_nom; + if (dyn_rtt_nom_mask & 4) + mp1.s.rtt_nom_10 = rtt_nom; + if (dyn_rtt_nom_mask & 8) + mp1.s.rtt_nom_11 = rtt_nom; + // FIXME? rank 0 ohms always? + print_nom_ohms = + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_00]; + } + + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS1(if_num), + mp1.u64); + + if (print_nom_ohms >= 0 && rl_print > 1) { + debug("\n"); + debug("RTT_NOM %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_11], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_10], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_01], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_00], + mp1.s.rtt_nom_11, + mp1.s.rtt_nom_10, + mp1.s.rtt_nom_01, + mp1.s.rtt_nom_00); + } + + ddr_init_seq(priv, rank_mask, if_num); + + // Try RANK outside RODT to rearrange the output... + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + for (rodt_ctl = max_rodt_ctl; + rodt_ctl >= min_rodt_ctl; --rodt_ctl) + rodt_loop(priv, rankx, rl_score); + } + } + + /* Re-enable dynamic compensation settings. */ + if (rl_comp_offs != 0) { + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + + cc2.cn78xx.ptune = 0; + cc2.cn78xx.ntune = 0; + cc2.cn78xx.byp = 0; /* Disable bypass mode */ + lmc_wr(priv, CVMX_LMCX_COMP_CTL2(if_num), cc2.u64); + /* Read once */ + lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + + /* Read again */ + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + debug("DDR__PTUNE/DDR__NTUNE : %d/%d\n", + cc2.cn78xx.ddr__ptune, cc2.cn78xx.ddr__ntune); + + ctl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + /* Restore original setting */ + ctl.s.int_zqcs_dis = saved_int_zqcs_dis; + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctl.u64); + } + + int override_compensation = 0; + + s = lookup_env(priv, "ddr__ptune"); + if (s) + saved_ddr__ptune = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr__ntune"); + if (s) { + saved_ddr__ntune = strtoul(s, NULL, 0); + override_compensation = 1; + } + + if (override_compensation) { + cc2.cn78xx.ptune = saved_ddr__ptune; + cc2.cn78xx.ntune = saved_ddr__ntune; + + ctl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + saved_int_zqcs_dis = ctl.s.int_zqcs_dis; + /* Disable ZQCS while in bypass. */ + ctl.s.int_zqcs_dis = 1; + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctl.u64); + + cc2.cn78xx.byp = 1; /* Enable bypass mode */ + lmc_wr(priv, CVMX_LMCX_COMP_CTL2(if_num), cc2.u64); + /* Read again */ + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + + debug("DDR__PTUNE/DDR__NTUNE : %d/%d\n", + cc2.cn78xx.ptune, cc2.cn78xx.ntune); + } + + /* Evaluation block */ + /* Still at initial value? */ + int best_rodt_score = DEFAULT_BEST_RANK_SCORE; + int auto_rodt_ctl = 0; + int auto_rtt_nom = 0; + int rodt_score; + + rodt_row_skip_mask = 0; + + // just add specific RODT rows to the skip mask for DDR4 + // at this time... + if (ddr_type == DDR4_DRAM) { + // skip RODT row 34 ohms for all DDR4 types + rodt_row_skip_mask |= (1 << ddr4_rodt_ctl_34_ohm); + // skip RODT row 40 ohms for all DDR4 types + rodt_row_skip_mask |= (1 << ddr4_rodt_ctl_40_ohm); + // For now, do not skip RODT row 40 or 48 ohm when + // ddr_hertz is above 1075 MHz + if (ddr_hertz > 1075000000) { + // noskip RODT row 40 ohms + rodt_row_skip_mask &= + ~(1 << ddr4_rodt_ctl_40_ohm); + // noskip RODT row 48 ohms + rodt_row_skip_mask &= + ~(1 << ddr4_rodt_ctl_48_ohm); + } + // For now, do not skip RODT row 48 ohm for 2Rx4 + // stacked die DIMMs + if (is_stacked_die && num_ranks == 2 && + dram_width == 4) { + // noskip RODT row 48 ohms + rodt_row_skip_mask &= + ~(1 << ddr4_rodt_ctl_48_ohm); + } + // for now, leave all rows eligible when we have + // mini-DIMMs... + if (spd_dimm_type == 5 || spd_dimm_type == 6) + rodt_row_skip_mask = 0; + // for now, leave all rows eligible when we have + // a 2-slot 1-rank config + if (dimm_count == 2 && num_ranks == 1) + rodt_row_skip_mask = 0; + + debug("Evaluating Read-Leveling Scoreboard for AUTO settings.\n"); + for (rtt_idx = min_rtt_nom_idx; + rtt_idx <= max_rtt_nom_idx; ++rtt_idx) { + rtt_nom = imp_val->rtt_nom_table[rtt_idx]; + + for (rodt_ctl = max_rodt_ctl; + rodt_ctl >= min_rodt_ctl; --rodt_ctl) { + rodt_score = 0; + for (rankx = 0; rankx < dimm_count * 4; + rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + debug("rl_score[rtt_nom=%d][rodt_ctl=%d][rankx=%d].score:%d\n", + rtt_nom, rodt_ctl, rankx, + rl_score[rtt_nom][rodt_ctl][rankx].score); + rodt_score += + rl_score[rtt_nom][rodt_ctl][rankx].score; + } + // FIXME: do we need to skip RODT rows + // here, like we do below in the + // by-RANK settings? + + /* + * When using automatic ODT settings use + * the ODT settings associated with the + * best score for all of the tested ODT + * combinations. + */ + + if (rodt_score < best_rodt_score || + (rodt_score == best_rodt_score && + (imp_val->rodt_ohms[rodt_ctl] > + imp_val->rodt_ohms[auto_rodt_ctl]))) { + debug("AUTO: new best score for rodt:%d (%d), new score:%d, previous score:%d\n", + rodt_ctl, + imp_val->rodt_ohms[rodt_ctl], + rodt_score, + best_rodt_score); + best_rodt_score = rodt_score; + auto_rodt_ctl = rodt_ctl; + auto_rtt_nom = rtt_nom; + } + } + } + + mp1.u64 = lmc_rd(priv, + CVMX_LMCX_MODEREG_PARAMS1(if_num)); + + if (ddr_rtt_nom_auto) { + /* Store the automatically set RTT_NOM value */ + if (dyn_rtt_nom_mask & 1) + mp1.s.rtt_nom_00 = auto_rtt_nom; + if (dyn_rtt_nom_mask & 2) + mp1.s.rtt_nom_01 = auto_rtt_nom; + if (dyn_rtt_nom_mask & 4) + mp1.s.rtt_nom_10 = auto_rtt_nom; + if (dyn_rtt_nom_mask & 8) + mp1.s.rtt_nom_11 = auto_rtt_nom; + } else { + /* + * restore the manual settings to the register + */ + mp1.s.rtt_nom_00 = default_rtt_nom[0]; + mp1.s.rtt_nom_01 = default_rtt_nom[1]; + mp1.s.rtt_nom_10 = default_rtt_nom[2]; + mp1.s.rtt_nom_11 = default_rtt_nom[3]; + } + + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS1(if_num), + mp1.u64); + debug("RTT_NOM %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_11], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_10], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_01], + imp_val->rtt_nom_ohms[mp1.s.rtt_nom_00], + mp1.s.rtt_nom_11, + mp1.s.rtt_nom_10, + mp1.s.rtt_nom_01, + mp1.s.rtt_nom_00); + + debug("RTT_WR %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 3)], + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 2)], + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 1)], + imp_val->rtt_wr_ohms[extr_wr(mp1.u64, 0)], + extr_wr(mp1.u64, 3), + extr_wr(mp1.u64, 2), + extr_wr(mp1.u64, 1), + extr_wr(mp1.u64, 0)); + + debug("DIC %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->dic_ohms[mp1.s.dic_11], + imp_val->dic_ohms[mp1.s.dic_10], + imp_val->dic_ohms[mp1.s.dic_01], + imp_val->dic_ohms[mp1.s.dic_00], + mp1.s.dic_11, + mp1.s.dic_10, + mp1.s.dic_01, + mp1.s.dic_00); + + if (ddr_type == DDR4_DRAM) { + union cvmx_lmcx_modereg_params2 mp2; + /* + * We must read the CSR, and not depend on + * odt_config[odt_idx].odt_mask2, since we could + * have overridden values with envvars. + * NOTE: this corrects the printout, since the + * CSR is not written with the old values... + */ + mp2.u64 = lmc_rd(priv, + CVMX_LMCX_MODEREG_PARAMS2(if_num)); + + debug("RTT_PARK %3d, %3d, %3d, %3d ohms : %x,%x,%x,%x\n", + imp_val->rtt_nom_ohms[mp2.s.rtt_park_11], + imp_val->rtt_nom_ohms[mp2.s.rtt_park_10], + imp_val->rtt_nom_ohms[mp2.s.rtt_park_01], + imp_val->rtt_nom_ohms[mp2.s.rtt_park_00], + mp2.s.rtt_park_11, + mp2.s.rtt_park_10, + mp2.s.rtt_park_01, + mp2.s.rtt_park_00); + + debug("%-45s : 0x%x,0x%x,0x%x,0x%x\n", + "VREF_RANGE", + mp2.s.vref_range_11, + mp2.s.vref_range_10, + mp2.s.vref_range_01, + mp2.s.vref_range_00); + + debug("%-45s : 0x%x,0x%x,0x%x,0x%x\n", + "VREF_VALUE", + mp2.s.vref_value_11, + mp2.s.vref_value_10, + mp2.s.vref_value_01, + mp2.s.vref_value_00); + } + + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + if (ddr_rodt_ctl_auto) { + cc2.cn78xx.rodt_ctl = auto_rodt_ctl; + } else { + // back to the original setting + cc2.cn78xx.rodt_ctl = default_rodt_ctl; + } + lmc_wr(priv, CVMX_LMCX_COMP_CTL2(if_num), cc2.u64); + cc2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(if_num)); + debug("Read ODT_CTL : 0x%x (%d ohms)\n", + cc2.cn78xx.rodt_ctl, + imp_val->rodt_ohms[cc2.cn78xx.rodt_ctl]); + + /* + * Use the delays associated with the best score for + * each individual rank + */ + debug("Evaluating Read-Leveling Scoreboard for per-RANK settings.\n"); + + // this is the the RANK MAJOR LOOP + for (rankx = 0; rankx < dimm_count * 4; rankx++) + rank_major_loop(priv, rankx, rl_score); + } /* Evaluation block */ + } /* while(rl_dbg_loops--) */ + + ctl.cn78xx.ddr2t = save_ddr2t; + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctl.u64); + ctl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + /* Display final 2T value */ + debug("DDR2T : %6d\n", + ctl.cn78xx.ddr2t); + + ddr_init_seq(priv, rank_mask, if_num); + + for (rankx = 0; rankx < dimm_count * 4; rankx++) { + u64 value; + int parameter_set = 0; + + if (!(rank_mask & (1 << rankx))) + continue; + + rl_rank.u64 = lmc_rd(priv, CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + + for (i = 0; i < 9; ++i) { + s = lookup_env(priv, "ddr%d_rlevel_rank%d_byte%d", + if_num, rankx, i); + if (s) { + parameter_set |= 1; + value = simple_strtoul(s, NULL, 0); + + upd_rl_rank(&rl_rank, i, value); + } + } + + s = lookup_env_ull(priv, "ddr%d_rlevel_rank%d", if_num, rankx); + if (s) { + parameter_set |= 1; + value = simple_strtoull(s, NULL, 0); + rl_rank.u64 = value; + } + + if (parameter_set) { + lmc_wr(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, if_num), + rl_rank.u64); + rl_rank.u64 = lmc_rd(priv, + CVMX_LMCX_RLEVEL_RANKX(rankx, + if_num)); + display_rl(if_num, rl_rank, rankx); + } + } +} + +int init_octeon3_ddr3_interface(struct ddr_priv *priv, + struct ddr_conf *_ddr_conf, u32 _ddr_hertz, + u32 cpu_hertz, u32 ddr_ref_hertz, int _if_num, + u32 _if_mask) +{ + union cvmx_lmcx_control ctrl; + int ret; + char *s; + int i; + + if_num = _if_num; + ddr_hertz = _ddr_hertz; + ddr_conf = _ddr_conf; + if_mask = _if_mask; + odt_1rank_config = ddr_conf->odt_1rank_config; + odt_2rank_config = ddr_conf->odt_2rank_config; + odt_4rank_config = ddr_conf->odt_4rank_config; + dimm_config_table = ddr_conf->dimm_config_table; + c_cfg = &ddr_conf->custom_lmc_config; + + /* + * Compute clock rates to the nearest picosecond. + */ + tclk_psecs = hertz_to_psecs(ddr_hertz); /* Clock in psecs */ + eclk_psecs = hertz_to_psecs(cpu_hertz); /* Clock in psecs */ + + dimm_count = 0; + /* Accumulate and report all the errors before giving up */ + fatal_error = 0; + + /* Flag that indicates safe DDR settings should be used */ + safe_ddr_flag = 0; + if_64b = 1; /* Octeon II Default: 64bit interface width */ + mem_size_mbytes = 0; + bank_bits = 0; + column_bits_start = 1; + use_ecc = 1; + min_cas_latency = 0, max_cas_latency = 0, override_cas_latency = 0; + spd_package = 0; + spd_rawcard = 0; + spd_rawcard_aorb = 0; + spd_rdimm_registers = 0; + is_stacked_die = 0; + is_3ds_dimm = 0; // 3DS + lranks_per_prank = 1; // 3DS: logical ranks per package rank + lranks_bits = 0; // 3DS: logical ranks bits + die_capacity = 0; // in Mbits; only used for 3DS + + wl_mask_err = 0; + dyn_rtt_nom_mask = 0; + ddr_disable_chip_reset = 1; + match_wl_rtt_nom = 0; + + internal_retries = 0; + + disable_deskew_training = 0; + restart_if_dsk_incomplete = 0; + last_lane = ((if_64b) ? 8 : 4) + use_ecc; + + disable_sequential_delay_check = 0; + wl_print = WLEVEL_PRINTALL_DEFAULT; + + enable_by_rank_init = 1; // FIXME: default by-rank ON + saved_rank_mask = 0; + + node = 0; + + memset(hwl_alts, 0, sizeof(hwl_alts)); + + /* + * Initialize these to shut up the compiler. They are configured + * and used only for DDR4 + */ + ddr4_trrd_lmin = 6000; + ddr4_tccd_lmin = 6000; + + debug("\nInitializing node %d DDR interface %d, DDR Clock %d, DDR Reference Clock %d, CPUID 0x%08x\n", + node, if_num, ddr_hertz, ddr_ref_hertz, read_c0_prid()); + + if (dimm_config_table[0].spd_addrs[0] == 0 && + !dimm_config_table[0].spd_ptrs[0]) { + printf("ERROR: No dimms specified in the dimm_config_table.\n"); + return -1; + } + + // allow some overrides to be done + + // this one controls several things related to DIMM geometry: HWL and RL + disable_sequential_delay_check = c_cfg->disable_sequential_delay_check; + s = lookup_env(priv, "ddr_disable_sequential_delay_check"); + if (s) + disable_sequential_delay_check = strtoul(s, NULL, 0); + + // this one controls whether chip RESET is done, or LMC init restarted + // from step 6.9.6 + s = lookup_env(priv, "ddr_disable_chip_reset"); + if (s) + ddr_disable_chip_reset = !!strtoul(s, NULL, 0); + + // this one controls whether Deskew Training is performed + s = lookup_env(priv, "ddr_disable_deskew_training"); + if (s) + disable_deskew_training = !!strtoul(s, NULL, 0); + + if (ddr_verbose(priv)) { + printf("DDR SPD Table:"); + for (didx = 0; didx < DDR_CFG_T_MAX_DIMMS; ++didx) { + if (dimm_config_table[didx].spd_addrs[0] == 0) + break; + + printf(" --ddr%dspd=0x%02x", if_num, + dimm_config_table[didx].spd_addrs[0]); + if (dimm_config_table[didx].spd_addrs[1] != 0) + printf(",0x%02x", + dimm_config_table[didx].spd_addrs[1]); + } + printf("\n"); + } + + /* + * Walk the DRAM Socket Configuration Table to see what is installed. + */ + for (didx = 0; didx < DDR_CFG_T_MAX_DIMMS; ++didx) { + /* Check for lower DIMM socket populated */ + if (validate_dimm(priv, &dimm_config_table[didx], 0)) { + if (ddr_verbose(priv)) + report_dimm(&dimm_config_table[didx], 0, + dimm_count, if_num); + ++dimm_count; + } else { + break; + } /* Finished when there is no lower DIMM */ + } + + initialize_ddr_clock(priv, ddr_conf, cpu_hertz, ddr_hertz, + ddr_ref_hertz, if_num, if_mask); + + if (!odt_1rank_config) + odt_1rank_config = disable_odt_config; + if (!odt_2rank_config) + odt_2rank_config = disable_odt_config; + if (!odt_4rank_config) + odt_4rank_config = disable_odt_config; + + s = env_get("ddr_safe"); + if (s) { + safe_ddr_flag = !!simple_strtoul(s, NULL, 0); + printf("Parameter found in environment. ddr_safe = %d\n", + safe_ddr_flag); + } + + if (dimm_count == 0) { + printf("ERROR: DIMM 0 not detected.\n"); + return (-1); + } + + if (c_cfg->mode32b) + if_64b = 0; + + s = lookup_env(priv, "if_64b"); + if (s) + if_64b = !!simple_strtoul(s, NULL, 0); + + if (if_64b == 1) { + if (octeon_is_cpuid(OCTEON_CN70XX)) { + printf("64-bit interface width is not supported for this Octeon model\n"); + ++fatal_error; + } + } + + /* ddr_type only indicates DDR4 or DDR3 */ + ddr_type = (read_spd(&dimm_config_table[0], 0, + DDR4_SPD_KEY_BYTE_DEVICE_TYPE) == 0x0C) ? 4 : 3; + debug("DRAM Device Type: DDR%d\n", ddr_type); + + if (ddr_type == DDR4_DRAM) { + int spd_module_type; + int asymmetric; + const char *signal_load[4] = { "", "MLS", "3DS", "RSV" }; + + imp_val = &ddr4_impedence_val; + + spd_addr = + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_ADDRESSING_ROW_COL_BITS); + spd_org = + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MODULE_ORGANIZATION); + spd_banks = + 0xFF & read_spd(&dimm_config_table[0], 0, + DDR4_SPD_DENSITY_BANKS); + + bank_bits = + (2 + ((spd_banks >> 4) & 0x3)) + ((spd_banks >> 6) & 0x3); + /* Controller can only address 4 bits. */ + bank_bits = min((int)bank_bits, 4); + + spd_package = + 0XFF & read_spd(&dimm_config_table[0], 0, + DDR4_SPD_PACKAGE_TYPE); + if (spd_package & 0x80) { // non-monolithic device + is_stacked_die = ((spd_package & 0x73) == 0x11); + debug("DDR4: Package Type 0x%02x (%s), %d die\n", + spd_package, signal_load[(spd_package & 3)], + ((spd_package >> 4) & 7) + 1); + is_3ds_dimm = ((spd_package & 3) == 2); // is it 3DS? + if (is_3ds_dimm) { // is it 3DS? + lranks_per_prank = ((spd_package >> 4) & 7) + 1; + // FIXME: should make sure it is only 2H or 4H + // or 8H? + lranks_bits = lranks_per_prank >> 1; + if (lranks_bits == 4) + lranks_bits = 3; + } + } else if (spd_package != 0) { + // FIXME: print non-zero monolithic device definition + debug("DDR4: Package Type MONOLITHIC: %d die, signal load %d\n", + ((spd_package >> 4) & 7) + 1, (spd_package & 3)); + } + + asymmetric = (spd_org >> 6) & 1; + if (asymmetric) { + int spd_secondary_pkg = + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_SECONDARY_PACKAGE_TYPE); + debug("DDR4: Module Organization: ASYMMETRICAL: Secondary Package Type 0x%02x\n", + spd_secondary_pkg); + } else { + u64 bus_width = + 8 << (0x07 & + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MODULE_MEMORY_BUS_WIDTH)); + u64 ddr_width = 4 << ((spd_org >> 0) & 0x7); + u64 module_cap; + int shift = (spd_banks & 0x0F); + + die_capacity = (shift < 8) ? (256UL << shift) : + ((12UL << (shift & 1)) << 10); + debug("DDR4: Module Organization: SYMMETRICAL: capacity per die %d %cbit\n", + (die_capacity > 512) ? (die_capacity >> 10) : + die_capacity, (die_capacity > 512) ? 'G' : 'M'); + module_cap = ((u64)die_capacity << 20) / 8UL * + bus_width / ddr_width * + (1UL + ((spd_org >> 3) & 0x7)); + + // is it 3DS? + if (is_3ds_dimm) { + module_cap *= (u64)(((spd_package >> 4) & 7) + + 1); + } + debug("DDR4: Module Organization: SYMMETRICAL: capacity per module %lld GB\n", + module_cap >> 30); + } + + spd_rawcard = + 0xFF & read_spd(&dimm_config_table[0], 0, + DDR4_SPD_REFERENCE_RAW_CARD); + debug("DDR4: Reference Raw Card 0x%02x\n", spd_rawcard); + + spd_module_type = + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_KEY_BYTE_MODULE_TYPE); + if (spd_module_type & 0x80) { // HYBRID module + debug("DDR4: HYBRID module, type %s\n", + ((spd_module_type & 0x70) == + 0x10) ? "NVDIMM" : "UNKNOWN"); + } + spd_thermal_sensor = + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MODULE_THERMAL_SENSOR); + spd_dimm_type = spd_module_type & 0x0F; + spd_rdimm = (spd_dimm_type == 1) || (spd_dimm_type == 5) || + (spd_dimm_type == 8); + if (spd_rdimm) { + u16 spd_mfgr_id, spd_register_rev, spd_mod_attr; + static const u16 manu_ids[4] = { + 0xb380, 0x3286, 0x9780, 0xb304 + }; + static const char *manu_names[4] = { + "XXX", "XXXXXXX", "XX", "XXXXX" + }; + int mc; + + spd_mfgr_id = + (0xFFU & + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_REGISTER_MANUFACTURER_ID_LSB)) | + ((0xFFU & + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_REGISTER_MANUFACTURER_ID_MSB)) + << 8); + spd_register_rev = + 0xFFU & read_spd(&dimm_config_table[0], 0, + DDR4_SPD_REGISTER_REVISION_NUMBER); + for (mc = 0; mc < 4; mc++) + if (manu_ids[mc] == spd_mfgr_id) + break; + + debug("DDR4: RDIMM Register Manufacturer ID: %s, Revision: 0x%02x\n", + (mc >= 4) ? "UNKNOWN" : manu_names[mc], + spd_register_rev); + + // RAWCARD A or B must be bit 7=0 and bits 4-0 + // either 00000(A) or 00001(B) + spd_rawcard_aorb = ((spd_rawcard & 0x9fUL) <= 1); + // RDIMM Module Attributes + spd_mod_attr = + 0xFFU & read_spd(&dimm_config_table[0], 0, + DDR4_SPD_UDIMM_ADDR_MAPPING_FROM_EDGE); + spd_rdimm_registers = ((1 << (spd_mod_attr & 3)) >> 1); + debug("DDR4: RDIMM Module Attributes (0x%02x): Register Type DDR4RCD%02d, DRAM rows %d, Registers %d\n", + spd_mod_attr, (spd_mod_attr >> 4) + 1, + ((1 << ((spd_mod_attr >> 2) & 3)) >> 1), + spd_rdimm_registers); + } + dimm_type_name = ddr4_dimm_types[spd_dimm_type]; + } else { /* if (ddr_type == DDR4_DRAM) */ + const char *signal_load[4] = { "UNK", "MLS", "SLS", "RSV" }; + + imp_val = &ddr3_impedence_val; + + spd_addr = + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_ADDRESSING_ROW_COL_BITS); + spd_org = + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MODULE_ORGANIZATION); + spd_banks = + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_DENSITY_BANKS) & 0xff; + + bank_bits = 3 + ((spd_banks >> 4) & 0x7); + /* Controller can only address 3 bits. */ + bank_bits = min((int)bank_bits, 3); + spd_dimm_type = + 0x0f & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_KEY_BYTE_MODULE_TYPE); + spd_rdimm = (spd_dimm_type == 1) || (spd_dimm_type == 5) || + (spd_dimm_type == 9); + + spd_package = + 0xFF & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_SDRAM_DEVICE_TYPE); + if (spd_package & 0x80) { // non-standard device + debug("DDR3: Device Type 0x%02x (%s), %d die\n", + spd_package, signal_load[(spd_package & 3)], + ((1 << ((spd_package >> 4) & 7)) >> 1)); + } else if (spd_package != 0) { + // FIXME: print non-zero monolithic device definition + debug("DDR3: Device Type MONOLITHIC: %d die, signal load %d\n", + ((1 << (spd_package >> 4) & 7) >> 1), + (spd_package & 3)); + } + + spd_rawcard = + 0xFF & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_REFERENCE_RAW_CARD); + debug("DDR3: Reference Raw Card 0x%02x\n", spd_rawcard); + spd_thermal_sensor = + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MODULE_THERMAL_SENSOR); + + if (spd_rdimm) { + int spd_mfgr_id, spd_register_rev, spd_mod_attr; + + spd_mfgr_id = + (0xFFU & + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_REGISTER_MANUFACTURER_ID_LSB)) | + ((0xFFU & + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_REGISTER_MANUFACTURER_ID_MSB)) + << 8); + spd_register_rev = + 0xFFU & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_REGISTER_REVISION_NUMBER); + debug("DDR3: RDIMM Register Manufacturer ID 0x%x Revision 0x%02x\n", + spd_mfgr_id, spd_register_rev); + // Module Attributes + spd_mod_attr = + 0xFFU & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_ADDRESS_MAPPING); + spd_rdimm_registers = ((1 << (spd_mod_attr & 3)) >> 1); + debug("DDR3: RDIMM Module Attributes (0x%02x): DRAM rows %d, Registers %d\n", + spd_mod_attr, + ((1 << ((spd_mod_attr >> 2) & 3)) >> 1), + spd_rdimm_registers); + } + dimm_type_name = ddr3_dimm_types[spd_dimm_type]; + } + + if (spd_thermal_sensor & 0x80) { + debug("DDR%d: SPD: Thermal Sensor PRESENT\n", + (ddr_type == DDR4_DRAM) ? 4 : 3); + } + + debug("spd_addr : %#06x\n", spd_addr); + debug("spd_org : %#06x\n", spd_org); + debug("spd_banks : %#06x\n", spd_banks); + + row_bits = 12 + ((spd_addr >> 3) & 0x7); + col_bits = 9 + ((spd_addr >> 0) & 0x7); + + num_ranks = 1 + ((spd_org >> 3) & 0x7); + dram_width = 4 << ((spd_org >> 0) & 0x7); + num_banks = 1 << bank_bits; + + s = lookup_env(priv, "ddr_num_ranks"); + if (s) + num_ranks = simple_strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_enable_by_rank_init"); + if (s) + enable_by_rank_init = !!simple_strtoul(s, NULL, 0); + + // FIXME: for now, we can only handle a DDR4 2rank-1slot config + // FIXME: also, by-rank init does not work correctly if 32-bit mode... + if (enable_by_rank_init && (ddr_type != DDR4_DRAM || + dimm_count != 1 || if_64b != 1 || + num_ranks != 2)) + enable_by_rank_init = 0; + + if (enable_by_rank_init) { + struct dimm_odt_config *odt_config; + union cvmx_lmcx_modereg_params1 mp1; + union cvmx_lmcx_modereg_params2 modereg_params2; + int by_rank_rodt, by_rank_wr, by_rank_park; + + // Do ODT settings changes which work best for 2R-1S configs + debug("DDR4: 2R-1S special BY-RANK init ODT settings updated\n"); + + // setup for modifying config table values - 2 ranks and 1 DIMM + odt_config = + (struct dimm_odt_config *)&ddr_conf->odt_2rank_config[0]; + + // original was 80, first try was 60 + by_rank_rodt = ddr4_rodt_ctl_48_ohm; + s = lookup_env(priv, "ddr_by_rank_rodt"); + if (s) + by_rank_rodt = strtoul(s, NULL, 0); + + odt_config->qs_dic = /*RODT_CTL */ by_rank_rodt; + + // this is for MODEREG_PARAMS1 fields + // fetch the original settings + mp1.u64 = odt_config->modereg_params1.u64; + + by_rank_wr = ddr4_rttwr_80ohm; // originals were 240 + s = lookup_env(priv, "ddr_by_rank_wr"); + if (s) + by_rank_wr = simple_strtoul(s, NULL, 0); + + // change specific settings here... + insrt_wr(&mp1.u64, /*rank */ 00, by_rank_wr); + insrt_wr(&mp1.u64, /*rank */ 01, by_rank_wr); + + // save final settings + odt_config->modereg_params1.u64 = mp1.u64; + + // this is for MODEREG_PARAMS2 fields + // fetch the original settings + modereg_params2.u64 = odt_config->modereg_params2.u64; + + by_rank_park = ddr4_rttpark_none; // originals were 120 + s = lookup_env(priv, "ddr_by_rank_park"); + if (s) + by_rank_park = simple_strtoul(s, NULL, 0); + + // change specific settings here... + modereg_params2.s.rtt_park_00 = by_rank_park; + modereg_params2.s.rtt_park_01 = by_rank_park; + + // save final settings + odt_config->modereg_params2.u64 = modereg_params2.u64; + } + + /* + * FIX + * Check that values are within some theoretical limits. + * col_bits(min) = row_lsb(min) - bank_bits(max) - bus_bits(max) = + * 14 - 3 - 4 = 7 + * col_bits(max) = row_lsb(max) - bank_bits(min) - bus_bits(min) = + * 18 - 2 - 3 = 13 + */ + if (col_bits > 13 || col_bits < 7) { + printf("Unsupported number of Col Bits: %d\n", col_bits); + ++fatal_error; + } + + /* + * FIX + * Check that values are within some theoretical limits. + * row_bits(min) = pbank_lsb(min) - row_lsb(max) - rank_bits = + * 26 - 18 - 1 = 7 + * row_bits(max) = pbank_lsb(max) - row_lsb(min) - rank_bits = + * 33 - 14 - 1 = 18 + */ + if (row_bits > 18 || row_bits < 7) { + printf("Unsupported number of Row Bits: %d\n", row_bits); + ++fatal_error; + } + + s = lookup_env(priv, "ddr_rdimm_ena"); + if (s) + spd_rdimm = !!simple_strtoul(s, NULL, 0); + + wl_loops = WLEVEL_LOOPS_DEFAULT; + // accept generic or interface-specific override + s = lookup_env(priv, "ddr_wlevel_loops"); + if (!s) + s = lookup_env(priv, "ddr%d_wlevel_loops", if_num); + + if (s) + wl_loops = strtoul(s, NULL, 0); + + s = lookup_env(priv, "ddr_ranks"); + if (s) + num_ranks = simple_strtoul(s, NULL, 0); + + bunk_enable = (num_ranks > 1); + + if (octeon_is_cpuid(OCTEON_CN7XXX)) + column_bits_start = 3; + else + printf("ERROR: Unsupported Octeon model: 0x%x\n", + read_c0_prid()); + + row_lsb = column_bits_start + col_bits + bank_bits - (!if_64b); + debug("row_lsb = column_bits_start + col_bits + bank_bits = %d\n", + row_lsb); + + pbank_lsb = row_lsb + row_bits + bunk_enable; + debug("pbank_lsb = row_lsb + row_bits + bunk_enable = %d\n", pbank_lsb); + + if (lranks_per_prank > 1) { + pbank_lsb = row_lsb + row_bits + lranks_bits + bunk_enable; + debug("DDR4: 3DS: pbank_lsb = (%d row_lsb) + (%d row_bits) + (%d lranks_bits) + (%d bunk_enable) = %d\n", + row_lsb, row_bits, lranks_bits, bunk_enable, pbank_lsb); + } + + mem_size_mbytes = dimm_count * ((1ull << pbank_lsb) >> 20); + if (num_ranks == 4) { + /* + * Quad rank dimm capacity is equivalent to two dual-rank + * dimms. + */ + mem_size_mbytes *= 2; + } + + /* + * Mask with 1 bits set for for each active rank, allowing 2 bits + * per dimm. This makes later calculations simpler, as a variety + * of CSRs use this layout. This init needs to be updated for dual + * configs (ie non-identical DIMMs). + * + * Bit 0 = dimm0, rank 0 + * Bit 1 = dimm0, rank 1 + * Bit 2 = dimm1, rank 0 + * Bit 3 = dimm1, rank 1 + * ... + */ + rank_mask = 0x1; + if (num_ranks > 1) + rank_mask = 0x3; + if (num_ranks > 2) + rank_mask = 0xf; + + for (i = 1; i < dimm_count; i++) + rank_mask |= ((rank_mask & 0x3) << (2 * i)); + + /* + * If we are booting from RAM, the DRAM controller is + * already set up. Just return the memory size + */ + if (priv->flags & FLAG_RAM_RESIDENT) { + debug("Ram Boot: Skipping LMC config\n"); + return mem_size_mbytes; + } + + if (ddr_type == DDR4_DRAM) { + spd_ecc = + !!(read_spd + (&dimm_config_table[0], 0, + DDR4_SPD_MODULE_MEMORY_BUS_WIDTH) & 8); + } else { + spd_ecc = + !!(read_spd + (&dimm_config_table[0], 0, + DDR3_SPD_MEMORY_BUS_WIDTH) & 8); + } + + char rank_spec[8]; + + printable_rank_spec(rank_spec, num_ranks, dram_width, spd_package); + debug("Summary: %d %s%s %s %s, row bits=%d, col bits=%d, bank bits=%d\n", + dimm_count, dimm_type_name, (dimm_count > 1) ? "s" : "", + rank_spec, + (spd_ecc) ? "ECC" : "non-ECC", row_bits, col_bits, bank_bits); + + if (ddr_type == DDR4_DRAM) { + spd_cas_latency = + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_CAS_LATENCIES_BYTE0)) << 0); + spd_cas_latency |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_CAS_LATENCIES_BYTE1)) << 8); + spd_cas_latency |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_CAS_LATENCIES_BYTE2)) << 16); + spd_cas_latency |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR4_SPD_CAS_LATENCIES_BYTE3)) << 24); + } else { + spd_cas_latency = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_CAS_LATENCIES_LSB); + spd_cas_latency |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_CAS_LATENCIES_MSB)) << 8); + } + debug("spd_cas_latency : %#06x\n", spd_cas_latency); + + if (ddr_type == DDR4_DRAM) { + /* + * No other values for DDR4 MTB and FTB are specified at the + * current time so don't bother reading them. Can't speculate + * how new values will be represented. + */ + int spdmtb = 125; + int spdftb = 1; + + taamin = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_CAS_LATENCY_TAAMIN) + + spdftb * (signed char)read_spd(&dimm_config_table[0], + 0, DDR4_SPD_MIN_CAS_LATENCY_FINE_TAAMIN); + + ddr4_tckavgmin = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MINIMUM_CYCLE_TIME_TCKAVGMIN) + + spdftb * (signed char)read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_CYCLE_TIME_FINE_TCKAVGMIN); + + ddr4_tckavgmax = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MAXIMUM_CYCLE_TIME_TCKAVGMAX) + + spdftb * (signed char)read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MAX_CYCLE_TIME_FINE_TCKAVGMAX); + + ddr4_trdcmin = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_RAS_CAS_DELAY_TRCDMIN) + + spdftb * (signed char)read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_RAS_TO_CAS_DELAY_FINE_TRCDMIN); + + ddr4_trpmin = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_ROW_PRECHARGE_DELAY_TRPMIN) + + spdftb * (signed char)read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_ROW_PRECHARGE_DELAY_FINE_TRPMIN); + + ddr4_trasmin = spdmtb * + (((read_spd + (&dimm_config_table[0], 0, + DDR4_SPD_UPPER_NIBBLES_TRAS_TRC) & 0xf) << 8) + + (read_spd + (&dimm_config_table[0], 0, + DDR4_SPD_MIN_ACTIVE_PRECHARGE_LSB_TRASMIN) & 0xff)); + + ddr4_trcmin = spdmtb * + ((((read_spd + (&dimm_config_table[0], 0, + DDR4_SPD_UPPER_NIBBLES_TRAS_TRC) >> 4) & 0xf) << + 8) + (read_spd + (&dimm_config_table[0], 0, + DDR4_SPD_MIN_ACTIVE_REFRESH_LSB_TRCMIN) & + 0xff)) + + spdftb * (signed char)read_spd(&dimm_config_table[0], + 0, + DDR4_SPD_MIN_ACT_TO_ACT_REFRESH_DELAY_FINE_TRCMIN); + + ddr4_trfc1min = spdmtb * (((read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC1MIN) & 0xff) << + 8) + (read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC1MIN) & 0xff)); + + ddr4_trfc2min = spdmtb * (((read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC2MIN) & 0xff) << + 8) + (read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC2MIN) & 0xff)); + + ddr4_trfc4min = spdmtb * (((read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC4MIN) & 0xff) << + 8) + (read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC4MIN) & 0xff)); + + ddr4_tfawmin = spdmtb * (((read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_FOUR_ACTIVE_WINDOW_MSN_TFAWMIN) & 0xf) << + 8) + (read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_FOUR_ACTIVE_WINDOW_LSB_TFAWMIN) & 0xff)); + + ddr4_trrd_smin = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_ROW_ACTIVE_DELAY_SAME_TRRD_SMIN) + + spdftb * (signed char)read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_ACT_TO_ACT_DELAY_DIFF_FINE_TRRD_SMIN); + + ddr4_trrd_lmin = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_ROW_ACTIVE_DELAY_DIFF_TRRD_LMIN) + + spdftb * (signed char)read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_ACT_TO_ACT_DELAY_SAME_FINE_TRRD_LMIN); + + ddr4_tccd_lmin = spdmtb * read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_CAS_TO_CAS_DELAY_TCCD_LMIN) + + spdftb * (signed char)read_spd(&dimm_config_table[0], 0, + DDR4_SPD_MIN_CAS_TO_CAS_DELAY_FINE_TCCD_LMIN); + + debug("%-45s : %6d ps\n", "Medium Timebase (MTB)", spdmtb); + debug("%-45s : %6d ps\n", "Fine Timebase (FTB)", spdftb); + + debug("%-45s : %6d ps (%ld MT/s)\n", + "SDRAM Minimum Cycle Time (tCKAVGmin)", ddr4_tckavgmin, + pretty_psecs_to_mts(ddr4_tckavgmin)); + debug("%-45s : %6d ps\n", + "SDRAM Maximum Cycle Time (tCKAVGmax)", ddr4_tckavgmax); + debug("%-45s : %6d ps\n", "Minimum CAS Latency Time (taamin)", + taamin); + debug("%-45s : %6d ps\n", + "Minimum RAS to CAS Delay Time (tRCDmin)", ddr4_trdcmin); + debug("%-45s : %6d ps\n", + "Minimum Row Precharge Delay Time (tRPmin)", ddr4_trpmin); + debug("%-45s : %6d ps\n", + "Minimum Active to Precharge Delay (tRASmin)", + ddr4_trasmin); + debug("%-45s : %6d ps\n", + "Minimum Active to Active/Refr. Delay (tRCmin)", + ddr4_trcmin); + debug("%-45s : %6d ps\n", + "Minimum Refresh Recovery Delay (tRFC1min)", + ddr4_trfc1min); + debug("%-45s : %6d ps\n", + "Minimum Refresh Recovery Delay (tRFC2min)", + ddr4_trfc2min); + debug("%-45s : %6d ps\n", + "Minimum Refresh Recovery Delay (tRFC4min)", + ddr4_trfc4min); + debug("%-45s : %6d ps\n", + "Minimum Four Activate Window Time (tFAWmin)", + ddr4_tfawmin); + debug("%-45s : %6d ps\n", + "Minimum Act. to Act. Delay (tRRD_Smin)", ddr4_trrd_smin); + debug("%-45s : %6d ps\n", + "Minimum Act. to Act. Delay (tRRD_Lmin)", ddr4_trrd_lmin); + debug("%-45s : %6d ps\n", + "Minimum CAS to CAS Delay Time (tCCD_Lmin)", + ddr4_tccd_lmin); + +#define DDR4_TWR 15000 +#define DDR4_TWTR_S 2500 + + tckmin = ddr4_tckavgmin; + twr = DDR4_TWR; + trcd = ddr4_trdcmin; + trrd = ddr4_trrd_smin; + trp = ddr4_trpmin; + tras = ddr4_trasmin; + trc = ddr4_trcmin; + trfc = ddr4_trfc1min; + twtr = DDR4_TWTR_S; + tfaw = ddr4_tfawmin; + + if (spd_rdimm) { + spd_addr_mirror = read_spd(&dimm_config_table[0], 0, + DDR4_SPD_RDIMM_ADDR_MAPPING_FROM_REGISTER_TO_DRAM) & + 0x1; + } else { + spd_addr_mirror = read_spd(&dimm_config_table[0], 0, + DDR4_SPD_UDIMM_ADDR_MAPPING_FROM_EDGE) & 0x1; + } + debug("spd_addr_mirror : %#06x\n", spd_addr_mirror); + } else { + spd_mtb_dividend = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MEDIUM_TIMEBASE_DIVIDEND); + spd_mtb_divisor = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MEDIUM_TIMEBASE_DIVISOR); + spd_tck_min = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MINIMUM_CYCLE_TIME_TCKMIN); + spd_taa_min = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_CAS_LATENCY_TAAMIN); + + spd_twr = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_WRITE_RECOVERY_TWRMIN); + spd_trcd = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_RAS_CAS_DELAY_TRCDMIN); + spd_trrd = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_ROW_ACTIVE_DELAY_TRRDMIN); + spd_trp = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_ROW_PRECHARGE_DELAY_TRPMIN); + spd_tras = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_ACTIVE_PRECHARGE_LSB_TRASMIN); + spd_tras |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_UPPER_NIBBLES_TRAS_TRC) & 0xf) << 8); + spd_trc = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_ACTIVE_REFRESH_LSB_TRCMIN); + spd_trc |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_UPPER_NIBBLES_TRAS_TRC) & 0xf0) << 4); + spd_trfc = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_REFRESH_RECOVERY_LSB_TRFCMIN); + spd_trfc |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_REFRESH_RECOVERY_MSB_TRFCMIN)) << + 8); + spd_twtr = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_INTERNAL_WRITE_READ_CMD_TWTRMIN); + spd_trtp = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_INTERNAL_READ_PRECHARGE_CMD_TRTPMIN); + spd_tfaw = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_MIN_FOUR_ACTIVE_WINDOW_TFAWMIN); + spd_tfaw |= + ((0xff & + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_UPPER_NIBBLE_TFAW) & 0xf) << 8); + spd_addr_mirror = + 0xff & read_spd(&dimm_config_table[0], 0, + DDR3_SPD_ADDRESS_MAPPING) & 0x1; + /* Only address mirror unbuffered dimms. */ + spd_addr_mirror = spd_addr_mirror && !spd_rdimm; + ftb_dividend = + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_FINE_TIMEBASE_DIVIDEND_DIVISOR) >> 4; + ftb_divisor = + read_spd(&dimm_config_table[0], 0, + DDR3_SPD_FINE_TIMEBASE_DIVIDEND_DIVISOR) & 0xf; + /* Make sure that it is not 0 */ + ftb_divisor = (ftb_divisor == 0) ? 1 : ftb_divisor; + + debug("spd_twr : %#06x\n", spd_twr); + debug("spd_trcd : %#06x\n", spd_trcd); + debug("spd_trrd : %#06x\n", spd_trrd); + debug("spd_trp : %#06x\n", spd_trp); + debug("spd_tras : %#06x\n", spd_tras); + debug("spd_trc : %#06x\n", spd_trc); + debug("spd_trfc : %#06x\n", spd_trfc); + debug("spd_twtr : %#06x\n", spd_twtr); + debug("spd_trtp : %#06x\n", spd_trtp); + debug("spd_tfaw : %#06x\n", spd_tfaw); + debug("spd_addr_mirror : %#06x\n", spd_addr_mirror); + + mtb_psec = spd_mtb_dividend * 1000 / spd_mtb_divisor; + taamin = mtb_psec * spd_taa_min; + taamin += ftb_dividend * + (signed char)read_spd(&dimm_config_table[0], + 0, DDR3_SPD_MIN_CAS_LATENCY_FINE_TAAMIN) / + ftb_divisor; + tckmin = mtb_psec * spd_tck_min; + tckmin += ftb_dividend * + (signed char)read_spd(&dimm_config_table[0], + 0, DDR3_SPD_MINIMUM_CYCLE_TIME_FINE_TCKMIN) / + ftb_divisor; + + twr = spd_twr * mtb_psec; + trcd = spd_trcd * mtb_psec; + trrd = spd_trrd * mtb_psec; + trp = spd_trp * mtb_psec; + tras = spd_tras * mtb_psec; + trc = spd_trc * mtb_psec; + trfc = spd_trfc * mtb_psec; + if (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X) && trfc < 260000) { + // default to this - because it works... + int new_trfc = 260000; + + s = env_get("ddr_trfc"); + if (s) { + new_trfc = simple_strtoul(s, NULL, 0); + printf("Parameter found in environment. ddr_trfc = %d\n", + new_trfc); + if (new_trfc < 160000 || new_trfc > 260000) { + // back to default if out of range + new_trfc = 260000; + } + } + debug("N%d.LMC%d: Adjusting tRFC from %d to %d, for CN78XX Pass 2.x\n", + node, if_num, trfc, new_trfc); + trfc = new_trfc; + } + + twtr = spd_twtr * mtb_psec; + trtp = spd_trtp * mtb_psec; + tfaw = spd_tfaw * mtb_psec; + + debug("Medium Timebase (MTB) : %6d ps\n", + mtb_psec); + debug("Minimum Cycle Time (tckmin) : %6d ps (%ld MT/s)\n", + tckmin, pretty_psecs_to_mts(tckmin)); + debug("Minimum CAS Latency Time (taamin) : %6d ps\n", + taamin); + debug("Write Recovery Time (tWR) : %6d ps\n", + twr); + debug("Minimum RAS to CAS delay (tRCD) : %6d ps\n", + trcd); + debug("Minimum Row Active to Row Active delay (tRRD) : %6d ps\n", + trrd); + debug("Minimum Row Precharge Delay (tRP) : %6d ps\n", + trp); + debug("Minimum Active to Precharge (tRAS) : %6d ps\n", + tras); + debug("Minimum Active to Active/Refresh Delay (tRC) : %6d ps\n", + trc); + debug("Minimum Refresh Recovery Delay (tRFC) : %6d ps\n", + trfc); + debug("Internal write to read command delay (tWTR) : %6d ps\n", + twtr); + debug("Min Internal Rd to Precharge Cmd Delay (tRTP) : %6d ps\n", + trtp); + debug("Minimum Four Activate Window Delay (tFAW) : %6d ps\n", + tfaw); + } + + /* + * When the cycle time is within 1 psec of the minimum accept it + * as a slight rounding error and adjust it to exactly the minimum + * cycle time. This avoids an unnecessary warning. + */ + if (abs(tclk_psecs - tckmin) < 2) + tclk_psecs = tckmin; + + if (tclk_psecs < (u64)tckmin) { + printf("WARNING!!!!: DDR Clock Rate (tCLK: %ld) exceeds DIMM specifications (tckmin: %ld)!!!!\n", + tclk_psecs, (ulong)tckmin); + } + + debug("DDR Clock Rate (tCLK) : %6ld ps\n", + tclk_psecs); + debug("Core Clock Rate (eCLK) : %6ld ps\n", + eclk_psecs); + + s = env_get("ddr_use_ecc"); + if (s) { + use_ecc = !!simple_strtoul(s, NULL, 0); + printf("Parameter found in environment. ddr_use_ecc = %d\n", + use_ecc); + } + use_ecc = use_ecc && spd_ecc; + + if_bytemask = if_64b ? (use_ecc ? 0x1ff : 0xff) + : (use_ecc ? 0x01f : 0x0f); + + debug("DRAM Interface width: %d bits %s bytemask 0x%03x\n", + if_64b ? 64 : 32, use_ecc ? "+ECC" : "", if_bytemask); + + debug("\n------ Board Custom Configuration Settings ------\n"); + debug("%-45s : %d\n", "MIN_RTT_NOM_IDX ", c_cfg->min_rtt_nom_idx); + debug("%-45s : %d\n", "MAX_RTT_NOM_IDX ", c_cfg->max_rtt_nom_idx); + debug("%-45s : %d\n", "MIN_RODT_CTL ", c_cfg->min_rodt_ctl); + debug("%-45s : %d\n", "MAX_RODT_CTL ", c_cfg->max_rodt_ctl); + debug("%-45s : %d\n", "MIN_CAS_LATENCY ", c_cfg->min_cas_latency); + debug("%-45s : %d\n", "OFFSET_EN ", c_cfg->offset_en); + debug("%-45s : %d\n", "OFFSET_UDIMM ", c_cfg->offset_udimm); + debug("%-45s : %d\n", "OFFSET_RDIMM ", c_cfg->offset_rdimm); + debug("%-45s : %d\n", "DDR_RTT_NOM_AUTO ", c_cfg->ddr_rtt_nom_auto); + debug("%-45s : %d\n", "DDR_RODT_CTL_AUTO ", c_cfg->ddr_rodt_ctl_auto); + if (spd_rdimm) + debug("%-45s : %d\n", "RLEVEL_COMP_OFFSET", + c_cfg->rlevel_comp_offset_rdimm); + else + debug("%-45s : %d\n", "RLEVEL_COMP_OFFSET", + c_cfg->rlevel_comp_offset_udimm); + debug("%-45s : %d\n", "RLEVEL_COMPUTE ", c_cfg->rlevel_compute); + debug("%-45s : %d\n", "DDR2T_UDIMM ", c_cfg->ddr2t_udimm); + debug("%-45s : %d\n", "DDR2T_RDIMM ", c_cfg->ddr2t_rdimm); + debug("%-45s : %d\n", "FPRCH2 ", c_cfg->fprch2); + debug("%-45s : %d\n", "PTUNE_OFFSET ", c_cfg->ptune_offset); + debug("%-45s : %d\n", "NTUNE_OFFSET ", c_cfg->ntune_offset); + debug("-------------------------------------------------\n"); + + cl = divide_roundup(taamin, tclk_psecs); + + debug("Desired CAS Latency : %6d\n", cl); + + min_cas_latency = c_cfg->min_cas_latency; + + s = lookup_env(priv, "ddr_min_cas_latency"); + if (s) + min_cas_latency = simple_strtoul(s, NULL, 0); + + debug("CAS Latencies supported in DIMM :"); + base_cl = (ddr_type == DDR4_DRAM) ? 7 : 4; + for (i = 0; i < 32; ++i) { + if ((spd_cas_latency >> i) & 1) { + debug(" %d", i + base_cl); + max_cas_latency = i + base_cl; + if (min_cas_latency == 0) + min_cas_latency = i + base_cl; + } + } + debug("\n"); + + /* + * Use relaxed timing when running slower than the minimum + * supported speed. Adjust timing to match the smallest supported + * CAS Latency. + */ + if (min_cas_latency > cl) { + ulong adjusted_tclk = taamin / min_cas_latency; + + cl = min_cas_latency; + debug("Slow clock speed. Adjusting timing: tClk = %ld, Adjusted tClk = %ld\n", + tclk_psecs, adjusted_tclk); + tclk_psecs = adjusted_tclk; + } + + s = env_get("ddr_cas_latency"); + if (s) { + override_cas_latency = simple_strtoul(s, NULL, 0); + printf("Parameter found in environment. ddr_cas_latency = %d\n", + override_cas_latency); + } + + /* Make sure that the selected cas latency is legal */ + for (i = (cl - base_cl); i < 32; ++i) { + if ((spd_cas_latency >> i) & 1) { + cl = i + base_cl; + break; + } + } + + if (max_cas_latency < cl) + cl = max_cas_latency; + + if (override_cas_latency != 0) + cl = override_cas_latency; + + debug("CAS Latency : %6d\n", cl); + + if ((cl * tckmin) > 20000) { + debug("(CLactual * tckmin) = %d exceeds 20 ns\n", + (cl * tckmin)); + } + + if (tclk_psecs < (ulong)tckmin) { + printf("WARNING!!!!!!: DDR3 Clock Rate (tCLK: %ld) exceeds DIMM specifications (tckmin:%ld)!!!!!!!!\n", + tclk_psecs, (ulong)tckmin); + } + + if (num_banks != 4 && num_banks != 8 && num_banks != 16) { + printf("Unsupported number of banks %d. Must be 4 or 8.\n", + num_banks); + ++fatal_error; + } + + if (num_ranks != 1 && num_ranks != 2 && num_ranks != 4) { + printf("Unsupported number of ranks: %d\n", num_ranks); + ++fatal_error; + } + + if (octeon_is_cpuid(OCTEON_CN78XX) || + octeon_is_cpuid(OCTEON_CN73XX) || + octeon_is_cpuid(OCTEON_CNF75XX)) { + if (dram_width != 8 && dram_width != 16 && dram_width != 4) { + printf("Unsupported SDRAM Width, %d. Must be 4, 8 or 16.\n", + dram_width); + ++fatal_error; + } + } else if (dram_width != 8 && dram_width != 16) { + printf("Unsupported SDRAM Width, %d. Must be 8 or 16.\n", + dram_width); + ++fatal_error; + } + + /* + ** Bail out here if things are not copasetic. + */ + if (fatal_error) + return (-1); + + /* + * 4.8.4 LMC RESET Initialization + * + * The purpose of this step is to assert/deassert the RESET# pin at the + * DDR3/DDR4 parts. + * + * This LMC RESET step is done for all enabled LMCs. + */ + perform_lmc_reset(priv, node, if_num); + + // Make sure scrambling is disabled during init... + ctrl.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + ctrl.s.scramble_ena = 0; + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), ctrl.u64); + + lmc_wr(priv, CVMX_LMCX_SCRAMBLE_CFG0(if_num), 0); + lmc_wr(priv, CVMX_LMCX_SCRAMBLE_CFG1(if_num), 0); + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS1_X)) + lmc_wr(priv, CVMX_LMCX_SCRAMBLE_CFG2(if_num), 0); + + odt_idx = min(dimm_count - 1, 3); + + switch (num_ranks) { + case 1: + odt_config = odt_1rank_config; + break; + case 2: + odt_config = odt_2rank_config; + break; + case 4: + odt_config = odt_4rank_config; + break; + default: + odt_config = disable_odt_config; + printf("Unsupported number of ranks: %d\n", num_ranks); + ++fatal_error; + } + + /* + * 4.8.5 Early LMC Initialization + * + * All of DDR PLL, LMC CK, and LMC DRESET initializations must be + * completed prior to starting this LMC initialization sequence. + * + * Perform the following five substeps for early LMC initialization: + * + * 1. Software must ensure there are no pending DRAM transactions. + * + * 2. Write LMC(0)_CONFIG, LMC(0)_CONTROL, LMC(0)_TIMING_PARAMS0, + * LMC(0)_TIMING_PARAMS1, LMC(0)_MODEREG_PARAMS0, + * LMC(0)_MODEREG_PARAMS1, LMC(0)_DUAL_MEMCFG, LMC(0)_NXM, + * LMC(0)_WODT_MASK, LMC(0)_RODT_MASK, LMC(0)_COMP_CTL2, + * LMC(0)_PHY_CTL, LMC(0)_DIMM0/1_PARAMS, and LMC(0)_DIMM_CTL with + * appropriate values. All sections in this chapter can be used to + * derive proper register settings. + */ + + /* LMC(0)_CONFIG */ + lmc_config(priv); + + /* LMC(0)_CONTROL */ + lmc_control(priv); + + /* LMC(0)_TIMING_PARAMS0 */ + lmc_timing_params0(priv); + + /* LMC(0)_TIMING_PARAMS1 */ + lmc_timing_params1(priv); + + /* LMC(0)_TIMING_PARAMS2 */ + lmc_timing_params2(priv); + + /* LMC(0)_MODEREG_PARAMS0 */ + lmc_modereg_params0(priv); + + /* LMC(0)_MODEREG_PARAMS1 */ + lmc_modereg_params1(priv); + + /* LMC(0)_MODEREG_PARAMS2 */ + lmc_modereg_params2(priv); + + /* LMC(0)_MODEREG_PARAMS3 */ + lmc_modereg_params3(priv); + + /* LMC(0)_NXM */ + lmc_nxm(priv); + + /* LMC(0)_WODT_MASK */ + lmc_wodt_mask(priv); + + /* LMC(0)_RODT_MASK */ + lmc_rodt_mask(priv); + + /* LMC(0)_COMP_CTL2 */ + lmc_comp_ctl2(priv); + + /* LMC(0)_PHY_CTL */ + lmc_phy_ctl(priv); + + /* LMC(0)_EXT_CONFIG */ + lmc_ext_config(priv); + + /* LMC(0)_EXT_CONFIG2 */ + lmc_ext_config2(priv); + + /* LMC(0)_DIMM0/1_PARAMS */ + lmc_dimm01_params(priv); + + ret = lmc_rank_init(priv); + if (ret < 0) + return 0; /* 0 indicates problem */ + + lmc_config_2(priv); + + lmc_write_leveling(priv); + + lmc_read_leveling(priv); + + lmc_workaround(priv); + + ret = lmc_sw_write_leveling(priv); + if (ret < 0) + return 0; /* 0 indicates problem */ + + // this sometimes causes stack overflow crashes.. + // display only for DDR4 RDIMMs. + if (ddr_type == DDR4_DRAM && spd_rdimm) { + int i; + + for (i = 0; i < 3; i += 2) // just pages 0 and 2 for now.. + display_mpr_page(priv, rank_mask, if_num, i); + } + + lmc_dll(priv); + + lmc_workaround_2(priv); + + lmc_final(priv); + + lmc_scrambling(priv); + + return mem_size_mbytes; +} + +///// HW-assist byte DLL offset tuning ////// + +static int cvmx_dram_get_num_lmc(struct ddr_priv *priv) +{ + union cvmx_lmcx_dll_ctl2 lmcx_dll_ctl2; + + if (octeon_is_cpuid(OCTEON_CN70XX)) + return 1; + + if (octeon_is_cpuid(OCTEON_CN73XX) || octeon_is_cpuid(OCTEON_CNF75XX)) { + // sample LMC1 + lmcx_dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(1)); + if (lmcx_dll_ctl2.cn78xx.intf_en) + return 2; + else + return 1; + } + + // for CN78XX, LMCs are always active in pairs, and always LMC0/1 + // so, we sample LMC2 to see if 2 and 3 are active + lmcx_dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(2)); + if (lmcx_dll_ctl2.cn78xx.intf_en) + return 4; + else + return 2; +} + +// got to do these here, even though already defined in BDK + +// all DDR3, and DDR4 x16 today, use only 3 bank bits; +// DDR4 x4 and x8 always have 4 bank bits +// NOTE: this will change in the future, when DDR4 x16 devices can +// come with 16 banks!! FIXME!! +static int cvmx_dram_get_num_bank_bits(struct ddr_priv *priv, int lmc) +{ + union cvmx_lmcx_dll_ctl2 lmcx_dll_ctl2; + union cvmx_lmcx_config lmcx_config; + union cvmx_lmcx_ddr_pll_ctl lmcx_ddr_pll_ctl; + int bank_width; + + // can always read this + lmcx_dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(lmc)); + + if (lmcx_dll_ctl2.cn78xx.dreset) // check LMCn + return 0; + + lmcx_config.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(lmc)); + lmcx_ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(lmc)); + + bank_width = ((lmcx_ddr_pll_ctl.s.ddr4_mode != 0) && + (lmcx_config.s.bg2_enable)) ? 4 : 3; + + return bank_width; +} + +#define EXTRACT(v, lsb, width) (((v) >> (lsb)) & ((1ull << (width)) - 1)) +#define ADDRESS_HOLE 0x10000000ULL + +static void cvmx_dram_address_extract_info(struct ddr_priv *priv, u64 address, + int *node, int *lmc, int *dimm, + int *prank, int *lrank, int *bank, + int *row, int *col) +{ + int bank_lsb, xbits; + union cvmx_l2c_ctl l2c_ctl; + union cvmx_lmcx_config lmcx_config; + union cvmx_lmcx_control lmcx_control; + union cvmx_lmcx_ext_config ext_config; + int bitno = (octeon_is_cpuid(OCTEON_CN7XXX)) ? 20 : 18; + int bank_width; + int dimm_lsb; + int dimm_width; + int prank_lsb, lrank_lsb; + int prank_width, lrank_width; + int row_lsb; + int row_width; + int col_hi_lsb; + int col_hi_width; + int col_hi; + + if (octeon_is_cpuid(OCTEON_CN73XX) || octeon_is_cpuid(OCTEON_CNF75XX)) + bitno = 18; + + *node = EXTRACT(address, 40, 2); /* Address bits [41:40] */ + + address &= (1ULL << 40) - 1; // lop off any node bits or above + if (address >= ADDRESS_HOLE) // adjust down if at HOLE or above + address -= ADDRESS_HOLE; + + /* Determine the LMC controllers */ + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + + /* xbits depends on number of LMCs */ + xbits = cvmx_dram_get_num_lmc(priv) >> 1; // 4->2, 2->1, 1->0 + bank_lsb = 7 + xbits; + + /* LMC number is probably aliased */ + if (l2c_ctl.s.disidxalias) { + *lmc = EXTRACT(address, 7, xbits); + } else { + *lmc = EXTRACT(address, 7, xbits) ^ + EXTRACT(address, bitno, xbits) ^ + EXTRACT(address, 12, xbits); + } + + /* Figure out the bank field width */ + lmcx_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(*lmc)); + ext_config.u64 = lmc_rd(priv, CVMX_LMCX_EXT_CONFIG(*lmc)); + bank_width = cvmx_dram_get_num_bank_bits(priv, *lmc); + + /* Extract additional info from the LMC_CONFIG CSR */ + dimm_lsb = 28 + lmcx_config.s.pbank_lsb + xbits; + dimm_width = 40 - dimm_lsb; + prank_lsb = dimm_lsb - lmcx_config.s.rank_ena; + prank_width = dimm_lsb - prank_lsb; + lrank_lsb = prank_lsb - ext_config.s.dimm0_cid; + lrank_width = prank_lsb - lrank_lsb; + row_lsb = 14 + lmcx_config.s.row_lsb + xbits; + row_width = lrank_lsb - row_lsb; + col_hi_lsb = bank_lsb + bank_width; + col_hi_width = row_lsb - col_hi_lsb; + + /* Extract the parts of the address */ + *dimm = EXTRACT(address, dimm_lsb, dimm_width); + *prank = EXTRACT(address, prank_lsb, prank_width); + *lrank = EXTRACT(address, lrank_lsb, lrank_width); + *row = EXTRACT(address, row_lsb, row_width); + + /* bank calculation may be aliased... */ + lmcx_control.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(*lmc)); + if (lmcx_control.s.xor_bank) { + *bank = EXTRACT(address, bank_lsb, bank_width) ^ + EXTRACT(address, 12 + xbits, bank_width); + } else { + *bank = EXTRACT(address, bank_lsb, bank_width); + } + + /* LMC number already extracted */ + col_hi = EXTRACT(address, col_hi_lsb, col_hi_width); + *col = EXTRACT(address, 3, 4) | (col_hi << 4); + /* Bus byte is address bits [2:0]. Unused here */ +} + +// end of added workarounds + +// NOTE: "mode" argument: +// DBTRAIN_TEST: for testing using GP patterns, includes ECC +// DBTRAIN_DBI: for DBI deskew training behavior (uses GP patterns) +// DBTRAIN_LFSR: for testing using LFSR patterns, includes ECC +// NOTE: trust the caller to specify the correct/supported mode +// +static int test_dram_byte_hw(struct ddr_priv *priv, int if_num, u64 p, + int mode, u64 *xor_data) +{ + u64 p1; + u64 k; + int errors = 0; + + u64 mpr_data0, mpr_data1; + u64 bad_bits[2] = { 0, 0 }; + + int node_address, lmc, dimm; + int prank, lrank; + int bank, row, col; + int save_or_dis; + int byte; + int ba_loop, ba_bits; + + union cvmx_lmcx_rlevel_ctl rlevel_ctl; + union cvmx_lmcx_dbtrain_ctl dbtrain_ctl; + union cvmx_lmcx_phy_ctl phy_ctl; + + int biter_errs; + + // FIXME: K iterations set to 4 for now. + // FIXME: decrement to increase interations. + // FIXME: must be no less than 22 to stay above an LMC hash field. + int kshift = 27; + + const char *s; + int node = 0; + + // allow override default setting for kshift + s = env_get("ddr_tune_set_kshift"); + if (s) { + int temp = simple_strtoul(s, NULL, 0); + + if (temp < 22 || temp > 28) { + debug("N%d.LMC%d: ILLEGAL override of kshift to %d, using default %d\n", + node, if_num, temp, kshift); + } else { + debug("N%d.LMC%d: overriding kshift (%d) to %d\n", + node, if_num, kshift, temp); + kshift = temp; + } + } + + /* + * 1) Make sure that RLEVEL_CTL[OR_DIS] = 0. + */ + rlevel_ctl.u64 = lmc_rd(priv, CVMX_LMCX_RLEVEL_CTL(if_num)); + save_or_dis = rlevel_ctl.s.or_dis; + /* or_dis must be disabled for this sequence */ + rlevel_ctl.s.or_dis = 0; + lmc_wr(priv, CVMX_LMCX_RLEVEL_CTL(if_num), rlevel_ctl.u64); + + /* + * NOTE: this step done in the calling routine(s)... + * 3) Setup GENERAL_PURPOSE[0-2] registers with the data pattern + * of choice. + * a. GENERAL_PURPOSE0[DATA<63:0>] – sets the initial lower + * (rising edge) 64 bits of data. + * b. GENERAL_PURPOSE1[DATA<63:0>] – sets the initial upper + * (falling edge) 64 bits of data. + * c. GENERAL_PURPOSE2[DATA<15:0>] – sets the initial lower + * (rising edge <7:0>) and upper (falling edge <15:8>) ECC data. + */ + + // final address must include LMC and node + p |= (if_num << 7); /* Map address into proper interface */ + p |= (u64)node << CVMX_NODE_MEM_SHIFT; // map to node + + /* + * Add base offset to both test regions to not clobber u-boot stuff + * when running from L2 for NAND boot. + */ + p += 0x20000000; // offset to 512MB, ie above THE HOLE!!! + p |= 1ull << 63; // needed for OCTEON + + errors = 0; + + cvmx_dram_address_extract_info(priv, p, &node_address, &lmc, &dimm, + &prank, &lrank, &bank, &row, &col); + debug("%s: START at A:0x%012llx, N%d L%d D%d/%d R%d B%1x Row:%05x Col:%05x\n", + __func__, p, node_address, lmc, dimm, prank, lrank, bank, + row, col); + + // only check once per call, and ignore if no match... + if ((int)node != node_address) { + printf("ERROR: Node address mismatch\n"); + return 0; + } + if (lmc != if_num) { + printf("ERROR: LMC address mismatch\n"); + return 0; + } + + /* + * 7) Set PHY_CTL[PHY_RESET] = 1 (LMC automatically clears this as + * it’s a one-shot operation). This is to get into the habit of + * resetting PHY’s SILO to the original 0 location. + */ + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.phy_reset = 1; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + /* + * Walk through a range of addresses avoiding bits that alias + * interfaces on the CN88XX. + */ + + // FIXME: want to try to keep the K increment from affecting the + // LMC via hash, so keep it above bit 21 we also want to keep k + // less than the base offset of bit 29 (512MB) + + for (k = 0; k < (1UL << 29); k += (1UL << kshift)) { + // FIXME: the sequence will interate over 1/2 cacheline + // FIXME: for each unit specified in "read_cmd_count", + // FIXME: so, we setup each sequence to do the max cachelines + // it can + + p1 = p + k; + + cvmx_dram_address_extract_info(priv, p1, &node_address, &lmc, + &dimm, &prank, &lrank, &bank, + &row, &col); + + /* + * 2) Setup the fields of the CSR DBTRAIN_CTL as follows: + * a. COL, ROW, BA, BG, PRANK points to the starting point + * of the address. + * You can just set them to all 0. + * b. RW_TRAIN – set this to 1. + * c. TCCD_L – set this to 0. + * d. READ_CMD_COUNT – instruct the sequence to the how many + * writes/reads. + * It is 5 bits field, so set to 31 of maximum # of r/w. + */ + dbtrain_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DBTRAIN_CTL(if_num)); + dbtrain_ctl.s.column_a = col; + dbtrain_ctl.s.row_a = row; + dbtrain_ctl.s.bg = (bank >> 2) & 3; + dbtrain_ctl.s.prank = (dimm * 2) + prank; // FIXME? + dbtrain_ctl.s.lrank = lrank; // FIXME? + dbtrain_ctl.s.activate = (mode == DBTRAIN_DBI); + dbtrain_ctl.s.write_ena = 1; + dbtrain_ctl.s.read_cmd_count = 31; // max count pass 1.x + if (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X) || + octeon_is_cpuid(OCTEON_CNF75XX)) { + // max count on chips that support it + dbtrain_ctl.s.cmd_count_ext = 3; + } else { + // max count pass 1.x + dbtrain_ctl.s.cmd_count_ext = 0; + } + + dbtrain_ctl.s.rw_train = 1; + dbtrain_ctl.s.tccd_sel = (mode == DBTRAIN_DBI); + // LFSR should only be on when chip supports it... + dbtrain_ctl.s.lfsr_pattern_sel = (mode == DBTRAIN_LFSR) ? 1 : 0; + + biter_errs = 0; + + // for each address, iterate over the 4 "banks" in the BA + for (ba_loop = 0, ba_bits = bank & 3; + ba_loop < 4; ba_loop++, ba_bits = (ba_bits + 1) & 3) { + dbtrain_ctl.s.ba = ba_bits; + lmc_wr(priv, CVMX_LMCX_DBTRAIN_CTL(if_num), + dbtrain_ctl.u64); + + /* + * We will use the RW_TRAINING sequence (14) for + * this task. + * + * 4) Kick off the sequence (SEQ_CTL[SEQ_SEL] = 14, + * SEQ_CTL[INIT_START] = 1). + * 5) Poll on SEQ_CTL[SEQ_COMPLETE] for completion. + */ + oct3_ddr3_seq(priv, prank, if_num, 14); + + /* + * 6) Read MPR_DATA0 and MPR_DATA1 for results. + * a. MPR_DATA0[MPR_DATA<63:0>] – comparison results + * for DQ63:DQ0. (1 means MATCH, 0 means FAIL). + * b. MPR_DATA1[MPR_DATA<7:0>] – comparison results + * for ECC bit7:0. + */ + mpr_data0 = lmc_rd(priv, CVMX_LMCX_MPR_DATA0(if_num)); + mpr_data1 = lmc_rd(priv, CVMX_LMCX_MPR_DATA1(if_num)); + + /* + * 7) Set PHY_CTL[PHY_RESET] = 1 (LMC automatically + * clears this as it’s a one-shot operation). + * This is to get into the habit of resetting PHY’s + * SILO to the original 0 location. + */ + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(if_num)); + phy_ctl.s.phy_reset = 1; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(if_num), phy_ctl.u64); + + // bypass any error checking or updating when DBI mode + if (mode == DBTRAIN_DBI) + continue; + + // data bytes + if (~mpr_data0) { + for (byte = 0; byte < 8; byte++) { + if ((~mpr_data0 >> (8 * byte)) & 0xffUL) + biter_errs |= (1 << byte); + } + // accumulate bad bits + bad_bits[0] |= ~mpr_data0; + } + + // include ECC byte errors + if (~mpr_data1 & 0xffUL) { + biter_errs |= (1 << 8); + bad_bits[1] |= ~mpr_data1 & 0xffUL; + } + } + + errors |= biter_errs; + } /* end for (k=...) */ + + rlevel_ctl.s.or_dis = save_or_dis; + lmc_wr(priv, CVMX_LMCX_RLEVEL_CTL(if_num), rlevel_ctl.u64); + + // send the bad bits back... + if (mode != DBTRAIN_DBI && xor_data) { + xor_data[0] = bad_bits[0]; + xor_data[1] = bad_bits[1]; + } + + return errors; +} + +// setup default for byte test pattern array +// take these from the HRM section 6.9.13 +static const u64 byte_pattern_0[] = { + 0xFFAAFFFFFF55FFFFULL, // GP0 + 0x55555555AAAAAAAAULL, // GP1 + 0xAA55AAAAULL, // GP2 +}; + +static const u64 byte_pattern_1[] = { + 0xFBF7EFDFBF7FFEFDULL, // GP0 + 0x0F1E3C78F0E1C387ULL, // GP1 + 0xF0E1BF7FULL, // GP2 +}; + +// this is from Andrew via LFSR with PRBS=0xFFFFAAAA +static const u64 byte_pattern_2[] = { + 0xEE55AADDEE55AADDULL, // GP0 + 0x55AADDEE55AADDEEULL, // GP1 + 0x55EEULL, // GP2 +}; + +// this is from Mike via LFSR with PRBS=0x4A519909 +static const u64 byte_pattern_3[] = { + 0x0088CCEE0088CCEEULL, // GP0 + 0xBB552211BB552211ULL, // GP1 + 0xBB00ULL, // GP2 +}; + +static const u64 *byte_patterns[4] = { + byte_pattern_0, byte_pattern_1, byte_pattern_2, byte_pattern_3 +}; + +static const u32 lfsr_patterns[4] = { + 0xFFFFAAAAUL, 0x06000000UL, 0xAAAAFFFFUL, 0x4A519909UL +}; + +#define NUM_BYTE_PATTERNS 4 + +#define DEFAULT_BYTE_BURSTS 32 // compromise between time and rigor + +static void setup_hw_pattern(struct ddr_priv *priv, int lmc, + const u64 *pattern_p) +{ + /* + * 3) Setup GENERAL_PURPOSE[0-2] registers with the data pattern + * of choice. + * a. GENERAL_PURPOSE0[DATA<63:0>] – sets the initial lower + * (rising edge) 64 bits of data. + * b. GENERAL_PURPOSE1[DATA<63:0>] – sets the initial upper + * (falling edge) 64 bits of data. + * c. GENERAL_PURPOSE2[DATA<15:0>] – sets the initial lower + * (rising edge <7:0>) and upper + * (falling edge <15:8>) ECC data. + */ + lmc_wr(priv, CVMX_LMCX_GENERAL_PURPOSE0(lmc), pattern_p[0]); + lmc_wr(priv, CVMX_LMCX_GENERAL_PURPOSE1(lmc), pattern_p[1]); + lmc_wr(priv, CVMX_LMCX_GENERAL_PURPOSE2(lmc), pattern_p[2]); +} + +static void setup_lfsr_pattern(struct ddr_priv *priv, int lmc, u32 data) +{ + union cvmx_lmcx_char_ctl char_ctl; + u32 prbs; + const char *s; + + s = env_get("ddr_lfsr_prbs"); + if (s) + prbs = simple_strtoul(s, NULL, 0); + else + prbs = data; + + /* + * 2) DBTRAIN_CTL[LFSR_PATTERN_SEL] = 1 + * here data comes from the LFSR generating a PRBS pattern + * CHAR_CTL.EN = 0 + * CHAR_CTL.SEL = 0; // for PRBS + * CHAR_CTL.DR = 1; + * CHAR_CTL.PRBS = setup for whatever type of PRBS to send + * CHAR_CTL.SKEW_ON = 1; + */ + char_ctl.u64 = lmc_rd(priv, CVMX_LMCX_CHAR_CTL(lmc)); + char_ctl.s.en = 0; + char_ctl.s.sel = 0; + char_ctl.s.dr = 1; + char_ctl.s.prbs = prbs; + char_ctl.s.skew_on = 1; + lmc_wr(priv, CVMX_LMCX_CHAR_CTL(lmc), char_ctl.u64); +} + +static int choose_best_hw_patterns(int lmc, int mode) +{ + int new_mode = mode; + const char *s; + + switch (mode) { + case DBTRAIN_TEST: // always choose LFSR if chip supports it + if (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X)) { + int lfsr_enable = 1; + + s = env_get("ddr_allow_lfsr"); + if (s) { + // override? + lfsr_enable = !!strtoul(s, NULL, 0); + } + + if (lfsr_enable) + new_mode = DBTRAIN_LFSR; + } + break; + + case DBTRAIN_DBI: // possibly can allow LFSR use? + break; + + case DBTRAIN_LFSR: // forced already + if (!octeon_is_cpuid(OCTEON_CN78XX_PASS2_X)) { + debug("ERROR: illegal HW assist mode %d\n", mode); + new_mode = DBTRAIN_TEST; + } + break; + + default: + debug("ERROR: unknown HW assist mode %d\n", mode); + } + + if (new_mode != mode) + debug("%s: changing mode %d to %d\n", __func__, mode, new_mode); + + return new_mode; +} + +int run_best_hw_patterns(struct ddr_priv *priv, int lmc, u64 phys_addr, + int mode, u64 *xor_data) +{ + int pattern; + const u64 *pattern_p; + int errs, errors = 0; + + // FIXME? always choose LFSR if chip supports it??? + mode = choose_best_hw_patterns(lmc, mode); + + for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) { + if (mode == DBTRAIN_LFSR) { + setup_lfsr_pattern(priv, lmc, lfsr_patterns[pattern]); + } else { + pattern_p = byte_patterns[pattern]; + setup_hw_pattern(priv, lmc, pattern_p); + } + errs = test_dram_byte_hw(priv, lmc, phys_addr, mode, xor_data); + + debug("%s: PATTERN %d at A:0x%012llx errors 0x%x\n", + __func__, pattern, phys_addr, errs); + + errors |= errs; + } + + return errors; +} + +static void hw_assist_test_dll_offset(struct ddr_priv *priv, + int dll_offset_mode, int lmc, + int bytelane, + int if_64b, + u64 dram_tune_rank_offset, + int dram_tune_byte_bursts) +{ + int byte_offset, new_best_offset[9]; + int rank_delay_start[4][9]; + int rank_delay_count[4][9]; + int rank_delay_best_start[4][9]; + int rank_delay_best_count[4][9]; + int errors[4], off_errors, tot_errors; + int rank_mask, rankx, active_ranks; + int pattern; + const u64 *pattern_p; + int byte; + char *mode_str = (dll_offset_mode == 2) ? "Read" : "Write"; + int pat_best_offset[9]; + u64 phys_addr; + int pat_beg, pat_end; + int rank_beg, rank_end; + int byte_lo, byte_hi; + union cvmx_lmcx_config lmcx_config; + u64 hw_rank_offset; + int num_lmcs = cvmx_dram_get_num_lmc(priv); + // FIXME? always choose LFSR if chip supports it??? + int mode = choose_best_hw_patterns(lmc, DBTRAIN_TEST); + int node = 0; + + if (bytelane == 0x0A) { // all bytelanes + byte_lo = 0; + byte_hi = 8; + } else { // just 1 + byte_lo = bytelane; + byte_hi = bytelane; + } + + lmcx_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(lmc)); + rank_mask = lmcx_config.s.init_status; + + // this should be correct for 1 or 2 ranks, 1 or 2 DIMMs + hw_rank_offset = + 1ull << (28 + lmcx_config.s.pbank_lsb - lmcx_config.s.rank_ena + + (num_lmcs / 2)); + + debug("N%d: %s: starting LMC%d with rank offset 0x%016llx\n", + node, __func__, lmc, (unsigned long long)hw_rank_offset); + + // start of pattern loop + // we do the set of tests for each pattern supplied... + + memset(new_best_offset, 0, sizeof(new_best_offset)); + for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) { + memset(pat_best_offset, 0, sizeof(pat_best_offset)); + + if (mode == DBTRAIN_TEST) { + pattern_p = byte_patterns[pattern]; + setup_hw_pattern(priv, lmc, pattern_p); + } else { + setup_lfsr_pattern(priv, lmc, lfsr_patterns[pattern]); + } + + // now loop through all legal values for the DLL byte offset... + +#define BYTE_OFFSET_INCR 3 // FIXME: make this tunable? + + tot_errors = 0; + + memset(rank_delay_count, 0, sizeof(rank_delay_count)); + memset(rank_delay_start, 0, sizeof(rank_delay_start)); + memset(rank_delay_best_count, 0, sizeof(rank_delay_best_count)); + memset(rank_delay_best_start, 0, sizeof(rank_delay_best_start)); + + for (byte_offset = -63; byte_offset < 64; + byte_offset += BYTE_OFFSET_INCR) { + // do the setup on the active LMC + // set the bytelanes DLL offsets + change_dll_offset_enable(priv, lmc, 0); + // FIXME? bytelane? + load_dll_offset(priv, lmc, dll_offset_mode, + byte_offset, bytelane); + change_dll_offset_enable(priv, lmc, 1); + + //bdk_watchdog_poke(); + + // run the test on each rank + // only 1 call per rank should be enough, let the + // bursts, loops, etc, control the load... + + // errors for this byte_offset, all ranks + off_errors = 0; + + active_ranks = 0; + + for (rankx = 0; rankx < 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + phys_addr = hw_rank_offset * active_ranks; + // FIXME: now done by test_dram_byte_hw() + //phys_addr |= (lmc << 7); + //phys_addr |= (u64)node << CVMX_NODE_MEM_SHIFT; + + active_ranks++; + + // NOTE: return is a now a bitmask of the + // erroring bytelanes. + errors[rankx] = + test_dram_byte_hw(priv, lmc, phys_addr, + mode, NULL); + + // process any errors in the bytelane(s) that + // are being tested + for (byte = byte_lo; byte <= byte_hi; byte++) { + // check errors + // yes, an error in the byte lane in + // this rank + if (errors[rankx] & (1 << byte)) { + off_errors |= (1 << byte); + + debug("N%d.LMC%d.R%d: Bytelane %d DLL %s Offset Test %3d: Address 0x%012llx errors\n", + node, lmc, rankx, byte, + mode_str, byte_offset, + phys_addr); + + // had started run + if (rank_delay_count + [rankx][byte] > 0) { + debug("N%d.LMC%d.R%d: Bytelane %d DLL %s Offset Test %3d: stopping a run here\n", + node, lmc, rankx, + byte, mode_str, + byte_offset); + // stop now + rank_delay_count + [rankx][byte] = + 0; + } + // FIXME: else had not started + // run - nothing else to do? + } else { + // no error in the byte lane + // first success, set run start + if (rank_delay_count[rankx] + [byte] == 0) { + debug("N%d.LMC%d.R%d: Bytelane %d DLL %s Offset Test %3d: starting a run here\n", + node, lmc, rankx, + byte, mode_str, + byte_offset); + rank_delay_start[rankx] + [byte] = + byte_offset; + } + // bump run length + rank_delay_count[rankx][byte] + += BYTE_OFFSET_INCR; + + // is this now the biggest + // window? + if (rank_delay_count[rankx] + [byte] > + rank_delay_best_count[rankx] + [byte]) { + rank_delay_best_count + [rankx][byte] = + rank_delay_count + [rankx][byte]; + rank_delay_best_start + [rankx][byte] = + rank_delay_start + [rankx][byte]; + debug("N%d.LMC%d.R%d: Bytelane %d DLL %s Offset Test %3d: updating best to %d/%d\n", + node, lmc, rankx, + byte, mode_str, + byte_offset, + rank_delay_best_start + [rankx][byte], + rank_delay_best_count + [rankx][byte]); + } + } + } + } /* for (rankx = 0; rankx < 4; rankx++) */ + + tot_errors |= off_errors; + } + + // set the bytelanes DLL offsets all back to 0 + change_dll_offset_enable(priv, lmc, 0); + load_dll_offset(priv, lmc, dll_offset_mode, 0, bytelane); + change_dll_offset_enable(priv, lmc, 1); + + // now choose the best byte_offsets for this pattern + // according to the best windows of the tested ranks + // calculate offset by constructing an average window + // from the rank windows + for (byte = byte_lo; byte <= byte_hi; byte++) { + pat_beg = -999; + pat_end = 999; + + for (rankx = 0; rankx < 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + rank_beg = rank_delay_best_start[rankx][byte]; + pat_beg = max(pat_beg, rank_beg); + rank_end = rank_beg + + rank_delay_best_count[rankx][byte] - + BYTE_OFFSET_INCR; + pat_end = min(pat_end, rank_end); + + debug("N%d.LMC%d.R%d: Bytelane %d DLL %s Offset Test: Rank Window %3d:%3d\n", + node, lmc, rankx, byte, mode_str, + rank_beg, rank_end); + + } /* for (rankx = 0; rankx < 4; rankx++) */ + + pat_best_offset[byte] = (pat_end + pat_beg) / 2; + + // sum the pattern averages + new_best_offset[byte] += pat_best_offset[byte]; + } + + // now print them on 1 line, descending order... + debug("N%d.LMC%d: HW DLL %s Offset Pattern %d :", + node, lmc, mode_str, pattern); + for (byte = byte_hi; byte >= byte_lo; --byte) + debug(" %4d", pat_best_offset[byte]); + debug("\n"); + } + // end of pattern loop + + debug("N%d.LMC%d: HW DLL %s Offset Average : ", node, lmc, mode_str); + + // print in decending byte index order + for (byte = byte_hi; byte >= byte_lo; --byte) { + // create the new average NINT + new_best_offset[byte] = divide_nint(new_best_offset[byte], + NUM_BYTE_PATTERNS); + + // print the best offsets from all patterns + + // print just the offset of all the bytes + if (bytelane == 0x0A) + debug("%4d ", new_best_offset[byte]); + else // print the bytelanes also + debug("(byte %d) %4d ", byte, new_best_offset[byte]); + + // done with testing, load up the best offsets we found... + // disable offsets while we load... + change_dll_offset_enable(priv, lmc, 0); + load_dll_offset(priv, lmc, dll_offset_mode, + new_best_offset[byte], byte); + // re-enable the offsets now that we are done loading + change_dll_offset_enable(priv, lmc, 1); + } + + debug("\n"); +} + +/* + * Automatically adjust the DLL offset for the selected bytelane using + * hardware-assist + */ +static int perform_HW_dll_offset_tuning(struct ddr_priv *priv, + int dll_offset_mode, int bytelane) +{ + int if_64b; + int save_ecc_ena[4]; + union cvmx_lmcx_config lmc_config; + int lmc, num_lmcs = cvmx_dram_get_num_lmc(priv); + const char *s; + int loops = 1, loop; + int by; + u64 dram_tune_rank_offset; + int dram_tune_byte_bursts = DEFAULT_BYTE_BURSTS; + int node = 0; + + // see if we want to do the tuning more than once per LMC... + s = env_get("ddr_tune_ecc_loops"); + if (s) + loops = strtoul(s, NULL, 0); + + // allow override of the test repeats (bursts) + s = env_get("ddr_tune_byte_bursts"); + if (s) + dram_tune_byte_bursts = strtoul(s, NULL, 10); + + // print current working values + debug("N%d: H/W Tuning for bytelane %d will use %d loops, %d bursts, and %d patterns.\n", + node, bytelane, loops, dram_tune_byte_bursts, NUM_BYTE_PATTERNS); + + // FIXME? get flag from LMC0 only + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(0)); + if_64b = !lmc_config.s.mode32b; + + // this should be correct for 1 or 2 ranks, 1 or 2 DIMMs + dram_tune_rank_offset = + 1ull << (28 + lmc_config.s.pbank_lsb - lmc_config.s.rank_ena + + (num_lmcs / 2)); + + // do once for each active LMC + + for (lmc = 0; lmc < num_lmcs; lmc++) { + debug("N%d: H/W Tuning: starting LMC%d bytelane %d tune.\n", + node, lmc, bytelane); + + /* Enable ECC for the HW tests */ + // NOTE: we do enable ECC, but the HW tests used will not + // generate "visible" errors + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(lmc)); + save_ecc_ena[lmc] = lmc_config.s.ecc_ena; + lmc_config.s.ecc_ena = 1; + lmc_wr(priv, CVMX_LMCX_CONFIG(lmc), lmc_config.u64); + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(lmc)); + + // testing is done on a single LMC at a time + // FIXME: for now, loop here to show what happens multiple times + for (loop = 0; loop < loops; loop++) { + /* Perform DLL offset tuning */ + hw_assist_test_dll_offset(priv, 2 /* 2=read */, lmc, + bytelane, + if_64b, dram_tune_rank_offset, + dram_tune_byte_bursts); + } + + // perform cleanup on active LMC + debug("N%d: H/W Tuning: finishing LMC%d bytelane %d tune.\n", + node, lmc, bytelane); + + /* Restore ECC for DRAM tests */ + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(lmc)); + lmc_config.s.ecc_ena = save_ecc_ena[lmc]; + lmc_wr(priv, CVMX_LMCX_CONFIG(lmc), lmc_config.u64); + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(lmc)); + + // finally, see if there are any read offset overrides + // after tuning + for (by = 0; by < 9; by++) { + s = lookup_env(priv, "ddr%d_tune_byte%d", lmc, by); + if (s) { + int dllro = strtoul(s, NULL, 10); + + change_dll_offset_enable(priv, lmc, 0); + load_dll_offset(priv, lmc, 2, dllro, by); + change_dll_offset_enable(priv, lmc, 1); + } + } + + } /* for (lmc = 0; lmc < num_lmcs; lmc++) */ + + // finish up... + + return 0; + +} /* perform_HW_dll_offset_tuning */ + +// this routine simply makes the calls to the tuning routine and returns +// any errors +static int cvmx_tune_node(struct ddr_priv *priv) +{ + int errs, tot_errs; + int do_dllwo = 0; // default to NO + const char *str; + int node = 0; + + // Automatically tune the data and ECC byte DLL read offsets + debug("N%d: Starting DLL Read Offset Tuning for LMCs\n", node); + errs = perform_HW_dll_offset_tuning(priv, 2, 0x0A /* all bytelanes */); + debug("N%d: Finished DLL Read Offset Tuning for LMCs, %d errors\n", + node, errs); + tot_errs = errs; + + // disabled by default for now, does not seem to be needed? + // Automatically tune the data and ECC byte DLL write offsets + // allow override of default setting + str = env_get("ddr_tune_write_offsets"); + if (str) + do_dllwo = !!strtoul(str, NULL, 0); + if (do_dllwo) { + debug("N%d: Starting DLL Write Offset Tuning for LMCs\n", node); + errs = + perform_HW_dll_offset_tuning(priv, 1, + 0x0A /* all bytelanes */); + debug("N%d: Finished DLL Write Offset Tuning for LMCs, %d errors\n", + node, errs); + tot_errs += errs; + } + + return tot_errs; +} + +// this routine makes the calls to the tuning routines when criteria are met +// intended to be called for automated tuning, to apply filtering... + +#define IS_DDR4 1 +#define IS_DDR3 0 +#define IS_RDIMM 1 +#define IS_UDIMM 0 +#define IS_1SLOT 1 +#define IS_2SLOT 0 + +// FIXME: DDR3 is not tuned +static const u32 ddr_speed_filter[2][2][2] = { + [IS_DDR4] = { + [IS_RDIMM] = { + [IS_1SLOT] = 940, + [IS_2SLOT] = 800}, + [IS_UDIMM] = { + [IS_1SLOT] = 1050, + [IS_2SLOT] = 940}, + }, + [IS_DDR3] = { + [IS_RDIMM] = { + [IS_1SLOT] = 0, // disabled + [IS_2SLOT] = 0 // disabled + }, + [IS_UDIMM] = { + [IS_1SLOT] = 0, // disabled + [IS_2SLOT] = 0 // disabled + } + } +}; + +void cvmx_maybe_tune_node(struct ddr_priv *priv, u32 ddr_speed) +{ + const char *s; + union cvmx_lmcx_config lmc_config; + union cvmx_lmcx_control lmc_control; + union cvmx_lmcx_ddr_pll_ctl lmc_ddr_pll_ctl; + int is_ddr4; + int is_rdimm; + int is_1slot; + int do_tune = 0; + u32 ddr_min_speed; + int node = 0; + + // scale it down from Hz to MHz + ddr_speed = divide_nint(ddr_speed, 1000000); + + // FIXME: allow an override here so that all configs can be tuned + // or none + // If the envvar is defined, always either force it or avoid it + // accordingly + s = env_get("ddr_tune_all_configs"); + if (s) { + do_tune = !!strtoul(s, NULL, 0); + printf("N%d: DRAM auto-tuning %s.\n", node, + (do_tune) ? "forced" : "disabled"); + if (do_tune) + cvmx_tune_node(priv); + + return; + } + + // filter the tuning calls here... + // determine if we should/can run automatically for this configuration + // + // FIXME: tune only when the configuration indicates it will help: + // DDR type, RDIMM or UDIMM, 1-slot or 2-slot, and speed + // + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(0)); // sample LMC0 + lmc_control.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(0)); // sample LMC0 + // sample LMC0 + lmc_ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0)); + + is_ddr4 = (lmc_ddr_pll_ctl.s.ddr4_mode != 0); + is_rdimm = (lmc_control.s.rdimm_ena != 0); + // HACK, should do better + is_1slot = (lmc_config.s.init_status < 4); + + ddr_min_speed = ddr_speed_filter[is_ddr4][is_rdimm][is_1slot]; + do_tune = ((ddr_min_speed != 0) && (ddr_speed > ddr_min_speed)); + + debug("N%d: DDR%d %cDIMM %d-slot at %d MHz %s eligible for auto-tuning.\n", + node, (is_ddr4) ? 4 : 3, (is_rdimm) ? 'R' : 'U', + (is_1slot) ? 1 : 2, ddr_speed, (do_tune) ? "is" : "is not"); + + // call the tuning routine, filtering is done... + if (do_tune) + cvmx_tune_node(priv); +} + +/* + * first pattern example: + * GENERAL_PURPOSE0.DATA == 64'h00ff00ff00ff00ff; + * GENERAL_PURPOSE1.DATA == 64'h00ff00ff00ff00ff; + * GENERAL_PURPOSE0.DATA == 16'h0000; + */ + +static const u64 dbi_pattern[3] = { + 0x00ff00ff00ff00ffULL, 0x00ff00ff00ff00ffULL, 0x0000ULL }; + +// Perform switchover to DBI +static void cvmx_dbi_switchover_interface(struct ddr_priv *priv, int lmc) +{ + union cvmx_lmcx_modereg_params0 modereg_params0; + union cvmx_lmcx_modereg_params3 modereg_params3; + union cvmx_lmcx_phy_ctl phy_ctl; + union cvmx_lmcx_config lmcx_config; + union cvmx_lmcx_ddr_pll_ctl ddr_pll_ctl; + int rank_mask, rankx, active_ranks; + u64 phys_addr, rank_offset; + int num_lmcs, errors; + int dbi_settings[9], byte, unlocked, retries; + int ecc_ena; + int rank_max = 1; // FIXME: make this 4 to try all the ranks + int node = 0; + + ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0)); + + lmcx_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(lmc)); + rank_mask = lmcx_config.s.init_status; + ecc_ena = lmcx_config.s.ecc_ena; + + // FIXME: must filter out any non-supported configs + // ie, no DDR3, no x4 devices + if (ddr_pll_ctl.s.ddr4_mode == 0 || lmcx_config.s.mode_x4dev == 1) { + debug("N%d.LMC%d: DBI switchover: inappropriate device; EXITING...\n", + node, lmc); + return; + } + + // this should be correct for 1 or 2 ranks, 1 or 2 DIMMs + num_lmcs = cvmx_dram_get_num_lmc(priv); + rank_offset = 1ull << (28 + lmcx_config.s.pbank_lsb - + lmcx_config.s.rank_ena + (num_lmcs / 2)); + + debug("N%d.LMC%d: DBI switchover: rank mask 0x%x, rank size 0x%016llx.\n", + node, lmc, rank_mask, (unsigned long long)rank_offset); + + /* + * 1. conduct the current init sequence as usual all the way + * after software write leveling. + */ + + read_dac_dbi_settings(priv, lmc, /*DBI*/ 0, dbi_settings); + + display_dac_dbi_settings(lmc, /*DBI*/ 0, ecc_ena, dbi_settings, + " INIT"); + + /* + * 2. set DBI related CSRs as below and issue MR write. + * MODEREG_PARAMS3.WR_DBI=1 + * MODEREG_PARAMS3.RD_DBI=1 + * PHY_CTL.DBI_MODE_ENA=1 + */ + modereg_params0.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS0(lmc)); + + modereg_params3.u64 = lmc_rd(priv, CVMX_LMCX_MODEREG_PARAMS3(lmc)); + modereg_params3.s.wr_dbi = 1; + modereg_params3.s.rd_dbi = 1; + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS3(lmc), modereg_params3.u64); + + phy_ctl.u64 = lmc_rd(priv, CVMX_LMCX_PHY_CTL(lmc)); + phy_ctl.s.dbi_mode_ena = 1; + lmc_wr(priv, CVMX_LMCX_PHY_CTL(lmc), phy_ctl.u64); + + /* + * there are two options for data to send. Lets start with (1) + * and could move to (2) in the future: + * + * 1) DBTRAIN_CTL[LFSR_PATTERN_SEL] = 0 (or for older chips where + * this does not exist) set data directly in these reigsters. + * this will yield a clk/2 pattern: + * GENERAL_PURPOSE0.DATA == 64'h00ff00ff00ff00ff; + * GENERAL_PURPOSE1.DATA == 64'h00ff00ff00ff00ff; + * GENERAL_PURPOSE0.DATA == 16'h0000; + * 2) DBTRAIN_CTL[LFSR_PATTERN_SEL] = 1 + * here data comes from the LFSR generating a PRBS pattern + * CHAR_CTL.EN = 0 + * CHAR_CTL.SEL = 0; // for PRBS + * CHAR_CTL.DR = 1; + * CHAR_CTL.PRBS = setup for whatever type of PRBS to send + * CHAR_CTL.SKEW_ON = 1; + */ + lmc_wr(priv, CVMX_LMCX_GENERAL_PURPOSE0(lmc), dbi_pattern[0]); + lmc_wr(priv, CVMX_LMCX_GENERAL_PURPOSE1(lmc), dbi_pattern[1]); + lmc_wr(priv, CVMX_LMCX_GENERAL_PURPOSE2(lmc), dbi_pattern[2]); + + /* + * 3. adjust cas_latency (only necessary if RD_DBI is set). + * here is my code for doing this: + * + * if (csr_model.MODEREG_PARAMS3.RD_DBI.value == 1) begin + * case (csr_model.MODEREG_PARAMS0.CL.value) + * 0,1,2,3,4: csr_model.MODEREG_PARAMS0.CL.value += 2; + * // CL 9-13 -> 11-15 + * 5: begin + * // CL=14, CWL=10,12 gets +2, CLW=11,14 gets +3 + * if((csr_model.MODEREG_PARAMS0.CWL.value==1 || + * csr_model.MODEREG_PARAMS0.CWL.value==3)) + * csr_model.MODEREG_PARAMS0.CL.value = 7; // 14->16 + * else + * csr_model.MODEREG_PARAMS0.CL.value = 13; // 14->17 + * end + * 6: csr_model.MODEREG_PARAMS0.CL.value = 8; // 15->18 + * 7: csr_model.MODEREG_PARAMS0.CL.value = 14; // 16->19 + * 8: csr_model.MODEREG_PARAMS0.CL.value = 15; // 18->21 + * default: + * `cn_fatal(("Error mem_cfg (%s) CL (%d) with RD_DBI=1, + * I am not sure what to do.", + * mem_cfg, csr_model.MODEREG_PARAMS3.RD_DBI.value)) + * endcase + * end + */ + + if (modereg_params3.s.rd_dbi == 1) { + int old_cl, new_cl, old_cwl; + + old_cl = modereg_params0.s.cl; + old_cwl = modereg_params0.s.cwl; + + switch (old_cl) { + case 0: + case 1: + case 2: + case 3: + case 4: + new_cl = old_cl + 2; + break; // 9-13->11-15 + // CL=14, CWL=10,12 gets +2, CLW=11,14 gets +3 + case 5: + new_cl = ((old_cwl == 1) || (old_cwl == 3)) ? 7 : 13; + break; + case 6: + new_cl = 8; + break; // 15->18 + case 7: + new_cl = 14; + break; // 16->19 + case 8: + new_cl = 15; + break; // 18->21 + default: + printf("ERROR: Bad CL value (%d) for DBI switchover.\n", + old_cl); + // FIXME: need to error exit here... + old_cl = -1; + new_cl = -1; + break; + } + debug("N%d.LMC%d: DBI switchover: CL ADJ: old_cl 0x%x, old_cwl 0x%x, new_cl 0x%x.\n", + node, lmc, old_cl, old_cwl, new_cl); + modereg_params0.s.cl = new_cl; + lmc_wr(priv, CVMX_LMCX_MODEREG_PARAMS0(lmc), + modereg_params0.u64); + } + + /* + * 4. issue MRW to MR0 (CL) and MR5 (DBI), using LMC sequence + * SEQ_CTL[SEQ_SEL] = MRW. + */ + // Use the default values, from the CSRs fields + // also, do B-sides for RDIMMs... + + for (rankx = 0; rankx < 4; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + // for RDIMMs, B-side writes should get done automatically + // when the A-side is written + ddr4_mrw(priv, lmc, rankx, -1 /* use_default */, + 0 /*MRreg */, 0 /*A-side */); /* MR0 */ + ddr4_mrw(priv, lmc, rankx, -1 /* use_default */, + 5 /*MRreg */, 0 /*A-side */); /* MR5 */ + } + + /* + * 5. conduct DBI bit deskew training via the General Purpose + * R/W sequence (dbtrain). may need to run this over and over to get + * a lock (I need up to 5 in simulation): + * SEQ_CTL[SEQ_SEL] = RW_TRAINING (15) + * DBTRAIN_CTL.CMD_COUNT_EXT = all 1's + * DBTRAIN_CTL.READ_CMD_COUNT = all 1's + * DBTRAIN_CTL.TCCD_SEL = set according to MODEREG_PARAMS3[TCCD_L] + * DBTRAIN_CTL.RW_TRAIN = 1 + * DBTRAIN_CTL.READ_DQ_COUNT = dont care + * DBTRAIN_CTL.WRITE_ENA = 1; + * DBTRAIN_CTL.ACTIVATE = 1; + * DBTRAIN_CTL LRANK, PRANK, ROW_A, BG, BA, COLUMN_A = set to a + * valid address + */ + + // NOW - do the training + debug("N%d.LMC%d: DBI switchover: TRAINING begins...\n", node, lmc); + + active_ranks = 0; + for (rankx = 0; rankx < rank_max; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + phys_addr = rank_offset * active_ranks; + // FIXME: now done by test_dram_byte_hw() + + active_ranks++; + + retries = 0; + +restart_training: + + // NOTE: return is a bitmask of the erroring bytelanes - + // we only print it + errors = + test_dram_byte_hw(priv, lmc, phys_addr, DBTRAIN_DBI, NULL); + + debug("N%d.LMC%d: DBI switchover: TEST: rank %d, phys_addr 0x%llx, errors 0x%x.\n", + node, lmc, rankx, (unsigned long long)phys_addr, errors); + + // NEXT - check for locking + unlocked = 0; + read_dac_dbi_settings(priv, lmc, /*DBI*/ 0, dbi_settings); + + for (byte = 0; byte < (8 + ecc_ena); byte++) + unlocked += (dbi_settings[byte] & 1) ^ 1; + + // FIXME: print out the DBI settings array after each rank? + if (rank_max > 1) // only when doing more than 1 rank + display_dac_dbi_settings(lmc, /*DBI*/ 0, ecc_ena, + dbi_settings, " RANK"); + + if (unlocked > 0) { + debug("N%d.LMC%d: DBI switchover: LOCK: %d still unlocked.\n", + node, lmc, unlocked); + retries++; + if (retries < 10) { + goto restart_training; + } else { + debug("N%d.LMC%d: DBI switchover: LOCK: %d retries exhausted.\n", + node, lmc, retries); + } + } + } /* for (rankx = 0; rankx < 4; rankx++) */ + + // print out the final DBI settings array + display_dac_dbi_settings(lmc, /*DBI*/ 0, ecc_ena, dbi_settings, + "FINAL"); +} + +void cvmx_dbi_switchover(struct ddr_priv *priv) +{ + int lmc; + int num_lmcs = cvmx_dram_get_num_lmc(priv); + + for (lmc = 0; lmc < num_lmcs; lmc++) + cvmx_dbi_switchover_interface(priv, lmc); +} diff --git a/roms/u-boot/drivers/ram/octeon/octeon_ddr.c b/roms/u-boot/drivers/ram/octeon/octeon_ddr.c new file mode 100644 index 000000000..e7b61d39f --- /dev/null +++ b/roms/u-boot/drivers/ram/octeon/octeon_ddr.c @@ -0,0 +1,2729 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define CONFIG_REF_HERTZ 50000000 + +DECLARE_GLOBAL_DATA_PTR; + +/* Sign of an integer */ +static s64 _sign(s64 v) +{ + return (v < 0); +} + +#ifndef DDR_NO_DEBUG +char *lookup_env(struct ddr_priv *priv, const char *format, ...) +{ + char *s; + unsigned long value; + va_list args; + char buffer[64]; + + va_start(args, format); + vsnprintf(buffer, sizeof(buffer), format, args); + va_end(args); + + s = ddr_getenv_debug(priv, buffer); + if (s) { + value = simple_strtoul(s, NULL, 0); + printf("Parameter found in environment %s=\"%s\" 0x%lx (%ld)\n", + buffer, s, value, value); + } + + return s; +} + +char *lookup_env_ull(struct ddr_priv *priv, const char *format, ...) +{ + char *s; + u64 value; + va_list args; + char buffer[64]; + + va_start(args, format); + vsnprintf(buffer, sizeof(buffer), format, args); + va_end(args); + + s = ddr_getenv_debug(priv, buffer); + if (s) { + value = simple_strtoull(s, NULL, 0); + printf("Parameter found in environment. %s = 0x%016llx\n", + buffer, value); + } + + return s; +} +#else +char *lookup_env(struct ddr_priv *priv, const char *format, ...) +{ + return NULL; +} + +char *lookup_env_ull(struct ddr_priv *priv, const char *format, ...) +{ + return NULL; +} +#endif + +/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ +#define CVMX_L2C_TADS ((OCTEON_IS_MODEL(OCTEON_CN68XX) || \ + OCTEON_IS_MODEL(OCTEON_CN73XX) || \ + OCTEON_IS_MODEL(OCTEON_CNF75XX)) ? 4 : \ + (OCTEON_IS_MODEL(OCTEON_CN78XX)) ? 8 : 1) + +/* Number of L2C IOBs connected to LMC. */ +#define CVMX_L2C_IOBS ((OCTEON_IS_MODEL(OCTEON_CN68XX) || \ + OCTEON_IS_MODEL(OCTEON_CN78XX) || \ + OCTEON_IS_MODEL(OCTEON_CN73XX) || \ + OCTEON_IS_MODEL(OCTEON_CNF75XX)) ? 2 : 1) + +#define CVMX_L2C_MAX_MEMSZ_ALLOWED (OCTEON_IS_OCTEON2() ? \ + (32 * CVMX_L2C_TADS) : \ + (OCTEON_IS_MODEL(OCTEON_CN70XX) ? \ + 512 : (OCTEON_IS_OCTEON3() ? 1024 : 0))) + +/** + * Initialize the BIG address in L2C+DRAM to generate proper error + * on reading/writing to an non-existent memory location. + * + * @param node OCX CPU node number + * @param mem_size Amount of DRAM configured in MB. + * @param mode Allow/Disallow reporting errors L2C_INT_SUM[BIGRD,BIGWR]. + */ +static void cvmx_l2c_set_big_size(struct ddr_priv *priv, u64 mem_size, int mode) +{ + if ((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) && + !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { + union cvmx_l2c_big_ctl big_ctl; + int bits = 0, zero_bits = 0; + u64 mem; + + if (mem_size > (CVMX_L2C_MAX_MEMSZ_ALLOWED * 1024ull)) { + printf("WARNING: Invalid memory size(%lld) requested, should be <= %lld\n", + mem_size, + (u64)CVMX_L2C_MAX_MEMSZ_ALLOWED * 1024); + mem_size = CVMX_L2C_MAX_MEMSZ_ALLOWED * 1024; + } + + mem = mem_size; + while (mem) { + if ((mem & 1) == 0) + zero_bits++; + bits++; + mem >>= 1; + } + + if ((bits - zero_bits) != 1 || (bits - 9) <= 0) { + printf("ERROR: Invalid DRAM size (%lld) requested, refer to L2C_BIG_CTL[maxdram] for valid options.\n", + mem_size); + return; + } + + /* + * The BIG/HOLE is logic is not supported in pass1 as per + * Errata L2C-17736 + */ + if (mode == 0 && OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) + mode = 1; + + big_ctl.u64 = 0; + big_ctl.s.maxdram = bits - 9; + big_ctl.cn61xx.disable = mode; + l2c_wr(priv, CVMX_L2C_BIG_CTL_REL, big_ctl.u64); + } +} + +static u32 octeon3_refclock(u32 alt_refclk, u32 ddr_hertz, + struct dimm_config *dimm_config) +{ + u32 ddr_ref_hertz = CONFIG_REF_HERTZ; + int ddr_type; + int spd_dimm_type; + + debug("%s(%u, %u, %p)\n", __func__, alt_refclk, ddr_hertz, dimm_config); + + /* Octeon 3 case... */ + + /* we know whether alternate refclk is always wanted + * we also know already if we want 2133 MT/s + * if alt refclk not always wanted, then probe DDR and + * DIMM type if DDR4 and RDIMMs, then set desired refclk + * to 100MHz, otherwise to default (50MHz) + * depend on ddr_initialize() to do the refclk selection + * and validation/ + */ + if (alt_refclk) { + /* + * If alternate refclk was specified, let it override + * everything + */ + ddr_ref_hertz = alt_refclk * 1000000; + printf("%s: DRAM init: %d MHz refclk is REQUESTED ALWAYS\n", + __func__, alt_refclk); + } else if (ddr_hertz > 1000000000) { + ddr_type = get_ddr_type(dimm_config, 0); + spd_dimm_type = get_dimm_module_type(dimm_config, 0, ddr_type); + + debug("ddr type: 0x%x, dimm type: 0x%x\n", ddr_type, + spd_dimm_type); + /* Is DDR4 and RDIMM just to be sure. */ + if (ddr_type == DDR4_DRAM && + (spd_dimm_type == 1 || spd_dimm_type == 5 || + spd_dimm_type == 8)) { + /* Yes, we require 100MHz refclk, so set it. */ + ddr_ref_hertz = 100000000; + puts("DRAM init: 100 MHz refclk is REQUIRED\n"); + } + } + + debug("%s: speed: %u\n", __func__, ddr_ref_hertz); + return ddr_ref_hertz; +} + +int encode_row_lsb_ddr3(int row_lsb) +{ + int row_lsb_start = 14; + + /* Decoding for row_lsb */ + /* 000: row_lsb = mem_adr[14] */ + /* 001: row_lsb = mem_adr[15] */ + /* 010: row_lsb = mem_adr[16] */ + /* 011: row_lsb = mem_adr[17] */ + /* 100: row_lsb = mem_adr[18] */ + /* 101: row_lsb = mem_adr[19] */ + /* 110: row_lsb = mem_adr[20] */ + /* 111: RESERVED */ + + if (octeon_is_cpuid(OCTEON_CN6XXX) || + octeon_is_cpuid(OCTEON_CNF7XXX) || octeon_is_cpuid(OCTEON_CN7XXX)) + row_lsb_start = 14; + else + printf("ERROR: Unsupported Octeon model: 0x%x\n", + read_c0_prid()); + + return row_lsb - row_lsb_start; +} + +int encode_pbank_lsb_ddr3(int pbank_lsb) +{ + /* Decoding for pbank_lsb */ + /* 0000:DIMM = mem_adr[28] / rank = mem_adr[27] (if RANK_ENA) */ + /* 0001:DIMM = mem_adr[29] / rank = mem_adr[28] " */ + /* 0010:DIMM = mem_adr[30] / rank = mem_adr[29] " */ + /* 0011:DIMM = mem_adr[31] / rank = mem_adr[30] " */ + /* 0100:DIMM = mem_adr[32] / rank = mem_adr[31] " */ + /* 0101:DIMM = mem_adr[33] / rank = mem_adr[32] " */ + /* 0110:DIMM = mem_adr[34] / rank = mem_adr[33] " */ + /* 0111:DIMM = 0 / rank = mem_adr[34] " */ + /* 1000-1111: RESERVED */ + + int pbank_lsb_start = 0; + + if (octeon_is_cpuid(OCTEON_CN6XXX) || + octeon_is_cpuid(OCTEON_CNF7XXX) || octeon_is_cpuid(OCTEON_CN7XXX)) + pbank_lsb_start = 28; + else + printf("ERROR: Unsupported Octeon model: 0x%x\n", + read_c0_prid()); + + return pbank_lsb - pbank_lsb_start; +} + +static void set_ddr_clock_initialized(struct ddr_priv *priv, int if_num, + bool inited_flag) +{ + priv->ddr_clock_initialized[if_num] = inited_flag; +} + +static int ddr_clock_initialized(struct ddr_priv *priv, int if_num) +{ + return priv->ddr_clock_initialized[if_num]; +} + +static void set_ddr_memory_preserved(struct ddr_priv *priv) +{ + priv->ddr_memory_preserved = true; +} + +bool ddr_memory_preserved(struct ddr_priv *priv) +{ + return priv->ddr_memory_preserved; +} + +static void cn78xx_lmc_dreset_init(struct ddr_priv *priv, int if_num) +{ + union cvmx_lmcx_dll_ctl2 dll_ctl2; + + /* + * The remainder of this section describes the sequence for LMCn. + * + * 1. If not done already, write LMC(0..3)_DLL_CTL2 to its reset value + * (except without changing the LMC(0..3)_DLL_CTL2[INTF_EN] value from + * that set in the prior Step 3), including + * LMC(0..3)_DLL_CTL2[DRESET] = 1. + * + * 2. Without changing any other LMC(0..3)_DLL_CTL2 fields, write + * LMC(0..3)_DLL_CTL2[DLL_BRINGUP] = 1. + */ + + dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(if_num)); + dll_ctl2.cn78xx.dll_bringup = 1; + lmc_wr(priv, CVMX_LMCX_DLL_CTL2(if_num), dll_ctl2.u64); + + /* + * 3. Read LMC(0..3)_DLL_CTL2 and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DLL_CTL2(if_num)); + + /* + * 4. Wait for a minimum of 10 LMC CK cycles. + */ + + udelay(1); + + /* + * 5. Without changing any other fields in LMC(0..3)_DLL_CTL2, write + * LMC(0..3)_DLL_CTL2[QUAD_DLL_ENA] = 1. + * LMC(0..3)_DLL_CTL2[QUAD_DLL_ENA] must not change after this point + * without restarting the LMCn DRESET initialization sequence. + */ + + dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(if_num)); + dll_ctl2.cn78xx.quad_dll_ena = 1; + lmc_wr(priv, CVMX_LMCX_DLL_CTL2(if_num), dll_ctl2.u64); + + /* + * 6. Read LMC(0..3)_DLL_CTL2 and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DLL_CTL2(if_num)); + + /* + * 7. Wait a minimum of 10 us. + */ + + udelay(10); + + /* + * 8. Without changing any other fields in LMC(0..3)_DLL_CTL2, write + * LMC(0..3)_DLL_CTL2[DLL_BRINGUP] = 0. + * LMC(0..3)_DLL_CTL2[DLL_BRINGUP] must not change after this point + * without restarting the LMCn DRESET initialization sequence. + */ + + dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(if_num)); + dll_ctl2.cn78xx.dll_bringup = 0; + lmc_wr(priv, CVMX_LMCX_DLL_CTL2(if_num), dll_ctl2.u64); + + /* + * 9. Read LMC(0..3)_DLL_CTL2 and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DLL_CTL2(if_num)); + + /* + * 10. Without changing any other fields in LMC(0..3)_DLL_CTL2, write + * LMC(0..3)_DLL_CTL2[DRESET] = 0. + * LMC(0..3)_DLL_CTL2[DRESET] must not change after this point without + * restarting the LMCn DRESET initialization sequence. + * + * After completing LMCn DRESET initialization, all LMC CSRs may be + * accessed. Prior to completing LMC DRESET initialization, only + * LMC(0..3)_DDR_PLL_CTL, LMC(0..3)_DLL_CTL2, LMC(0..3)_RESET_CTL, and + * LMC(0..3)_COMP_CTL2 LMC CSRs can be accessed. + */ + + dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(if_num)); + dll_ctl2.cn78xx.dreset = 0; + lmc_wr(priv, CVMX_LMCX_DLL_CTL2(if_num), dll_ctl2.u64); +} + +int initialize_ddr_clock(struct ddr_priv *priv, struct ddr_conf *ddr_conf, + u32 cpu_hertz, u32 ddr_hertz, u32 ddr_ref_hertz, + int if_num, u32 if_mask) +{ + char *s; + + if (ddr_clock_initialized(priv, if_num)) + return 0; + + if (!ddr_clock_initialized(priv, 0)) { /* Do this once */ + union cvmx_lmcx_reset_ctl reset_ctl; + int i; + + /* + * Check to see if memory is to be preserved and set global + * flag + */ + for (i = 3; i >= 0; --i) { + if ((if_mask & (1 << i)) == 0) + continue; + + reset_ctl.u64 = lmc_rd(priv, CVMX_LMCX_RESET_CTL(i)); + if (reset_ctl.s.ddr3psv == 1) { + debug("LMC%d Preserving memory\n", i); + set_ddr_memory_preserved(priv); + + /* Re-initialize flags */ + reset_ctl.s.ddr3pwarm = 0; + reset_ctl.s.ddr3psoft = 0; + reset_ctl.s.ddr3psv = 0; + lmc_wr(priv, CVMX_LMCX_RESET_CTL(i), + reset_ctl.u64); + } + } + } + + /* + * ToDo: Add support for these SoCs: + * + * if (octeon_is_cpuid(OCTEON_CN63XX) || + * octeon_is_cpuid(OCTEON_CN66XX) || + * octeon_is_cpuid(OCTEON_CN61XX) || octeon_is_cpuid(OCTEON_CNF71XX)) + * + * and + * + * if (octeon_is_cpuid(OCTEON_CN68XX)) + * + * and + * + * if (octeon_is_cpuid(OCTEON_CN70XX)) + * + */ + + if (octeon_is_cpuid(OCTEON_CN78XX) || octeon_is_cpuid(OCTEON_CN73XX) || + octeon_is_cpuid(OCTEON_CNF75XX)) { + union cvmx_lmcx_dll_ctl2 dll_ctl2; + union cvmx_lmcx_dll_ctl3 ddr_dll_ctl3; + union cvmx_lmcx_ddr_pll_ctl ddr_pll_ctl; + struct dimm_config *dimm_config_table = + ddr_conf->dimm_config_table; + int en_idx, save_en_idx, best_en_idx = 0; + u64 clkf, clkr, max_clkf = 127; + u64 best_clkf = 0, best_clkr = 0; + u64 best_pll_MHz = 0; + u64 pll_MHz; + u64 min_pll_MHz = 800; + u64 max_pll_MHz = 5000; + u64 error; + u64 best_error; + u64 best_calculated_ddr_hertz = 0; + u64 calculated_ddr_hertz = 0; + u64 orig_ddr_hertz = ddr_hertz; + const int _en[] = { 1, 2, 3, 4, 5, 6, 7, 8, 10, 12 }; + int override_pll_settings; + int new_bwadj; + int ddr_type; + int i; + + /* ddr_type only indicates DDR4 or DDR3 */ + ddr_type = (read_spd(&dimm_config_table[0], 0, + DDR4_SPD_KEY_BYTE_DEVICE_TYPE) == + 0x0C) ? DDR4_DRAM : DDR3_DRAM; + + /* + * 5.9 LMC Initialization Sequence + * + * There are 13 parts to the LMC initialization procedure: + * + * 1. DDR PLL initialization + * + * 2. LMC CK initialization + * + * 3. LMC interface enable initialization + * + * 4. LMC DRESET initialization + * + * 5. LMC CK local initialization + * + * 6. LMC RESET initialization + * + * 7. Early LMC initialization + * + * 8. LMC offset training + * + * 9. LMC internal Vref training + * + * 10. LMC deskew training + * + * 11. LMC write leveling + * + * 12. LMC read leveling + * + * 13. Final LMC initialization + * + * CN78XX supports two modes: + * + * - two-LMC mode: both LMCs 2/3 must not be enabled + * (LMC2/3_DLL_CTL2[DRESET] must be set to 1 and + * LMC2/3_DLL_CTL2[INTF_EN] + * must be set to 0) and both LMCs 0/1 must be enabled). + * + * - four-LMC mode: all four LMCs 0..3 must be enabled. + * + * Steps 4 and 6..13 should each be performed for each + * enabled LMC (either twice or four times). Steps 1..3 and + * 5 are more global in nature and each must be executed + * exactly once (not once per LMC) each time the DDR PLL + * changes or is first brought up. Steps 1..3 and 5 need + * not be performed if the DDR PLL is stable. + * + * Generally, the steps are performed in order. The exception + * is that the CK local initialization (step 5) must be + * performed after some DRESET initializations (step 4) and + * before other DRESET initializations when the DDR PLL is + * brought up or changed. (The CK local initialization uses + * information from some LMCs to bring up the other local + * CKs.) The following text describes these ordering + * requirements in more detail. + * + * Following any chip reset, the DDR PLL must be brought up, + * and all 13 steps should be executed. Subsequently, it is + * possible to execute only steps 4 and 6..13, or to execute + * only steps 8..13. + * + * The remainder of this section covers these initialization + * steps in sequence. + */ + + /* Do the following init only once */ + if (if_num != 0) + goto not_if0; + + /* Only for interface #0 ... */ + + /* + * 5.9.3 LMC Interface-Enable Initialization + * + * LMC interface-enable initialization (Step 3) must be# + * performed after Step 2 for each chip reset and whenever + * the DDR clock speed changes. This step needs to be + * performed only once, not once per LMC. Perform the + * following three substeps for the LMC interface-enable + * initialization: + * + * 1. Without changing any other LMC2_DLL_CTL2 fields + * (LMC(0..3)_DLL_CTL2 should be at their reset values after + * Step 1), write LMC2_DLL_CTL2[INTF_EN] = 1 if four-LMC + * mode is desired. + * + * 2. Without changing any other LMC3_DLL_CTL2 fields, write + * LMC3_DLL_CTL2[INTF_EN] = 1 if four-LMC mode is desired. + * + * 3. Read LMC2_DLL_CTL2 and wait for the result. + * + * The LMC2_DLL_CTL2[INTF_EN] and LMC3_DLL_CTL2[INTF_EN] + * values should not be changed by software from this point. + */ + + for (i = 0; i < 4; ++i) { + if ((if_mask & (1 << i)) == 0) + continue; + + dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(i)); + + dll_ctl2.cn78xx.byp_setting = 0; + dll_ctl2.cn78xx.byp_sel = 0; + dll_ctl2.cn78xx.quad_dll_ena = 0; + dll_ctl2.cn78xx.dreset = 1; + dll_ctl2.cn78xx.dll_bringup = 0; + dll_ctl2.cn78xx.intf_en = 0; + + lmc_wr(priv, CVMX_LMCX_DLL_CTL2(i), dll_ctl2.u64); + } + + /* + * ###### Interface enable (intf_en) deferred until after + * DDR_DIV_RESET=0 ####### + */ + + /* + * 5.9.1 DDR PLL Initialization + * + * DDR PLL initialization (Step 1) must be performed for each + * chip reset and whenever the DDR clock speed changes. This + * step needs to be performed only once, not once per LMC. + * + * Perform the following eight substeps to initialize the + * DDR PLL: + * + * 1. If not done already, write all fields in + * LMC(0..3)_DDR_PLL_CTL and + * LMC(0..1)_DLL_CTL2 to their reset values, including: + * + * .. LMC0_DDR_PLL_CTL[DDR_DIV_RESET] = 1 + * .. LMC0_DLL_CTL2[DRESET] = 1 + * + * This substep is not necessary after a chip reset. + * + */ + + ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0)); + + ddr_pll_ctl.cn78xx.reset_n = 0; + ddr_pll_ctl.cn78xx.ddr_div_reset = 1; + ddr_pll_ctl.cn78xx.phy_dcok = 0; + + /* + * 73XX pass 1.3 has LMC0 DCLK_INVERT tied to 1; earlier + * 73xx passes are tied to 0 + * + * 75XX needs LMC0 DCLK_INVERT set to 1 to minimize duty + * cycle falling points + * + * and we default all other chips LMC0 to DCLK_INVERT=0 + */ + ddr_pll_ctl.cn78xx.dclk_invert = + !!(octeon_is_cpuid(OCTEON_CN73XX_PASS1_3) || + octeon_is_cpuid(OCTEON_CNF75XX)); + + /* + * allow override of LMC0 desired setting for DCLK_INVERT, + * but not on 73XX; + * we cannot change LMC0 DCLK_INVERT on 73XX any pass + */ + if (!(octeon_is_cpuid(OCTEON_CN73XX))) { + s = lookup_env(priv, "ddr0_set_dclk_invert"); + if (s) { + ddr_pll_ctl.cn78xx.dclk_invert = + !!simple_strtoul(s, NULL, 0); + debug("LMC0: override DDR_PLL_CTL[dclk_invert] to %d\n", + ddr_pll_ctl.cn78xx.dclk_invert); + } + } + + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(0), ddr_pll_ctl.u64); + debug("%-45s : 0x%016llx\n", "LMC0: DDR_PLL_CTL", + ddr_pll_ctl.u64); + + // only when LMC1 is active + if (if_mask & 0x2) { + /* + * For CNF75XX, both LMC0 and LMC1 use the same PLL, + * so we use the LMC0 setting of DCLK_INVERT for LMC1. + */ + if (!octeon_is_cpuid(OCTEON_CNF75XX)) { + int override = 0; + + /* + * by default, for non-CNF75XX, we want + * LMC1 toggled LMC0 + */ + int lmc0_dclk_invert = + ddr_pll_ctl.cn78xx.dclk_invert; + + /* + * FIXME: work-around for DDR3 UDIMM problems + * is to use LMC0 setting on LMC1 and if + * 73xx pass 1.3, we want to default LMC1 + * DCLK_INVERT to LMC0, not the invert of LMC0 + */ + int lmc1_dclk_invert; + + lmc1_dclk_invert = + ((ddr_type == DDR4_DRAM) && + !octeon_is_cpuid(OCTEON_CN73XX_PASS1_3)) + ? lmc0_dclk_invert ^ 1 : + lmc0_dclk_invert; + + /* + * allow override of LMC1 desired setting for + * DCLK_INVERT + */ + s = lookup_env(priv, "ddr1_set_dclk_invert"); + if (s) { + lmc1_dclk_invert = + !!simple_strtoul(s, NULL, 0); + override = 1; + } + debug("LMC1: %s DDR_PLL_CTL[dclk_invert] to %d (LMC0 %d)\n", + (override) ? "override" : + "default", lmc1_dclk_invert, + lmc0_dclk_invert); + + ddr_pll_ctl.cn78xx.dclk_invert = + lmc1_dclk_invert; + } + + // but always write LMC1 CSR if it is active + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(1), ddr_pll_ctl.u64); + debug("%-45s : 0x%016llx\n", + "LMC1: DDR_PLL_CTL", ddr_pll_ctl.u64); + } + + /* + * 2. If the current DRAM contents are not preserved (see + * LMC(0..3)_RESET_ CTL[DDR3PSV]), this is also an appropriate + * time to assert the RESET# pin of the DDR3/DDR4 DRAM parts. + * If desired, write + * LMC0_RESET_ CTL[DDR3RST] = 0 without modifying any other + * LMC0_RESET_CTL fields to assert the DDR_RESET_L pin. + * No action is required here to assert DDR_RESET_L + * following a chip reset. Refer to Section 5.9.6. Do this + * for all enabled LMCs. + */ + + for (i = 0; (!ddr_memory_preserved(priv)) && i < 4; ++i) { + union cvmx_lmcx_reset_ctl reset_ctl; + + if ((if_mask & (1 << i)) == 0) + continue; + + reset_ctl.u64 = lmc_rd(priv, CVMX_LMCX_RESET_CTL(i)); + reset_ctl.cn78xx.ddr3rst = 0; /* Reset asserted */ + debug("LMC%d Asserting DDR_RESET_L\n", i); + lmc_wr(priv, CVMX_LMCX_RESET_CTL(i), reset_ctl.u64); + lmc_rd(priv, CVMX_LMCX_RESET_CTL(i)); + } + + /* + * 3. Without changing any other LMC0_DDR_PLL_CTL values, + * write LMC0_DDR_PLL_CTL[CLKF] with a value that gives a + * desired DDR PLL speed. The LMC0_DDR_PLL_CTL[CLKF] value + * should be selected in conjunction with the post-scalar + * divider values for LMC (LMC0_DDR_PLL_CTL[DDR_PS_EN]) so + * that the desired LMC CK speeds are is produced (all + * enabled LMCs must run the same speed). Section 5.14 + * describes LMC0_DDR_PLL_CTL[CLKF] and + * LMC0_DDR_PLL_CTL[DDR_PS_EN] programmings that produce + * the desired LMC CK speed. Section 5.9.2 describes LMC CK + * initialization, which can be done separately from the DDR + * PLL initialization described in this section. + * + * The LMC0_DDR_PLL_CTL[CLKF] value must not change after + * this point without restarting this SDRAM PLL + * initialization sequence. + */ + + /* Init to max error */ + error = ddr_hertz; + best_error = ddr_hertz; + + debug("DDR Reference Hertz = %d\n", ddr_ref_hertz); + + while (best_error == ddr_hertz) { + for (clkr = 0; clkr < 4; ++clkr) { + for (en_idx = + sizeof(_en) / sizeof(int) - + 1; en_idx >= 0; --en_idx) { + save_en_idx = en_idx; + clkf = + ((ddr_hertz) * + (clkr + 1) * (_en[save_en_idx])); + clkf = divide_nint(clkf, ddr_ref_hertz) + - 1; + pll_MHz = + ddr_ref_hertz * + (clkf + 1) / (clkr + 1) / 1000000; + calculated_ddr_hertz = + ddr_ref_hertz * + (clkf + + 1) / ((clkr + + 1) * (_en[save_en_idx])); + error = + ddr_hertz - calculated_ddr_hertz; + + if (pll_MHz < min_pll_MHz || + pll_MHz > max_pll_MHz) + continue; + if (clkf > max_clkf) { + /* + * PLL requires clkf to be + * limited + */ + continue; + } + if (abs(error) > abs(best_error)) + continue; + + debug("clkr: %2llu, en[%d]: %2d, clkf: %4llu, pll_MHz: %4llu, ddr_hertz: %8llu, error: %8lld\n", + clkr, save_en_idx, + _en[save_en_idx], clkf, pll_MHz, + calculated_ddr_hertz, error); + + /* Favor the highest PLL frequency. */ + if (abs(error) < abs(best_error) || + pll_MHz > best_pll_MHz) { + best_pll_MHz = pll_MHz; + best_calculated_ddr_hertz = + calculated_ddr_hertz; + best_error = error; + best_clkr = clkr; + best_clkf = clkf; + best_en_idx = save_en_idx; + } + } + } + + override_pll_settings = 0; + + s = lookup_env(priv, "ddr_pll_clkr"); + if (s) { + best_clkr = simple_strtoul(s, NULL, 0); + override_pll_settings = 1; + } + + s = lookup_env(priv, "ddr_pll_clkf"); + if (s) { + best_clkf = simple_strtoul(s, NULL, 0); + override_pll_settings = 1; + } + + s = lookup_env(priv, "ddr_pll_en_idx"); + if (s) { + best_en_idx = simple_strtoul(s, NULL, 0); + override_pll_settings = 1; + } + + if (override_pll_settings) { + best_pll_MHz = + ddr_ref_hertz * (best_clkf + + 1) / + (best_clkr + 1) / 1000000; + best_calculated_ddr_hertz = + ddr_ref_hertz * (best_clkf + + 1) / + ((best_clkr + 1) * (_en[best_en_idx])); + best_error = + ddr_hertz - best_calculated_ddr_hertz; + } + + debug("clkr: %2llu, en[%d]: %2d, clkf: %4llu, pll_MHz: %4llu, ddr_hertz: %8llu, error: %8lld <==\n", + best_clkr, best_en_idx, _en[best_en_idx], + best_clkf, best_pll_MHz, + best_calculated_ddr_hertz, best_error); + + /* + * Try lowering the frequency if we can't get a + * working configuration + */ + if (best_error == ddr_hertz) { + if (ddr_hertz < orig_ddr_hertz - 10000000) + break; + ddr_hertz -= 1000000; + best_error = ddr_hertz; + } + } + + if (best_error == ddr_hertz) { + printf("ERROR: Can not compute a legal DDR clock speed configuration.\n"); + return -1; + } + + new_bwadj = (best_clkf + 1) / 10; + debug("bwadj: %2d\n", new_bwadj); + + s = lookup_env(priv, "ddr_pll_bwadj"); + if (s) { + new_bwadj = strtoul(s, NULL, 0); + debug("bwadj: %2d\n", new_bwadj); + } + + for (i = 0; i < 2; ++i) { + if ((if_mask & (1 << i)) == 0) + continue; + + ddr_pll_ctl.u64 = + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + debug("LMC%d: DDR_PLL_CTL : 0x%016llx\n", + i, ddr_pll_ctl.u64); + + ddr_pll_ctl.cn78xx.ddr_ps_en = best_en_idx; + ddr_pll_ctl.cn78xx.clkf = best_clkf; + ddr_pll_ctl.cn78xx.clkr = best_clkr; + ddr_pll_ctl.cn78xx.reset_n = 0; + ddr_pll_ctl.cn78xx.bwadj = new_bwadj; + + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64); + debug("LMC%d: DDR_PLL_CTL : 0x%016llx\n", + i, ddr_pll_ctl.u64); + + /* + * For cnf75xx LMC0 and LMC1 use the same PLL so + * only program LMC0 PLL. + */ + if (octeon_is_cpuid(OCTEON_CNF75XX)) + break; + } + + for (i = 0; i < 4; ++i) { + if ((if_mask & (1 << i)) == 0) + continue; + + /* + * 4. Read LMC0_DDR_PLL_CTL and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + + /* + * 5. Wait a minimum of 3 us. + */ + + udelay(3); /* Wait 3 us */ + + /* + * 6. Write LMC0_DDR_PLL_CTL[RESET_N] = 1 without + * changing any other LMC0_DDR_PLL_CTL values. + */ + + ddr_pll_ctl.u64 = + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + ddr_pll_ctl.cn78xx.reset_n = 1; + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64); + + /* + * 7. Read LMC0_DDR_PLL_CTL and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + + /* + * 8. Wait a minimum of 25 us. + */ + + udelay(25); /* Wait 25 us */ + + /* + * For cnf75xx LMC0 and LMC1 use the same PLL so + * only program LMC0 PLL. + */ + if (octeon_is_cpuid(OCTEON_CNF75XX)) + break; + } + + for (i = 0; i < 4; ++i) { + if ((if_mask & (1 << i)) == 0) + continue; + + /* + * 5.9.2 LMC CK Initialization + * + * DDR PLL initialization must be completed prior to + * starting LMC CK initialization. + * + * Perform the following substeps to initialize the + * LMC CK: + * + * 1. Without changing any other LMC(0..3)_DDR_PLL_CTL + * values, write + * LMC(0..3)_DDR_PLL_CTL[DDR_DIV_RESET] = 1 and + * LMC(0..3)_DDR_PLL_CTL[DDR_PS_EN] with the + * appropriate value to get the desired LMC CK speed. + * Section 5.14 discusses CLKF and DDR_PS_EN + * programmings. The LMC(0..3)_DDR_PLL_CTL[DDR_PS_EN] + * must not change after this point without restarting + * this LMC CK initialization sequence. + */ + + ddr_pll_ctl.u64 = lmc_rd(priv, + CVMX_LMCX_DDR_PLL_CTL(i)); + ddr_pll_ctl.cn78xx.ddr_div_reset = 1; + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64); + + /* + * 2. Without changing any other fields in + * LMC(0..3)_DDR_PLL_CTL, write + * LMC(0..3)_DDR_PLL_CTL[DDR4_MODE] = 0. + */ + + ddr_pll_ctl.u64 = + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + ddr_pll_ctl.cn78xx.ddr4_mode = + (ddr_type == DDR4_DRAM) ? 1 : 0; + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64); + + /* + * 3. Read LMC(0..3)_DDR_PLL_CTL and wait for the + * result. + */ + + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + + /* + * 4. Wait a minimum of 1 us. + */ + + udelay(1); /* Wait 1 us */ + + /* + * ###### Steps 5 through 7 deferred until after + * DDR_DIV_RESET=0 ####### + */ + + /* + * 8. Without changing any other LMC(0..3)_COMP_CTL2 + * values, write + * LMC(0..3)_COMP_CTL2[CK_CTL,CONTROL_CTL,CMD_CTL] + * to the desired DDR*_CK_*_P control and command + * signals drive strength. + */ + + union cvmx_lmcx_comp_ctl2 comp_ctl2; + const struct ddr3_custom_config *custom_lmc_config = + &ddr_conf->custom_lmc_config; + + comp_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_COMP_CTL2(i)); + + /* Default 4=34.3 ohm */ + comp_ctl2.cn78xx.dqx_ctl = + (custom_lmc_config->dqx_ctl == + 0) ? 4 : custom_lmc_config->dqx_ctl; + /* Default 4=34.3 ohm */ + comp_ctl2.cn78xx.ck_ctl = + (custom_lmc_config->ck_ctl == + 0) ? 4 : custom_lmc_config->ck_ctl; + /* Default 4=34.3 ohm */ + comp_ctl2.cn78xx.cmd_ctl = + (custom_lmc_config->cmd_ctl == + 0) ? 4 : custom_lmc_config->cmd_ctl; + + comp_ctl2.cn78xx.rodt_ctl = 0x4; /* 60 ohm */ + + comp_ctl2.cn70xx.ptune_offset = + (abs(custom_lmc_config->ptune_offset) & 0x7) + | (_sign(custom_lmc_config->ptune_offset) << 3); + comp_ctl2.cn70xx.ntune_offset = + (abs(custom_lmc_config->ntune_offset) & 0x7) + | (_sign(custom_lmc_config->ntune_offset) << 3); + + s = lookup_env(priv, "ddr_clk_ctl"); + if (s) { + comp_ctl2.cn78xx.ck_ctl = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_ck_ctl"); + if (s) { + comp_ctl2.cn78xx.ck_ctl = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_cmd_ctl"); + if (s) { + comp_ctl2.cn78xx.cmd_ctl = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_dqx_ctl"); + if (s) { + comp_ctl2.cn78xx.dqx_ctl = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_ptune_offset"); + if (s) { + comp_ctl2.cn78xx.ptune_offset = + simple_strtoul(s, NULL, 0); + } + + s = lookup_env(priv, "ddr_ntune_offset"); + if (s) { + comp_ctl2.cn78xx.ntune_offset = + simple_strtoul(s, NULL, 0); + } + + lmc_wr(priv, CVMX_LMCX_COMP_CTL2(i), comp_ctl2.u64); + + /* + * 9. Read LMC(0..3)_DDR_PLL_CTL and wait for the + * result. + */ + + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + + /* + * 10. Wait a minimum of 200 ns. + */ + + udelay(1); /* Wait 1 us */ + + /* + * 11. Without changing any other + * LMC(0..3)_DDR_PLL_CTL values, write + * LMC(0..3)_DDR_PLL_CTL[DDR_DIV_RESET] = 0. + */ + + ddr_pll_ctl.u64 = lmc_rd(priv, + CVMX_LMCX_DDR_PLL_CTL(i)); + ddr_pll_ctl.cn78xx.ddr_div_reset = 0; + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64); + + /* + * 12. Read LMC(0..3)_DDR_PLL_CTL and wait for the + * result. + */ + + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + + /* + * 13. Wait a minimum of 200 ns. + */ + + udelay(1); /* Wait 1 us */ + } + + /* + * Relocated Interface Enable (intf_en) Step + */ + for (i = (octeon_is_cpuid(OCTEON_CN73XX) || + octeon_is_cpuid(OCTEON_CNF75XX)) ? 1 : 2; + i < 4; ++i) { + /* + * This step is only necessary for LMC 2 and 3 in + * 4-LMC mode. The mask will cause the unpopulated + * interfaces to be skipped. + */ + if ((if_mask & (1 << i)) == 0) + continue; + + dll_ctl2.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL2(i)); + dll_ctl2.cn78xx.intf_en = 1; + lmc_wr(priv, CVMX_LMCX_DLL_CTL2(i), dll_ctl2.u64); + lmc_rd(priv, CVMX_LMCX_DLL_CTL2(i)); + } + + /* + * Relocated PHY_DCOK Step + */ + for (i = 0; i < 4; ++i) { + if ((if_mask & (1 << i)) == 0) + continue; + /* + * 5. Without changing any other fields in + * LMC(0..3)_DDR_PLL_CTL, write + * LMC(0..3)_DDR_PLL_CTL[PHY_DCOK] = 1. + */ + + ddr_pll_ctl.u64 = lmc_rd(priv, + CVMX_LMCX_DDR_PLL_CTL(i)); + ddr_pll_ctl.cn78xx.phy_dcok = 1; + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(i), ddr_pll_ctl.u64); + /* + * 6. Read LMC(0..3)_DDR_PLL_CTL and wait for + * the result. + */ + + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(i)); + + /* + * 7. Wait a minimum of 20 us. + */ + + udelay(20); /* Wait 20 us */ + } + + /* + * 5.9.4 LMC DRESET Initialization + * + * All of the DDR PLL, LMC global CK, and LMC interface + * enable initializations must be completed prior to starting + * this LMC DRESET initialization (Step 4). + * + * This LMC DRESET step is done for all enabled LMCs. + * + * There are special constraints on the ordering of DRESET + * initialization (Steps 4) and CK local initialization + * (Step 5) whenever CK local initialization must be executed. + * CK local initialization must be executed whenever the DDR + * PLL is being brought up (for each chip reset* and whenever + * the DDR clock speed changes). + * + * When Step 5 must be executed in the two-LMC mode case: + * - LMC0 DRESET initialization must occur before Step 5. + * - LMC1 DRESET initialization must occur after Step 5. + * + * When Step 5 must be executed in the four-LMC mode case: + * - LMC2 and LMC3 DRESET initialization must occur before + * Step 5. + * - LMC0 and LMC1 DRESET initialization must occur after + * Step 5. + */ + + if (octeon_is_cpuid(OCTEON_CN73XX)) { + /* ONE-LMC or TWO-LMC MODE BEFORE STEP 5 for cn73xx */ + cn78xx_lmc_dreset_init(priv, 0); + } else if (octeon_is_cpuid(OCTEON_CNF75XX)) { + if (if_mask == 0x3) { + /* + * 2-LMC Mode: LMC1 DRESET must occur + * before Step 5 + */ + cn78xx_lmc_dreset_init(priv, 1); + } + } else { + /* TWO-LMC MODE DRESET BEFORE STEP 5 */ + if (if_mask == 0x3) + cn78xx_lmc_dreset_init(priv, 0); + + /* FOUR-LMC MODE BEFORE STEP 5 */ + if (if_mask == 0xf) { + cn78xx_lmc_dreset_init(priv, 2); + cn78xx_lmc_dreset_init(priv, 3); + } + } + + /* + * 5.9.5 LMC CK Local Initialization + * + * All of DDR PLL, LMC global CK, and LMC interface-enable + * initializations must be completed prior to starting this + * LMC CK local initialization (Step 5). + * + * LMC CK Local initialization must be performed for each + * chip reset and whenever the DDR clock speed changes. This + * step needs to be performed only once, not once per LMC. + * + * There are special constraints on the ordering of DRESET + * initialization (Steps 4) and CK local initialization + * (Step 5) whenever CK local initialization must be executed. + * CK local initialization must be executed whenever the + * DDR PLL is being brought up (for each chip reset and + * whenever the DDR clock speed changes). + * + * When Step 5 must be executed in the two-LMC mode case: + * - LMC0 DRESET initialization must occur before Step 5. + * - LMC1 DRESET initialization must occur after Step 5. + * + * When Step 5 must be executed in the four-LMC mode case: + * - LMC2 and LMC3 DRESET initialization must occur before + * Step 5. + * - LMC0 and LMC1 DRESET initialization must occur after + * Step 5. + * + * LMC CK local initialization is different depending on + * whether two-LMC or four-LMC modes are desired. + */ + + if (if_mask == 0x3) { + int temp_lmc_if_num = octeon_is_cpuid(OCTEON_CNF75XX) ? + 1 : 0; + + /* + * 5.9.5.1 LMC CK Local Initialization for Two-LMC + * Mode + * + * 1. Write LMC0_DLL_CTL3 to its reset value. (Note + * that LMC0_DLL_CTL3[DLL_90_BYTE_SEL] = 0x2 .. 0x8 + * should also work.) + */ + + ddr_dll_ctl3.u64 = 0; + ddr_dll_ctl3.cn78xx.dclk90_recal_dis = 1; + + if (octeon_is_cpuid(OCTEON_CNF75XX)) + ddr_dll_ctl3.cn78xx.dll90_byte_sel = 7; + else + ddr_dll_ctl3.cn78xx.dll90_byte_sel = 1; + + lmc_wr(priv, + CVMX_LMCX_DLL_CTL3(temp_lmc_if_num), + ddr_dll_ctl3.u64); + + /* + * 2. Read LMC0_DLL_CTL3 and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DLL_CTL3(temp_lmc_if_num)); + + /* + * 3. Without changing any other fields in + * LMC0_DLL_CTL3, write + * LMC0_DLL_CTL3[DCLK90_FWD] = 1. Writing + * LMC0_DLL_CTL3[DCLK90_FWD] = 1 + * causes clock-delay information to be forwarded + * from LMC0 to LMC1. + */ + + ddr_dll_ctl3.cn78xx.dclk90_fwd = 1; + lmc_wr(priv, + CVMX_LMCX_DLL_CTL3(temp_lmc_if_num), + ddr_dll_ctl3.u64); + + /* + * 4. Read LMC0_DLL_CTL3 and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DLL_CTL3(temp_lmc_if_num)); + } + + if (if_mask == 0xf) { + /* + * 5.9.5.2 LMC CK Local Initialization for Four-LMC + * Mode + * + * 1. Write LMC2_DLL_CTL3 to its reset value except + * LMC2_DLL_CTL3[DLL90_BYTE_SEL] = 0x7. + */ + + ddr_dll_ctl3.u64 = 0; + ddr_dll_ctl3.cn78xx.dclk90_recal_dis = 1; + ddr_dll_ctl3.cn78xx.dll90_byte_sel = 7; + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(2), ddr_dll_ctl3.u64); + + /* + * 2. Write LMC3_DLL_CTL3 to its reset value except + * LMC3_DLL_CTL3[DLL90_BYTE_SEL] = 0x2. + */ + + ddr_dll_ctl3.u64 = 0; + ddr_dll_ctl3.cn78xx.dclk90_recal_dis = 1; + ddr_dll_ctl3.cn78xx.dll90_byte_sel = 2; + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(3), ddr_dll_ctl3.u64); + + /* + * 3. Read LMC3_DLL_CTL3 and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DLL_CTL3(3)); + + /* + * 4. Without changing any other fields in + * LMC2_DLL_CTL3, write LMC2_DLL_CTL3[DCLK90_FWD] = 1 + * and LMC2_DLL_CTL3[DCLK90_RECAL_ DIS] = 1. + * Writing LMC2_DLL_CTL3[DCLK90_FWD] = 1 causes LMC 2 + * to forward clockdelay information to LMC0. Setting + * LMC2_DLL_CTL3[DCLK90_RECAL_DIS] to 1 prevents LMC2 + * from periodically recalibrating this delay + * information. + */ + + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(2)); + ddr_dll_ctl3.cn78xx.dclk90_fwd = 1; + ddr_dll_ctl3.cn78xx.dclk90_recal_dis = 1; + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(2), ddr_dll_ctl3.u64); + + /* + * 5. Without changing any other fields in + * LMC3_DLL_CTL3, write LMC3_DLL_CTL3[DCLK90_FWD] = 1 + * and LMC3_DLL_CTL3[DCLK90_RECAL_ DIS] = 1. + * Writing LMC3_DLL_CTL3[DCLK90_FWD] = 1 causes LMC3 + * to forward clockdelay information to LMC1. Setting + * LMC3_DLL_CTL3[DCLK90_RECAL_DIS] to 1 prevents LMC3 + * from periodically recalibrating this delay + * information. + */ + + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(3)); + ddr_dll_ctl3.cn78xx.dclk90_fwd = 1; + ddr_dll_ctl3.cn78xx.dclk90_recal_dis = 1; + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(3), ddr_dll_ctl3.u64); + + /* + * 6. Read LMC3_DLL_CTL3 and wait for the result. + */ + + lmc_rd(priv, CVMX_LMCX_DLL_CTL3(3)); + } + + if (octeon_is_cpuid(OCTEON_CNF75XX)) { + /* + * cnf75xx 2-LMC Mode: LMC0 DRESET must occur after + * Step 5, Do LMC0 for 1-LMC Mode here too + */ + cn78xx_lmc_dreset_init(priv, 0); + } + + /* TWO-LMC MODE AFTER STEP 5 */ + if (if_mask == 0x3) { + if (octeon_is_cpuid(OCTEON_CNF75XX)) { + /* + * cnf75xx 2-LMC Mode: LMC0 DRESET must + * occur after Step 5 + */ + cn78xx_lmc_dreset_init(priv, 0); + } else { + cn78xx_lmc_dreset_init(priv, 1); + } + } + + /* FOUR-LMC MODE AFTER STEP 5 */ + if (if_mask == 0xf) { + cn78xx_lmc_dreset_init(priv, 0); + cn78xx_lmc_dreset_init(priv, 1); + + /* + * Enable periodic recalibration of DDR90 delay + * line in. + */ + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(0)); + ddr_dll_ctl3.cn78xx.dclk90_recal_dis = 0; + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(0), ddr_dll_ctl3.u64); + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(1)); + ddr_dll_ctl3.cn78xx.dclk90_recal_dis = 0; + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(1), ddr_dll_ctl3.u64); + } + + /* Enable fine tune mode for all LMCs */ + for (i = 0; i < 4; ++i) { + if ((if_mask & (1 << i)) == 0) + continue; + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(i)); + ddr_dll_ctl3.cn78xx.fine_tune_mode = 1; + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(i), ddr_dll_ctl3.u64); + } + + /* + * Enable the trim circuit on the appropriate channels to + * adjust the DDR clock duty cycle for chips that support + * it + */ + if (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X) || + octeon_is_cpuid(OCTEON_CN73XX) || + octeon_is_cpuid(OCTEON_CNF75XX)) { + union cvmx_lmcx_phy_ctl lmc_phy_ctl; + int i; + + for (i = 0; i < 4; ++i) { + if ((if_mask & (1 << i)) == 0) + continue; + + lmc_phy_ctl.u64 = + lmc_rd(priv, CVMX_LMCX_PHY_CTL(i)); + + if (octeon_is_cpuid(OCTEON_CNF75XX) || + octeon_is_cpuid(OCTEON_CN73XX_PASS1_3)) { + /* Both LMCs */ + lmc_phy_ctl.s.lv_mode = 0; + } else { + /* Odd LMCs = 0, Even LMCs = 1 */ + lmc_phy_ctl.s.lv_mode = (~i) & 1; + } + + debug("LMC%d: PHY_CTL : 0x%016llx\n", + i, lmc_phy_ctl.u64); + lmc_wr(priv, CVMX_LMCX_PHY_CTL(i), + lmc_phy_ctl.u64); + } + } + } + + /* + * 5.9.6 LMC RESET Initialization + * + * NOTE: this is now done as the first step in + * init_octeon3_ddr3_interface, rather than the last step in clock + * init. This reorg allows restarting per-LMC initialization should + * problems be encountered, rather than being forced to resort to + * resetting the chip and starting all over. + * + * Look for the code in octeon3_lmc.c: perform_lmc_reset(). + */ + + /* Fallthrough for all interfaces... */ +not_if0: + + /* + * Start the DDR clock so that its frequency can be measured. + * For some chips we must activate the memory controller with + * init_start to make the DDR clock start to run. + */ + if ((!octeon_is_cpuid(OCTEON_CN6XXX)) && + (!octeon_is_cpuid(OCTEON_CNF7XXX)) && + (!octeon_is_cpuid(OCTEON_CN7XXX))) { + union cvmx_lmcx_mem_cfg0 mem_cfg0; + + mem_cfg0.u64 = 0; + mem_cfg0.s.init_start = 1; + lmc_wr(priv, CVMX_LMCX_MEM_CFG0(if_num), mem_cfg0.u64); + lmc_rd(priv, CVMX_LMCX_MEM_CFG0(if_num)); + } + + set_ddr_clock_initialized(priv, if_num, 1); + + return 0; +} + +static void octeon_ipd_delay_cycles(u64 cycles) +{ + u64 start = csr_rd(CVMX_IPD_CLK_COUNT); + + while (start + cycles > csr_rd(CVMX_IPD_CLK_COUNT)) + ; +} + +static void octeon_ipd_delay_cycles_o3(u64 cycles) +{ + u64 start = csr_rd(CVMX_FPA_CLK_COUNT); + + while (start + cycles > csr_rd(CVMX_FPA_CLK_COUNT)) + ; +} + +static u32 measure_octeon_ddr_clock(struct ddr_priv *priv, + struct ddr_conf *ddr_conf, u32 cpu_hertz, + u32 ddr_hertz, u32 ddr_ref_hertz, + int if_num, u32 if_mask) +{ + u64 core_clocks; + u64 ddr_clocks; + u64 calc_ddr_hertz; + + if (ddr_conf) { + if (initialize_ddr_clock(priv, ddr_conf, cpu_hertz, + ddr_hertz, ddr_ref_hertz, if_num, + if_mask) != 0) + return 0; + } + + /* Dynamically determine the DDR clock speed */ + if (OCTEON_IS_OCTEON2() || octeon_is_cpuid(OCTEON_CN70XX)) { + core_clocks = csr_rd(CVMX_IPD_CLK_COUNT); + ddr_clocks = lmc_rd(priv, CVMX_LMCX_DCLK_CNT(if_num)); + /* How many cpu cycles to measure over */ + octeon_ipd_delay_cycles(100000000); + core_clocks = csr_rd(CVMX_IPD_CLK_COUNT) - core_clocks; + ddr_clocks = + lmc_rd(priv, CVMX_LMCX_DCLK_CNT(if_num)) - ddr_clocks; + calc_ddr_hertz = ddr_clocks * gd->bus_clk / core_clocks; + } else if (octeon_is_cpuid(OCTEON_CN7XXX)) { + core_clocks = csr_rd(CVMX_FPA_CLK_COUNT); + ddr_clocks = lmc_rd(priv, CVMX_LMCX_DCLK_CNT(if_num)); + /* How many cpu cycles to measure over */ + octeon_ipd_delay_cycles_o3(100000000); + core_clocks = csr_rd(CVMX_FPA_CLK_COUNT) - core_clocks; + ddr_clocks = + lmc_rd(priv, CVMX_LMCX_DCLK_CNT(if_num)) - ddr_clocks; + calc_ddr_hertz = ddr_clocks * gd->bus_clk / core_clocks; + } else { + core_clocks = csr_rd(CVMX_IPD_CLK_COUNT); + /* + * ignore overflow, starts counting when we enable the + * controller + */ + ddr_clocks = lmc_rd(priv, CVMX_LMCX_DCLK_CNT_LO(if_num)); + /* How many cpu cycles to measure over */ + octeon_ipd_delay_cycles(100000000); + core_clocks = csr_rd(CVMX_IPD_CLK_COUNT) - core_clocks; + ddr_clocks = + lmc_rd(priv, CVMX_LMCX_DCLK_CNT_LO(if_num)) - ddr_clocks; + calc_ddr_hertz = ddr_clocks * cpu_hertz / core_clocks; + } + + debug("core clocks: %llu, ddr clocks: %llu, calc rate: %llu\n", + core_clocks, ddr_clocks, calc_ddr_hertz); + debug("LMC%d: Measured DDR clock: %lld, cpu clock: %u, ddr clocks: %llu\n", + if_num, calc_ddr_hertz, cpu_hertz, ddr_clocks); + + /* Check for unreasonable settings. */ + if (calc_ddr_hertz < 10000) { + udelay(8000000 * 100); + printf("DDR clock misconfigured on interface %d. Resetting...\n", + if_num); + do_reset(NULL, 0, 0, NULL); + } + + return calc_ddr_hertz; +} + +u64 lmc_ddr3_rl_dbg_read(struct ddr_priv *priv, int if_num, int idx) +{ + union cvmx_lmcx_rlevel_dbg rlevel_dbg; + union cvmx_lmcx_rlevel_ctl rlevel_ctl; + + rlevel_ctl.u64 = lmc_rd(priv, CVMX_LMCX_RLEVEL_CTL(if_num)); + rlevel_ctl.s.byte = idx; + + lmc_wr(priv, CVMX_LMCX_RLEVEL_CTL(if_num), rlevel_ctl.u64); + lmc_rd(priv, CVMX_LMCX_RLEVEL_CTL(if_num)); + + rlevel_dbg.u64 = lmc_rd(priv, CVMX_LMCX_RLEVEL_DBG(if_num)); + return rlevel_dbg.s.bitmask; +} + +u64 lmc_ddr3_wl_dbg_read(struct ddr_priv *priv, int if_num, int idx) +{ + union cvmx_lmcx_wlevel_dbg wlevel_dbg; + + wlevel_dbg.u64 = 0; + wlevel_dbg.s.byte = idx; + + lmc_wr(priv, CVMX_LMCX_WLEVEL_DBG(if_num), wlevel_dbg.u64); + lmc_rd(priv, CVMX_LMCX_WLEVEL_DBG(if_num)); + + wlevel_dbg.u64 = lmc_rd(priv, CVMX_LMCX_WLEVEL_DBG(if_num)); + return wlevel_dbg.s.bitmask; +} + +int validate_ddr3_rlevel_bitmask(struct rlevel_bitmask *rlevel_bitmask_p, + int ddr_type) +{ + int i; + int errors = 0; + u64 mask = 0; /* Used in 64-bit comparisons */ + u8 mstart = 0; + u8 width = 0; + u8 firstbit = 0; + u8 lastbit = 0; + u8 bubble = 0; + u8 tbubble = 0; + u8 blank = 0; + u8 narrow = 0; + u8 trailing = 0; + u64 bitmask = rlevel_bitmask_p->bm; + u8 extras = 0; + u8 toolong = 0; + u64 temp; + + if (bitmask == 0) { + blank += RLEVEL_BITMASK_BLANK_ERROR; + } else { + /* Look for fb, the first bit */ + temp = bitmask; + while (!(temp & 1)) { + firstbit++; + temp >>= 1; + } + + /* Look for lb, the last bit */ + lastbit = firstbit; + while ((temp >>= 1)) + lastbit++; + + /* + * Start with the max range to try to find the largest mask + * within the bitmask data + */ + width = MASKRANGE_BITS; + for (mask = MASKRANGE; mask > 0; mask >>= 1, --width) { + for (mstart = lastbit - width + 1; mstart >= firstbit; + --mstart) { + temp = mask << mstart; + if ((bitmask & temp) == temp) + goto done_now; + } + } +done_now: + /* look for any more contiguous 1's to the right of mstart */ + if (width == MASKRANGE_BITS) { // only when maximum mask + while ((bitmask >> (mstart - 1)) & 1) { + // slide right over more 1's + --mstart; + // count the number of extra bits only for DDR4 + if (ddr_type == DDR4_DRAM) + extras++; + } + } + + /* Penalize any extra 1's beyond the maximum desired mask */ + if (extras > 0) + toolong = + RLEVEL_BITMASK_TOOLONG_ERROR * ((1 << extras) - 1); + + /* Detect if bitmask is too narrow. */ + if (width < 4) + narrow = (4 - width) * RLEVEL_BITMASK_NARROW_ERROR; + + /* + * detect leading bubble bits, that is, any 0's between first + * and mstart + */ + temp = bitmask >> (firstbit + 1); + i = mstart - firstbit - 1; + while (--i >= 0) { + if ((temp & 1) == 0) + bubble += RLEVEL_BITMASK_BUBBLE_BITS_ERROR; + temp >>= 1; + } + + temp = bitmask >> (mstart + width + extras); + i = lastbit - (mstart + width + extras - 1); + while (--i >= 0) { + if (temp & 1) { + /* + * Detect 1 bits after the trailing end of + * the mask, including last. + */ + trailing += RLEVEL_BITMASK_TRAILING_BITS_ERROR; + } else { + /* + * Detect trailing bubble bits, that is, + * any 0's between end-of-mask and last + */ + tbubble += RLEVEL_BITMASK_BUBBLE_BITS_ERROR; + } + temp >>= 1; + } + } + + errors = bubble + tbubble + blank + narrow + trailing + toolong; + + /* Pass out useful statistics */ + rlevel_bitmask_p->mstart = mstart; + rlevel_bitmask_p->width = width; + + debug_bitmask_print("bm:%08lx mask:%02lx, width:%2u, mstart:%2d, fb:%2u, lb:%2u (bu:%2d, tb:%2d, bl:%2d, n:%2d, t:%2d, x:%2d) errors:%3d %s\n", + (unsigned long)bitmask, mask, width, mstart, + firstbit, lastbit, bubble, tbubble, blank, + narrow, trailing, toolong, errors, + (errors) ? "=> invalid" : ""); + + return errors; +} + +int compute_ddr3_rlevel_delay(u8 mstart, u8 width, + union cvmx_lmcx_rlevel_ctl rlevel_ctl) +{ + int delay; + + debug_bitmask_print(" offset_en:%d", rlevel_ctl.s.offset_en); + + if (rlevel_ctl.s.offset_en) { + delay = max((int)mstart, + (int)(mstart + width - 1 - rlevel_ctl.s.offset)); + } else { + /* if (rlevel_ctl.s.offset) { *//* Experimental */ + if (0) { + delay = max(mstart + rlevel_ctl.s.offset, mstart + 1); + /* + * Insure that the offset delay falls within the + * bitmask + */ + delay = min(delay, mstart + width - 1); + } else { + /* Round down */ + delay = (width - 1) / 2 + mstart; + } + } + + return delay; +} + +/* Default ODT config must disable ODT */ +/* Must be const (read only) so that the structure is in flash */ +const struct dimm_odt_config disable_odt_config[] = { + /* 1 */ { 0, 0x0000, {.u64 = 0x0000}, {.u64 = 0x0000}, 0, 0x0000, 0 }, + /* 2 */ { 0, 0x0000, {.u64 = 0x0000}, {.u64 = 0x0000}, 0, 0x0000, 0 }, + /* 3 */ { 0, 0x0000, {.u64 = 0x0000}, {.u64 = 0x0000}, 0, 0x0000, 0 }, + /* 4 */ { 0, 0x0000, {.u64 = 0x0000}, {.u64 = 0x0000}, 0, 0x0000, 0 }, +}; + +/* Memory controller setup function */ +static int init_octeon_dram_interface(struct ddr_priv *priv, + struct ddr_conf *ddr_conf, + u32 ddr_hertz, u32 cpu_hertz, + u32 ddr_ref_hertz, int if_num, + u32 if_mask) +{ + u32 mem_size_mbytes = 0; + char *s; + + s = lookup_env(priv, "ddr_timing_hertz"); + if (s) + ddr_hertz = simple_strtoul(s, NULL, 0); + + if (OCTEON_IS_OCTEON3()) { + int lmc_restart_retries = 0; +#define DEFAULT_RESTART_RETRIES 3 + int lmc_restart_retries_limit = DEFAULT_RESTART_RETRIES; + + s = lookup_env(priv, "ddr_restart_retries_limit"); + if (s) + lmc_restart_retries_limit = simple_strtoul(s, NULL, 0); + +restart_lmc_init: + mem_size_mbytes = init_octeon3_ddr3_interface(priv, ddr_conf, + ddr_hertz, + cpu_hertz, + ddr_ref_hertz, + if_num, if_mask); + if (mem_size_mbytes == 0) { // 0 means restart is possible + if (lmc_restart_retries < lmc_restart_retries_limit) { + lmc_restart_retries++; + printf("N0.LMC%d Configuration problem: attempting LMC reset and init restart %d\n", + if_num, lmc_restart_retries); + goto restart_lmc_init; + } else { + if (lmc_restart_retries_limit > 0) { + printf("INFO: N0.LMC%d Configuration: fatal problem remains after %d LMC init retries - Resetting node...\n", + if_num, lmc_restart_retries); + mdelay(500); + do_reset(NULL, 0, 0, NULL); + } else { + // return an error, no restart + mem_size_mbytes = -1; + } + } + } + } + + debug("N0.LMC%d Configuration Completed: %d MB\n", + if_num, mem_size_mbytes); + + return mem_size_mbytes; +} + +#define WLEVEL_BYTE_BITS 5 +#define WLEVEL_BYTE_MSK ((1ULL << 5) - 1) + +void upd_wl_rank(union cvmx_lmcx_wlevel_rankx *lmc_wlevel_rank, + int byte, int delay) +{ + union cvmx_lmcx_wlevel_rankx temp_wlevel_rank; + + if (byte >= 0 && byte <= 8) { + temp_wlevel_rank.u64 = lmc_wlevel_rank->u64; + temp_wlevel_rank.u64 &= + ~(WLEVEL_BYTE_MSK << (WLEVEL_BYTE_BITS * byte)); + temp_wlevel_rank.u64 |= + ((delay & WLEVEL_BYTE_MSK) << (WLEVEL_BYTE_BITS * byte)); + lmc_wlevel_rank->u64 = temp_wlevel_rank.u64; + } +} + +int get_wl_rank(union cvmx_lmcx_wlevel_rankx *lmc_wlevel_rank, int byte) +{ + int delay = 0; + + if (byte >= 0 && byte <= 8) + delay = + ((lmc_wlevel_rank->u64) >> (WLEVEL_BYTE_BITS * + byte)) & WLEVEL_BYTE_MSK; + + return delay; +} + +void upd_rl_rank(union cvmx_lmcx_rlevel_rankx *lmc_rlevel_rank, + int byte, int delay) +{ + union cvmx_lmcx_rlevel_rankx temp_rlevel_rank; + + if (byte >= 0 && byte <= 8) { + temp_rlevel_rank.u64 = + lmc_rlevel_rank->u64 & ~(RLEVEL_BYTE_MSK << + (RLEVEL_BYTE_BITS * byte)); + temp_rlevel_rank.u64 |= + ((delay & RLEVEL_BYTE_MSK) << (RLEVEL_BYTE_BITS * byte)); + lmc_rlevel_rank->u64 = temp_rlevel_rank.u64; + } +} + +int get_rl_rank(union cvmx_lmcx_rlevel_rankx *lmc_rlevel_rank, int byte) +{ + int delay = 0; + + if (byte >= 0 && byte <= 8) + delay = + ((lmc_rlevel_rank->u64) >> (RLEVEL_BYTE_BITS * + byte)) & RLEVEL_BYTE_MSK; + + return delay; +} + +void rlevel_to_wlevel(union cvmx_lmcx_rlevel_rankx *lmc_rlevel_rank, + union cvmx_lmcx_wlevel_rankx *lmc_wlevel_rank, int byte) +{ + int byte_delay = get_rl_rank(lmc_rlevel_rank, byte); + + debug("Estimating Wlevel delay byte %d: ", byte); + debug("Rlevel=%d => ", byte_delay); + byte_delay = divide_roundup(byte_delay, 2) & 0x1e; + debug("Wlevel=%d\n", byte_delay); + upd_wl_rank(lmc_wlevel_rank, byte, byte_delay); +} + +/* Delay trend: constant=0, decreasing=-1, increasing=1 */ +static s64 calc_delay_trend(s64 v) +{ + if (v == 0) + return 0; + if (v < 0) + return -1; + + return 1; +} + +/* + * Evaluate delay sequence across the whole range of byte delays while + * keeping track of the overall delay trend, increasing or decreasing. + * If the trend changes charge an error amount to the score. + */ + +// NOTE: "max_adj_delay_inc" argument is, by default, 1 for DDR3 and 2 for DDR4 + +int nonseq_del(struct rlevel_byte_data *rlevel_byte, int start, int end, + int max_adj_delay_inc) +{ + s64 error = 0; + s64 delay_trend, prev_trend = 0; + int byte_idx; + s64 seq_err; + s64 adj_err; + s64 delay_inc; + s64 delay_diff; + + for (byte_idx = start; byte_idx < end; ++byte_idx) { + delay_diff = rlevel_byte[byte_idx + 1].delay - + rlevel_byte[byte_idx].delay; + delay_trend = calc_delay_trend(delay_diff); + + /* + * Increment error each time the trend changes to the + * opposite direction. + */ + if (prev_trend != 0 && delay_trend != 0 && + prev_trend != delay_trend) { + seq_err = RLEVEL_NONSEQUENTIAL_DELAY_ERROR; + } else { + seq_err = 0; + } + + // how big was the delay change, if any + delay_inc = abs(delay_diff); + + /* + * Even if the trend did not change to the opposite direction, + * check for the magnitude of the change, and scale the + * penalty by the amount that the size is larger than the + * provided limit. + */ + if (max_adj_delay_inc != 0 && delay_inc > max_adj_delay_inc) { + adj_err = (delay_inc - max_adj_delay_inc) * + RLEVEL_ADJACENT_DELAY_ERROR; + } else { + adj_err = 0; + } + + rlevel_byte[byte_idx + 1].sqerrs = seq_err + adj_err; + error += seq_err + adj_err; + + debug_bitmask_print("Byte %d: %d, Byte %d: %d, delay_trend: %ld, prev_trend: %ld, [%ld/%ld]%s%s\n", + byte_idx + 0, + rlevel_byte[byte_idx + 0].delay, + byte_idx + 1, + rlevel_byte[byte_idx + 1].delay, + delay_trend, + prev_trend, seq_err, adj_err, + (seq_err) ? + " => Nonsequential byte delay" : "", + (adj_err) ? + " => Adjacent delay error" : ""); + + if (delay_trend != 0) + prev_trend = delay_trend; + } + + return (int)error; +} + +int roundup_ddr3_wlevel_bitmask(int bitmask) +{ + int shifted_bitmask; + int leader; + int delay; + + for (leader = 0; leader < 8; ++leader) { + shifted_bitmask = (bitmask >> leader); + if ((shifted_bitmask & 1) == 0) + break; + } + + for (leader = leader; leader < 16; ++leader) { + shifted_bitmask = (bitmask >> (leader % 8)); + if (shifted_bitmask & 1) + break; + } + + delay = (leader & 1) ? leader + 1 : leader; + delay = delay % 8; + + return delay; +} + +/* Octeon 2 */ +static void oct2_ddr3_seq(struct ddr_priv *priv, int rank_mask, int if_num, + int sequence) +{ + char *s; + +#ifdef DEBUG_PERFORM_DDR3_SEQUENCE + static const char * const sequence_str[] = { + "power-up/init", + "read-leveling", + "self-refresh entry", + "self-refresh exit", + "precharge power-down entry", + "precharge power-down exit", + "write-leveling", + "illegal" + }; +#endif + + union cvmx_lmcx_control lmc_control; + union cvmx_lmcx_config lmc_config; + int save_ddr2t; + + lmc_control.u64 = lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); + save_ddr2t = lmc_control.s.ddr2t; + + if (save_ddr2t == 0 && octeon_is_cpuid(OCTEON_CN63XX_PASS1_X)) { + /* Some register parts (IDT and TI included) do not like + * the sequence that LMC generates for an MRS register + * write in 1T mode. In this case, the register part does + * not properly forward the MRS register write to the DRAM + * parts. See errata (LMC-14548) Issues with registered + * DIMMs. + */ + debug("Forcing DDR 2T during init seq. Re: Pass 1 LMC-14548\n"); + lmc_control.s.ddr2t = 1; + } + + s = lookup_env(priv, "ddr_init_2t"); + if (s) + lmc_control.s.ddr2t = simple_strtoul(s, NULL, 0); + + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), lmc_control.u64); + + lmc_config.u64 = lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + + lmc_config.s.init_start = 1; + if (OCTEON_IS_OCTEON2()) + lmc_config.cn63xx.sequence = sequence; + lmc_config.s.rankmask = rank_mask; + +#ifdef DEBUG_PERFORM_DDR3_SEQUENCE + debug("Performing LMC sequence: rank_mask=0x%02x, sequence=%d, %s\n", + rank_mask, sequence, sequence_str[sequence]); +#endif + + lmc_wr(priv, CVMX_LMCX_CONFIG(if_num), lmc_config.u64); + lmc_rd(priv, CVMX_LMCX_CONFIG(if_num)); + udelay(600); /* Wait a while */ + + lmc_control.s.ddr2t = save_ddr2t; + lmc_wr(priv, CVMX_LMCX_CONTROL(if_num), lmc_control.u64); + lmc_rd(priv, CVMX_LMCX_CONTROL(if_num)); +} + +/* Check to see if any custom offset values are used */ +static int is_dll_offset_provided(const int8_t *dll_offset_table) +{ + int i; + + if (!dll_offset_table) /* Check for pointer to table. */ + return 0; + + for (i = 0; i < 9; ++i) { + if (dll_offset_table[i] != 0) + return 1; + } + + return 0; +} + +void change_dll_offset_enable(struct ddr_priv *priv, int if_num, int change) +{ + union cvmx_lmcx_dll_ctl3 ddr_dll_ctl3; + + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + SET_DDR_DLL_CTL3(offset_ena, !!change); + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); +} + +unsigned short load_dll_offset(struct ddr_priv *priv, int if_num, + int dll_offset_mode, int byte_offset, int byte) +{ + union cvmx_lmcx_dll_ctl3 ddr_dll_ctl3; + int field_width = 6; + /* + * byte_sel: + * 0x1 = byte 0, ..., 0x9 = byte 8 + * 0xA = all bytes + */ + int byte_sel = (byte == 10) ? byte : byte + 1; + + if (octeon_is_cpuid(OCTEON_CN6XXX)) + field_width = 5; + + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + SET_DDR_DLL_CTL3(load_offset, 0); + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + + SET_DDR_DLL_CTL3(mode_sel, dll_offset_mode); + SET_DDR_DLL_CTL3(offset, + (abs(byte_offset) & (~(-1 << field_width))) | + (_sign(byte_offset) << field_width)); + SET_DDR_DLL_CTL3(byte_sel, byte_sel); + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + + SET_DDR_DLL_CTL3(load_offset, 1); + lmc_wr(priv, CVMX_LMCX_DLL_CTL3(if_num), ddr_dll_ctl3.u64); + ddr_dll_ctl3.u64 = lmc_rd(priv, CVMX_LMCX_DLL_CTL3(if_num)); + + return (unsigned short)GET_DDR_DLL_CTL3(offset); +} + +void process_custom_dll_offsets(struct ddr_priv *priv, int if_num, + const char *enable_str, + const int8_t *offsets, const char *byte_str, + int mode) +{ + const char *s; + int enabled; + int provided; + int byte_offset; + unsigned short offset[9] = { 0 }; + int byte; + + s = lookup_env(priv, enable_str); + if (s) + enabled = !!simple_strtol(s, NULL, 0); + else + enabled = -1; + + /* + * enabled == -1: no override, do only configured offsets if provided + * enabled == 0: override OFF, do NOT do it even if configured + * offsets provided + * enabled == 1: override ON, do it for overrides plus configured + * offsets + */ + + if (enabled == 0) + return; + + provided = is_dll_offset_provided(offsets); + + if (enabled < 0 && !provided) + return; + + change_dll_offset_enable(priv, if_num, 0); + + for (byte = 0; byte < 9; ++byte) { + // always take the provided, if available + byte_offset = (provided) ? offsets[byte] : 0; + + // then, if enabled, use any overrides present + if (enabled > 0) { + s = lookup_env(priv, byte_str, if_num, byte); + if (s) + byte_offset = simple_strtol(s, NULL, 0); + } + + offset[byte] = + load_dll_offset(priv, if_num, mode, byte_offset, byte); + } + + change_dll_offset_enable(priv, if_num, 1); + + debug("N0.LMC%d: DLL %s Offset 8:0 : 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", + if_num, (mode == 2) ? "Read " : "Write", + offset[8], offset[7], offset[6], offset[5], offset[4], + offset[3], offset[2], offset[1], offset[0]); +} + +void ddr_init_seq(struct ddr_priv *priv, int rank_mask, int if_num) +{ + char *s; + int ddr_init_loops = 1; + int rankx; + + s = lookup_env(priv, "ddr%d_init_loops", if_num); + if (s) + ddr_init_loops = simple_strtoul(s, NULL, 0); + + while (ddr_init_loops--) { + for (rankx = 0; rankx < 8; rankx++) { + if (!(rank_mask & (1 << rankx))) + continue; + + if (OCTEON_IS_OCTEON3()) { + /* power-up/init */ + oct3_ddr3_seq(priv, 1 << rankx, if_num, 0); + } else { + /* power-up/init */ + oct2_ddr3_seq(priv, 1 << rankx, if_num, 0); + } + + udelay(1000); /* Wait a while. */ + + s = lookup_env(priv, "ddr_sequence1"); + if (s) { + int sequence1; + + sequence1 = simple_strtoul(s, NULL, 0); + + if (OCTEON_IS_OCTEON3()) { + oct3_ddr3_seq(priv, 1 << rankx, + if_num, sequence1); + } else { + oct2_ddr3_seq(priv, 1 << rankx, + if_num, sequence1); + } + } + + s = lookup_env(priv, "ddr_sequence2"); + if (s) { + int sequence2; + + sequence2 = simple_strtoul(s, NULL, 0); + + if (OCTEON_IS_OCTEON3()) + oct3_ddr3_seq(priv, 1 << rankx, + if_num, sequence2); + else + oct2_ddr3_seq(priv, 1 << rankx, + if_num, sequence2); + } + } + } +} + +static int octeon_ddr_initialize(struct ddr_priv *priv, u32 cpu_hertz, + u32 ddr_hertz, u32 ddr_ref_hertz, + u32 if_mask, + struct ddr_conf *ddr_conf, + u32 *measured_ddr_hertz) +{ + u32 ddr_conf_valid_mask = 0; + int memsize_mbytes = 0; + char *eptr; + int if_idx; + u32 ddr_max_speed = 667000000; + u32 calc_ddr_hertz = -1; + int val; + int ret; + + if (env_get("ddr_verbose") || env_get("ddr_prompt")) + priv->flags |= FLAG_DDR_VERBOSE; + +#ifdef DDR_VERBOSE + priv->flags |= FLAG_DDR_VERBOSE; +#endif + + if (env_get("ddr_trace_init")) { + printf("Parameter ddr_trace_init found in environment.\n"); + priv->flags |= FLAG_DDR_TRACE_INIT; + priv->flags |= FLAG_DDR_VERBOSE; + } + + priv->flags |= FLAG_DDR_DEBUG; + + val = env_get_ulong("ddr_debug", 10, (u32)-1); + switch (val) { + case 0: + priv->flags &= ~FLAG_DDR_DEBUG; + printf("Parameter ddr_debug clear in environment\n"); + break; + case (u32)-1: + break; + default: + printf("Parameter ddr_debug set in environment\n"); + priv->flags |= FLAG_DDR_DEBUG; + priv->flags |= FLAG_DDR_VERBOSE; + break; + } + if (env_get("ddr_prompt")) + priv->flags |= FLAG_DDR_PROMPT; + + /* Force ddr_verbose for failsafe debugger */ + if (priv->flags & FLAG_FAILSAFE_MODE) + priv->flags |= FLAG_DDR_VERBOSE; + +#ifdef DDR_DEBUG + priv->flags |= FLAG_DDR_DEBUG; + /* Keep verbose on while we are still debugging. */ + priv->flags |= FLAG_DDR_VERBOSE; +#endif + + if ((octeon_is_cpuid(OCTEON_CN61XX) || + octeon_is_cpuid(OCTEON_CNF71XX)) && ddr_max_speed > 533333333) { + ddr_max_speed = 533333333; + } else if (octeon_is_cpuid(OCTEON_CN7XXX)) { + /* Override speed restrictions to support internal testing. */ + ddr_max_speed = 1210000000; + } + + if (ddr_hertz > ddr_max_speed) { + printf("DDR clock speed %u exceeds maximum supported DDR speed, reducing to %uHz\n", + ddr_hertz, ddr_max_speed); + ddr_hertz = ddr_max_speed; + } + + if (OCTEON_IS_OCTEON3()) { // restrict check + if (ddr_hertz > cpu_hertz) { + printf("\nFATAL ERROR: DDR speed %u exceeds CPU speed %u, exiting...\n\n", + ddr_hertz, cpu_hertz); + return -1; + } + } + + /* Enable L2 ECC */ + eptr = env_get("disable_l2_ecc"); + if (eptr) { + printf("Disabling L2 ECC based on disable_l2_ecc environment variable\n"); + union cvmx_l2c_ctl l2c_val; + + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + l2c_val.s.disecc = 1; + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); + } else { + union cvmx_l2c_ctl l2c_val; + + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + l2c_val.s.disecc = 0; + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); + } + + /* + * Init the L2C, must be done before DRAM access so that we + * know L2 is empty + */ + eptr = env_get("disable_l2_index_aliasing"); + if (eptr) { + union cvmx_l2c_ctl l2c_val; + + puts("L2 index aliasing disabled.\n"); + + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + l2c_val.s.disidxalias = 1; + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); + } else { + union cvmx_l2c_ctl l2c_val; + + /* Enable L2C index aliasing */ + + l2c_val.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + l2c_val.s.disidxalias = 0; + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_val.u64); + } + + if (OCTEON_IS_OCTEON3()) { + /* + * rdf_cnt: Defines the sample point of the LMC response data in + * the DDR-clock/core-clock crossing. For optimal + * performance set to 10 * (DDR-clock period/core-clock + * period) - 1. To disable set to 0. All other values + * are reserved. + */ + + union cvmx_l2c_ctl l2c_ctl; + u64 rdf_cnt; + char *s; + + l2c_ctl.u64 = l2c_rd(priv, CVMX_L2C_CTL_REL); + + /* + * It is more convenient to compute the ratio using clock + * frequencies rather than clock periods. + */ + rdf_cnt = (((u64)10 * cpu_hertz) / ddr_hertz) - 1; + rdf_cnt = rdf_cnt < 256 ? rdf_cnt : 255; + l2c_ctl.cn78xx.rdf_cnt = rdf_cnt; + + s = lookup_env(priv, "early_fill_count"); + if (s) + l2c_ctl.cn78xx.rdf_cnt = simple_strtoul(s, NULL, 0); + + debug("%-45s : %d, cpu_hertz:%d, ddr_hertz:%d\n", + "EARLY FILL COUNT ", l2c_ctl.cn78xx.rdf_cnt, cpu_hertz, + ddr_hertz); + l2c_wr(priv, CVMX_L2C_CTL_REL, l2c_ctl.u64); + } + + /* Check for lower DIMM socket populated */ + for (if_idx = 0; if_idx < 4; ++if_idx) { + if ((if_mask & (1 << if_idx)) && + validate_dimm(priv, + &ddr_conf[(int)if_idx].dimm_config_table[0], + 0)) + ddr_conf_valid_mask |= (1 << if_idx); + } + + if (octeon_is_cpuid(OCTEON_CN68XX) || octeon_is_cpuid(OCTEON_CN78XX)) { + int four_lmc_mode = 1; + char *s; + + if (priv->flags & FLAG_FAILSAFE_MODE) + four_lmc_mode = 0; + + /* Pass 1.0 disable four LMC mode. + * See errata (LMC-15811) + */ + if (octeon_is_cpuid(OCTEON_CN68XX_PASS1_0)) + four_lmc_mode = 0; + + s = env_get("ddr_four_lmc"); + if (s) { + four_lmc_mode = simple_strtoul(s, NULL, 0); + printf("Parameter found in environment. ddr_four_lmc = %d\n", + four_lmc_mode); + } + + if (!four_lmc_mode) { + puts("Forcing two-LMC Mode.\n"); + /* Invalidate LMC[2:3] */ + ddr_conf_valid_mask &= ~(3 << 2); + } + } else if (octeon_is_cpuid(OCTEON_CN73XX)) { + int one_lmc_mode = 0; + char *s; + + s = env_get("ddr_one_lmc"); + if (s) { + one_lmc_mode = simple_strtoul(s, NULL, 0); + printf("Parameter found in environment. ddr_one_lmc = %d\n", + one_lmc_mode); + } + + if (one_lmc_mode) { + puts("Forcing one-LMC Mode.\n"); + /* Invalidate LMC[1:3] */ + ddr_conf_valid_mask &= ~(1 << 1); + } + } + + if (!ddr_conf_valid_mask) { + printf + ("ERROR: No valid DIMMs detected on any DDR interface.\n"); + hang(); + return -1; // testr-only: no ret negativ!!! + } + + /* + * We measure the DDR frequency by counting DDR clocks. We can + * confirm or adjust the expected frequency as necessary. We use + * the measured frequency to make accurate timing calculations + * used to configure the controller. + */ + for (if_idx = 0; if_idx < 4; ++if_idx) { + u32 tmp_hertz; + + if (!(ddr_conf_valid_mask & (1 << if_idx))) + continue; + +try_again: + /* + * only check for alternate refclk wanted on chips that + * support it + */ + if ((octeon_is_cpuid(OCTEON_CN73XX)) || + (octeon_is_cpuid(OCTEON_CNF75XX)) || + (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X))) { + // only need do this if we are LMC0 + if (if_idx == 0) { + union cvmx_lmcx_ddr_pll_ctl ddr_pll_ctl; + + ddr_pll_ctl.u64 = + lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0)); + + /* + * If we are asking for 100 MHz refclk, we can + * only get it via alternate, so switch to it + */ + if (ddr_ref_hertz == 100000000) { + ddr_pll_ctl.cn78xx.dclk_alt_refclk_sel = + 1; + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(0), + ddr_pll_ctl.u64); + udelay(1000); // wait 1 msec + } else { + /* + * If we are NOT asking for 100MHz, + * then reset to (assumed) 50MHz and go + * on + */ + ddr_pll_ctl.cn78xx.dclk_alt_refclk_sel = + 0; + lmc_wr(priv, CVMX_LMCX_DDR_PLL_CTL(0), + ddr_pll_ctl.u64); + udelay(1000); // wait 1 msec + } + } + } else { + if (ddr_ref_hertz == 100000000) { + debug("N0: DRAM init: requested 100 MHz refclk NOT SUPPORTED\n"); + ddr_ref_hertz = CONFIG_REF_HERTZ; + } + } + + tmp_hertz = measure_octeon_ddr_clock(priv, &ddr_conf[if_idx], + cpu_hertz, ddr_hertz, + ddr_ref_hertz, if_idx, + ddr_conf_valid_mask); + + /* + * only check for alternate refclk acquired on chips that + * support it + */ + if ((octeon_is_cpuid(OCTEON_CN73XX)) || + (octeon_is_cpuid(OCTEON_CNF75XX)) || + (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X))) { + /* + * if we are LMC0 and we are asked for 100 MHz refclk, + * we must be sure it is available + * If not, we print an error message, set to 50MHz, + * and go on... + */ + if (if_idx == 0 && ddr_ref_hertz == 100000000) { + /* + * Validate that the clock returned is close + * enough to the clock desired + */ + // FIXME: is 5% close enough? + int hertz_diff = + abs((int)tmp_hertz - (int)ddr_hertz); + if (hertz_diff > ((int)ddr_hertz * 5 / 100)) { + // nope, diff is greater than than 5% + debug("N0: DRAM init: requested 100 MHz refclk NOT FOUND\n"); + ddr_ref_hertz = CONFIG_REF_HERTZ; + // clear the flag before trying again!! + set_ddr_clock_initialized(priv, 0, 0); + goto try_again; + } else { + debug("N0: DRAM Init: requested 100 MHz refclk FOUND and SELECTED\n"); + } + } + } + + if (tmp_hertz > 0) + calc_ddr_hertz = tmp_hertz; + debug("LMC%d: measured speed: %u hz\n", if_idx, tmp_hertz); + } + + if (measured_ddr_hertz) + *measured_ddr_hertz = calc_ddr_hertz; + + memsize_mbytes = 0; + for (if_idx = 0; if_idx < 4; ++if_idx) { + if (!(ddr_conf_valid_mask & (1 << if_idx))) + continue; + + ret = init_octeon_dram_interface(priv, &ddr_conf[if_idx], + calc_ddr_hertz, + cpu_hertz, ddr_ref_hertz, + if_idx, ddr_conf_valid_mask); + if (ret > 0) + memsize_mbytes += ret; + } + + if (memsize_mbytes == 0) + /* All interfaces failed to initialize, so return error */ + return -1; + + /* + * switch over to DBI mode only for chips that support it, and + * enabled by envvar + */ + if ((octeon_is_cpuid(OCTEON_CN73XX)) || + (octeon_is_cpuid(OCTEON_CNF75XX)) || + (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X))) { + eptr = env_get("ddr_dbi_switchover"); + if (eptr) { + printf("DBI Switchover starting...\n"); + cvmx_dbi_switchover(priv); + printf("DBI Switchover finished.\n"); + } + } + + /* call HW-assist tuning here on chips that support it */ + if ((octeon_is_cpuid(OCTEON_CN73XX)) || + (octeon_is_cpuid(OCTEON_CNF75XX)) || + (octeon_is_cpuid(OCTEON_CN78XX_PASS2_X))) + cvmx_maybe_tune_node(priv, calc_ddr_hertz); + + eptr = env_get("limit_dram_mbytes"); + if (eptr) { + unsigned int mbytes = simple_strtoul(eptr, NULL, 10); + + if (mbytes > 0) { + memsize_mbytes = mbytes; + printf("Limiting DRAM size to %d MBytes based on limit_dram_mbytes env. variable\n", + mbytes); + } + } + + debug("LMC Initialization complete. Total DRAM %d MB\n", + memsize_mbytes); + + return memsize_mbytes; +} + +static int octeon_ddr_probe(struct udevice *dev) +{ + struct ddr_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args l2c_node; + struct ddr_conf *ddr_conf_ptr; + u32 ddr_conf_valid_mask = 0; + u32 measured_ddr_hertz = 0; + int conf_table_count; + int def_ddr_freq; + u32 mem_mbytes = 0; + u32 ddr_hertz; + u32 ddr_ref_hertz; + int alt_refclk; + const char *eptr; + fdt_addr_t addr; + u64 *ptr; + u64 val; + int ret; + int i; + + /* Don't try to re-init the DDR controller after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* + * Dummy read all local variables into cache, so that they are + * locked in cache when the DDR code runs with flushes etc enabled + */ + ptr = (u64 *)_end; + for (i = 0; i < (0x100000 / sizeof(u64)); i++) + val = readq(ptr++); + + /* + * The base addresses of LMC and L2C are read from the DT. This + * makes it possible to use the DDR init code without the need + * of the "node" variable, describing on which node to access. The + * node number is already included implicitly in the base addresses + * read from the DT this way. + */ + + /* Get LMC base address */ + priv->lmc_base = dev_remap_addr(dev); + debug("%s: lmc_base=%p\n", __func__, priv->lmc_base); + + /* Get L2C base address */ + ret = dev_read_phandle_with_args(dev, "l2c-handle", NULL, 0, 0, + &l2c_node); + if (ret) { + printf("Can't access L2C node!\n"); + return -ENODEV; + } + + addr = ofnode_get_addr(l2c_node.node); + if (addr == FDT_ADDR_T_NONE) { + printf("Can't access L2C node!\n"); + return -ENODEV; + } + + priv->l2c_base = map_physmem(addr, 0, MAP_NOCACHE); + debug("%s: l2c_base=%p\n", __func__, priv->l2c_base); + + ddr_conf_ptr = octeon_ddr_conf_table_get(&conf_table_count, + &def_ddr_freq); + if (!ddr_conf_ptr) { + printf("ERROR: unable to determine DDR configuration\n"); + return -ENODEV; + } + + for (i = 0; i < conf_table_count; i++) { + if (ddr_conf_ptr[i].dimm_config_table[0].spd_addrs[0] || + ddr_conf_ptr[i].dimm_config_table[0].spd_ptrs[0]) + ddr_conf_valid_mask |= 1 << i; + } + + /* + * Check for special case of mismarked 3005 samples, + * and adjust cpuid + */ + alt_refclk = 0; + ddr_hertz = def_ddr_freq * 1000000; + + eptr = env_get("ddr_clock_hertz"); + if (eptr) { + ddr_hertz = simple_strtoul(eptr, NULL, 0); + gd->mem_clk = divide_nint(ddr_hertz, 1000000); + printf("Parameter found in environment. ddr_clock_hertz = %d\n", + ddr_hertz); + } + + ddr_ref_hertz = octeon3_refclock(alt_refclk, + ddr_hertz, + &ddr_conf_ptr[0].dimm_config_table[0]); + + debug("Initializing DDR, clock = %uhz, reference = %uhz\n", + ddr_hertz, ddr_ref_hertz); + + mem_mbytes = octeon_ddr_initialize(priv, gd->cpu_clk, + ddr_hertz, ddr_ref_hertz, + ddr_conf_valid_mask, + ddr_conf_ptr, &measured_ddr_hertz); + debug("Mem size in MBYTES: %u\n", mem_mbytes); + + gd->mem_clk = divide_nint(measured_ddr_hertz, 1000000); + + debug("Measured DDR clock %d Hz\n", measured_ddr_hertz); + + if (measured_ddr_hertz != 0) { + if (!gd->mem_clk) { + /* + * If ddr_clock not set, use measured clock + * and don't warn + */ + gd->mem_clk = divide_nint(measured_ddr_hertz, 1000000); + } else if ((measured_ddr_hertz > ddr_hertz + 3000000) || + (measured_ddr_hertz < ddr_hertz - 3000000)) { + printf("\nWARNING:\n"); + printf("WARNING: Measured DDR clock mismatch! expected: %lld MHz, measured: %lldMHz, cpu clock: %lu MHz\n", + divide_nint(ddr_hertz, 1000000), + divide_nint(measured_ddr_hertz, 1000000), + gd->cpu_clk); + printf("WARNING:\n\n"); + gd->mem_clk = divide_nint(measured_ddr_hertz, 1000000); + } + } + + if (!mem_mbytes) + return -ENODEV; + + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = MB(mem_mbytes); + + /* + * For 6XXX generate a proper error when reading/writing + * non-existent memory locations. + */ + cvmx_l2c_set_big_size(priv, mem_mbytes, 0); + + debug("Ram size %uMiB\n", mem_mbytes); + + return 0; +} + +static int octeon_get_info(struct udevice *dev, struct ram_info *info) +{ + struct ddr_priv *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops octeon_ops = { + .get_info = octeon_get_info, +}; + +static const struct udevice_id octeon_ids[] = { + {.compatible = "cavium,octeon-7xxx-ddr4" }, + { } +}; + +U_BOOT_DRIVER(octeon_ddr) = { + .name = "octeon_ddr", + .id = UCLASS_RAM, + .of_match = octeon_ids, + .ops = &octeon_ops, + .probe = octeon_ddr_probe, + .plat_auto = sizeof(struct ddr_priv), +}; diff --git a/roms/u-boot/drivers/ram/ram-uclass.c b/roms/u-boot/drivers/ram/ram-uclass.c new file mode 100644 index 000000000..f4d387fed --- /dev/null +++ b/roms/u-boot/drivers/ram/ram-uclass.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +int ram_get_info(struct udevice *dev, struct ram_info *info) +{ + struct ram_ops *ops = ram_get_ops(dev); + + if (!ops->get_info) + return -ENOSYS; + + return ops->get_info(dev, info); +} + +UCLASS_DRIVER(ram) = { + .id = UCLASS_RAM, + .name = "ram", +}; diff --git a/roms/u-boot/drivers/ram/rockchip/Kconfig b/roms/u-boot/drivers/ram/rockchip/Kconfig new file mode 100644 index 000000000..c459bbf5e --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/Kconfig @@ -0,0 +1,52 @@ +config RAM_ROCKCHIP + bool "Ram drivers support for Rockchip SoCs" + depends on RAM && ARCH_ROCKCHIP + default y + help + This enables support for ram drivers Rockchip SoCs. + +config ROCKCHIP_SDRAM_COMMON + bool "Enable rockchip sdram common driver" + depends on TPL_RAM || SPL_RAM + help + This enable sdram common driver + +config RAM_ROCKCHIP_DEBUG + bool "Rockchip ram drivers debugging" + depends on RAM_ROCKCHIP + default y + help + This enables debugging ram driver API's for the platforms + based on Rockchip SoCs. + + This is an option for developers to understand the ram drivers + initialization, configurations and etc. + +config RAM_PX30_DDR4 + bool "DDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables DDR4 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR2 + bool "LPDDR2 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR2 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_PX30_LPDDR3 + bool "LPDDR3 support for Rockchip PX30" + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 + help + This enables LPDDR3 sdram support instead of the default DDR3 support + on Rockchip PC30 SoCs. + +config RAM_RK3399_LPDDR4 + bool "LPDDR4 support for Rockchip RK3399" + depends on RAM_ROCKCHIP && ROCKCHIP_RK3399 + help + This enables LPDDR4 sdram code support for the platforms based + on Rockchip RK3399 SoC. + diff --git a/roms/u-boot/drivers/ram/rockchip/Makefile b/roms/u-boot/drivers/ram/rockchip/Makefile new file mode 100644 index 000000000..c3ec89ada --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH +# + +obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o +obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o +obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o +obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o +obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o +obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o +obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o +obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o diff --git a/roms/u-boot/drivers/ram/rockchip/dmc-rk3368.c b/roms/u-boot/drivers/ram/rockchip/dmc-rk3368.c new file mode 100644 index 000000000..a9d051852 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/dmc-rk3368.c @@ -0,0 +1,1006 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct dram_info { + struct ram_info info; + struct clk ddr_clk; + struct rk3368_cru *cru; + struct rk3368_grf *grf; + struct rk3368_ddr_pctl *pctl; + struct rk3368_ddrphy *phy; + struct rk3368_pmu_grf *pmugrf; + struct rk3368_msch *msch; +}; + +struct rk3368_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3368_dmc of_plat; +#endif + struct rk3288_sdram_pctl_timing pctl_timing; + u32 trefi_mem_ddr3; + struct rk3288_sdram_channel chan; + struct regmap *map; + u32 ddr_freq; + u32 memory_schedule; + u32 ddr_speed_bin; + u32 tfaw_mult; +}; + +/* PTCL bits */ +enum { + /* PCTL_DFISTCFG0 */ + DFI_INIT_START = BIT(0), + DFI_DATA_BYTE_DISABLE_EN = BIT(2), + + /* PCTL_DFISTCFG1 */ + DFI_DRAM_CLK_SR_EN = BIT(0), + DFI_DRAM_CLK_DPD_EN = BIT(1), + ODT_LEN_BL8_W_SHIFT = 16, + + /* PCTL_DFISTCFG2 */ + DFI_PARITY_INTR_EN = BIT(0), + DFI_PARITY_EN = BIT(1), + + /* PCTL_DFILPCFG0 */ + TLP_RESP_TIME_SHIFT = 16, + LP_SR_EN = BIT(8), + LP_PD_EN = BIT(0), + + /* PCTL_DFIODTCFG */ + RANK0_ODT_WRITE_SEL = BIT(3), + RANK1_ODT_WRITE_SEL = BIT(11), + + /* PCTL_SCFG */ + HW_LOW_POWER_EN = BIT(0), + + /* PCTL_MCMD */ + START_CMD = BIT(31), + MCMD_RANK0 = BIT(20), + MCMD_RANK1 = BIT(21), + DESELECT_CMD = 0, + PREA_CMD, + REF_CMD, + MRS_CMD, + ZQCS_CMD, + ZQCL_CMD, + RSTL_CMD, + MRR_CMD = 8, + DPDE_CMD, + + /* PCTL_POWCTL */ + POWER_UP_START = BIT(0), + + /* PCTL_POWSTAT */ + POWER_UP_DONE = BIT(0), + + /* PCTL_SCTL */ + INIT_STATE = 0, + CFG_STATE, + GO_STATE, + SLEEP_STATE, + WAKEUP_STATE, + + /* PCTL_STAT */ + LP_TRIG_SHIFT = 4, + LP_TRIG_MASK = 7, + PCTL_STAT_MSK = 7, + INIT_MEM = 0, + CONFIG, + CONFIG_REQ, + ACCESS, + ACCESS_REQ, + LOW_POWER, + LOW_POWER_ENTRY_REQ, + LOW_POWER_EXIT_REQ, + + /* PCTL_MCFG */ + DDR2_DDR3_BL_8 = BIT(0), + DDR3_EN = BIT(5), + TFAW_TRRD_MULT4 = (0 << 18), + TFAW_TRRD_MULT5 = (1 << 18), + TFAW_TRRD_MULT6 = (2 << 18), +}; + +#define DDR3_MR0_WR(n) \ + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) +#define DDR3_MR0_CL(n) \ + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) +#define DDR3_MR0_BL8 \ + (0 << 0) +#define DDR3_MR0_DLL_RESET \ + (1 << 8) +#define DDR3_MR1_RTT120OHM \ + ((0 << 9) | (1 << 6) | (0 << 2)) +#define DDR3_MR2_TWL(n) \ + (((n - 5) & 0x7) << 3) + + +#ifdef CONFIG_TPL_BUILD + +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable) +{ + if (enable) + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); + else + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); +} + +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode) +{ + if (ddr3_mode) + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); + else + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); +} + +static void ddrphy_config(struct rk3368_ddrphy *phy, + u32 tcl, u32 tal, u32 tcwl) +{ + int i; + + /* Set to DDR3 mode */ + clrsetbits_le32(&phy->reg[1], 0x3, 0x0); + + /* DDRPHY_REGB: CL, AL */ + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal); + /* DDRPHY_REGC: CWL */ + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl); + + /* Update drive-strength */ + writel(0xcc, &phy->reg[0x11]); + writel(0xaa, &phy->reg[0x16]); + /* + * Update NRCOMP/PRCOMP for all 4 channels (for details of all + * affected registers refer to the documentation of DDRPHY_REG20 + * and DDRPHY_REG21 in the RK3368 TRM. + */ + for (i = 0; i < 4; ++i) { + writel(0xcc, &phy->reg[0x20 + i * 0x10]); + writel(0x44, &phy->reg[0x21 + i * 0x10]); + } + + /* Enable write-leveling calibration bypass */ + setbits_le32(&phy->reg[2], BIT(3)); +} + +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) + writel(*src++, dest++); +} + +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd) +{ + u32 mcmd = START_CMD | cmd | rank; + + debug("%s: writing %x to MCMD\n", __func__, mcmd); + writel(mcmd, &pctl->mcmd); + while (readl(&pctl->mcmd) & START_CMD) + /* spin */; +} + +static void send_mrs(struct rk3368_ddr_pctl *pctl, + u32 rank, u32 mr_num, u32 mr_data) +{ + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4); + + debug("%s: writing %x to MCMD\n", __func__, mcmd); + writel(mcmd, &pctl->mcmd); + while (readl(&pctl->mcmd) & START_CMD) + /* spin */; +} + +static int memory_init(struct rk3368_ddr_pctl *pctl, + struct rk3368_sdram_params *params) +{ + u32 mr[4]; + const ulong timeout_ms = 500; + ulong tmp; + + /* + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register + * of PCTL. + */ + writel(POWER_UP_START, &pctl->powctl); + + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + pr_err("%s: POWER_UP_START did not complete in %ld ms\n", + __func__, timeout_ms); + return -ETIME; + } + } while (!(readl(&pctl->powstat) & POWER_UP_DONE)); + + /* Configure MR0 through MR3 */ + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) | + DDR3_MR0_CL(params->pctl_timing.tcl) | + DDR3_MR0_DLL_RESET; + mr[1] = DDR3_MR1_RTT120OHM; + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl); + mr[3] = 0; + + /* + * Also see RK3368 Technical Reference Manual: + * "16.6.2 Initialization (DDR3 Initialization Sequence)" + */ + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD); + udelay(1); + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]); + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]); + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD); + + return 0; +} + +static void move_to_config_state(struct rk3368_ddr_pctl *pctl) +{ + /* + * Also see RK3368 Technical Reference Manual: + * "16.6.1 State transition of PCTL (Moving to Config State)" + */ + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + /* spin */; + + /* fall-through */ + case ACCESS: + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + /* spin */; + break; + + case CONFIG: + return; + + default: + break; + } +} + +static void move_to_access_state(struct rk3368_ddr_pctl *pctl) +{ + /* + * Also see RK3368 Technical Reference Manual: + * "16.6.1 State transition of PCTL (Moving to Access State)" + */ + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + /* spin */; + + /* fall-through */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + /* spin */; + + /* fall-through */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + /* spin */; + break; + + case ACCESS: + return; + + default: + break; + } +} + +static void ddrctl_reset(struct rk3368_cru *cru) +{ + const u32 ctl_reset = BIT(3) | BIT(2); + const u32 phy_reset = BIT(1) | BIT(0); + + /* + * The PHY reset should be released before the PCTL reset. + * + * Note that the following sequence (including the number of + * us to delay between releasing the PHY and PCTL reset) has + * been adapted per feedback received from Rockchips, so do + * not try to optimise. + */ + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset); + udelay(1); + rk_clrreg(&cru->softrst_con[10], phy_reset); + udelay(5); + rk_clrreg(&cru->softrst_con[10], ctl_reset); +} + +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy) +{ + /* + * The analog part of the PHY should be release at least 1000 + * DRAM cycles before the digital part of the PHY (waiting for + * 5us will ensure this for a DRAM clock as low as 200MHz). + */ + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2)); + udelay(1); + setbits_le32(&ddrphy->reg[0], BIT(2)); + udelay(5); + setbits_le32(&ddrphy->reg[0], BIT(3)); +} + +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq) +{ + u32 dqs_dll_delay; + + setbits_le32(&ddrphy->reg[0x13], BIT(4)); + clrbits_le32(&ddrphy->reg[0x14], BIT(3)); + + setbits_le32(&ddrphy->reg[0x26], BIT(4)); + clrbits_le32(&ddrphy->reg[0x27], BIT(3)); + + setbits_le32(&ddrphy->reg[0x36], BIT(4)); + clrbits_le32(&ddrphy->reg[0x37], BIT(3)); + + setbits_le32(&ddrphy->reg[0x46], BIT(4)); + clrbits_le32(&ddrphy->reg[0x47], BIT(3)); + + setbits_le32(&ddrphy->reg[0x56], BIT(4)); + clrbits_le32(&ddrphy->reg[0x57], BIT(3)); + + if (freq <= 400000000) + setbits_le32(&ddrphy->reg[0xa4], 0x1f); + else + clrbits_le32(&ddrphy->reg[0xa4], 0x1f); + + if (freq < 681000000) + dqs_dll_delay = 3; /* 67.5 degree delay */ + else + dqs_dll_delay = 2; /* 45 degree delay */ + + writel(dqs_dll_delay, &ddrphy->reg[0x28]); + writel(dqs_dll_delay, &ddrphy->reg[0x38]); + writel(dqs_dll_delay, &ddrphy->reg[0x48]); + writel(dqs_dll_delay, &ddrphy->reg[0x58]); +} + +static int dfi_cfg(struct rk3368_ddr_pctl *pctl) +{ + const ulong timeout_ms = 200; + ulong tmp; + + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); + + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(1, &pctl->dfitphyupdtype0); + + writel(0x1f, &pctl->dfitphyrdlat); + writel(0, &pctl->dfitphywrdata); + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */ + + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START); + + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + pr_err("%s: DFI init did not complete within %ld ms\n", + __func__, timeout_ms); + return -ETIME; + } + } while ((readl(&pctl->dfiststat0) & 1) == 0); + + return 0; +} + +static inline u32 ps_to_tCK(const u32 ps, const ulong freq) +{ + const ulong MHz = 1000000; + return DIV_ROUND_UP(ps * freq, 1000000 * MHz); +} + +static inline u32 ns_to_tCK(const u32 ns, const ulong freq) +{ + return ps_to_tCK(ns * 1000, freq); +} + +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq) +{ + const ulong MHz = 1000000; + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq); +} + +static int pctl_calc_timings(struct rk3368_sdram_params *params, + ulong freq) +{ + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing; + const ulong MHz = 1000000; + u32 tccd; + u32 tfaw_as_ps; + + if (params->ddr_speed_bin != DDR3_1600K) { + pr_err("%s: unimplemented DDR3 speed bin %d\n", + __func__, params->ddr_speed_bin); + return -1; + } + + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */ + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz); + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz); + + pctl_timing->tinit = 200; /* 200 usec */ + pctl_timing->trsth = 500; /* 500 usec */ + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */ + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq); + + if (freq <= (400 * MHz)) { + pctl_timing->tcl = 6; + pctl_timing->tcwl = 10; + } else if (freq <= (533 * MHz)) { + pctl_timing->tcl = 8; + pctl_timing->tcwl = 6; + } else if (freq <= (666 * MHz)) { + pctl_timing->tcl = 10; + pctl_timing->tcwl = 7; + } else { + pctl_timing->tcl = 11; + pctl_timing->tcwl = 8; + } + + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */ + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */ + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq)); + /* + * JESD-79: + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL + */ + tccd = 4; + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; + pctl_timing->tal = 0; + pctl_timing->tras = ps_to_tCK(35000, freq); + pctl_timing->trc = ps_to_tCK(48750, freq); + pctl_timing->trcd = ps_to_tCK(13750, freq); + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq)); + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq)); + pctl_timing->twr = ps_to_tCK(15000, freq); + /* The DDR3 mode-register does only support even values for tWR > 8. */ + if (pctl_timing->twr > 8) + pctl_timing->twr = (pctl_timing->twr + 1) & ~1; + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq)); + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */ + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq)); + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq)); + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq)); + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */ + pctl_timing->tdqs = 1; /* fixed for DDR3 */ + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq)); + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq)); + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq)); + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq)); + pctl_timing->trstl = ns_to_tCK(100, freq); + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */ + pctl_timing->tmrr = 0; + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */ + + + /* + * The controller can represent tFAW as 4x, 5x or 6x tRRD only. + * We want to use the smallest multiplier that satisfies the tFAW + * requirements of the given speed-bin. If necessary, we stretch out + * tRRD to allow us to operate on a 6x multiplier for tFAW. + */ + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */ + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) { + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */ + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq); + params->tfaw_mult = TFAW_TRRD_MULT6; + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) { + params->tfaw_mult = TFAW_TRRD_MULT6; + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) { + params->tfaw_mult = TFAW_TRRD_MULT5; + } else { + params->tfaw_mult = TFAW_TRRD_MULT4; + } + + return 0; +} + +static void pctl_cfg(struct rk3368_ddr_pctl *pctl, + struct rk3368_sdram_params *params, + struct rk3368_grf *grf) +{ + /* Configure PCTL timing registers */ + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */ + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u, + sizeof(params->pctl_timing)); + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3); + + /* Set up ODT write selector and ODT write length */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg); + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + + /* Set up the CL/CWL-dependent timings of DFI */ + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat); + + /* DDR3 */ + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg); + writel(0x001c0004, &grf->ddrc0_con0); + + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); +} + +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl, + struct rk3368_ddrphy *ddrphy) +{ + const u32 trefi = readl(&pctl->trefi); + const ulong timeout_ms = 500; + ulong tmp; + + /* disable auto-refresh */ + writel(0 | BIT(31), &pctl->trefi); + + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21); + + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + pr_err("%s: did not complete within %ld ms\n", + __func__, timeout_ms); + return -ETIME; + } + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf); + + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD); + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20); + /* resume auto-refresh */ + writel(trefi | BIT(31), &pctl->trefi); + + return 0; +} + +static int sdram_col_row_detect(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3368_sdram_params *params = dev_get_plat(dev); + struct rk3368_ddr_pctl *pctl = priv->pctl; + struct rk3368_msch *msch = priv->msch; + const u32 test_pattern = 0x5aa5f00f; + int row, col; + uintptr_t addr; + + move_to_config_state(pctl); + writel(6, &msch->ddrconf); + move_to_access_state(pctl); + + /* Detect col */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + params->chan.bw - 1)); + writel(test_pattern, addr); + if ((readl(addr) == test_pattern) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + + if (col == 8) { + pr_err("%s: col detect error\n", __func__); + return -EINVAL; + } + + move_to_config_state(pctl); + writel(15, &msch->ddrconf); + move_to_access_state(pctl); + + /* Detect row*/ + for (row = 16; row >= 12; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(test_pattern, addr); + if ((readl(addr) == test_pattern) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + + if (row == 11) { + pr_err("%s: row detect error\n", __func__); + return -EINVAL; + } + + /* Record results */ + debug("%s: col %d, row %d\n", __func__, col, row); + params->chan.col = col; + params->chan.cs0_row = row; + params->chan.cs1_row = row; + params->chan.row_3_4 = 0; + + return 0; +} + +static int msch_niu_config(struct rk3368_msch *msch, + struct rk3368_sdram_params *params) +{ + int i; + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1); + const u8 rows = params->chan.cs0_row; + + /* + * The DDR address-translation table always assumes a 32bit + * bus and the comparison below takes care of adjusting for + * a 16bit bus (i.e. one column-address is consumed). + */ + const struct { + u8 rows; + u8 columns; + u8 type; + } ddrconf_table[] = { + /* + * C-B-R-D patterns are first. For these we require an + * exact match for the columns and rows (as there's + * one entry per possible configuration). + */ + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD }, + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD }, + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD }, + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD }, + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD }, + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD }, + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD }, + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD }, + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD }, + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD }, + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD }, + /* + * 11 through 13 are C-R-B-D patterns. These are + * matched for an exact number of columns and to + * ensure that the hardware uses at least as many rows + * as the pattern requires (i.e. we make sure that + * there's no gaps up until we hit the device/chip-select; + * however, these patterns can accept up to 16 rows, + * as the row-address continues right after the CS + * switching) + */ + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD }, + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD }, + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD }, + /* + * 14 and 15 are catch-all variants using a C-B-D-R + * scheme (i.e. alternating the chip-select every time + * C-B overflows) and stuffing the remaining C-bits + * into the top. Matching needs to make sure that the + * number of columns is either an exact match (i.e. we + * can use less the the maximum number of rows) -or- + * that the columns exceed what is given in this table + * and the rows are an exact match (in which case the + * remaining C-bits will be stuffed onto the top after + * the device/chip-select switches). + */ + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR }, + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR }, + }; + + /* + * For C-B-R-D, we need an exact match (i.e. both for the number of + * columns and rows), while for C-B-D-R, only the the number of + * columns needs to match. + */ + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) { + bool match = false; + + /* If this entry if for a different matcher, then skip it */ + if (ddrconf_table[i].type != params->memory_schedule) + continue; + + /* + * Match according to the rules (exact/inexact/at-least) + * documented in the ddrconf_table above. + */ + switch (params->memory_schedule) { + case DMC_MSCH_CBRD: + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows == rows); + break; + + case DMC_MSCH_CRBD: + match = (ddrconf_table[i].columns == cols) && + (ddrconf_table[i].rows <= rows); + break; + + case DMC_MSCH_CBDR: + match = (ddrconf_table[i].columns == cols) || + ((ddrconf_table[i].columns <= cols) && + (ddrconf_table[i].rows == rows)); + break; + + default: + break; + } + + if (match) { + debug("%s: setting ddrconf 0x%x\n", __func__, i); + writel(i, &msch->ddrconf); + return 0; + } + } + + pr_err("%s: ddrconf (NIU config) not found\n", __func__); + return -EINVAL; +} + +static void dram_all_config(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3368_pmu_grf *pmugrf = priv->pmugrf; + struct rk3368_sdram_params *params = dev_get_plat(dev); + const struct rk3288_sdram_channel *info = ¶ms->chan; + u32 sys_reg = 0; + const int chan = 0; + + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + writel(sys_reg, &pmugrf->os_reg[2]); +} + +static int setup_sdram(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3368_sdram_params *params = dev_get_plat(dev); + + struct rk3368_ddr_pctl *pctl = priv->pctl; + struct rk3368_ddrphy *ddrphy = priv->phy; + struct rk3368_cru *cru = priv->cru; + struct rk3368_grf *grf = priv->grf; + struct rk3368_msch *msch = priv->msch; + + int ret; + + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */ + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); + if (ret < 0) { + debug("%s: could not set DDR clock: %d\n", __func__, ret); + return ret; + } + + /* Update the read-latency for the RK3368 */ + writel(0x32, &msch->readlatency); + + /* Initialise the DDR PCTL and DDR PHY */ + ddrctl_reset(cru); + ddrphy_reset(ddrphy); + ddrphy_config_delays(ddrphy, params->ddr_freq); + dfi_cfg(pctl); + /* Configure relative system information of grf_ddrc0_con0 register */ + ddr_set_ddr3_mode(grf, true); + ddr_set_noc_spr_err_stall(grf, true); + /* Calculate timings */ + pctl_calc_timings(params, params->ddr_freq); + /* Initialise the device timings in protocol controller */ + pctl_cfg(pctl, params, grf); + /* Configure AL, CL ... information of PHY registers */ + ddrphy_config(ddrphy, + params->pctl_timing.tcl, + params->pctl_timing.tal, + params->pctl_timing.tcwl); + + /* Initialize DRAM and configure with mode-register values */ + ret = memory_init(pctl, params); + if (ret) + goto error; + + move_to_config_state(pctl); + /* Perform data-training */ + ddrphy_data_training(pctl, ddrphy); + move_to_access_state(pctl); + + /* TODO(prt): could detect rank in training... */ +#ifdef CONFIG_TARGET_EVB_PX5 + params->chan.rank = 1; +#else + params->chan.rank = 2; +#endif + /* TODO(prt): bus width is not auto-detected (yet)... */ + params->chan.bw = 2; /* 32bit wide bus */ + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */ + + /* DDR3 is always 8 bank */ + params->chan.bk = 3; + /* Detect col and row number */ + ret = sdram_col_row_detect(dev); + if (ret) + goto error; + + /* Configure NIU DDR configuration */ + ret = msch_niu_config(msch, params); + if (ret) + goto error; + + /* set up OS_REG to communicate w/ next stage and OS */ + dram_all_config(dev); + + return 0; + +error: + printf("DRAM init failed!\n"); + hang(); +} +#endif + +static int rk3368_dmc_of_to_plat(struct udevice *dev) +{ + int ret = 0; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3368_sdram_params *plat = dev_get_plat(dev); + + ret = regmap_init_mem(dev_ofnode(dev), &plat->map); + if (ret) + return ret; +#endif + + return ret; +} + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_plat(struct udevice *dev) +{ + struct rk3368_sdram_params *plat = dev_get_plat(dev); + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat; + + plat->ddr_freq = of_plat->rockchip_ddr_frequency; + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin; + plat->memory_schedule = of_plat->rockchip_memory_schedule; + + return 0; +} +#endif + +static int rk3368_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD + struct rk3368_sdram_params *plat = dev_get_plat(dev); + struct rk3368_ddr_pctl *pctl; + struct rk3368_ddrphy *ddrphy; + struct rk3368_cru *cru; + struct rk3368_grf *grf; + struct rk3368_msch *msch; + int ret; + struct udevice *dev_clk; +#endif + struct dram_info *priv = dev_get_priv(dev); + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_plat(dev); + if (ret) + return ret; +#endif + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); + +#ifdef CONFIG_TPL_BUILD + pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0]; + ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2]; + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + priv->pctl = pctl; + priv->phy = ddrphy; + priv->msch = msch; + priv->grf = grf; + + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + cru = rockchip_get_cru(); + priv->cru = cru; + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); + + ret = setup_sdram(dev); + if (ret) + return ret; +#endif + + priv->info.base = 0; + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); + + /* + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is + * inaccessible for some IP controller. + */ + priv->info.size = min(priv->info.size, (size_t)0xfe000000); + + return 0; +} + +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + return 0; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible = "rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3368_dmc) = { + .name = "rockchip_rk3368_dmc", + .id = UCLASS_RAM, + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto = sizeof(struct dram_info), + .of_to_plat = rk3368_dmc_of_to_plat, + .probe = rk3368_dmc_probe, + .priv_auto = sizeof(struct dram_info), + .plat_auto = sizeof(struct rk3368_sdram_params), +}; diff --git a/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr3-detect-333.inc b/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr3-detect-333.inc new file mode 100644 index 000000000..76cd8dc1a --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr3-detect-333.inc @@ -0,0 +1,72 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0, + }, + { + {0x290b0609}, + {0x08020401}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000222}, + 0x000000ff + } + }, + { + .ddr_freq = 333, + .dramtype = DDR3, + .num_channels = 1, + .stride = 0, + .odt = 0, + }, + { + { + {0x00000000, 0x43041001}, /* MSTR */ + {0x00000064, 0x0028003b}, /* RFSHTMG */ + {0x000000d0, 0x00020053}, /* INIT0 */ + {0x000000d4, 0x00020000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x03200000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00090000}, /* INIT5 */ + {0x000000f4, 0x000f012f}, /* RANKCTL */ + {0x00000100, 0x07090b06}, /* DRAMTMG0 */ + {0x00000104, 0x00050209}, /* DRAMTMG1 */ + {0x00000108, 0x03030407}, /* DRAMTMG2 */ + {0x0000010c, 0x00202006}, /* DRAMTMG3 */ + {0x00000110, 0x03020204}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x00000903}, /* DRAMTMG8 */ + {0x00000180, 0x00800020}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07010001}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000000a}, /* PHYREG01 */ + {0x00000028, 0x00000006}, /* PHYREG0A */ + {0x0000002c, 0x00000000}, /* PHYREG0B */ + {0x00000030, 0x00000005}, /* PHYREG0C */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr4-detect-333.inc b/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr4-detect-333.inc new file mode 100644 index 000000000..f804d2839 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr4-detect-333.inc @@ -0,0 +1,75 @@ +{ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x2, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x11, + .cs1_row = 0x0, + .cs0_high16bit_row = 0x11, + .cs1_high16bit_row = 0x0, + .ddrconfig = 0, + }, + { + {0x4d110a08}, + {0x06020501}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000022a}, + 0x000000ff + } + }, + { + .ddr_freq = 333, + .dramtype = DDR4, + .num_channels = 1, + .stride = 0, + .odt = 0, + }, + { + { + {0x00000000, 0x43049010}, /* MSTR */ + {0x00000064, 0x0028003b}, /* RFSHTMG */ + {0x000000d0, 0x00020053}, /* INIT0 */ + {0x000000d4, 0x00220000}, /* INIT1 */ + {0x000000d8, 0x00000100}, /* INIT2 */ + {0x000000dc, 0x00040000}, /* INIT3 */ + {0x000000e0, 0x00000000}, /* INIT4 */ + {0x000000e4, 0x00110000}, /* INIT5 */ + {0x000000e8, 0x00000420}, /* INIT6 */ + {0x000000ec, 0x00000400}, /* INIT7 */ + {0x000000f4, 0x000f012f}, /* RANKCTL */ + {0x00000100, 0x09060b06}, /* DRAMTMG0 */ + {0x00000104, 0x00020209}, /* DRAMTMG1 */ + {0x00000108, 0x0505040a}, /* DRAMTMG2 */ + {0x0000010c, 0x0040400c}, /* DRAMTMG3 */ + {0x00000110, 0x05030206}, /* DRAMTMG4 */ + {0x00000114, 0x03030202}, /* DRAMTMG5 */ + {0x00000120, 0x03030b03}, /* DRAMTMG8 */ + {0x00000124, 0x00020208}, /* DRAMTMG9 */ + {0x00000180, 0x01000040}, /* ZQCTL0 */ + {0x00000184, 0x00000000}, /* ZQCTL1 */ + {0x00000190, 0x07030003}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x06000604}, /* ODTCFG */ + {0x00000244, 0x00000201}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000000c}, /* PHYREG01 */ + {0x00000028, 0x0000000a}, /* PHYREG0A */ + {0x0000002c, 0x00000000}, /* PHYREG0B */ + {0x00000030, 0x00000009}, /* PHYREG0C */ + {0xffffffff, 0xffffffff} + } + } +}, \ No newline at end of file diff --git a/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr_skew.inc b/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr_skew.inc new file mode 100644 index 000000000..f24343dda --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram-px30-ddr_skew.inc @@ -0,0 +1,121 @@ + { + 0x77, + 0x88, + 0x79, + 0x79, + 0x87, + 0x97, + 0x87, + 0x78, + 0x77, + 0x78, + 0x87, + 0x88, + 0x87, + 0x87, + 0x77 + }, + { + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x69, + 0x9, + }, + { + 0x77, + 0x78, + 0x77, + 0x78, + 0x77, + 0x78, + 0x77, + 0x78, + 0x77, + 0x79, + 0x9, + }, + { + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x69, + 0x9, + }, + { + 0x77, + 0x78, + 0x77, + 0x77, + 0x77, + 0x77, + 0x77, + 0x77, + 0x77, + 0x79, + 0x9, + }, + { + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x69, + 0x9, + }, + { + 0x77, + 0x78, + 0x77, + 0x78, + 0x77, + 0x78, + 0x77, + 0x78, + 0x77, + 0x79, + 0x9, + }, + { + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x78, + 0x69, + 0x9, + }, + { + 0x77, + 0x78, + 0x77, + 0x77, + 0x77, + 0x77, + 0x77, + 0x77, + 0x77, + 0x79, + 0x9, + } diff --git a/roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr2-detect-333.inc b/roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr2-detect-333.inc new file mode 100644 index 000000000..948ade483 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr2-detect-333.inc @@ -0,0 +1,73 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .cs0_high16bit_row = 0xF, + .cs1_high16bit_row = 0xF, + .ddrconfig = 0, + }, + { + {0x2b0c070a}, + {0x08020303}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x00000219}, + 0x000000ff + } + }, + { + .ddr_freq = 333, + .dramtype = LPDDR2, + .num_channels = 1, + .stride = 0, + .odt = 0, + }, + { + { + {0x00000000, 0x41041004}, /* MSTR */ + {0x00000064, 0x00140023}, /* RFSHTMG */ + {0x000000d0, 0x00220002}, /* INIT0 */ + {0x000000d4, 0x00010000}, /* INIT1 */ + {0x000000d8, 0x00000703}, /* INIT2 */ + {0x000000dc, 0x00630005}, /* INIT3 */ + {0x000000e0, 0x00010000}, /* INIT4 */ + {0x000000e4, 0x00070003}, /* INIT5 */ + {0x000000f4, 0x000f012f}, /* RANKCTL */ + {0x00000100, 0x07090b07}, /* DRAMTMG0 */ + {0x00000104, 0x0002010b}, /* DRAMTMG1 */ + {0x00000108, 0x02040506}, /* DRAMTMG2 */ + {0x0000010c, 0x00303000}, /* DRAMTMG3 */ + {0x00000110, 0x04010204}, /* DRAMTMG4 */ + {0x00000114, 0x01010303}, /* DRAMTMG5 */ + {0x00000118, 0x02020003}, /* DRAMTMG6 */ + {0x00000120, 0x00000303}, /* DRAMTMG8 */ + {0x00000138, 0x00000025}, /* DRAMTMG14 */ + {0x00000180, 0x003c000f}, /* ZQCTL0 */ + {0x00000184, 0x00900000}, /* ZQCTL1 */ + {0x00000190, 0x07020001}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x07030718}, /* ODTCFG */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x00000009}, /* PHYREG01 */ + {0x00000028, 0x00000007}, /* PHYREG0A */ + {0x0000002c, 0x00000000}, /* PHYREG0B */ + {0x00000030, 0x00000004}, /* PHYREG0C */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc b/roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc new file mode 100644 index 000000000..f694a0e5b --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram-px30-lpddr3-detect-333.inc @@ -0,0 +1,74 @@ +{ + { + { + .rank = 0x1, + .col = 0xC, + .bk = 0x3, + .bw = 0x1, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x10, + .cs1_row = 0x10, + .cs0_high16bit_row = 0x10, + .cs1_high16bit_row = 0x10, + .ddrconfig = 0, + }, + { + {0x290a060a}, + {0x08020303}, + {0x00000002}, + {0x00001111}, + {0x0000000c}, + {0x0000021a}, + 0x000000ff + } + }, + { + .ddr_freq = 333, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 0, + .odt = 0, + }, + { + { + {0x00000000, 0x43041008}, /* MSTR */ + {0x00000064, 0x00140023}, /* RFSHTMG */ + {0x000000d0, 0x00220002}, /* INIT0 */ + {0x000000d4, 0x00010000}, /* INIT1 */ + {0x000000d8, 0x00000703}, /* INIT2 */ + {0x000000dc, 0x00830004}, /* INIT3 */ + {0x000000e0, 0x00010000}, /* INIT4 */ + {0x000000e4, 0x00070003}, /* INIT5 */ + {0x000000f4, 0x000f012f}, /* RANKCTL */ + {0x00000100, 0x06090b07}, /* DRAMTMG0 */ + {0x00000104, 0x0002020b}, /* DRAMTMG1 */ + {0x00000108, 0x02030506}, /* DRAMTMG2 */ + {0x0000010c, 0x00505000}, /* DRAMTMG3 */ + {0x00000110, 0x03020204}, /* DRAMTMG4 */ + {0x00000114, 0x01010303}, /* DRAMTMG5 */ + {0x00000118, 0x02020003}, /* DRAMTMG6 */ + {0x00000120, 0x00000303}, /* DRAMTMG8 */ + {0x00000138, 0x00000025}, /* DRAMTMG14 */ + {0x00000180, 0x003c000f}, /* ZQCTL0 */ + {0x00000184, 0x00900000}, /* ZQCTL1 */ + {0x00000190, 0x07020000}, /* DFITMG0 */ + {0x00000198, 0x07000101}, /* DFILPCFG0 */ + {0x000001a0, 0xc0400003}, /* DFIUPD0 */ + {0x00000240, 0x0900090c}, /* ODTCFG */ + {0x00000244, 0x00000101}, /* ODTMAP */ + {0x00000250, 0x00001f00}, /* SCHED */ + {0x00000490, 0x00000001}, /* PCTRL_0 */ + {0xffffffff, 0xffffffff} + } + }, + { + { + {0x00000004, 0x0000000b}, /* PHYREG01 */ + {0x00000028, 0x00000006}, /* PHYREG0A */ + {0x0000002c, 0x00000000}, /* PHYREG0B */ + {0x00000030, 0x00000003}, /* PHYREG0C */ + {0xffffffff, 0xffffffff} + } + } +}, diff --git a/roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc b/roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc new file mode 100644 index 000000000..209ef5722 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc @@ -0,0 +1,1586 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + * (C) Copyright 2019 Amarula Solutions + */ + +{ + { + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .cs0_high16bit_row = 0xF, + .cs1_high16bit_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = { + 0x8010100d, + }, + .ddrtimingb0 = { + 0x08020b04, + }, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = { + 0x00002562, + }, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + }, + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .cs0_high16bit_row = 0xF, + .cs1_high16bit_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = { + 0x8010100d, + }, + .ddrtimingb0 = { + 0x08020b04, + }, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = { + 0x00002562, + }, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + } + }, + { + .ddr_freq = 400 * MHz, + .dramtype = LPDDR4, + .num_channels = 2, + .stride = 13, + .odt = 1, + }, + { + { + 0x00000b00, /* DENALI_CTL_00_DATA */ + 0x00000000, /* DENALI_CTL_01_DATA */ + 0x00000000, /* DENALI_CTL_02_DATA */ + 0x00000000, /* DENALI_CTL_03_DATA */ + 0x00000000, /* DENALI_CTL_04_DATA */ + 0x00013880, /* DENALI_CTL_05_DATA */ + 0x000c3500, /* DENALI_CTL_06_DATA */ + 0x00000005, /* DENALI_CTL_07_DATA */ + 0x00000320, /* DENALI_CTL_08_DATA */ + 0x00027100, /* DENALI_CTL_09_DATA */ + 0x00186a00, /* DENALI_CTL_10_DATA */ + 0x00000005, /* DENALI_CTL_11_DATA */ + 0x00000640, /* DENALI_CTL_12_DATA */ + 0x00002710, /* DENALI_CTL_13_DATA */ + 0x000186a0, /* DENALI_CTL_14_DATA */ + 0x00000005, /* DENALI_CTL_15_DATA */ + 0x01000064, /* DENALI_CTL_16_DATA */ + 0x00000000, /* DENALI_CTL_17_DATA */ + 0x02020101, /* DENALI_CTL_18_DATA */ + 0x00000102, /* DENALI_CTL_19_DATA */ + 0x00000050, /* DENALI_CTL_20_DATA */ + 0x000000c8, /* DENALI_CTL_21_DATA */ + 0x00000000, /* DENALI_CTL_22_DATA */ + 0x06140000, /* DENALI_CTL_23_DATA */ + 0x00081c00, /* DENALI_CTL_24_DATA */ + 0x0400040c, /* DENALI_CTL_25_DATA */ + 0x19042008, /* DENALI_CTL_26_DATA */ + 0x10080a11, /* DENALI_CTL_27_DATA */ + 0x22310800, /* DENALI_CTL_28_DATA */ + 0x00200f0a, /* DENALI_CTL_29_DATA */ + 0x0a030704, /* DENALI_CTL_30_DATA */ + 0x08000204, /* DENALI_CTL_31_DATA */ + 0x00000a0a, /* DENALI_CTL_32_DATA */ + 0x04006db0, /* DENALI_CTL_33_DATA */ + 0x0a0a0804, /* DENALI_CTL_34_DATA */ + 0x0600db60, /* DENALI_CTL_35_DATA */ + 0x0a0a0806, /* DENALI_CTL_36_DATA */ + 0x04000db6, /* DENALI_CTL_37_DATA */ + 0x02030404, /* DENALI_CTL_38_DATA */ + 0x0f0a0800, /* DENALI_CTL_39_DATA */ + 0x08040411, /* DENALI_CTL_40_DATA */ + 0x1400640a, /* DENALI_CTL_41_DATA */ + 0x02010a0a, /* DENALI_CTL_42_DATA */ + 0x00010001, /* DENALI_CTL_43_DATA */ + 0x04082012, /* DENALI_CTL_44_DATA */ + 0x00041109, /* DENALI_CTL_45_DATA */ + 0x00000000, /* DENALI_CTL_46_DATA */ + 0x03010000, /* DENALI_CTL_47_DATA */ + 0x06100034, /* DENALI_CTL_48_DATA */ + 0x0c280068, /* DENALI_CTL_49_DATA */ + 0x00bb0007, /* DENALI_CTL_50_DATA */ + 0x00000000, /* DENALI_CTL_51_DATA */ + 0x00060003, /* DENALI_CTL_52_DATA */ + 0x000a0003, /* DENALI_CTL_53_DATA */ + 0x000a0014, /* DENALI_CTL_54_DATA */ + 0x01000000, /* DENALI_CTL_55_DATA */ + 0x030a0000, /* DENALI_CTL_56_DATA */ + 0x0c000002, /* DENALI_CTL_57_DATA */ + 0x00000103, /* DENALI_CTL_58_DATA */ + 0x0003030a, /* DENALI_CTL_59_DATA */ + 0x00060037, /* DENALI_CTL_60_DATA */ + 0x0003006e, /* DENALI_CTL_61_DATA */ + 0x05050007, /* DENALI_CTL_62_DATA */ + 0x03020605, /* DENALI_CTL_63_DATA */ + 0x06050301, /* DENALI_CTL_64_DATA */ + 0x06020c05, /* DENALI_CTL_65_DATA */ + 0x05050302, /* DENALI_CTL_66_DATA */ + 0x03020305, /* DENALI_CTL_67_DATA */ + 0x00000301, /* DENALI_CTL_68_DATA */ + 0x00000301, /* DENALI_CTL_69_DATA */ + 0x00000001, /* DENALI_CTL_70_DATA */ + 0x00000000, /* DENALI_CTL_71_DATA */ + 0x00000000, /* DENALI_CTL_72_DATA */ + 0x01000000, /* DENALI_CTL_73_DATA */ + 0x80104002, /* DENALI_CTL_74_DATA */ + 0x00040003, /* DENALI_CTL_75_DATA */ + 0x00040005, /* DENALI_CTL_76_DATA */ + 0x00030000, /* DENALI_CTL_77_DATA */ + 0x00050004, /* DENALI_CTL_78_DATA */ + 0x00000004, /* DENALI_CTL_79_DATA */ + 0x00040003, /* DENALI_CTL_80_DATA */ + 0x00040005, /* DENALI_CTL_81_DATA */ + 0x18400000, /* DENALI_CTL_82_DATA */ + 0x00000c20, /* DENALI_CTL_83_DATA */ + 0x185030a0, /* DENALI_CTL_84_DATA */ + 0x02ec0000, /* DENALI_CTL_85_DATA */ + 0x00000176, /* DENALI_CTL_86_DATA */ + 0x00000000, /* DENALI_CTL_87_DATA */ + 0x00000000, /* DENALI_CTL_88_DATA */ + 0x00000000, /* DENALI_CTL_89_DATA */ + 0x00000000, /* DENALI_CTL_90_DATA */ + 0x00000000, /* DENALI_CTL_91_DATA */ + 0x06030300, /* DENALI_CTL_92_DATA */ + 0x00030303, /* DENALI_CTL_93_DATA */ + 0x02030200, /* DENALI_CTL_94_DATA */ + 0x00040703, /* DENALI_CTL_95_DATA */ + 0x03020302, /* DENALI_CTL_96_DATA */ + 0x02000407, /* DENALI_CTL_97_DATA */ + 0x07030203, /* DENALI_CTL_98_DATA */ + 0x00030f04, /* DENALI_CTL_99_DATA */ + 0x00070004, /* DENALI_CTL_100_DATA */ + 0x00000000, /* DENALI_CTL_101_DATA */ + 0x00000000, /* DENALI_CTL_102_DATA */ + 0x00000000, /* DENALI_CTL_103_DATA */ + 0x00000000, /* DENALI_CTL_104_DATA */ + 0x00000000, /* DENALI_CTL_105_DATA */ + 0x00000000, /* DENALI_CTL_106_DATA */ + 0x00000000, /* DENALI_CTL_107_DATA */ + 0x00010000, /* DENALI_CTL_108_DATA */ + 0x20040020, /* DENALI_CTL_109_DATA */ + 0x00200400, /* DENALI_CTL_110_DATA */ + 0x01000400, /* DENALI_CTL_111_DATA */ + 0x00000b80, /* DENALI_CTL_112_DATA */ + 0x00000000, /* DENALI_CTL_113_DATA */ + 0x00000001, /* DENALI_CTL_114_DATA */ + 0x00000002, /* DENALI_CTL_115_DATA */ + 0x0000000e, /* DENALI_CTL_116_DATA */ + 0x00000000, /* DENALI_CTL_117_DATA */ + 0x00000000, /* DENALI_CTL_118_DATA */ + 0x00000000, /* DENALI_CTL_119_DATA */ + 0x00000000, /* DENALI_CTL_120_DATA */ + 0x00000000, /* DENALI_CTL_121_DATA */ + 0x00500000, /* DENALI_CTL_122_DATA */ + 0x00640028, /* DENALI_CTL_123_DATA */ + 0x00640404, /* DENALI_CTL_124_DATA */ + 0x005000a0, /* DENALI_CTL_125_DATA */ + 0x060600c8, /* DENALI_CTL_126_DATA */ + 0x000a00c8, /* DENALI_CTL_127_DATA */ + 0x000d0005, /* DENALI_CTL_128_DATA */ + 0x000d0404, /* DENALI_CTL_129_DATA */ + 0x00000000, /* DENALI_CTL_130_DATA */ + 0x00000000, /* DENALI_CTL_131_DATA */ + 0x00000000, /* DENALI_CTL_132_DATA */ + 0x001400a3, /* DENALI_CTL_133_DATA */ + 0x00e30009, /* DENALI_CTL_134_DATA */ + 0x00120024, /* DENALI_CTL_135_DATA */ + 0x00040063, /* DENALI_CTL_136_DATA */ + 0x00000000, /* DENALI_CTL_137_DATA */ + 0x00310031, /* DENALI_CTL_138_DATA */ + 0x00000031, /* DENALI_CTL_139_DATA */ + 0x004d0000, /* DENALI_CTL_140_DATA */ + 0x004d004d, /* DENALI_CTL_141_DATA */ + 0x004d0000, /* DENALI_CTL_142_DATA */ + 0x004d004d, /* DENALI_CTL_143_DATA */ + 0x00010101, /* DENALI_CTL_144_DATA */ + 0x00000000, /* DENALI_CTL_145_DATA */ + 0x00000000, /* DENALI_CTL_146_DATA */ + 0x001400a3, /* DENALI_CTL_147_DATA */ + 0x00e30009, /* DENALI_CTL_148_DATA */ + 0x00120024, /* DENALI_CTL_149_DATA */ + 0x00040063, /* DENALI_CTL_150_DATA */ + 0x00000000, /* DENALI_CTL_151_DATA */ + 0x00310031, /* DENALI_CTL_152_DATA */ + 0x00000031, /* DENALI_CTL_153_DATA */ + 0x004d0000, /* DENALI_CTL_154_DATA */ + 0x004d004d, /* DENALI_CTL_155_DATA */ + 0x004d0000, /* DENALI_CTL_156_DATA */ + 0x004d004d, /* DENALI_CTL_157_DATA */ + 0x00010101, /* DENALI_CTL_158_DATA */ + 0x00000000, /* DENALI_CTL_159_DATA */ + 0x00000000, /* DENALI_CTL_160_DATA */ + 0x00000000, /* DENALI_CTL_161_DATA */ + 0x00000001, /* DENALI_CTL_162_DATA */ + 0x00000000, /* DENALI_CTL_163_DATA */ + 0x18151100, /* DENALI_CTL_164_DATA */ + 0x0000000c, /* DENALI_CTL_165_DATA */ + 0x00000000, /* DENALI_CTL_166_DATA */ + 0x00000000, /* DENALI_CTL_167_DATA */ + 0x00000000, /* DENALI_CTL_168_DATA */ + 0x00000000, /* DENALI_CTL_169_DATA */ + 0x00000000, /* DENALI_CTL_170_DATA */ + 0x00000000, /* DENALI_CTL_171_DATA */ + 0x00000000, /* DENALI_CTL_172_DATA */ + 0x00000000, /* DENALI_CTL_173_DATA */ + 0x00000000, /* DENALI_CTL_174_DATA */ + 0x00000000, /* DENALI_CTL_175_DATA */ + 0x00000000, /* DENALI_CTL_176_DATA */ + 0x00000000, /* DENALI_CTL_177_DATA */ + 0x00000000, /* DENALI_CTL_178_DATA */ + 0x00020003, /* DENALI_CTL_179_DATA */ + 0x00400100, /* DENALI_CTL_180_DATA */ + 0x000c0190, /* DENALI_CTL_181_DATA */ + 0x01000200, /* DENALI_CTL_182_DATA */ + 0x03200040, /* DENALI_CTL_183_DATA */ + 0x00020018, /* DENALI_CTL_184_DATA */ + 0x00400100, /* DENALI_CTL_185_DATA */ + 0x00080032, /* DENALI_CTL_186_DATA */ + 0x00140000, /* DENALI_CTL_187_DATA */ + 0x00030028, /* DENALI_CTL_188_DATA */ + 0x01010100, /* DENALI_CTL_189_DATA */ + 0x02000202, /* DENALI_CTL_190_DATA */ + 0x0b000002, /* DENALI_CTL_191_DATA */ + 0x01000f0f, /* DENALI_CTL_192_DATA */ + 0x00000000, /* DENALI_CTL_193_DATA */ + 0x00000000, /* DENALI_CTL_194_DATA */ + 0x00010003, /* DENALI_CTL_195_DATA */ + 0x00000c03, /* DENALI_CTL_196_DATA */ + 0x00040101, /* DENALI_CTL_197_DATA */ + 0x04010100, /* DENALI_CTL_198_DATA */ + 0x01000000, /* DENALI_CTL_199_DATA */ + 0x02010000, /* DENALI_CTL_200_DATA */ + 0x00000001, /* DENALI_CTL_201_DATA */ + 0x00000000, /* DENALI_CTL_202_DATA */ + 0x00000000, /* DENALI_CTL_203_DATA */ + 0x00000000, /* DENALI_CTL_204_DATA */ + 0x00000000, /* DENALI_CTL_205_DATA */ + 0x00000000, /* DENALI_CTL_206_DATA */ + 0x00000000, /* DENALI_CTL_207_DATA */ + 0x00000000, /* DENALI_CTL_208_DATA */ + 0x00000000, /* DENALI_CTL_209_DATA */ + 0x00000000, /* DENALI_CTL_210_DATA */ + 0x00010000, /* DENALI_CTL_211_DATA */ + 0x00000001, /* DENALI_CTL_212_DATA */ + 0x01010001, /* DENALI_CTL_213_DATA */ + 0x05040001, /* DENALI_CTL_214_DATA */ + 0x040a0703, /* DENALI_CTL_215_DATA */ + 0x02080808, /* DENALI_CTL_216_DATA */ + 0x020e000a, /* DENALI_CTL_217_DATA */ + 0x020f010b, /* DENALI_CTL_218_DATA */ + 0x000d0008, /* DENALI_CTL_219_DATA */ + 0x00080b0a, /* DENALI_CTL_220_DATA */ + 0x03000200, /* DENALI_CTL_221_DATA */ + 0x00000100, /* DENALI_CTL_222_DATA */ + 0x00000000, /* DENALI_CTL_223_DATA */ + 0x00000000, /* DENALI_CTL_224_DATA */ + 0x0d000001, /* DENALI_CTL_225_DATA */ + 0x00000028, /* DENALI_CTL_226_DATA */ + 0x00010000, /* DENALI_CTL_227_DATA */ + 0x00000003, /* DENALI_CTL_228_DATA */ + 0x00000000, /* DENALI_CTL_229_DATA */ + 0x00000000, /* DENALI_CTL_230_DATA */ + 0x00000000, /* DENALI_CTL_231_DATA */ + 0x00000000, /* DENALI_CTL_232_DATA */ + 0x00000000, /* DENALI_CTL_233_DATA */ + 0x00000000, /* DENALI_CTL_234_DATA */ + 0x00000000, /* DENALI_CTL_235_DATA */ + 0x00000000, /* DENALI_CTL_236_DATA */ + 0x00010100, /* DENALI_CTL_237_DATA */ + 0x01000000, /* DENALI_CTL_238_DATA */ + 0x00000001, /* DENALI_CTL_239_DATA */ + 0x00000303, /* DENALI_CTL_240_DATA */ + 0x00000000, /* DENALI_CTL_241_DATA */ + 0x00000000, /* DENALI_CTL_242_DATA */ + 0x00000000, /* DENALI_CTL_243_DATA */ + 0x00000000, /* DENALI_CTL_244_DATA */ + 0x00000000, /* DENALI_CTL_245_DATA */ + 0x00000000, /* DENALI_CTL_246_DATA */ + 0x00000000, /* DENALI_CTL_247_DATA */ + 0x00000000, /* DENALI_CTL_248_DATA */ + 0x00000000, /* DENALI_CTL_249_DATA */ + 0x00000000, /* DENALI_CTL_250_DATA */ + 0x00000000, /* DENALI_CTL_251_DATA */ + 0x00000000, /* DENALI_CTL_252_DATA */ + 0x00000000, /* DENALI_CTL_253_DATA */ + 0x00000000, /* DENALI_CTL_254_DATA */ + 0x00000000, /* DENALI_CTL_255_DATA */ + 0x000556aa, /* DENALI_CTL_256_DATA */ + 0x000aaaaa, /* DENALI_CTL_257_DATA */ + 0x000aa955, /* DENALI_CTL_258_DATA */ + 0x00055555, /* DENALI_CTL_259_DATA */ + 0x000b3133, /* DENALI_CTL_260_DATA */ + 0x0004cd33, /* DENALI_CTL_261_DATA */ + 0x0004cecc, /* DENALI_CTL_262_DATA */ + 0x000b32cc, /* DENALI_CTL_263_DATA */ + 0x00010300, /* DENALI_CTL_264_DATA */ + 0x03000100, /* DENALI_CTL_265_DATA */ + 0x00000000, /* DENALI_CTL_266_DATA */ + 0x00000000, /* DENALI_CTL_267_DATA */ + 0x00000000, /* DENALI_CTL_268_DATA */ + 0x00000000, /* DENALI_CTL_269_DATA */ + 0x00000000, /* DENALI_CTL_270_DATA */ + 0x00000000, /* DENALI_CTL_271_DATA */ + 0x00000000, /* DENALI_CTL_272_DATA */ + 0x00000000, /* DENALI_CTL_273_DATA */ + 0x00ffff00, /* DENALI_CTL_274_DATA */ + 0x1a160000, /* DENALI_CTL_275_DATA */ + 0x08000012, /* DENALI_CTL_276_DATA */ + 0x00000c20, /* DENALI_CTL_277_DATA */ + 0x00000200, /* DENALI_CTL_278_DATA */ + 0x00000200, /* DENALI_CTL_279_DATA */ + 0x00000200, /* DENALI_CTL_280_DATA */ + 0x00000200, /* DENALI_CTL_281_DATA */ + 0x00000c20, /* DENALI_CTL_282_DATA */ + 0x00007940, /* DENALI_CTL_283_DATA */ + 0x18500409, /* DENALI_CTL_284_DATA */ + 0x00000200, /* DENALI_CTL_285_DATA */ + 0x00000200, /* DENALI_CTL_286_DATA */ + 0x00000200, /* DENALI_CTL_287_DATA */ + 0x00000200, /* DENALI_CTL_288_DATA */ + 0x00001850, /* DENALI_CTL_289_DATA */ + 0x0000f320, /* DENALI_CTL_290_DATA */ + 0x0176060c, /* DENALI_CTL_291_DATA */ + 0x00000200, /* DENALI_CTL_292_DATA */ + 0x00000200, /* DENALI_CTL_293_DATA */ + 0x00000200, /* DENALI_CTL_294_DATA */ + 0x00000200, /* DENALI_CTL_295_DATA */ + 0x00000176, /* DENALI_CTL_296_DATA */ + 0x00000e9c, /* DENALI_CTL_297_DATA */ + 0x02020205, /* DENALI_CTL_298_DATA */ + 0x03030202, /* DENALI_CTL_299_DATA */ + 0x00000018, /* DENALI_CTL_300_DATA */ + 0x00000000, /* DENALI_CTL_301_DATA */ + 0x00000000, /* DENALI_CTL_302_DATA */ + 0x00001403, /* DENALI_CTL_303_DATA */ + 0x00000000, /* DENALI_CTL_304_DATA */ + 0x00000000, /* DENALI_CTL_305_DATA */ + 0x00000000, /* DENALI_CTL_306_DATA */ + 0x00030000, /* DENALI_CTL_307_DATA */ + 0x000a001c, /* DENALI_CTL_308_DATA */ + 0x000e0020, /* DENALI_CTL_309_DATA */ + 0x00060018, /* DENALI_CTL_310_DATA */ + 0x00000000, /* DENALI_CTL_311_DATA */ + 0x00000000, /* DENALI_CTL_312_DATA */ + 0x02000000, /* DENALI_CTL_313_DATA */ + 0x00090305, /* DENALI_CTL_314_DATA */ + 0x00050101, /* DENALI_CTL_315_DATA */ + 0x00000000, /* DENALI_CTL_316_DATA */ + 0x00000000, /* DENALI_CTL_317_DATA */ + 0x00000000, /* DENALI_CTL_318_DATA */ + 0x00000000, /* DENALI_CTL_319_DATA */ + 0x00000000, /* DENALI_CTL_320_DATA */ + 0x00000000, /* DENALI_CTL_321_DATA */ + 0x00000000, /* DENALI_CTL_322_DATA */ + 0x00000000, /* DENALI_CTL_323_DATA */ + 0x01000001, /* DENALI_CTL_324_DATA */ + 0x01010101, /* DENALI_CTL_325_DATA */ + 0x01000101, /* DENALI_CTL_326_DATA */ + 0x01000100, /* DENALI_CTL_327_DATA */ + 0x00010001, /* DENALI_CTL_328_DATA */ + 0x00010002, /* DENALI_CTL_329_DATA */ + 0x00020100, /* DENALI_CTL_330_DATA */ + 0x00000002 /* DENALI_CTL_331_DATA */ + } + }, + { + { + 0x00000b00, /* DENALI_PI_00_DATA */ + 0x00000000, /* DENALI_PI_01_DATA */ + 0x000002ec, /* DENALI_PI_02_DATA */ + 0x00000176, /* DENALI_PI_03_DATA */ + 0x000030a0, /* DENALI_PI_04_DATA */ + 0x00001850, /* DENALI_PI_05_DATA */ + 0x00001840, /* DENALI_PI_06_DATA */ + 0x01760c20, /* DENALI_PI_07_DATA */ + 0x00000200, /* DENALI_PI_08_DATA */ + 0x00000200, /* DENALI_PI_09_DATA */ + 0x00000200, /* DENALI_PI_10_DATA */ + 0x00000200, /* DENALI_PI_11_DATA */ + 0x00001850, /* DENALI_PI_12_DATA */ + 0x00000200, /* DENALI_PI_13_DATA */ + 0x00000200, /* DENALI_PI_14_DATA */ + 0x00000200, /* DENALI_PI_15_DATA */ + 0x00000200, /* DENALI_PI_16_DATA */ + 0x00000c20, /* DENALI_PI_17_DATA */ + 0x00000200, /* DENALI_PI_18_DATA */ + 0x00000200, /* DENALI_PI_19_DATA */ + 0x00000200, /* DENALI_PI_20_DATA */ + 0x00000200, /* DENALI_PI_21_DATA */ + 0x00010000, /* DENALI_PI_22_DATA */ + 0x00000007, /* DENALI_PI_23_DATA */ + 0x01000001, /* DENALI_PI_24_DATA */ + 0x00000000, /* DENALI_PI_25_DATA */ + 0x3fffffff, /* DENALI_PI_26_DATA */ + 0x00000000, /* DENALI_PI_27_DATA */ + 0x00000000, /* DENALI_PI_28_DATA */ + 0x00000000, /* DENALI_PI_29_DATA */ + 0x00000000, /* DENALI_PI_30_DATA */ + 0x00000000, /* DENALI_PI_31_DATA */ + 0x00000000, /* DENALI_PI_32_DATA */ + 0x00000000, /* DENALI_PI_33_DATA */ + 0x00000000, /* DENALI_PI_34_DATA */ + 0x00000000, /* DENALI_PI_35_DATA */ + 0x00000000, /* DENALI_PI_36_DATA */ + 0x00000000, /* DENALI_PI_37_DATA */ + 0x00000000, /* DENALI_PI_38_DATA */ + 0x00000000, /* DENALI_PI_39_DATA */ + 0x00000000, /* DENALI_PI_40_DATA */ + 0x0f000101, /* DENALI_PI_41_DATA */ + 0x082b3223, /* DENALI_PI_42_DATA */ + 0x080c0004, /* DENALI_PI_43_DATA */ + 0x00061c00, /* DENALI_PI_44_DATA */ + 0x00000214, /* DENALI_PI_45_DATA */ + 0x00bb0007, /* DENALI_PI_46_DATA */ + 0x0c280068, /* DENALI_PI_47_DATA */ + 0x06100034, /* DENALI_PI_48_DATA */ + 0x00000500, /* DENALI_PI_49_DATA */ + 0x00000000, /* DENALI_PI_50_DATA */ + 0x00000000, /* DENALI_PI_51_DATA */ + 0x00000000, /* DENALI_PI_52_DATA */ + 0x00000000, /* DENALI_PI_53_DATA */ + 0x00000000, /* DENALI_PI_54_DATA */ + 0x00000000, /* DENALI_PI_55_DATA */ + 0x00000000, /* DENALI_PI_56_DATA */ + 0x00000000, /* DENALI_PI_57_DATA */ + 0x04040100, /* DENALI_PI_58_DATA */ + 0x0a000004, /* DENALI_PI_59_DATA */ + 0x00000128, /* DENALI_PI_60_DATA */ + 0x00000000, /* DENALI_PI_61_DATA */ + 0x0003000f, /* DENALI_PI_62_DATA */ + 0x00000018, /* DENALI_PI_63_DATA */ + 0x00000000, /* DENALI_PI_64_DATA */ + 0x00000000, /* DENALI_PI_65_DATA */ + 0x00060002, /* DENALI_PI_66_DATA */ + 0x00010001, /* DENALI_PI_67_DATA */ + 0x00000101, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ + 0x00000000, /* DENALI_PI_71_DATA */ + 0x05030000, /* DENALI_PI_72_DATA */ + 0x070a0404, /* DENALI_PI_73_DATA */ + 0x00000000, /* DENALI_PI_74_DATA */ + 0x00000000, /* DENALI_PI_75_DATA */ + 0x00000000, /* DENALI_PI_76_DATA */ + 0x000f0f00, /* DENALI_PI_77_DATA */ + 0x0000001e, /* DENALI_PI_78_DATA */ + 0x00000000, /* DENALI_PI_79_DATA */ + 0x01010300, /* DENALI_PI_80_DATA */ + 0x00000000, /* DENALI_PI_81_DATA */ + 0x00000000, /* DENALI_PI_82_DATA */ + 0x01000000, /* DENALI_PI_83_DATA */ + 0x00000101, /* DENALI_PI_84_DATA */ + 0x55555a5a, /* DENALI_PI_85_DATA */ + 0x55555a5a, /* DENALI_PI_86_DATA */ + 0x55555a5a, /* DENALI_PI_87_DATA */ + 0x55555a5a, /* DENALI_PI_88_DATA */ + 0x0c050001, /* DENALI_PI_89_DATA */ + 0x06020009, /* DENALI_PI_90_DATA */ + 0x00010004, /* DENALI_PI_91_DATA */ + 0x00000203, /* DENALI_PI_92_DATA */ + 0x00030000, /* DENALI_PI_93_DATA */ + 0x170f0000, /* DENALI_PI_94_DATA */ + 0x00060018, /* DENALI_PI_95_DATA */ + 0x000e0020, /* DENALI_PI_96_DATA */ + 0x000a001c, /* DENALI_PI_97_DATA */ + 0x00000000, /* DENALI_PI_98_DATA */ + 0x00000000, /* DENALI_PI_99_DATA */ + 0x00000100, /* DENALI_PI_100_DATA */ + 0x140a0000, /* DENALI_PI_101_DATA */ + 0x000d010a, /* DENALI_PI_102_DATA */ + 0x0100c802, /* DENALI_PI_103_DATA */ + 0x010a0064, /* DENALI_PI_104_DATA */ + 0x000e0100, /* DENALI_PI_105_DATA */ + 0x0100000e, /* DENALI_PI_106_DATA */ + 0x00c900c9, /* DENALI_PI_107_DATA */ + 0x00650100, /* DENALI_PI_108_DATA */ + 0x1e1a0065, /* DENALI_PI_109_DATA */ + 0x10010204, /* DENALI_PI_110_DATA */ + 0x06070605, /* DENALI_PI_111_DATA */ + 0x20000202, /* DENALI_PI_112_DATA */ + 0x00201000, /* DENALI_PI_113_DATA */ + 0x00201000, /* DENALI_PI_114_DATA */ + 0x04041000, /* DENALI_PI_115_DATA */ + 0x10020100, /* DENALI_PI_116_DATA */ + 0x0003010c, /* DENALI_PI_117_DATA */ + 0x004b004a, /* DENALI_PI_118_DATA */ + 0x1a0f0000, /* DENALI_PI_119_DATA */ + 0x0102041e, /* DENALI_PI_120_DATA */ + 0x34000000, /* DENALI_PI_121_DATA */ + 0x00000000, /* DENALI_PI_122_DATA */ + 0x00000000, /* DENALI_PI_123_DATA */ + 0x00010000, /* DENALI_PI_124_DATA */ + 0x00000400, /* DENALI_PI_125_DATA */ + 0x00310000, /* DENALI_PI_126_DATA */ + 0x004d4d00, /* DENALI_PI_127_DATA */ + 0x00120024, /* DENALI_PI_128_DATA */ + 0x4d000031, /* DENALI_PI_129_DATA */ + 0x0000144d, /* DENALI_PI_130_DATA */ + 0x00310009, /* DENALI_PI_131_DATA */ + 0x004d4d00, /* DENALI_PI_132_DATA */ + 0x00000004, /* DENALI_PI_133_DATA */ + 0x4d000031, /* DENALI_PI_134_DATA */ + 0x0000244d, /* DENALI_PI_135_DATA */ + 0x00310012, /* DENALI_PI_136_DATA */ + 0x004d4d00, /* DENALI_PI_137_DATA */ + 0x00090014, /* DENALI_PI_138_DATA */ + 0x4d000031, /* DENALI_PI_139_DATA */ + 0x0004004d, /* DENALI_PI_140_DATA */ + 0x00310000, /* DENALI_PI_141_DATA */ + 0x004d4d00, /* DENALI_PI_142_DATA */ + 0x00120024, /* DENALI_PI_143_DATA */ + 0x4d000031, /* DENALI_PI_144_DATA */ + 0x0000144d, /* DENALI_PI_145_DATA */ + 0x00310009, /* DENALI_PI_146_DATA */ + 0x004d4d00, /* DENALI_PI_147_DATA */ + 0x00000004, /* DENALI_PI_148_DATA */ + 0x4d000031, /* DENALI_PI_149_DATA */ + 0x0000244d, /* DENALI_PI_150_DATA */ + 0x00310012, /* DENALI_PI_151_DATA */ + 0x004d4d00, /* DENALI_PI_152_DATA */ + 0x00090014, /* DENALI_PI_153_DATA */ + 0x4d000031, /* DENALI_PI_154_DATA */ + 0x0200004d, /* DENALI_PI_155_DATA */ + 0x00c8000d, /* DENALI_PI_156_DATA */ + 0x08080064, /* DENALI_PI_157_DATA */ + 0x040a0404, /* DENALI_PI_158_DATA */ + 0x03000d92, /* DENALI_PI_159_DATA */ + 0x010a2001, /* DENALI_PI_160_DATA */ + 0x0f11080a, /* DENALI_PI_161_DATA */ + 0x0000110a, /* DENALI_PI_162_DATA */ + 0x2200d92e, /* DENALI_PI_163_DATA */ + 0x080c2003, /* DENALI_PI_164_DATA */ + 0x0809080a, /* DENALI_PI_165_DATA */ + 0x00000a0a, /* DENALI_PI_166_DATA */ + 0x11006c97, /* DENALI_PI_167_DATA */ + 0x040a2002, /* DENALI_PI_168_DATA */ + 0x0200020a, /* DENALI_PI_169_DATA */ + 0x02000200, /* DENALI_PI_170_DATA */ + 0x02000200, /* DENALI_PI_171_DATA */ + 0x02000200, /* DENALI_PI_172_DATA */ + 0x02000200, /* DENALI_PI_173_DATA */ + 0x00000000, /* DENALI_PI_174_DATA */ + 0x00000000, /* DENALI_PI_175_DATA */ + 0x00000000, /* DENALI_PI_176_DATA */ + 0x00000000, /* DENALI_PI_177_DATA */ + 0x00000000, /* DENALI_PI_178_DATA */ + 0x00000000, /* DENALI_PI_179_DATA */ + 0x00000000, /* DENALI_PI_180_DATA */ + 0x00000000, /* DENALI_PI_181_DATA */ + 0x00000000, /* DENALI_PI_182_DATA */ + 0x00000000, /* DENALI_PI_183_DATA */ + 0x00000000, /* DENALI_PI_184_DATA */ + 0x00000000, /* DENALI_PI_185_DATA */ + 0x01000400, /* DENALI_PI_186_DATA */ + 0x00017600, /* DENALI_PI_187_DATA */ + 0x00000e9c, /* DENALI_PI_188_DATA */ + 0x00001850, /* DENALI_PI_189_DATA */ + 0x0000f320, /* DENALI_PI_190_DATA */ + 0x00000c20, /* DENALI_PI_191_DATA */ + 0x00007940, /* DENALI_PI_192_DATA */ + 0x08000000, /* DENALI_PI_193_DATA */ + 0x00000100, /* DENALI_PI_194_DATA */ + 0x00000000, /* DENALI_PI_195_DATA */ + 0x00000000, /* DENALI_PI_196_DATA */ + 0x00000000, /* DENALI_PI_197_DATA */ + 0x00000000, /* DENALI_PI_198_DATA */ + 0x00000002 /* DENALI_PI_199_DATA */ + } + }, + { + { + 0x76543210, /* DENALI_PHY_00_DATA */ + 0x0004f008, /* DENALI_PHY_01_DATA */ + 0x00020119, /* DENALI_PHY_02_DATA */ + 0x00000000, /* DENALI_PHY_03_DATA */ + 0x00000000, /* DENALI_PHY_04_DATA */ + 0x00010000, /* DENALI_PHY_05_DATA */ + 0x01665555, /* DENALI_PHY_06_DATA */ + 0x03665555, /* DENALI_PHY_07_DATA */ + 0x00010f00, /* DENALI_PHY_08_DATA */ + 0x04000100, /* DENALI_PHY_09_DATA */ + 0x00000001, /* DENALI_PHY_10_DATA */ + 0x00170180, /* DENALI_PHY_11_DATA */ + 0x00cc0201, /* DENALI_PHY_12_DATA */ + 0x00030066, /* DENALI_PHY_13_DATA */ + 0x00000000, /* DENALI_PHY_14_DATA */ + 0x00000000, /* DENALI_PHY_15_DATA */ + 0x00000000, /* DENALI_PHY_16_DATA */ + 0x00000000, /* DENALI_PHY_17_DATA */ + 0x00000000, /* DENALI_PHY_18_DATA */ + 0x00000000, /* DENALI_PHY_19_DATA */ + 0x00000000, /* DENALI_PHY_20_DATA */ + 0x00000000, /* DENALI_PHY_21_DATA */ + 0x04080000, /* DENALI_PHY_22_DATA */ + 0x04080400, /* DENALI_PHY_23_DATA */ + 0x30000000, /* DENALI_PHY_24_DATA */ + 0x0c00c007, /* DENALI_PHY_25_DATA */ + 0x00000100, /* DENALI_PHY_26_DATA */ + 0x00000000, /* DENALI_PHY_27_DATA */ + 0xfd02fe01, /* DENALI_PHY_28_DATA */ + 0xf708fb04, /* DENALI_PHY_29_DATA */ + 0xdf20ef10, /* DENALI_PHY_30_DATA */ + 0x7f80bf40, /* DENALI_PHY_31_DATA */ + 0x0001aaaa, /* DENALI_PHY_32_DATA */ + 0x00000000, /* DENALI_PHY_33_DATA */ + 0x00000000, /* DENALI_PHY_34_DATA */ + 0x00000000, /* DENALI_PHY_35_DATA */ + 0x00000000, /* DENALI_PHY_36_DATA */ + 0x00000000, /* DENALI_PHY_37_DATA */ + 0x00000000, /* DENALI_PHY_38_DATA */ + 0x00000000, /* DENALI_PHY_39_DATA */ + 0x00000000, /* DENALI_PHY_40_DATA */ + 0x00000000, /* DENALI_PHY_41_DATA */ + 0x00000000, /* DENALI_PHY_42_DATA */ + 0x00000000, /* DENALI_PHY_43_DATA */ + 0x00000000, /* DENALI_PHY_44_DATA */ + 0x00000000, /* DENALI_PHY_45_DATA */ + 0x00000000, /* DENALI_PHY_46_DATA */ + 0x00000000, /* DENALI_PHY_47_DATA */ + 0x00000000, /* DENALI_PHY_48_DATA */ + 0x00000000, /* DENALI_PHY_49_DATA */ + 0x00000000, /* DENALI_PHY_50_DATA */ + 0x00000000, /* DENALI_PHY_51_DATA */ + 0x00200000, /* DENALI_PHY_52_DATA */ + 0x00000000, /* DENALI_PHY_53_DATA */ + 0x00000000, /* DENALI_PHY_54_DATA */ + 0x00000000, /* DENALI_PHY_55_DATA */ + 0x00000000, /* DENALI_PHY_56_DATA */ + 0x00000000, /* DENALI_PHY_57_DATA */ + 0x00000000, /* DENALI_PHY_58_DATA */ + 0x02800280, /* DENALI_PHY_59_DATA */ + 0x02800280, /* DENALI_PHY_60_DATA */ + 0x02800280, /* DENALI_PHY_61_DATA */ + 0x02800280, /* DENALI_PHY_62_DATA */ + 0x00000280, /* DENALI_PHY_63_DATA */ + 0x00000000, /* DENALI_PHY_64_DATA */ + 0x00000000, /* DENALI_PHY_65_DATA */ + 0x00000000, /* DENALI_PHY_66_DATA */ + 0x00000000, /* DENALI_PHY_67_DATA */ + 0x00800000, /* DENALI_PHY_68_DATA */ + 0x00800080, /* DENALI_PHY_69_DATA */ + 0x00800080, /* DENALI_PHY_70_DATA */ + 0x00800080, /* DENALI_PHY_71_DATA */ + 0x00800080, /* DENALI_PHY_72_DATA */ + 0x00800080, /* DENALI_PHY_73_DATA */ + 0x00800080, /* DENALI_PHY_74_DATA */ + 0x00800080, /* DENALI_PHY_75_DATA */ + 0x00800080, /* DENALI_PHY_76_DATA */ + 0x01190080, /* DENALI_PHY_77_DATA */ + 0x00000001, /* DENALI_PHY_78_DATA */ + 0x00000000, /* DENALI_PHY_79_DATA */ + 0x00000000, /* DENALI_PHY_80_DATA */ + 0x00000200, /* DENALI_PHY_81_DATA */ + 0x00000000, /* DENALI_PHY_82_DATA */ + 0x51315152, /* DENALI_PHY_83_DATA */ + 0xc0003150, /* DENALI_PHY_84_DATA */ + 0x010000c0, /* DENALI_PHY_85_DATA */ + 0x00100000, /* DENALI_PHY_86_DATA */ + 0x07044204, /* DENALI_PHY_87_DATA */ + 0x000f0c18, /* DENALI_PHY_88_DATA */ + 0x01000140, /* DENALI_PHY_89_DATA */ + 0x00000c10, /* DENALI_PHY_90_DATA */ + 0x00000000, /* DENALI_PHY_91_DATA */ + 0x00000000, /* DENALI_PHY_92_DATA */ + 0x00000000, /* DENALI_PHY_93_DATA */ + 0x00000000, /* DENALI_PHY_94_DATA */ + 0x00000000, /* DENALI_PHY_95_DATA */ + 0x00000000, /* DENALI_PHY_96_DATA */ + 0x00000000, /* DENALI_PHY_97_DATA */ + 0x00000000, /* DENALI_PHY_98_DATA */ + 0x00000000, /* DENALI_PHY_99_DATA */ + 0x00000000, /* DENALI_PHY_100_DATA */ + 0x00000000, /* DENALI_PHY_101_DATA */ + 0x00000000, /* DENALI_PHY_102_DATA */ + 0x00000000, /* DENALI_PHY_103_DATA */ + 0x00000000, /* DENALI_PHY_104_DATA */ + 0x00000000, /* DENALI_PHY_105_DATA */ + 0x00000000, /* DENALI_PHY_106_DATA */ + 0x00000000, /* DENALI_PHY_107_DATA */ + 0x00000000, /* DENALI_PHY_108_DATA */ + 0x00000000, /* DENALI_PHY_109_DATA */ + 0x00000000, /* DENALI_PHY_110_DATA */ + 0x00000000, /* DENALI_PHY_111_DATA */ + 0x00000000, /* DENALI_PHY_112_DATA */ + 0x00000000, /* DENALI_PHY_113_DATA */ + 0x00000000, /* DENALI_PHY_114_DATA */ + 0x00000000, /* DENALI_PHY_115_DATA */ + 0x00000000, /* DENALI_PHY_116_DATA */ + 0x00000000, /* DENALI_PHY_117_DATA */ + 0x00000000, /* DENALI_PHY_118_DATA */ + 0x00000000, /* DENALI_PHY_119_DATA */ + 0x00000000, /* DENALI_PHY_120_DATA */ + 0x00000000, /* DENALI_PHY_121_DATA */ + 0x00000000, /* DENALI_PHY_122_DATA */ + 0x00000000, /* DENALI_PHY_123_DATA */ + 0x00000000, /* DENALI_PHY_124_DATA */ + 0x00000000, /* DENALI_PHY_125_DATA */ + 0x00000000, /* DENALI_PHY_126_DATA */ + 0x00000000, /* DENALI_PHY_127_DATA */ + 0x76543210, /* DENALI_PHY_128_DATA */ + 0x0004f008, /* DENALI_PHY_129_DATA */ + 0x00020119, /* DENALI_PHY_130_DATA */ + 0x00000000, /* DENALI_PHY_131_DATA */ + 0x00000000, /* DENALI_PHY_132_DATA */ + 0x00010000, /* DENALI_PHY_133_DATA */ + 0x01665555, /* DENALI_PHY_134_DATA */ + 0x03665555, /* DENALI_PHY_135_DATA */ + 0x00010f00, /* DENALI_PHY_136_DATA */ + 0x04000100, /* DENALI_PHY_137_DATA */ + 0x00000001, /* DENALI_PHY_138_DATA */ + 0x00170180, /* DENALI_PHY_139_DATA */ + 0x00cc0201, /* DENALI_PHY_140_DATA */ + 0x00030066, /* DENALI_PHY_141_DATA */ + 0x00000000, /* DENALI_PHY_142_DATA */ + 0x00000000, /* DENALI_PHY_143_DATA */ + 0x00000000, /* DENALI_PHY_144_DATA */ + 0x00000000, /* DENALI_PHY_145_DATA */ + 0x00000000, /* DENALI_PHY_146_DATA */ + 0x00000000, /* DENALI_PHY_147_DATA */ + 0x00000000, /* DENALI_PHY_148_DATA */ + 0x00000000, /* DENALI_PHY_149_DATA */ + 0x04080000, /* DENALI_PHY_150_DATA */ + 0x04080400, /* DENALI_PHY_151_DATA */ + 0x30000000, /* DENALI_PHY_152_DATA */ + 0x0c00c007, /* DENALI_PHY_153_DATA */ + 0x00000100, /* DENALI_PHY_154_DATA */ + 0x00000000, /* DENALI_PHY_155_DATA */ + 0xfd02fe01, /* DENALI_PHY_156_DATA */ + 0xf708fb04, /* DENALI_PHY_157_DATA */ + 0xdf20ef10, /* DENALI_PHY_158_DATA */ + 0x7f80bf40, /* DENALI_PHY_159_DATA */ + 0x0000aaaa, /* DENALI_PHY_160_DATA */ + 0x00000000, /* DENALI_PHY_161_DATA */ + 0x00000000, /* DENALI_PHY_162_DATA */ + 0x00000000, /* DENALI_PHY_163_DATA */ + 0x00000000, /* DENALI_PHY_164_DATA */ + 0x00000000, /* DENALI_PHY_165_DATA */ + 0x00000000, /* DENALI_PHY_166_DATA */ + 0x00000000, /* DENALI_PHY_167_DATA */ + 0x00000000, /* DENALI_PHY_168_DATA */ + 0x00000000, /* DENALI_PHY_169_DATA */ + 0x00000000, /* DENALI_PHY_170_DATA */ + 0x00000000, /* DENALI_PHY_171_DATA */ + 0x00000000, /* DENALI_PHY_172_DATA */ + 0x00000000, /* DENALI_PHY_173_DATA */ + 0x00000000, /* DENALI_PHY_174_DATA */ + 0x00000000, /* DENALI_PHY_175_DATA */ + 0x00000000, /* DENALI_PHY_176_DATA */ + 0x00000000, /* DENALI_PHY_177_DATA */ + 0x00000000, /* DENALI_PHY_178_DATA */ + 0x00000000, /* DENALI_PHY_179_DATA */ + 0x00200000, /* DENALI_PHY_180_DATA */ + 0x00000000, /* DENALI_PHY_181_DATA */ + 0x00000000, /* DENALI_PHY_182_DATA */ + 0x00000000, /* DENALI_PHY_183_DATA */ + 0x00000000, /* DENALI_PHY_184_DATA */ + 0x00000000, /* DENALI_PHY_185_DATA */ + 0x00000000, /* DENALI_PHY_186_DATA */ + 0x02800280, /* DENALI_PHY_187_DATA */ + 0x02800280, /* DENALI_PHY_188_DATA */ + 0x02800280, /* DENALI_PHY_189_DATA */ + 0x02800280, /* DENALI_PHY_190_DATA */ + 0x00000280, /* DENALI_PHY_191_DATA */ + 0x00000000, /* DENALI_PHY_192_DATA */ + 0x00000000, /* DENALI_PHY_193_DATA */ + 0x00000000, /* DENALI_PHY_194_DATA */ + 0x00000000, /* DENALI_PHY_195_DATA */ + 0x00800000, /* DENALI_PHY_196_DATA */ + 0x00800080, /* DENALI_PHY_197_DATA */ + 0x00800080, /* DENALI_PHY_198_DATA */ + 0x00800080, /* DENALI_PHY_199_DATA */ + 0x00800080, /* DENALI_PHY_200_DATA */ + 0x00800080, /* DENALI_PHY_201_DATA */ + 0x00800080, /* DENALI_PHY_202_DATA */ + 0x00800080, /* DENALI_PHY_203_DATA */ + 0x00800080, /* DENALI_PHY_204_DATA */ + 0x01190080, /* DENALI_PHY_205_DATA */ + 0x00000001, /* DENALI_PHY_206_DATA */ + 0x00000000, /* DENALI_PHY_207_DATA */ + 0x00000000, /* DENALI_PHY_208_DATA */ + 0x00000200, /* DENALI_PHY_209_DATA */ + 0x00000000, /* DENALI_PHY_210_DATA */ + 0x51315152, /* DENALI_PHY_211_DATA */ + 0xc0003150, /* DENALI_PHY_212_DATA */ + 0x010000c0, /* DENALI_PHY_213_DATA */ + 0x00100000, /* DENALI_PHY_214_DATA */ + 0x07044204, /* DENALI_PHY_215_DATA */ + 0x000f0c18, /* DENALI_PHY_216_DATA */ + 0x01000140, /* DENALI_PHY_217_DATA */ + 0x00000c10, /* DENALI_PHY_218_DATA */ + 0x00000000, /* DENALI_PHY_219_DATA */ + 0x00000000, /* DENALI_PHY_220_DATA */ + 0x00000000, /* DENALI_PHY_221_DATA */ + 0x00000000, /* DENALI_PHY_222_DATA */ + 0x00000000, /* DENALI_PHY_223_DATA */ + 0x00000000, /* DENALI_PHY_224_DATA */ + 0x00000000, /* DENALI_PHY_225_DATA */ + 0x00000000, /* DENALI_PHY_226_DATA */ + 0x00000000, /* DENALI_PHY_227_DATA */ + 0x00000000, /* DENALI_PHY_228_DATA */ + 0x00000000, /* DENALI_PHY_229_DATA */ + 0x00000000, /* DENALI_PHY_230_DATA */ + 0x00000000, /* DENALI_PHY_231_DATA */ + 0x00000000, /* DENALI_PHY_232_DATA */ + 0x00000000, /* DENALI_PHY_233_DATA */ + 0x00000000, /* DENALI_PHY_234_DATA */ + 0x00000000, /* DENALI_PHY_235_DATA */ + 0x00000000, /* DENALI_PHY_236_DATA */ + 0x00000000, /* DENALI_PHY_237_DATA */ + 0x00000000, /* DENALI_PHY_238_DATA */ + 0x00000000, /* DENALI_PHY_239_DATA */ + 0x00000000, /* DENALI_PHY_240_DATA */ + 0x00000000, /* DENALI_PHY_241_DATA */ + 0x00000000, /* DENALI_PHY_242_DATA */ + 0x00000000, /* DENALI_PHY_243_DATA */ + 0x00000000, /* DENALI_PHY_244_DATA */ + 0x00000000, /* DENALI_PHY_245_DATA */ + 0x00000000, /* DENALI_PHY_246_DATA */ + 0x00000000, /* DENALI_PHY_247_DATA */ + 0x00000000, /* DENALI_PHY_248_DATA */ + 0x00000000, /* DENALI_PHY_249_DATA */ + 0x00000000, /* DENALI_PHY_250_DATA */ + 0x00000000, /* DENALI_PHY_251_DATA */ + 0x00000000, /* DENALI_PHY_252_DATA */ + 0x00000000, /* DENALI_PHY_253_DATA */ + 0x00000000, /* DENALI_PHY_254_DATA */ + 0x00000000, /* DENALI_PHY_255_DATA */ + 0x76543210, /* DENALI_PHY_256_DATA */ + 0x0004f008, /* DENALI_PHY_257_DATA */ + 0x00020119, /* DENALI_PHY_258_DATA */ + 0x00000000, /* DENALI_PHY_259_DATA */ + 0x00000000, /* DENALI_PHY_260_DATA */ + 0x00010000, /* DENALI_PHY_261_DATA */ + 0x01665555, /* DENALI_PHY_262_DATA */ + 0x03665555, /* DENALI_PHY_263_DATA */ + 0x00010f00, /* DENALI_PHY_264_DATA */ + 0x04000100, /* DENALI_PHY_265_DATA */ + 0x00000001, /* DENALI_PHY_266_DATA */ + 0x00170180, /* DENALI_PHY_267_DATA */ + 0x00cc0201, /* DENALI_PHY_268_DATA */ + 0x00030066, /* DENALI_PHY_269_DATA */ + 0x00000000, /* DENALI_PHY_270_DATA */ + 0x00000000, /* DENALI_PHY_271_DATA */ + 0x00000000, /* DENALI_PHY_272_DATA */ + 0x00000000, /* DENALI_PHY_273_DATA */ + 0x00000000, /* DENALI_PHY_274_DATA */ + 0x00000000, /* DENALI_PHY_275_DATA */ + 0x00000000, /* DENALI_PHY_276_DATA */ + 0x00000000, /* DENALI_PHY_277_DATA */ + 0x04080000, /* DENALI_PHY_278_DATA */ + 0x04080400, /* DENALI_PHY_279_DATA */ + 0x30000000, /* DENALI_PHY_280_DATA */ + 0x0c00c007, /* DENALI_PHY_281_DATA */ + 0x00000100, /* DENALI_PHY_282_DATA */ + 0x00000000, /* DENALI_PHY_283_DATA */ + 0xfd02fe01, /* DENALI_PHY_284_DATA */ + 0xf708fb04, /* DENALI_PHY_285_DATA */ + 0xdf20ef10, /* DENALI_PHY_286_DATA */ + 0x7f80bf40, /* DENALI_PHY_287_DATA */ + 0x0001aaaa, /* DENALI_PHY_288_DATA */ + 0x00000000, /* DENALI_PHY_289_DATA */ + 0x00000000, /* DENALI_PHY_290_DATA */ + 0x00000000, /* DENALI_PHY_291_DATA */ + 0x00000000, /* DENALI_PHY_292_DATA */ + 0x00000000, /* DENALI_PHY_293_DATA */ + 0x00000000, /* DENALI_PHY_294_DATA */ + 0x00000000, /* DENALI_PHY_295_DATA */ + 0x00000000, /* DENALI_PHY_296_DATA */ + 0x00000000, /* DENALI_PHY_297_DATA */ + 0x00000000, /* DENALI_PHY_298_DATA */ + 0x00000000, /* DENALI_PHY_299_DATA */ + 0x00000000, /* DENALI_PHY_300_DATA */ + 0x00000000, /* DENALI_PHY_301_DATA */ + 0x00000000, /* DENALI_PHY_302_DATA */ + 0x00000000, /* DENALI_PHY_303_DATA */ + 0x00000000, /* DENALI_PHY_304_DATA */ + 0x00000000, /* DENALI_PHY_305_DATA */ + 0x00000000, /* DENALI_PHY_306_DATA */ + 0x00000000, /* DENALI_PHY_307_DATA */ + 0x00200000, /* DENALI_PHY_308_DATA */ + 0x00000000, /* DENALI_PHY_309_DATA */ + 0x00000000, /* DENALI_PHY_310_DATA */ + 0x00000000, /* DENALI_PHY_311_DATA */ + 0x00000000, /* DENALI_PHY_312_DATA */ + 0x00000000, /* DENALI_PHY_313_DATA */ + 0x00000000, /* DENALI_PHY_314_DATA */ + 0x02800280, /* DENALI_PHY_315_DATA */ + 0x02800280, /* DENALI_PHY_316_DATA */ + 0x02800280, /* DENALI_PHY_317_DATA */ + 0x02800280, /* DENALI_PHY_318_DATA */ + 0x00000280, /* DENALI_PHY_319_DATA */ + 0x00000000, /* DENALI_PHY_320_DATA */ + 0x00000000, /* DENALI_PHY_321_DATA */ + 0x00000000, /* DENALI_PHY_322_DATA */ + 0x00000000, /* DENALI_PHY_323_DATA */ + 0x00800000, /* DENALI_PHY_324_DATA */ + 0x00800080, /* DENALI_PHY_325_DATA */ + 0x00800080, /* DENALI_PHY_326_DATA */ + 0x00800080, /* DENALI_PHY_327_DATA */ + 0x00800080, /* DENALI_PHY_328_DATA */ + 0x00800080, /* DENALI_PHY_329_DATA */ + 0x00800080, /* DENALI_PHY_330_DATA */ + 0x00800080, /* DENALI_PHY_331_DATA */ + 0x00800080, /* DENALI_PHY_332_DATA */ + 0x01190080, /* DENALI_PHY_333_DATA */ + 0x00000001, /* DENALI_PHY_334_DATA */ + 0x00000000, /* DENALI_PHY_335_DATA */ + 0x00000000, /* DENALI_PHY_336_DATA */ + 0x00000200, /* DENALI_PHY_337_DATA */ + 0x00000000, /* DENALI_PHY_338_DATA */ + 0x51315152, /* DENALI_PHY_339_DATA */ + 0xc0003150, /* DENALI_PHY_340_DATA */ + 0x010000c0, /* DENALI_PHY_341_DATA */ + 0x00100000, /* DENALI_PHY_342_DATA */ + 0x07044204, /* DENALI_PHY_343_DATA */ + 0x000f0c18, /* DENALI_PHY_344_DATA */ + 0x01000140, /* DENALI_PHY_345_DATA */ + 0x00000c10, /* DENALI_PHY_346_DATA */ + 0x00000000, /* DENALI_PHY_347_DATA */ + 0x00000000, /* DENALI_PHY_348_DATA */ + 0x00000000, /* DENALI_PHY_349_DATA */ + 0x00000000, /* DENALI_PHY_350_DATA */ + 0x00000000, /* DENALI_PHY_351_DATA */ + 0x00000000, /* DENALI_PHY_352_DATA */ + 0x00000000, /* DENALI_PHY_353_DATA */ + 0x00000000, /* DENALI_PHY_354_DATA */ + 0x00000000, /* DENALI_PHY_355_DATA */ + 0x00000000, /* DENALI_PHY_356_DATA */ + 0x00000000, /* DENALI_PHY_357_DATA */ + 0x00000000, /* DENALI_PHY_358_DATA */ + 0x00000000, /* DENALI_PHY_359_DATA */ + 0x00000000, /* DENALI_PHY_360_DATA */ + 0x00000000, /* DENALI_PHY_361_DATA */ + 0x00000000, /* DENALI_PHY_362_DATA */ + 0x00000000, /* DENALI_PHY_363_DATA */ + 0x00000000, /* DENALI_PHY_364_DATA */ + 0x00000000, /* DENALI_PHY_365_DATA */ + 0x00000000, /* DENALI_PHY_366_DATA */ + 0x00000000, /* DENALI_PHY_367_DATA */ + 0x00000000, /* DENALI_PHY_368_DATA */ + 0x00000000, /* DENALI_PHY_369_DATA */ + 0x00000000, /* DENALI_PHY_370_DATA */ + 0x00000000, /* DENALI_PHY_371_DATA */ + 0x00000000, /* DENALI_PHY_372_DATA */ + 0x00000000, /* DENALI_PHY_373_DATA */ + 0x00000000, /* DENALI_PHY_374_DATA */ + 0x00000000, /* DENALI_PHY_375_DATA */ + 0x00000000, /* DENALI_PHY_376_DATA */ + 0x00000000, /* DENALI_PHY_377_DATA */ + 0x00000000, /* DENALI_PHY_378_DATA */ + 0x00000000, /* DENALI_PHY_379_DATA */ + 0x00000000, /* DENALI_PHY_380_DATA */ + 0x00000000, /* DENALI_PHY_381_DATA */ + 0x00000000, /* DENALI_PHY_382_DATA */ + 0x00000000, /* DENALI_PHY_383_DATA */ + 0x76543210, /* DENALI_PHY_384_DATA */ + 0x0004f008, /* DENALI_PHY_385_DATA */ + 0x00020119, /* DENALI_PHY_386_DATA */ + 0x00000000, /* DENALI_PHY_387_DATA */ + 0x00000000, /* DENALI_PHY_388_DATA */ + 0x00010000, /* DENALI_PHY_389_DATA */ + 0x01665555, /* DENALI_PHY_390_DATA */ + 0x03665555, /* DENALI_PHY_391_DATA */ + 0x00010f00, /* DENALI_PHY_392_DATA */ + 0x04000100, /* DENALI_PHY_393_DATA */ + 0x00000001, /* DENALI_PHY_394_DATA */ + 0x00170180, /* DENALI_PHY_395_DATA */ + 0x00cc0201, /* DENALI_PHY_396_DATA */ + 0x00030066, /* DENALI_PHY_397_DATA */ + 0x00000000, /* DENALI_PHY_398_DATA */ + 0x00000000, /* DENALI_PHY_399_DATA */ + 0x00000000, /* DENALI_PHY_400_DATA */ + 0x00000000, /* DENALI_PHY_401_DATA */ + 0x00000000, /* DENALI_PHY_402_DATA */ + 0x00000000, /* DENALI_PHY_403_DATA */ + 0x00000000, /* DENALI_PHY_404_DATA */ + 0x00000000, /* DENALI_PHY_405_DATA */ + 0x04080000, /* DENALI_PHY_406_DATA */ + 0x04080400, /* DENALI_PHY_407_DATA */ + 0x30000000, /* DENALI_PHY_408_DATA */ + 0x0c00c007, /* DENALI_PHY_409_DATA */ + 0x00000100, /* DENALI_PHY_410_DATA */ + 0x00000000, /* DENALI_PHY_411_DATA */ + 0xfd02fe01, /* DENALI_PHY_412_DATA */ + 0xf708fb04, /* DENALI_PHY_413_DATA */ + 0xdf20ef10, /* DENALI_PHY_414_DATA */ + 0x7f80bf40, /* DENALI_PHY_415_DATA */ + 0x0000aaaa, /* DENALI_PHY_416_DATA */ + 0x00000000, /* DENALI_PHY_417_DATA */ + 0x00000000, /* DENALI_PHY_418_DATA */ + 0x00000000, /* DENALI_PHY_419_DATA */ + 0x00000000, /* DENALI_PHY_420_DATA */ + 0x00000000, /* DENALI_PHY_421_DATA */ + 0x00000000, /* DENALI_PHY_422_DATA */ + 0x00000000, /* DENALI_PHY_423_DATA */ + 0x00000000, /* DENALI_PHY_424_DATA */ + 0x00000000, /* DENALI_PHY_425_DATA */ + 0x00000000, /* DENALI_PHY_426_DATA */ + 0x00000000, /* DENALI_PHY_427_DATA */ + 0x00000000, /* DENALI_PHY_428_DATA */ + 0x00000000, /* DENALI_PHY_429_DATA */ + 0x00000000, /* DENALI_PHY_430_DATA */ + 0x00000000, /* DENALI_PHY_431_DATA */ + 0x00000000, /* DENALI_PHY_432_DATA */ + 0x00000000, /* DENALI_PHY_433_DATA */ + 0x00000000, /* DENALI_PHY_434_DATA */ + 0x00000000, /* DENALI_PHY_435_DATA */ + 0x00200000, /* DENALI_PHY_436_DATA */ + 0x00000000, /* DENALI_PHY_437_DATA */ + 0x00000000, /* DENALI_PHY_438_DATA */ + 0x00000000, /* DENALI_PHY_439_DATA */ + 0x00000000, /* DENALI_PHY_440_DATA */ + 0x00000000, /* DENALI_PHY_441_DATA */ + 0x00000000, /* DENALI_PHY_442_DATA */ + 0x02800280, /* DENALI_PHY_443_DATA */ + 0x02800280, /* DENALI_PHY_444_DATA */ + 0x02800280, /* DENALI_PHY_445_DATA */ + 0x02800280, /* DENALI_PHY_446_DATA */ + 0x00000280, /* DENALI_PHY_447_DATA */ + 0x00000000, /* DENALI_PHY_448_DATA */ + 0x00000000, /* DENALI_PHY_449_DATA */ + 0x00000000, /* DENALI_PHY_450_DATA */ + 0x00000000, /* DENALI_PHY_451_DATA */ + 0x00800000, /* DENALI_PHY_452_DATA */ + 0x00800080, /* DENALI_PHY_453_DATA */ + 0x00800080, /* DENALI_PHY_454_DATA */ + 0x00800080, /* DENALI_PHY_455_DATA */ + 0x00800080, /* DENALI_PHY_456_DATA */ + 0x00800080, /* DENALI_PHY_457_DATA */ + 0x00800080, /* DENALI_PHY_458_DATA */ + 0x00800080, /* DENALI_PHY_459_DATA */ + 0x00800080, /* DENALI_PHY_460_DATA */ + 0x01190080, /* DENALI_PHY_461_DATA */ + 0x00000001, /* DENALI_PHY_462_DATA */ + 0x00000000, /* DENALI_PHY_463_DATA */ + 0x00000000, /* DENALI_PHY_464_DATA */ + 0x00000200, /* DENALI_PHY_465_DATA */ + 0x00000000, /* DENALI_PHY_466_DATA */ + 0x51315152, /* DENALI_PHY_467_DATA */ + 0xc0003150, /* DENALI_PHY_468_DATA */ + 0x010000c0, /* DENALI_PHY_469_DATA */ + 0x00100000, /* DENALI_PHY_470_DATA */ + 0x07044204, /* DENALI_PHY_471_DATA */ + 0x000f0c18, /* DENALI_PHY_472_DATA */ + 0x01000140, /* DENALI_PHY_473_DATA */ + 0x00000c10, /* DENALI_PHY_474_DATA */ + 0x00000000, /* DENALI_PHY_475_DATA */ + 0x00000000, /* DENALI_PHY_476_DATA */ + 0x00000000, /* DENALI_PHY_477_DATA */ + 0x00000000, /* DENALI_PHY_478_DATA */ + 0x00000000, /* DENALI_PHY_479_DATA */ + 0x00000000, /* DENALI_PHY_480_DATA */ + 0x00000000, /* DENALI_PHY_481_DATA */ + 0x00000000, /* DENALI_PHY_482_DATA */ + 0x00000000, /* DENALI_PHY_483_DATA */ + 0x00000000, /* DENALI_PHY_484_DATA */ + 0x00000000, /* DENALI_PHY_485_DATA */ + 0x00000000, /* DENALI_PHY_486_DATA */ + 0x00000000, /* DENALI_PHY_487_DATA */ + 0x00000000, /* DENALI_PHY_488_DATA */ + 0x00000000, /* DENALI_PHY_489_DATA */ + 0x00000000, /* DENALI_PHY_490_DATA */ + 0x00000000, /* DENALI_PHY_491_DATA */ + 0x00000000, /* DENALI_PHY_492_DATA */ + 0x00000000, /* DENALI_PHY_493_DATA */ + 0x00000000, /* DENALI_PHY_494_DATA */ + 0x00000000, /* DENALI_PHY_495_DATA */ + 0x00000000, /* DENALI_PHY_496_DATA */ + 0x00000000, /* DENALI_PHY_497_DATA */ + 0x00000000, /* DENALI_PHY_498_DATA */ + 0x00000000, /* DENALI_PHY_499_DATA */ + 0x00000000, /* DENALI_PHY_500_DATA */ + 0x00000000, /* DENALI_PHY_501_DATA */ + 0x00000000, /* DENALI_PHY_502_DATA */ + 0x00000000, /* DENALI_PHY_503_DATA */ + 0x00000000, /* DENALI_PHY_504_DATA */ + 0x00000000, /* DENALI_PHY_505_DATA */ + 0x00000000, /* DENALI_PHY_506_DATA */ + 0x00000000, /* DENALI_PHY_507_DATA */ + 0x00000000, /* DENALI_PHY_508_DATA */ + 0x00000000, /* DENALI_PHY_509_DATA */ + 0x00000000, /* DENALI_PHY_510_DATA */ + 0x00000000, /* DENALI_PHY_511_DATA */ + 0x00000000, /* DENALI_PHY_512_DATA */ + 0x00000000, /* DENALI_PHY_513_DATA */ + 0x00000000, /* DENALI_PHY_514_DATA */ + 0x00000000, /* DENALI_PHY_515_DATA */ + 0x00000000, /* DENALI_PHY_516_DATA */ + 0x00000000, /* DENALI_PHY_517_DATA */ + 0x00000000, /* DENALI_PHY_518_DATA */ + 0x00000002, /* DENALI_PHY_519_DATA */ + 0x00000000, /* DENALI_PHY_520_DATA */ + 0x00000000, /* DENALI_PHY_521_DATA */ + 0x00000000, /* DENALI_PHY_522_DATA */ + 0x00400320, /* DENALI_PHY_523_DATA */ + 0x00000040, /* DENALI_PHY_524_DATA */ + 0x00dcba98, /* DENALI_PHY_525_DATA */ + 0x00000000, /* DENALI_PHY_526_DATA */ + 0x00dcba98, /* DENALI_PHY_527_DATA */ + 0x01000000, /* DENALI_PHY_528_DATA */ + 0x00020003, /* DENALI_PHY_529_DATA */ + 0x00000000, /* DENALI_PHY_530_DATA */ + 0x00000000, /* DENALI_PHY_531_DATA */ + 0x00000000, /* DENALI_PHY_532_DATA */ + 0x0000002a, /* DENALI_PHY_533_DATA */ + 0x00000015, /* DENALI_PHY_534_DATA */ + 0x00000015, /* DENALI_PHY_535_DATA */ + 0x0000002a, /* DENALI_PHY_536_DATA */ + 0x00000033, /* DENALI_PHY_537_DATA */ + 0x0000000c, /* DENALI_PHY_538_DATA */ + 0x0000000c, /* DENALI_PHY_539_DATA */ + 0x00000033, /* DENALI_PHY_540_DATA */ + 0x0a418820, /* DENALI_PHY_541_DATA */ + 0x003f0000, /* DENALI_PHY_542_DATA */ + 0x0000003f, /* DENALI_PHY_543_DATA */ + 0x00030055, /* DENALI_PHY_544_DATA */ + 0x03000300, /* DENALI_PHY_545_DATA */ + 0x03000300, /* DENALI_PHY_546_DATA */ + 0x00000300, /* DENALI_PHY_547_DATA */ + 0x42080010, /* DENALI_PHY_548_DATA */ + 0x00000003, /* DENALI_PHY_549_DATA */ + 0x00000000, /* DENALI_PHY_550_DATA */ + 0x00000000, /* DENALI_PHY_551_DATA */ + 0x00000000, /* DENALI_PHY_552_DATA */ + 0x00000000, /* DENALI_PHY_553_DATA */ + 0x00000000, /* DENALI_PHY_554_DATA */ + 0x00000000, /* DENALI_PHY_555_DATA */ + 0x00000000, /* DENALI_PHY_556_DATA */ + 0x00000000, /* DENALI_PHY_557_DATA */ + 0x00000000, /* DENALI_PHY_558_DATA */ + 0x00000000, /* DENALI_PHY_559_DATA */ + 0x00000000, /* DENALI_PHY_560_DATA */ + 0x00000000, /* DENALI_PHY_561_DATA */ + 0x00000000, /* DENALI_PHY_562_DATA */ + 0x00000000, /* DENALI_PHY_563_DATA */ + 0x00000000, /* DENALI_PHY_564_DATA */ + 0x00000000, /* DENALI_PHY_565_DATA */ + 0x00000000, /* DENALI_PHY_566_DATA */ + 0x00000000, /* DENALI_PHY_567_DATA */ + 0x00000000, /* DENALI_PHY_568_DATA */ + 0x00000000, /* DENALI_PHY_569_DATA */ + 0x00000000, /* DENALI_PHY_570_DATA */ + 0x00000000, /* DENALI_PHY_571_DATA */ + 0x00000000, /* DENALI_PHY_572_DATA */ + 0x00000000, /* DENALI_PHY_573_DATA */ + 0x00000000, /* DENALI_PHY_574_DATA */ + 0x00000000, /* DENALI_PHY_575_DATA */ + 0x00000000, /* DENALI_PHY_576_DATA */ + 0x00000000, /* DENALI_PHY_577_DATA */ + 0x00000000, /* DENALI_PHY_578_DATA */ + 0x00000000, /* DENALI_PHY_579_DATA */ + 0x00000000, /* DENALI_PHY_580_DATA */ + 0x00000000, /* DENALI_PHY_581_DATA */ + 0x00000000, /* DENALI_PHY_582_DATA */ + 0x00000000, /* DENALI_PHY_583_DATA */ + 0x00000000, /* DENALI_PHY_584_DATA */ + 0x00000000, /* DENALI_PHY_585_DATA */ + 0x00000000, /* DENALI_PHY_586_DATA */ + 0x00000000, /* DENALI_PHY_587_DATA */ + 0x00000000, /* DENALI_PHY_588_DATA */ + 0x00000000, /* DENALI_PHY_589_DATA */ + 0x00000000, /* DENALI_PHY_590_DATA */ + 0x00000000, /* DENALI_PHY_591_DATA */ + 0x00000000, /* DENALI_PHY_592_DATA */ + 0x00000000, /* DENALI_PHY_593_DATA */ + 0x00000000, /* DENALI_PHY_594_DATA */ + 0x00000000, /* DENALI_PHY_595_DATA */ + 0x00000000, /* DENALI_PHY_596_DATA */ + 0x00000000, /* DENALI_PHY_597_DATA */ + 0x00000000, /* DENALI_PHY_598_DATA */ + 0x00000000, /* DENALI_PHY_599_DATA */ + 0x00000000, /* DENALI_PHY_600_DATA */ + 0x00000000, /* DENALI_PHY_601_DATA */ + 0x00000000, /* DENALI_PHY_602_DATA */ + 0x00000000, /* DENALI_PHY_603_DATA */ + 0x00000000, /* DENALI_PHY_604_DATA */ + 0x00000000, /* DENALI_PHY_605_DATA */ + 0x00000000, /* DENALI_PHY_606_DATA */ + 0x00000000, /* DENALI_PHY_607_DATA */ + 0x00000000, /* DENALI_PHY_608_DATA */ + 0x00000000, /* DENALI_PHY_609_DATA */ + 0x00000000, /* DENALI_PHY_610_DATA */ + 0x00000000, /* DENALI_PHY_611_DATA */ + 0x00000000, /* DENALI_PHY_612_DATA */ + 0x00000000, /* DENALI_PHY_613_DATA */ + 0x00000000, /* DENALI_PHY_614_DATA */ + 0x00000000, /* DENALI_PHY_615_DATA */ + 0x00000000, /* DENALI_PHY_616_DATA */ + 0x00000000, /* DENALI_PHY_617_DATA */ + 0x00000000, /* DENALI_PHY_618_DATA */ + 0x00000000, /* DENALI_PHY_619_DATA */ + 0x00000000, /* DENALI_PHY_620_DATA */ + 0x00000000, /* DENALI_PHY_621_DATA */ + 0x00000000, /* DENALI_PHY_622_DATA */ + 0x00000000, /* DENALI_PHY_623_DATA */ + 0x00000000, /* DENALI_PHY_624_DATA */ + 0x00000000, /* DENALI_PHY_625_DATA */ + 0x00000000, /* DENALI_PHY_626_DATA */ + 0x00000000, /* DENALI_PHY_627_DATA */ + 0x00000000, /* DENALI_PHY_628_DATA */ + 0x00000000, /* DENALI_PHY_629_DATA */ + 0x00000000, /* DENALI_PHY_630_DATA */ + 0x00000000, /* DENALI_PHY_631_DATA */ + 0x00000000, /* DENALI_PHY_632_DATA */ + 0x00000000, /* DENALI_PHY_633_DATA */ + 0x00000000, /* DENALI_PHY_634_DATA */ + 0x00000000, /* DENALI_PHY_635_DATA */ + 0x00000000, /* DENALI_PHY_636_DATA */ + 0x00000000, /* DENALI_PHY_637_DATA */ + 0x00000000, /* DENALI_PHY_638_DATA */ + 0x00000000, /* DENALI_PHY_639_DATA */ + 0x00000000, /* DENALI_PHY_640_DATA */ + 0x00000000, /* DENALI_PHY_641_DATA */ + 0x00000000, /* DENALI_PHY_642_DATA */ + 0x00000000, /* DENALI_PHY_643_DATA */ + 0x00000000, /* DENALI_PHY_644_DATA */ + 0x00000000, /* DENALI_PHY_645_DATA */ + 0x00000000, /* DENALI_PHY_646_DATA */ + 0x00000002, /* DENALI_PHY_647_DATA */ + 0x00000000, /* DENALI_PHY_648_DATA */ + 0x00000000, /* DENALI_PHY_649_DATA */ + 0x00000000, /* DENALI_PHY_650_DATA */ + 0x00400320, /* DENALI_PHY_651_DATA */ + 0x00000040, /* DENALI_PHY_652_DATA */ + 0x00000000, /* DENALI_PHY_653_DATA */ + 0x00000000, /* DENALI_PHY_654_DATA */ + 0x00000000, /* DENALI_PHY_655_DATA */ + 0x01000000, /* DENALI_PHY_656_DATA */ + 0x00020003, /* DENALI_PHY_657_DATA */ + 0x00000000, /* DENALI_PHY_658_DATA */ + 0x00000000, /* DENALI_PHY_659_DATA */ + 0x00000000, /* DENALI_PHY_660_DATA */ + 0x0000002a, /* DENALI_PHY_661_DATA */ + 0x00000015, /* DENALI_PHY_662_DATA */ + 0x00000015, /* DENALI_PHY_663_DATA */ + 0x0000002a, /* DENALI_PHY_664_DATA */ + 0x00000033, /* DENALI_PHY_665_DATA */ + 0x0000000c, /* DENALI_PHY_666_DATA */ + 0x0000000c, /* DENALI_PHY_667_DATA */ + 0x00000033, /* DENALI_PHY_668_DATA */ + 0x00000000, /* DENALI_PHY_669_DATA */ + 0x00000000, /* DENALI_PHY_670_DATA */ + 0x00000000, /* DENALI_PHY_671_DATA */ + 0x00030055, /* DENALI_PHY_672_DATA */ + 0x03000300, /* DENALI_PHY_673_DATA */ + 0x03000300, /* DENALI_PHY_674_DATA */ + 0x00000300, /* DENALI_PHY_675_DATA */ + 0x42080010, /* DENALI_PHY_676_DATA */ + 0x00000003, /* DENALI_PHY_677_DATA */ + 0x00000000, /* DENALI_PHY_678_DATA */ + 0x00000000, /* DENALI_PHY_679_DATA */ + 0x00000000, /* DENALI_PHY_680_DATA */ + 0x00000000, /* DENALI_PHY_681_DATA */ + 0x00000000, /* DENALI_PHY_682_DATA */ + 0x00000000, /* DENALI_PHY_683_DATA */ + 0x00000000, /* DENALI_PHY_684_DATA */ + 0x00000000, /* DENALI_PHY_685_DATA */ + 0x00000000, /* DENALI_PHY_686_DATA */ + 0x00000000, /* DENALI_PHY_687_DATA */ + 0x00000000, /* DENALI_PHY_688_DATA */ + 0x00000000, /* DENALI_PHY_689_DATA */ + 0x00000000, /* DENALI_PHY_690_DATA */ + 0x00000000, /* DENALI_PHY_691_DATA */ + 0x00000000, /* DENALI_PHY_692_DATA */ + 0x00000000, /* DENALI_PHY_693_DATA */ + 0x00000000, /* DENALI_PHY_694_DATA */ + 0x00000000, /* DENALI_PHY_695_DATA */ + 0x00000000, /* DENALI_PHY_696_DATA */ + 0x00000000, /* DENALI_PHY_697_DATA */ + 0x00000000, /* DENALI_PHY_698_DATA */ + 0x00000000, /* DENALI_PHY_699_DATA */ + 0x00000000, /* DENALI_PHY_700_DATA */ + 0x00000000, /* DENALI_PHY_701_DATA */ + 0x00000000, /* DENALI_PHY_702_DATA */ + 0x00000000, /* DENALI_PHY_703_DATA */ + 0x00000000, /* DENALI_PHY_704_DATA */ + 0x00000000, /* DENALI_PHY_705_DATA */ + 0x00000000, /* DENALI_PHY_706_DATA */ + 0x00000000, /* DENALI_PHY_707_DATA */ + 0x00000000, /* DENALI_PHY_708_DATA */ + 0x00000000, /* DENALI_PHY_709_DATA */ + 0x00000000, /* DENALI_PHY_710_DATA */ + 0x00000000, /* DENALI_PHY_711_DATA */ + 0x00000000, /* DENALI_PHY_712_DATA */ + 0x00000000, /* DENALI_PHY_713_DATA */ + 0x00000000, /* DENALI_PHY_714_DATA */ + 0x00000000, /* DENALI_PHY_715_DATA */ + 0x00000000, /* DENALI_PHY_716_DATA */ + 0x00000000, /* DENALI_PHY_717_DATA */ + 0x00000000, /* DENALI_PHY_718_DATA */ + 0x00000000, /* DENALI_PHY_719_DATA */ + 0x00000000, /* DENALI_PHY_720_DATA */ + 0x00000000, /* DENALI_PHY_721_DATA */ + 0x00000000, /* DENALI_PHY_722_DATA */ + 0x00000000, /* DENALI_PHY_723_DATA */ + 0x00000000, /* DENALI_PHY_724_DATA */ + 0x00000000, /* DENALI_PHY_725_DATA */ + 0x00000000, /* DENALI_PHY_726_DATA */ + 0x00000000, /* DENALI_PHY_727_DATA */ + 0x00000000, /* DENALI_PHY_728_DATA */ + 0x00000000, /* DENALI_PHY_729_DATA */ + 0x00000000, /* DENALI_PHY_730_DATA */ + 0x00000000, /* DENALI_PHY_731_DATA */ + 0x00000000, /* DENALI_PHY_732_DATA */ + 0x00000000, /* DENALI_PHY_733_DATA */ + 0x00000000, /* DENALI_PHY_734_DATA */ + 0x00000000, /* DENALI_PHY_735_DATA */ + 0x00000000, /* DENALI_PHY_736_DATA */ + 0x00000000, /* DENALI_PHY_737_DATA */ + 0x00000000, /* DENALI_PHY_738_DATA */ + 0x00000000, /* DENALI_PHY_739_DATA */ + 0x00000000, /* DENALI_PHY_740_DATA */ + 0x00000000, /* DENALI_PHY_741_DATA */ + 0x00000000, /* DENALI_PHY_742_DATA */ + 0x00000000, /* DENALI_PHY_743_DATA */ + 0x00000000, /* DENALI_PHY_744_DATA */ + 0x00000000, /* DENALI_PHY_745_DATA */ + 0x00000000, /* DENALI_PHY_746_DATA */ + 0x00000000, /* DENALI_PHY_747_DATA */ + 0x00000000, /* DENALI_PHY_748_DATA */ + 0x00000000, /* DENALI_PHY_749_DATA */ + 0x00000000, /* DENALI_PHY_750_DATA */ + 0x00000000, /* DENALI_PHY_751_DATA */ + 0x00000000, /* DENALI_PHY_752_DATA */ + 0x00000000, /* DENALI_PHY_753_DATA */ + 0x00000000, /* DENALI_PHY_754_DATA */ + 0x00000000, /* DENALI_PHY_755_DATA */ + 0x00000000, /* DENALI_PHY_756_DATA */ + 0x00000000, /* DENALI_PHY_757_DATA */ + 0x00000000, /* DENALI_PHY_758_DATA */ + 0x00000000, /* DENALI_PHY_759_DATA */ + 0x00000000, /* DENALI_PHY_760_DATA */ + 0x00000000, /* DENALI_PHY_761_DATA */ + 0x00000000, /* DENALI_PHY_762_DATA */ + 0x00000000, /* DENALI_PHY_763_DATA */ + 0x00000000, /* DENALI_PHY_764_DATA */ + 0x00000000, /* DENALI_PHY_765_DATA */ + 0x00000000, /* DENALI_PHY_766_DATA */ + 0x00000000, /* DENALI_PHY_767_DATA */ + 0x00000000, /* DENALI_PHY_768_DATA */ + 0x00000000, /* DENALI_PHY_769_DATA */ + 0x00000000, /* DENALI_PHY_770_DATA */ + 0x00000000, /* DENALI_PHY_771_DATA */ + 0x00000000, /* DENALI_PHY_772_DATA */ + 0x00000000, /* DENALI_PHY_773_DATA */ + 0x00000000, /* DENALI_PHY_774_DATA */ + 0x00000002, /* DENALI_PHY_775_DATA */ + 0x00000000, /* DENALI_PHY_776_DATA */ + 0x00000000, /* DENALI_PHY_777_DATA */ + 0x00000000, /* DENALI_PHY_778_DATA */ + 0x00400320, /* DENALI_PHY_779_DATA */ + 0x00000040, /* DENALI_PHY_780_DATA */ + 0x00000000, /* DENALI_PHY_781_DATA */ + 0x00000000, /* DENALI_PHY_782_DATA */ + 0x00000000, /* DENALI_PHY_783_DATA */ + 0x01000000, /* DENALI_PHY_784_DATA */ + 0x00020003, /* DENALI_PHY_785_DATA */ + 0x00000000, /* DENALI_PHY_786_DATA */ + 0x00000000, /* DENALI_PHY_787_DATA */ + 0x00000000, /* DENALI_PHY_788_DATA */ + 0x0000002a, /* DENALI_PHY_789_DATA */ + 0x00000015, /* DENALI_PHY_790_DATA */ + 0x00000015, /* DENALI_PHY_791_DATA */ + 0x0000002a, /* DENALI_PHY_792_DATA */ + 0x00000033, /* DENALI_PHY_793_DATA */ + 0x0000000c, /* DENALI_PHY_794_DATA */ + 0x0000000c, /* DENALI_PHY_795_DATA */ + 0x00000033, /* DENALI_PHY_796_DATA */ + 0x1ee6b16a, /* DENALI_PHY_797_DATA */ + 0x10000000, /* DENALI_PHY_798_DATA */ + 0x00000000, /* DENALI_PHY_799_DATA */ + 0x00030055, /* DENALI_PHY_800_DATA */ + 0x03000300, /* DENALI_PHY_801_DATA */ + 0x03000300, /* DENALI_PHY_802_DATA */ + 0x00000300, /* DENALI_PHY_803_DATA */ + 0x42080010, /* DENALI_PHY_804_DATA */ + 0x00000003, /* DENALI_PHY_805_DATA */ + 0x00000000, /* DENALI_PHY_806_DATA */ + 0x00000000, /* DENALI_PHY_807_DATA */ + 0x00000000, /* DENALI_PHY_808_DATA */ + 0x00000000, /* DENALI_PHY_809_DATA */ + 0x00000000, /* DENALI_PHY_810_DATA */ + 0x00000000, /* DENALI_PHY_811_DATA */ + 0x00000000, /* DENALI_PHY_812_DATA */ + 0x00000000, /* DENALI_PHY_813_DATA */ + 0x00000000, /* DENALI_PHY_814_DATA */ + 0x00000000, /* DENALI_PHY_815_DATA */ + 0x00000000, /* DENALI_PHY_816_DATA */ + 0x00000000, /* DENALI_PHY_817_DATA */ + 0x00000000, /* DENALI_PHY_818_DATA */ + 0x00000000, /* DENALI_PHY_819_DATA */ + 0x00000000, /* DENALI_PHY_820_DATA */ + 0x00000000, /* DENALI_PHY_821_DATA */ + 0x00000000, /* DENALI_PHY_822_DATA */ + 0x00000000, /* DENALI_PHY_823_DATA */ + 0x00000000, /* DENALI_PHY_824_DATA */ + 0x00000000, /* DENALI_PHY_825_DATA */ + 0x00000000, /* DENALI_PHY_826_DATA */ + 0x00000000, /* DENALI_PHY_827_DATA */ + 0x00000000, /* DENALI_PHY_828_DATA */ + 0x00000000, /* DENALI_PHY_829_DATA */ + 0x00000000, /* DENALI_PHY_830_DATA */ + 0x00000000, /* DENALI_PHY_831_DATA */ + 0x00000000, /* DENALI_PHY_832_DATA */ + 0x00000000, /* DENALI_PHY_833_DATA */ + 0x00000000, /* DENALI_PHY_834_DATA */ + 0x00000000, /* DENALI_PHY_835_DATA */ + 0x00000000, /* DENALI_PHY_836_DATA */ + 0x00000000, /* DENALI_PHY_837_DATA */ + 0x00000000, /* DENALI_PHY_838_DATA */ + 0x00000000, /* DENALI_PHY_839_DATA */ + 0x00000000, /* DENALI_PHY_840_DATA */ + 0x00000000, /* DENALI_PHY_841_DATA */ + 0x00000000, /* DENALI_PHY_842_DATA */ + 0x00000000, /* DENALI_PHY_843_DATA */ + 0x00000000, /* DENALI_PHY_844_DATA */ + 0x00000000, /* DENALI_PHY_845_DATA */ + 0x00000000, /* DENALI_PHY_846_DATA */ + 0x00000000, /* DENALI_PHY_847_DATA */ + 0x00000000, /* DENALI_PHY_848_DATA */ + 0x00000000, /* DENALI_PHY_849_DATA */ + 0x00000000, /* DENALI_PHY_850_DATA */ + 0x00000000, /* DENALI_PHY_851_DATA */ + 0x00000000, /* DENALI_PHY_852_DATA */ + 0x00000000, /* DENALI_PHY_853_DATA */ + 0x00000000, /* DENALI_PHY_854_DATA */ + 0x00000000, /* DENALI_PHY_855_DATA */ + 0x00000000, /* DENALI_PHY_856_DATA */ + 0x00000000, /* DENALI_PHY_857_DATA */ + 0x00000000, /* DENALI_PHY_858_DATA */ + 0x00000000, /* DENALI_PHY_859_DATA */ + 0x00000000, /* DENALI_PHY_860_DATA */ + 0x00000000, /* DENALI_PHY_861_DATA */ + 0x00000000, /* DENALI_PHY_862_DATA */ + 0x00000000, /* DENALI_PHY_863_DATA */ + 0x00000000, /* DENALI_PHY_864_DATA */ + 0x00000000, /* DENALI_PHY_865_DATA */ + 0x00000000, /* DENALI_PHY_866_DATA */ + 0x00000000, /* DENALI_PHY_867_DATA */ + 0x00000000, /* DENALI_PHY_868_DATA */ + 0x00000000, /* DENALI_PHY_869_DATA */ + 0x00000000, /* DENALI_PHY_870_DATA */ + 0x00000000, /* DENALI_PHY_871_DATA */ + 0x00000000, /* DENALI_PHY_872_DATA */ + 0x00000000, /* DENALI_PHY_873_DATA */ + 0x00000000, /* DENALI_PHY_874_DATA */ + 0x00000000, /* DENALI_PHY_875_DATA */ + 0x00000000, /* DENALI_PHY_876_DATA */ + 0x00000000, /* DENALI_PHY_877_DATA */ + 0x00000000, /* DENALI_PHY_878_DATA */ + 0x00000000, /* DENALI_PHY_879_DATA */ + 0x00000000, /* DENALI_PHY_880_DATA */ + 0x00000000, /* DENALI_PHY_881_DATA */ + 0x00000000, /* DENALI_PHY_882_DATA */ + 0x00000000, /* DENALI_PHY_883_DATA */ + 0x00000000, /* DENALI_PHY_884_DATA */ + 0x00000000, /* DENALI_PHY_885_DATA */ + 0x00000000, /* DENALI_PHY_886_DATA */ + 0x00000000, /* DENALI_PHY_887_DATA */ + 0x00000000, /* DENALI_PHY_888_DATA */ + 0x00000000, /* DENALI_PHY_889_DATA */ + 0x00000000, /* DENALI_PHY_890_DATA */ + 0x00000000, /* DENALI_PHY_891_DATA */ + 0x00000000, /* DENALI_PHY_892_DATA */ + 0x00000000, /* DENALI_PHY_893_DATA */ + 0x00000000, /* DENALI_PHY_894_DATA */ + 0x00000000, /* DENALI_PHY_895_DATA */ + 0x00000000, /* DENALI_PHY_896_DATA */ + 0x00000000, /* DENALI_PHY_897_DATA */ + 0x00000005, /* DENALI_PHY_898_DATA */ + 0x04000f01, /* DENALI_PHY_899_DATA */ + 0x00020040, /* DENALI_PHY_900_DATA */ + 0x00020055, /* DENALI_PHY_901_DATA */ + 0x00000000, /* DENALI_PHY_902_DATA */ + 0x00000000, /* DENALI_PHY_903_DATA */ + 0x00000000, /* DENALI_PHY_904_DATA */ + 0x00000050, /* DENALI_PHY_905_DATA */ + 0x00000000, /* DENALI_PHY_906_DATA */ + 0x01010100, /* DENALI_PHY_907_DATA */ + 0x00000600, /* DENALI_PHY_908_DATA */ + 0x00000000, /* DENALI_PHY_909_DATA */ + 0x00006400, /* DENALI_PHY_910_DATA */ + 0x03221302, /* DENALI_PHY_911_DATA */ + 0x00000000, /* DENALI_PHY_912_DATA */ + 0x000d1f01, /* DENALI_PHY_913_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_914_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_915_DATA */ + 0x00030003, /* DENALI_PHY_916_DATA */ + 0x03000300, /* DENALI_PHY_917_DATA */ + 0x00000300, /* DENALI_PHY_918_DATA */ + 0x03221302, /* DENALI_PHY_919_DATA */ + 0x00000000, /* DENALI_PHY_920_DATA */ + 0x00000000, /* DENALI_PHY_921_DATA */ + 0x01020000, /* DENALI_PHY_922_DATA */ + 0x00000001, /* DENALI_PHY_923_DATA */ + 0x00000411, /* DENALI_PHY_924_DATA */ + 0x00000411, /* DENALI_PHY_925_DATA */ + 0x00000040, /* DENALI_PHY_926_DATA */ + 0x00000040, /* DENALI_PHY_927_DATA */ + 0x00000411, /* DENALI_PHY_928_DATA */ + 0x00000411, /* DENALI_PHY_929_DATA */ + 0x00004410, /* DENALI_PHY_930_DATA */ + 0x00004410, /* DENALI_PHY_931_DATA */ + 0x00004410, /* DENALI_PHY_932_DATA */ + 0x00004410, /* DENALI_PHY_933_DATA */ + 0x00004410, /* DENALI_PHY_934_DATA */ + 0x00000411, /* DENALI_PHY_935_DATA */ + 0x00004410, /* DENALI_PHY_936_DATA */ + 0x00000411, /* DENALI_PHY_937_DATA */ + 0x00004410, /* DENALI_PHY_938_DATA */ + 0x00000411, /* DENALI_PHY_939_DATA */ + 0x00004410, /* DENALI_PHY_940_DATA */ + 0x00000000, /* DENALI_PHY_941_DATA */ + 0x00000000, /* DENALI_PHY_942_DATA */ + 0x00000000, /* DENALI_PHY_943_DATA */ + 0x64000000, /* DENALI_PHY_944_DATA */ + 0x00000000, /* DENALI_PHY_945_DATA */ + 0x00000000, /* DENALI_PHY_946_DATA */ + 0x00000408, /* DENALI_PHY_947_DATA */ + 0x00000000, /* DENALI_PHY_948_DATA */ + 0x00000000, /* DENALI_PHY_949_DATA */ + 0x00000000, /* DENALI_PHY_950_DATA */ + 0x00000000, /* DENALI_PHY_951_DATA */ + 0x00000000, /* DENALI_PHY_952_DATA */ + 0x00000000, /* DENALI_PHY_953_DATA */ + 0xe4000000, /* DENALI_PHY_954_DATA */ + 0x00000000, /* DENALI_PHY_955_DATA */ + 0x00000000, /* DENALI_PHY_956_DATA */ + 0x01010000, /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + } + }, +}, diff --git a/roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc b/roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc new file mode 100644 index 000000000..7d11b4c56 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc @@ -0,0 +1,1586 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + * (C) Copyright 2019 Amarula Solutions + */ + +{ + { + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .cs0_high16bit_row = 0xF, + .cs1_high16bit_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = { + 0x801c1819, + }, + .ddrtimingb0 = { + 0x10040c05, + }, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = { + 0x00002672, + }, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + }, + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .cs0_high16bit_row = 0xF, + .cs1_high16bit_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = { + 0x80241d22, + }, + .ddrtimingb0 = { + 0x15050f08, + }, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = { + 0x00002122, + }, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + } + }, + { + .ddr_freq = 800 * MHz, + .dramtype = LPDDR4, + .num_channels = 2, + .stride = 13, + .odt = 1, + }, + { + { + 0x00000b00, /* DENALI_CTL_00_DATA */ + 0x00000000, /* DENALI_CTL_01_DATA */ + 0x00000000, /* DENALI_CTL_02_DATA */ + 0x00000000, /* DENALI_CTL_03_DATA */ + 0x00000000, /* DENALI_CTL_04_DATA */ + 0x00013880, /* DENALI_CTL_05_DATA */ + 0x000c3500, /* DENALI_CTL_06_DATA */ + 0x00000005, /* DENALI_CTL_07_DATA */ + 0x00000320, /* DENALI_CTL_08_DATA */ + 0x00027100, /* DENALI_CTL_09_DATA */ + 0x00186a00, /* DENALI_CTL_10_DATA */ + 0x00000005, /* DENALI_CTL_11_DATA */ + 0x00000640, /* DENALI_CTL_12_DATA */ + 0x00002710, /* DENALI_CTL_13_DATA */ + 0x000186a0, /* DENALI_CTL_14_DATA */ + 0x00000005, /* DENALI_CTL_15_DATA */ + 0x01000064, /* DENALI_CTL_16_DATA */ + 0x00000000, /* DENALI_CTL_17_DATA */ + 0x02020101, /* DENALI_CTL_18_DATA */ + 0x00000102, /* DENALI_CTL_19_DATA */ + 0x00000050, /* DENALI_CTL_20_DATA */ + 0x000000c8, /* DENALI_CTL_21_DATA */ + 0x00000000, /* DENALI_CTL_22_DATA */ + 0x06140000, /* DENALI_CTL_23_DATA */ + 0x00081c00, /* DENALI_CTL_24_DATA */ + 0x0400040c, /* DENALI_CTL_25_DATA */ + 0x19042008, /* DENALI_CTL_26_DATA */ + 0x10080a11, /* DENALI_CTL_27_DATA */ + 0x22310800, /* DENALI_CTL_28_DATA */ + 0x00200f0a, /* DENALI_CTL_29_DATA */ + 0x0a030704, /* DENALI_CTL_30_DATA */ + 0x08000204, /* DENALI_CTL_31_DATA */ + 0x00000a0a, /* DENALI_CTL_32_DATA */ + 0x04006db0, /* DENALI_CTL_33_DATA */ + 0x0a0a0804, /* DENALI_CTL_34_DATA */ + 0x0600db60, /* DENALI_CTL_35_DATA */ + 0x0a0a0806, /* DENALI_CTL_36_DATA */ + 0x04000db6, /* DENALI_CTL_37_DATA */ + 0x02030404, /* DENALI_CTL_38_DATA */ + 0x0f0a0800, /* DENALI_CTL_39_DATA */ + 0x08040411, /* DENALI_CTL_40_DATA */ + 0x1400640a, /* DENALI_CTL_41_DATA */ + 0x02010a0a, /* DENALI_CTL_42_DATA */ + 0x00010001, /* DENALI_CTL_43_DATA */ + 0x04082012, /* DENALI_CTL_44_DATA */ + 0x00041109, /* DENALI_CTL_45_DATA */ + 0x00000000, /* DENALI_CTL_46_DATA */ + 0x03010000, /* DENALI_CTL_47_DATA */ + 0x06100034, /* DENALI_CTL_48_DATA */ + 0x0c280068, /* DENALI_CTL_49_DATA */ + 0x00bb0007, /* DENALI_CTL_50_DATA */ + 0x00000000, /* DENALI_CTL_51_DATA */ + 0x00060003, /* DENALI_CTL_52_DATA */ + 0x000a0003, /* DENALI_CTL_53_DATA */ + 0x000a0014, /* DENALI_CTL_54_DATA */ + 0x01000000, /* DENALI_CTL_55_DATA */ + 0x030a0000, /* DENALI_CTL_56_DATA */ + 0x0c000002, /* DENALI_CTL_57_DATA */ + 0x00000103, /* DENALI_CTL_58_DATA */ + 0x0003030a, /* DENALI_CTL_59_DATA */ + 0x00060037, /* DENALI_CTL_60_DATA */ + 0x0003006e, /* DENALI_CTL_61_DATA */ + 0x05050007, /* DENALI_CTL_62_DATA */ + 0x03020605, /* DENALI_CTL_63_DATA */ + 0x06050301, /* DENALI_CTL_64_DATA */ + 0x06020c05, /* DENALI_CTL_65_DATA */ + 0x05050302, /* DENALI_CTL_66_DATA */ + 0x03020305, /* DENALI_CTL_67_DATA */ + 0x00000301, /* DENALI_CTL_68_DATA */ + 0x00000301, /* DENALI_CTL_69_DATA */ + 0x00000001, /* DENALI_CTL_70_DATA */ + 0x00000000, /* DENALI_CTL_71_DATA */ + 0x00000000, /* DENALI_CTL_72_DATA */ + 0x01000000, /* DENALI_CTL_73_DATA */ + 0x80104002, /* DENALI_CTL_74_DATA */ + 0x00040003, /* DENALI_CTL_75_DATA */ + 0x00040005, /* DENALI_CTL_76_DATA */ + 0x00030000, /* DENALI_CTL_77_DATA */ + 0x00050004, /* DENALI_CTL_78_DATA */ + 0x00000004, /* DENALI_CTL_79_DATA */ + 0x00040003, /* DENALI_CTL_80_DATA */ + 0x00040005, /* DENALI_CTL_81_DATA */ + 0x18400000, /* DENALI_CTL_82_DATA */ + 0x00000c20, /* DENALI_CTL_83_DATA */ + 0x185030a0, /* DENALI_CTL_84_DATA */ + 0x02ec0000, /* DENALI_CTL_85_DATA */ + 0x00000176, /* DENALI_CTL_86_DATA */ + 0x00000000, /* DENALI_CTL_87_DATA */ + 0x00000000, /* DENALI_CTL_88_DATA */ + 0x00000000, /* DENALI_CTL_89_DATA */ + 0x00000000, /* DENALI_CTL_90_DATA */ + 0x00000000, /* DENALI_CTL_91_DATA */ + 0x06030300, /* DENALI_CTL_92_DATA */ + 0x00030303, /* DENALI_CTL_93_DATA */ + 0x02030200, /* DENALI_CTL_94_DATA */ + 0x00040703, /* DENALI_CTL_95_DATA */ + 0x03020302, /* DENALI_CTL_96_DATA */ + 0x02000407, /* DENALI_CTL_97_DATA */ + 0x07030203, /* DENALI_CTL_98_DATA */ + 0x00030f04, /* DENALI_CTL_99_DATA */ + 0x00070004, /* DENALI_CTL_100_DATA */ + 0x00000000, /* DENALI_CTL_101_DATA */ + 0x00000000, /* DENALI_CTL_102_DATA */ + 0x00000000, /* DENALI_CTL_103_DATA */ + 0x00000000, /* DENALI_CTL_104_DATA */ + 0x00000000, /* DENALI_CTL_105_DATA */ + 0x00000000, /* DENALI_CTL_106_DATA */ + 0x00000000, /* DENALI_CTL_107_DATA */ + 0x00010000, /* DENALI_CTL_108_DATA */ + 0x20040020, /* DENALI_CTL_109_DATA */ + 0x00200400, /* DENALI_CTL_110_DATA */ + 0x01000400, /* DENALI_CTL_111_DATA */ + 0x00000b80, /* DENALI_CTL_112_DATA */ + 0x00000000, /* DENALI_CTL_113_DATA */ + 0x00000001, /* DENALI_CTL_114_DATA */ + 0x00000002, /* DENALI_CTL_115_DATA */ + 0x0000000e, /* DENALI_CTL_116_DATA */ + 0x00000000, /* DENALI_CTL_117_DATA */ + 0x00000000, /* DENALI_CTL_118_DATA */ + 0x00000000, /* DENALI_CTL_119_DATA */ + 0x00000000, /* DENALI_CTL_120_DATA */ + 0x00000000, /* DENALI_CTL_121_DATA */ + 0x00500000, /* DENALI_CTL_122_DATA */ + 0x00640028, /* DENALI_CTL_123_DATA */ + 0x00640404, /* DENALI_CTL_124_DATA */ + 0x005000a0, /* DENALI_CTL_125_DATA */ + 0x060600c8, /* DENALI_CTL_126_DATA */ + 0x000a00c8, /* DENALI_CTL_127_DATA */ + 0x000d0005, /* DENALI_CTL_128_DATA */ + 0x000d0404, /* DENALI_CTL_129_DATA */ + 0x00000000, /* DENALI_CTL_130_DATA */ + 0x00000000, /* DENALI_CTL_131_DATA */ + 0x00000000, /* DENALI_CTL_132_DATA */ + 0x001400a3, /* DENALI_CTL_133_DATA */ + 0x00e30009, /* DENALI_CTL_134_DATA */ + 0x00120024, /* DENALI_CTL_135_DATA */ + 0x00040063, /* DENALI_CTL_136_DATA */ + 0x00000000, /* DENALI_CTL_137_DATA */ + 0x00310031, /* DENALI_CTL_138_DATA */ + 0x00000031, /* DENALI_CTL_139_DATA */ + 0x004d0000, /* DENALI_CTL_140_DATA */ + 0x004d004d, /* DENALI_CTL_141_DATA */ + 0x004d0000, /* DENALI_CTL_142_DATA */ + 0x004d004d, /* DENALI_CTL_143_DATA */ + 0x00010101, /* DENALI_CTL_144_DATA */ + 0x00000000, /* DENALI_CTL_145_DATA */ + 0x00000000, /* DENALI_CTL_146_DATA */ + 0x001400a3, /* DENALI_CTL_147_DATA */ + 0x00e30009, /* DENALI_CTL_148_DATA */ + 0x00120024, /* DENALI_CTL_149_DATA */ + 0x00040063, /* DENALI_CTL_150_DATA */ + 0x00000000, /* DENALI_CTL_151_DATA */ + 0x00310031, /* DENALI_CTL_152_DATA */ + 0x00000031, /* DENALI_CTL_153_DATA */ + 0x004d0000, /* DENALI_CTL_154_DATA */ + 0x004d004d, /* DENALI_CTL_155_DATA */ + 0x004d0000, /* DENALI_CTL_156_DATA */ + 0x004d004d, /* DENALI_CTL_157_DATA */ + 0x00010101, /* DENALI_CTL_158_DATA */ + 0x00000000, /* DENALI_CTL_159_DATA */ + 0x00000000, /* DENALI_CTL_160_DATA */ + 0x00000000, /* DENALI_CTL_161_DATA */ + 0x00000001, /* DENALI_CTL_162_DATA */ + 0x00000000, /* DENALI_CTL_163_DATA */ + 0x18151100, /* DENALI_CTL_164_DATA */ + 0x0000000c, /* DENALI_CTL_165_DATA */ + 0x00000000, /* DENALI_CTL_166_DATA */ + 0x00000000, /* DENALI_CTL_167_DATA */ + 0x00000000, /* DENALI_CTL_168_DATA */ + 0x00000000, /* DENALI_CTL_169_DATA */ + 0x00000000, /* DENALI_CTL_170_DATA */ + 0x00000000, /* DENALI_CTL_171_DATA */ + 0x00000000, /* DENALI_CTL_172_DATA */ + 0x00000000, /* DENALI_CTL_173_DATA */ + 0x00000000, /* DENALI_CTL_174_DATA */ + 0x00000000, /* DENALI_CTL_175_DATA */ + 0x00000000, /* DENALI_CTL_176_DATA */ + 0x00000000, /* DENALI_CTL_177_DATA */ + 0x00000000, /* DENALI_CTL_178_DATA */ + 0x00020003, /* DENALI_CTL_179_DATA */ + 0x00400100, /* DENALI_CTL_180_DATA */ + 0x000c0190, /* DENALI_CTL_181_DATA */ + 0x01000200, /* DENALI_CTL_182_DATA */ + 0x03200040, /* DENALI_CTL_183_DATA */ + 0x00020018, /* DENALI_CTL_184_DATA */ + 0x00400100, /* DENALI_CTL_185_DATA */ + 0x00080032, /* DENALI_CTL_186_DATA */ + 0x00140000, /* DENALI_CTL_187_DATA */ + 0x00030028, /* DENALI_CTL_188_DATA */ + 0x01010100, /* DENALI_CTL_189_DATA */ + 0x02000202, /* DENALI_CTL_190_DATA */ + 0x0b000002, /* DENALI_CTL_191_DATA */ + 0x01000f0f, /* DENALI_CTL_192_DATA */ + 0x00000000, /* DENALI_CTL_193_DATA */ + 0x00000000, /* DENALI_CTL_194_DATA */ + 0x00010003, /* DENALI_CTL_195_DATA */ + 0x00000c03, /* DENALI_CTL_196_DATA */ + 0x00040101, /* DENALI_CTL_197_DATA */ + 0x04010100, /* DENALI_CTL_198_DATA */ + 0x01000000, /* DENALI_CTL_199_DATA */ + 0x02010000, /* DENALI_CTL_200_DATA */ + 0x00000001, /* DENALI_CTL_201_DATA */ + 0x00000000, /* DENALI_CTL_202_DATA */ + 0x00000000, /* DENALI_CTL_203_DATA */ + 0x00000000, /* DENALI_CTL_204_DATA */ + 0x00000000, /* DENALI_CTL_205_DATA */ + 0x00000000, /* DENALI_CTL_206_DATA */ + 0x00000000, /* DENALI_CTL_207_DATA */ + 0x00000000, /* DENALI_CTL_208_DATA */ + 0x00000000, /* DENALI_CTL_209_DATA */ + 0x00000000, /* DENALI_CTL_210_DATA */ + 0x00010000, /* DENALI_CTL_211_DATA */ + 0x00000001, /* DENALI_CTL_212_DATA */ + 0x01010001, /* DENALI_CTL_213_DATA */ + 0x05040001, /* DENALI_CTL_214_DATA */ + 0x040a0703, /* DENALI_CTL_215_DATA */ + 0x02080808, /* DENALI_CTL_216_DATA */ + 0x020e000a, /* DENALI_CTL_217_DATA */ + 0x020f010b, /* DENALI_CTL_218_DATA */ + 0x000d0008, /* DENALI_CTL_219_DATA */ + 0x00080b0a, /* DENALI_CTL_220_DATA */ + 0x03000200, /* DENALI_CTL_221_DATA */ + 0x00000100, /* DENALI_CTL_222_DATA */ + 0x00000000, /* DENALI_CTL_223_DATA */ + 0x00000000, /* DENALI_CTL_224_DATA */ + 0x0d000001, /* DENALI_CTL_225_DATA */ + 0x00000028, /* DENALI_CTL_226_DATA */ + 0x00010000, /* DENALI_CTL_227_DATA */ + 0x00000003, /* DENALI_CTL_228_DATA */ + 0x00000000, /* DENALI_CTL_229_DATA */ + 0x00000000, /* DENALI_CTL_230_DATA */ + 0x00000000, /* DENALI_CTL_231_DATA */ + 0x00000000, /* DENALI_CTL_232_DATA */ + 0x00000000, /* DENALI_CTL_233_DATA */ + 0x00000000, /* DENALI_CTL_234_DATA */ + 0x00000000, /* DENALI_CTL_235_DATA */ + 0x00000000, /* DENALI_CTL_236_DATA */ + 0x00010100, /* DENALI_CTL_237_DATA */ + 0x01000000, /* DENALI_CTL_238_DATA */ + 0x00000001, /* DENALI_CTL_239_DATA */ + 0x00000303, /* DENALI_CTL_240_DATA */ + 0x00000000, /* DENALI_CTL_241_DATA */ + 0x00000000, /* DENALI_CTL_242_DATA */ + 0x00000000, /* DENALI_CTL_243_DATA */ + 0x00000000, /* DENALI_CTL_244_DATA */ + 0x00000000, /* DENALI_CTL_245_DATA */ + 0x00000000, /* DENALI_CTL_246_DATA */ + 0x00000000, /* DENALI_CTL_247_DATA */ + 0x00000000, /* DENALI_CTL_248_DATA */ + 0x00000000, /* DENALI_CTL_249_DATA */ + 0x00000000, /* DENALI_CTL_250_DATA */ + 0x00000000, /* DENALI_CTL_251_DATA */ + 0x00000000, /* DENALI_CTL_252_DATA */ + 0x00000000, /* DENALI_CTL_253_DATA */ + 0x00000000, /* DENALI_CTL_254_DATA */ + 0x00000000, /* DENALI_CTL_255_DATA */ + 0x000556aa, /* DENALI_CTL_256_DATA */ + 0x000aaaaa, /* DENALI_CTL_257_DATA */ + 0x000aa955, /* DENALI_CTL_258_DATA */ + 0x00055555, /* DENALI_CTL_259_DATA */ + 0x000b3133, /* DENALI_CTL_260_DATA */ + 0x0004cd33, /* DENALI_CTL_261_DATA */ + 0x0004cecc, /* DENALI_CTL_262_DATA */ + 0x000b32cc, /* DENALI_CTL_263_DATA */ + 0x00010300, /* DENALI_CTL_264_DATA */ + 0x03000100, /* DENALI_CTL_265_DATA */ + 0x00000000, /* DENALI_CTL_266_DATA */ + 0x00000000, /* DENALI_CTL_267_DATA */ + 0x00000000, /* DENALI_CTL_268_DATA */ + 0x00000000, /* DENALI_CTL_269_DATA */ + 0x00000000, /* DENALI_CTL_270_DATA */ + 0x00000000, /* DENALI_CTL_271_DATA */ + 0x00000000, /* DENALI_CTL_272_DATA */ + 0x00000000, /* DENALI_CTL_273_DATA */ + 0x00ffff00, /* DENALI_CTL_274_DATA */ + 0x1a160000, /* DENALI_CTL_275_DATA */ + 0x08000012, /* DENALI_CTL_276_DATA */ + 0x00000c20, /* DENALI_CTL_277_DATA */ + 0x00000200, /* DENALI_CTL_278_DATA */ + 0x00000200, /* DENALI_CTL_279_DATA */ + 0x00000200, /* DENALI_CTL_280_DATA */ + 0x00000200, /* DENALI_CTL_281_DATA */ + 0x00000c20, /* DENALI_CTL_282_DATA */ + 0x00007940, /* DENALI_CTL_283_DATA */ + 0x18500409, /* DENALI_CTL_284_DATA */ + 0x00000200, /* DENALI_CTL_285_DATA */ + 0x00000200, /* DENALI_CTL_286_DATA */ + 0x00000200, /* DENALI_CTL_287_DATA */ + 0x00000200, /* DENALI_CTL_288_DATA */ + 0x00001850, /* DENALI_CTL_289_DATA */ + 0x0000f320, /* DENALI_CTL_290_DATA */ + 0x0176060c, /* DENALI_CTL_291_DATA */ + 0x00000200, /* DENALI_CTL_292_DATA */ + 0x00000200, /* DENALI_CTL_293_DATA */ + 0x00000200, /* DENALI_CTL_294_DATA */ + 0x00000200, /* DENALI_CTL_295_DATA */ + 0x00000176, /* DENALI_CTL_296_DATA */ + 0x00000e9c, /* DENALI_CTL_297_DATA */ + 0x02020205, /* DENALI_CTL_298_DATA */ + 0x03030202, /* DENALI_CTL_299_DATA */ + 0x00000018, /* DENALI_CTL_300_DATA */ + 0x00000000, /* DENALI_CTL_301_DATA */ + 0x00000000, /* DENALI_CTL_302_DATA */ + 0x00001403, /* DENALI_CTL_303_DATA */ + 0x00000000, /* DENALI_CTL_304_DATA */ + 0x00000000, /* DENALI_CTL_305_DATA */ + 0x00000000, /* DENALI_CTL_306_DATA */ + 0x00030000, /* DENALI_CTL_307_DATA */ + 0x000a001c, /* DENALI_CTL_308_DATA */ + 0x000e0020, /* DENALI_CTL_309_DATA */ + 0x00060018, /* DENALI_CTL_310_DATA */ + 0x00000000, /* DENALI_CTL_311_DATA */ + 0x00000000, /* DENALI_CTL_312_DATA */ + 0x02000000, /* DENALI_CTL_313_DATA */ + 0x00090305, /* DENALI_CTL_314_DATA */ + 0x00050101, /* DENALI_CTL_315_DATA */ + 0x00000000, /* DENALI_CTL_316_DATA */ + 0x00000000, /* DENALI_CTL_317_DATA */ + 0x00000000, /* DENALI_CTL_318_DATA */ + 0x00000000, /* DENALI_CTL_319_DATA */ + 0x00000000, /* DENALI_CTL_320_DATA */ + 0x00000000, /* DENALI_CTL_321_DATA */ + 0x00000000, /* DENALI_CTL_322_DATA */ + 0x00000000, /* DENALI_CTL_323_DATA */ + 0x01000001, /* DENALI_CTL_324_DATA */ + 0x01010101, /* DENALI_CTL_325_DATA */ + 0x01000101, /* DENALI_CTL_326_DATA */ + 0x01000100, /* DENALI_CTL_327_DATA */ + 0x00010001, /* DENALI_CTL_328_DATA */ + 0x00010002, /* DENALI_CTL_329_DATA */ + 0x00020100, /* DENALI_CTL_330_DATA */ + 0x00000002 /* DENALI_CTL_331_DATA */ + } + }, + { + { + 0x00000b00, /* DENALI_PI_00_DATA */ + 0x00000000, /* DENALI_PI_01_DATA */ + 0x000002ec, /* DENALI_PI_02_DATA */ + 0x00000176, /* DENALI_PI_03_DATA */ + 0x000030a0, /* DENALI_PI_04_DATA */ + 0x00001850, /* DENALI_PI_05_DATA */ + 0x00001840, /* DENALI_PI_06_DATA */ + 0x01760c20, /* DENALI_PI_07_DATA */ + 0x00000200, /* DENALI_PI_08_DATA */ + 0x00000200, /* DENALI_PI_09_DATA */ + 0x00000200, /* DENALI_PI_10_DATA */ + 0x00000200, /* DENALI_PI_11_DATA */ + 0x00001850, /* DENALI_PI_12_DATA */ + 0x00000200, /* DENALI_PI_13_DATA */ + 0x00000200, /* DENALI_PI_14_DATA */ + 0x00000200, /* DENALI_PI_15_DATA */ + 0x00000200, /* DENALI_PI_16_DATA */ + 0x00000c20, /* DENALI_PI_17_DATA */ + 0x00000200, /* DENALI_PI_18_DATA */ + 0x00000200, /* DENALI_PI_19_DATA */ + 0x00000200, /* DENALI_PI_20_DATA */ + 0x00000200, /* DENALI_PI_21_DATA */ + 0x00010000, /* DENALI_PI_22_DATA */ + 0x00000007, /* DENALI_PI_23_DATA */ + 0x01000001, /* DENALI_PI_24_DATA */ + 0x00000000, /* DENALI_PI_25_DATA */ + 0x3fffffff, /* DENALI_PI_26_DATA */ + 0x00000000, /* DENALI_PI_27_DATA */ + 0x00000000, /* DENALI_PI_28_DATA */ + 0x00000000, /* DENALI_PI_29_DATA */ + 0x00000000, /* DENALI_PI_30_DATA */ + 0x00000000, /* DENALI_PI_31_DATA */ + 0x00000000, /* DENALI_PI_32_DATA */ + 0x00000000, /* DENALI_PI_33_DATA */ + 0x00000000, /* DENALI_PI_34_DATA */ + 0x00000000, /* DENALI_PI_35_DATA */ + 0x00000000, /* DENALI_PI_36_DATA */ + 0x00000000, /* DENALI_PI_37_DATA */ + 0x00000000, /* DENALI_PI_38_DATA */ + 0x00000000, /* DENALI_PI_39_DATA */ + 0x00000000, /* DENALI_PI_40_DATA */ + 0x0f000101, /* DENALI_PI_41_DATA */ + 0x082b3223, /* DENALI_PI_42_DATA */ + 0x080c0004, /* DENALI_PI_43_DATA */ + 0x00061c00, /* DENALI_PI_44_DATA */ + 0x00000214, /* DENALI_PI_45_DATA */ + 0x00bb0007, /* DENALI_PI_46_DATA */ + 0x0c280068, /* DENALI_PI_47_DATA */ + 0x06100034, /* DENALI_PI_48_DATA */ + 0x00000500, /* DENALI_PI_49_DATA */ + 0x00000000, /* DENALI_PI_50_DATA */ + 0x00000000, /* DENALI_PI_51_DATA */ + 0x00000000, /* DENALI_PI_52_DATA */ + 0x00000000, /* DENALI_PI_53_DATA */ + 0x00000000, /* DENALI_PI_54_DATA */ + 0x00000000, /* DENALI_PI_55_DATA */ + 0x00000000, /* DENALI_PI_56_DATA */ + 0x00000000, /* DENALI_PI_57_DATA */ + 0x04040100, /* DENALI_PI_58_DATA */ + 0x0a000004, /* DENALI_PI_59_DATA */ + 0x00000128, /* DENALI_PI_60_DATA */ + 0x00000000, /* DENALI_PI_61_DATA */ + 0x0003000f, /* DENALI_PI_62_DATA */ + 0x00000018, /* DENALI_PI_63_DATA */ + 0x00000000, /* DENALI_PI_64_DATA */ + 0x00000000, /* DENALI_PI_65_DATA */ + 0x00060002, /* DENALI_PI_66_DATA */ + 0x00010001, /* DENALI_PI_67_DATA */ + 0x00000101, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ + 0x00000000, /* DENALI_PI_71_DATA */ + 0x05030000, /* DENALI_PI_72_DATA */ + 0x070a0404, /* DENALI_PI_73_DATA */ + 0x00000000, /* DENALI_PI_74_DATA */ + 0x00000000, /* DENALI_PI_75_DATA */ + 0x00000000, /* DENALI_PI_76_DATA */ + 0x000f0f00, /* DENALI_PI_77_DATA */ + 0x0000001e, /* DENALI_PI_78_DATA */ + 0x00000000, /* DENALI_PI_79_DATA */ + 0x01010300, /* DENALI_PI_80_DATA */ + 0x00000000, /* DENALI_PI_81_DATA */ + 0x00000000, /* DENALI_PI_82_DATA */ + 0x01000000, /* DENALI_PI_83_DATA */ + 0x00000101, /* DENALI_PI_84_DATA */ + 0x55555a5a, /* DENALI_PI_85_DATA */ + 0x55555a5a, /* DENALI_PI_86_DATA */ + 0x55555a5a, /* DENALI_PI_87_DATA */ + 0x55555a5a, /* DENALI_PI_88_DATA */ + 0x0c050001, /* DENALI_PI_89_DATA */ + 0x06020009, /* DENALI_PI_90_DATA */ + 0x00010004, /* DENALI_PI_91_DATA */ + 0x00000203, /* DENALI_PI_92_DATA */ + 0x00030000, /* DENALI_PI_93_DATA */ + 0x170f0000, /* DENALI_PI_94_DATA */ + 0x00060018, /* DENALI_PI_95_DATA */ + 0x000e0020, /* DENALI_PI_96_DATA */ + 0x000a001c, /* DENALI_PI_97_DATA */ + 0x00000000, /* DENALI_PI_98_DATA */ + 0x00000000, /* DENALI_PI_99_DATA */ + 0x00000100, /* DENALI_PI_100_DATA */ + 0x140a0000, /* DENALI_PI_101_DATA */ + 0x000d010a, /* DENALI_PI_102_DATA */ + 0x0100c802, /* DENALI_PI_103_DATA */ + 0x010a0064, /* DENALI_PI_104_DATA */ + 0x000e0100, /* DENALI_PI_105_DATA */ + 0x0100000e, /* DENALI_PI_106_DATA */ + 0x00c900c9, /* DENALI_PI_107_DATA */ + 0x00650100, /* DENALI_PI_108_DATA */ + 0x1e1a0065, /* DENALI_PI_109_DATA */ + 0x10010204, /* DENALI_PI_110_DATA */ + 0x06070605, /* DENALI_PI_111_DATA */ + 0x20000202, /* DENALI_PI_112_DATA */ + 0x00201000, /* DENALI_PI_113_DATA */ + 0x00201000, /* DENALI_PI_114_DATA */ + 0x04041000, /* DENALI_PI_115_DATA */ + 0x10020100, /* DENALI_PI_116_DATA */ + 0x0003010c, /* DENALI_PI_117_DATA */ + 0x004b004a, /* DENALI_PI_118_DATA */ + 0x1a0f0000, /* DENALI_PI_119_DATA */ + 0x0102041e, /* DENALI_PI_120_DATA */ + 0x34000000, /* DENALI_PI_121_DATA */ + 0x00000000, /* DENALI_PI_122_DATA */ + 0x00000000, /* DENALI_PI_123_DATA */ + 0x00010000, /* DENALI_PI_124_DATA */ + 0x00000400, /* DENALI_PI_125_DATA */ + 0x00310000, /* DENALI_PI_126_DATA */ + 0x004d4d00, /* DENALI_PI_127_DATA */ + 0x00120024, /* DENALI_PI_128_DATA */ + 0x4d000031, /* DENALI_PI_129_DATA */ + 0x0000144d, /* DENALI_PI_130_DATA */ + 0x00310009, /* DENALI_PI_131_DATA */ + 0x004d4d00, /* DENALI_PI_132_DATA */ + 0x00000004, /* DENALI_PI_133_DATA */ + 0x4d000031, /* DENALI_PI_134_DATA */ + 0x0000244d, /* DENALI_PI_135_DATA */ + 0x00310012, /* DENALI_PI_136_DATA */ + 0x004d4d00, /* DENALI_PI_137_DATA */ + 0x00090014, /* DENALI_PI_138_DATA */ + 0x4d000031, /* DENALI_PI_139_DATA */ + 0x0004004d, /* DENALI_PI_140_DATA */ + 0x00310000, /* DENALI_PI_141_DATA */ + 0x004d4d00, /* DENALI_PI_142_DATA */ + 0x00120024, /* DENALI_PI_143_DATA */ + 0x4d000031, /* DENALI_PI_144_DATA */ + 0x0000144d, /* DENALI_PI_145_DATA */ + 0x00310009, /* DENALI_PI_146_DATA */ + 0x004d4d00, /* DENALI_PI_147_DATA */ + 0x00000004, /* DENALI_PI_148_DATA */ + 0x4d000031, /* DENALI_PI_149_DATA */ + 0x0000244d, /* DENALI_PI_150_DATA */ + 0x00310012, /* DENALI_PI_151_DATA */ + 0x004d4d00, /* DENALI_PI_152_DATA */ + 0x00090014, /* DENALI_PI_153_DATA */ + 0x4d000031, /* DENALI_PI_154_DATA */ + 0x0200004d, /* DENALI_PI_155_DATA */ + 0x00c8000d, /* DENALI_PI_156_DATA */ + 0x08080064, /* DENALI_PI_157_DATA */ + 0x040a0404, /* DENALI_PI_158_DATA */ + 0x03000d92, /* DENALI_PI_159_DATA */ + 0x010a2001, /* DENALI_PI_160_DATA */ + 0x0f11080a, /* DENALI_PI_161_DATA */ + 0x0000110a, /* DENALI_PI_162_DATA */ + 0x2200d92e, /* DENALI_PI_163_DATA */ + 0x080c2003, /* DENALI_PI_164_DATA */ + 0x0809080a, /* DENALI_PI_165_DATA */ + 0x00000a0a, /* DENALI_PI_166_DATA */ + 0x11006c97, /* DENALI_PI_167_DATA */ + 0x040a2002, /* DENALI_PI_168_DATA */ + 0x0200020a, /* DENALI_PI_169_DATA */ + 0x02000200, /* DENALI_PI_170_DATA */ + 0x02000200, /* DENALI_PI_171_DATA */ + 0x02000200, /* DENALI_PI_172_DATA */ + 0x02000200, /* DENALI_PI_173_DATA */ + 0x00000000, /* DENALI_PI_174_DATA */ + 0x00000000, /* DENALI_PI_175_DATA */ + 0x00000000, /* DENALI_PI_176_DATA */ + 0x00000000, /* DENALI_PI_177_DATA */ + 0x00000000, /* DENALI_PI_178_DATA */ + 0x00000000, /* DENALI_PI_179_DATA */ + 0x00000000, /* DENALI_PI_180_DATA */ + 0x00000000, /* DENALI_PI_181_DATA */ + 0x00000000, /* DENALI_PI_182_DATA */ + 0x00000000, /* DENALI_PI_183_DATA */ + 0x00000000, /* DENALI_PI_184_DATA */ + 0x00000000, /* DENALI_PI_185_DATA */ + 0x01000400, /* DENALI_PI_186_DATA */ + 0x00017600, /* DENALI_PI_187_DATA */ + 0x00000e9c, /* DENALI_PI_188_DATA */ + 0x00001850, /* DENALI_PI_189_DATA */ + 0x0000f320, /* DENALI_PI_190_DATA */ + 0x00000c20, /* DENALI_PI_191_DATA */ + 0x00007940, /* DENALI_PI_192_DATA */ + 0x08000000, /* DENALI_PI_193_DATA */ + 0x00000100, /* DENALI_PI_194_DATA */ + 0x00000000, /* DENALI_PI_195_DATA */ + 0x00000000, /* DENALI_PI_196_DATA */ + 0x00000000, /* DENALI_PI_197_DATA */ + 0x00000000, /* DENALI_PI_198_DATA */ + 0x00000002 /* DENALI_PI_199_DATA */ + } + }, + { + { + 0x76543210, /* DENALI_PHY_00_DATA */ + 0x0004f008, /* DENALI_PHY_01_DATA */ + 0x00020119, /* DENALI_PHY_02_DATA */ + 0x00000000, /* DENALI_PHY_03_DATA */ + 0x00000000, /* DENALI_PHY_04_DATA */ + 0x00010000, /* DENALI_PHY_05_DATA */ + 0x01665555, /* DENALI_PHY_06_DATA */ + 0x03665555, /* DENALI_PHY_07_DATA */ + 0x00010f00, /* DENALI_PHY_08_DATA */ + 0x05010200, /* DENALI_PHY_09_DATA */ + 0x00000002, /* DENALI_PHY_10_DATA */ + 0x00170180, /* DENALI_PHY_11_DATA */ + 0x00cc0201, /* DENALI_PHY_12_DATA */ + 0x00030066, /* DENALI_PHY_13_DATA */ + 0x00000000, /* DENALI_PHY_14_DATA */ + 0x00000000, /* DENALI_PHY_15_DATA */ + 0x00000000, /* DENALI_PHY_16_DATA */ + 0x00000000, /* DENALI_PHY_17_DATA */ + 0x00000000, /* DENALI_PHY_18_DATA */ + 0x00000000, /* DENALI_PHY_19_DATA */ + 0x00000000, /* DENALI_PHY_20_DATA */ + 0x00000000, /* DENALI_PHY_21_DATA */ + 0x04080000, /* DENALI_PHY_22_DATA */ + 0x04080400, /* DENALI_PHY_23_DATA */ + 0x30000000, /* DENALI_PHY_24_DATA */ + 0x0c00c007, /* DENALI_PHY_25_DATA */ + 0x00000100, /* DENALI_PHY_26_DATA */ + 0x00000000, /* DENALI_PHY_27_DATA */ + 0xfd02fe01, /* DENALI_PHY_28_DATA */ + 0xf708fb04, /* DENALI_PHY_29_DATA */ + 0xdf20ef10, /* DENALI_PHY_30_DATA */ + 0x7f80bf40, /* DENALI_PHY_31_DATA */ + 0x0001aaaa, /* DENALI_PHY_32_DATA */ + 0x00000000, /* DENALI_PHY_33_DATA */ + 0x00000000, /* DENALI_PHY_34_DATA */ + 0x00000000, /* DENALI_PHY_35_DATA */ + 0x00000000, /* DENALI_PHY_36_DATA */ + 0x00000000, /* DENALI_PHY_37_DATA */ + 0x00000000, /* DENALI_PHY_38_DATA */ + 0x00000000, /* DENALI_PHY_39_DATA */ + 0x00000000, /* DENALI_PHY_40_DATA */ + 0x00000000, /* DENALI_PHY_41_DATA */ + 0x00000000, /* DENALI_PHY_42_DATA */ + 0x00000000, /* DENALI_PHY_43_DATA */ + 0x00000000, /* DENALI_PHY_44_DATA */ + 0x00000000, /* DENALI_PHY_45_DATA */ + 0x00000000, /* DENALI_PHY_46_DATA */ + 0x00000000, /* DENALI_PHY_47_DATA */ + 0x00000000, /* DENALI_PHY_48_DATA */ + 0x00000000, /* DENALI_PHY_49_DATA */ + 0x00000000, /* DENALI_PHY_50_DATA */ + 0x00000000, /* DENALI_PHY_51_DATA */ + 0x00200000, /* DENALI_PHY_52_DATA */ + 0x00000000, /* DENALI_PHY_53_DATA */ + 0x00000000, /* DENALI_PHY_54_DATA */ + 0x00000000, /* DENALI_PHY_55_DATA */ + 0x00000000, /* DENALI_PHY_56_DATA */ + 0x00000000, /* DENALI_PHY_57_DATA */ + 0x00000000, /* DENALI_PHY_58_DATA */ + 0x02800280, /* DENALI_PHY_59_DATA */ + 0x02800280, /* DENALI_PHY_60_DATA */ + 0x02800280, /* DENALI_PHY_61_DATA */ + 0x02800280, /* DENALI_PHY_62_DATA */ + 0x00000280, /* DENALI_PHY_63_DATA */ + 0x00000000, /* DENALI_PHY_64_DATA */ + 0x00000000, /* DENALI_PHY_65_DATA */ + 0x00000000, /* DENALI_PHY_66_DATA */ + 0x00000000, /* DENALI_PHY_67_DATA */ + 0x00800000, /* DENALI_PHY_68_DATA */ + 0x00800080, /* DENALI_PHY_69_DATA */ + 0x00800080, /* DENALI_PHY_70_DATA */ + 0x00800080, /* DENALI_PHY_71_DATA */ + 0x00800080, /* DENALI_PHY_72_DATA */ + 0x00800080, /* DENALI_PHY_73_DATA */ + 0x00800080, /* DENALI_PHY_74_DATA */ + 0x00800080, /* DENALI_PHY_75_DATA */ + 0x00800080, /* DENALI_PHY_76_DATA */ + 0x01190080, /* DENALI_PHY_77_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ + 0x00000000, /* DENALI_PHY_79_DATA */ + 0x00000000, /* DENALI_PHY_80_DATA */ + 0x00000200, /* DENALI_PHY_81_DATA */ + 0x00000000, /* DENALI_PHY_82_DATA */ + 0x51315152, /* DENALI_PHY_83_DATA */ + 0xc0013150, /* DENALI_PHY_84_DATA */ + 0x020000c0, /* DENALI_PHY_85_DATA */ + 0x00100001, /* DENALI_PHY_86_DATA */ + 0x07054204, /* DENALI_PHY_87_DATA */ + 0x000f0c18, /* DENALI_PHY_88_DATA */ + 0x01000140, /* DENALI_PHY_89_DATA */ + 0x00000c10, /* DENALI_PHY_90_DATA */ + 0x00000000, /* DENALI_PHY_91_DATA */ + 0x00000000, /* DENALI_PHY_92_DATA */ + 0x00000000, /* DENALI_PHY_93_DATA */ + 0x00000000, /* DENALI_PHY_94_DATA */ + 0x00000000, /* DENALI_PHY_95_DATA */ + 0x00000000, /* DENALI_PHY_96_DATA */ + 0x00000000, /* DENALI_PHY_97_DATA */ + 0x00000000, /* DENALI_PHY_98_DATA */ + 0x00000000, /* DENALI_PHY_99_DATA */ + 0x00000000, /* DENALI_PHY_100_DATA */ + 0x00000000, /* DENALI_PHY_101_DATA */ + 0x00000000, /* DENALI_PHY_102_DATA */ + 0x00000000, /* DENALI_PHY_103_DATA */ + 0x00000000, /* DENALI_PHY_104_DATA */ + 0x00000000, /* DENALI_PHY_105_DATA */ + 0x00000000, /* DENALI_PHY_106_DATA */ + 0x00000000, /* DENALI_PHY_107_DATA */ + 0x00000000, /* DENALI_PHY_108_DATA */ + 0x00000000, /* DENALI_PHY_109_DATA */ + 0x00000000, /* DENALI_PHY_110_DATA */ + 0x00000000, /* DENALI_PHY_111_DATA */ + 0x00000000, /* DENALI_PHY_112_DATA */ + 0x00000000, /* DENALI_PHY_113_DATA */ + 0x00000000, /* DENALI_PHY_114_DATA */ + 0x00000000, /* DENALI_PHY_115_DATA */ + 0x00000000, /* DENALI_PHY_116_DATA */ + 0x00000000, /* DENALI_PHY_117_DATA */ + 0x00000000, /* DENALI_PHY_118_DATA */ + 0x00000000, /* DENALI_PHY_119_DATA */ + 0x00000000, /* DENALI_PHY_120_DATA */ + 0x00000000, /* DENALI_PHY_121_DATA */ + 0x00000000, /* DENALI_PHY_122_DATA */ + 0x00000000, /* DENALI_PHY_123_DATA */ + 0x00000000, /* DENALI_PHY_124_DATA */ + 0x00000000, /* DENALI_PHY_125_DATA */ + 0x00000000, /* DENALI_PHY_126_DATA */ + 0x00000000, /* DENALI_PHY_127_DATA */ + 0x76543210, /* DENALI_PHY_128_DATA */ + 0x0004f008, /* DENALI_PHY_129_DATA */ + 0x00020119, /* DENALI_PHY_130_DATA */ + 0x00000000, /* DENALI_PHY_131_DATA */ + 0x00000000, /* DENALI_PHY_132_DATA */ + 0x00010000, /* DENALI_PHY_133_DATA */ + 0x01665555, /* DENALI_PHY_134_DATA */ + 0x03665555, /* DENALI_PHY_135_DATA */ + 0x00010f00, /* DENALI_PHY_136_DATA */ + 0x05010200, /* DENALI_PHY_137_DATA */ + 0x00000002, /* DENALI_PHY_138_DATA */ + 0x00170180, /* DENALI_PHY_139_DATA */ + 0x00cc0201, /* DENALI_PHY_140_DATA */ + 0x00030066, /* DENALI_PHY_141_DATA */ + 0x00000000, /* DENALI_PHY_142_DATA */ + 0x00000000, /* DENALI_PHY_143_DATA */ + 0x00000000, /* DENALI_PHY_144_DATA */ + 0x00000000, /* DENALI_PHY_145_DATA */ + 0x00000000, /* DENALI_PHY_146_DATA */ + 0x00000000, /* DENALI_PHY_147_DATA */ + 0x00000000, /* DENALI_PHY_148_DATA */ + 0x00000000, /* DENALI_PHY_149_DATA */ + 0x04080000, /* DENALI_PHY_150_DATA */ + 0x04080400, /* DENALI_PHY_151_DATA */ + 0x30000000, /* DENALI_PHY_152_DATA */ + 0x0c00c007, /* DENALI_PHY_153_DATA */ + 0x00000100, /* DENALI_PHY_154_DATA */ + 0x00000000, /* DENALI_PHY_155_DATA */ + 0xfd02fe01, /* DENALI_PHY_156_DATA */ + 0xf708fb04, /* DENALI_PHY_157_DATA */ + 0xdf20ef10, /* DENALI_PHY_158_DATA */ + 0x7f80bf40, /* DENALI_PHY_159_DATA */ + 0x0000aaaa, /* DENALI_PHY_160_DATA */ + 0x00000000, /* DENALI_PHY_161_DATA */ + 0x00000000, /* DENALI_PHY_162_DATA */ + 0x00000000, /* DENALI_PHY_163_DATA */ + 0x00000000, /* DENALI_PHY_164_DATA */ + 0x00000000, /* DENALI_PHY_165_DATA */ + 0x00000000, /* DENALI_PHY_166_DATA */ + 0x00000000, /* DENALI_PHY_167_DATA */ + 0x00000000, /* DENALI_PHY_168_DATA */ + 0x00000000, /* DENALI_PHY_169_DATA */ + 0x00000000, /* DENALI_PHY_170_DATA */ + 0x00000000, /* DENALI_PHY_171_DATA */ + 0x00000000, /* DENALI_PHY_172_DATA */ + 0x00000000, /* DENALI_PHY_173_DATA */ + 0x00000000, /* DENALI_PHY_174_DATA */ + 0x00000000, /* DENALI_PHY_175_DATA */ + 0x00000000, /* DENALI_PHY_176_DATA */ + 0x00000000, /* DENALI_PHY_177_DATA */ + 0x00000000, /* DENALI_PHY_178_DATA */ + 0x00000000, /* DENALI_PHY_179_DATA */ + 0x00200000, /* DENALI_PHY_180_DATA */ + 0x00000000, /* DENALI_PHY_181_DATA */ + 0x00000000, /* DENALI_PHY_182_DATA */ + 0x00000000, /* DENALI_PHY_183_DATA */ + 0x00000000, /* DENALI_PHY_184_DATA */ + 0x00000000, /* DENALI_PHY_185_DATA */ + 0x00000000, /* DENALI_PHY_186_DATA */ + 0x02800280, /* DENALI_PHY_187_DATA */ + 0x02800280, /* DENALI_PHY_188_DATA */ + 0x02800280, /* DENALI_PHY_189_DATA */ + 0x02800280, /* DENALI_PHY_190_DATA */ + 0x00000280, /* DENALI_PHY_191_DATA */ + 0x00000000, /* DENALI_PHY_192_DATA */ + 0x00000000, /* DENALI_PHY_193_DATA */ + 0x00000000, /* DENALI_PHY_194_DATA */ + 0x00000000, /* DENALI_PHY_195_DATA */ + 0x00800000, /* DENALI_PHY_196_DATA */ + 0x00800080, /* DENALI_PHY_197_DATA */ + 0x00800080, /* DENALI_PHY_198_DATA */ + 0x00800080, /* DENALI_PHY_199_DATA */ + 0x00800080, /* DENALI_PHY_200_DATA */ + 0x00800080, /* DENALI_PHY_201_DATA */ + 0x00800080, /* DENALI_PHY_202_DATA */ + 0x00800080, /* DENALI_PHY_203_DATA */ + 0x00800080, /* DENALI_PHY_204_DATA */ + 0x01190080, /* DENALI_PHY_205_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ + 0x00000000, /* DENALI_PHY_207_DATA */ + 0x00000000, /* DENALI_PHY_208_DATA */ + 0x00000200, /* DENALI_PHY_209_DATA */ + 0x00000000, /* DENALI_PHY_210_DATA */ + 0x51315152, /* DENALI_PHY_211_DATA */ + 0xc0013150, /* DENALI_PHY_212_DATA */ + 0x020000c0, /* DENALI_PHY_213_DATA */ + 0x00100001, /* DENALI_PHY_214_DATA */ + 0x07054204, /* DENALI_PHY_215_DATA */ + 0x000f0c18, /* DENALI_PHY_216_DATA */ + 0x01000140, /* DENALI_PHY_217_DATA */ + 0x00000c10, /* DENALI_PHY_218_DATA */ + 0x00000000, /* DENALI_PHY_219_DATA */ + 0x00000000, /* DENALI_PHY_220_DATA */ + 0x00000000, /* DENALI_PHY_221_DATA */ + 0x00000000, /* DENALI_PHY_222_DATA */ + 0x00000000, /* DENALI_PHY_223_DATA */ + 0x00000000, /* DENALI_PHY_224_DATA */ + 0x00000000, /* DENALI_PHY_225_DATA */ + 0x00000000, /* DENALI_PHY_226_DATA */ + 0x00000000, /* DENALI_PHY_227_DATA */ + 0x00000000, /* DENALI_PHY_228_DATA */ + 0x00000000, /* DENALI_PHY_229_DATA */ + 0x00000000, /* DENALI_PHY_230_DATA */ + 0x00000000, /* DENALI_PHY_231_DATA */ + 0x00000000, /* DENALI_PHY_232_DATA */ + 0x00000000, /* DENALI_PHY_233_DATA */ + 0x00000000, /* DENALI_PHY_234_DATA */ + 0x00000000, /* DENALI_PHY_235_DATA */ + 0x00000000, /* DENALI_PHY_236_DATA */ + 0x00000000, /* DENALI_PHY_237_DATA */ + 0x00000000, /* DENALI_PHY_238_DATA */ + 0x00000000, /* DENALI_PHY_239_DATA */ + 0x00000000, /* DENALI_PHY_240_DATA */ + 0x00000000, /* DENALI_PHY_241_DATA */ + 0x00000000, /* DENALI_PHY_242_DATA */ + 0x00000000, /* DENALI_PHY_243_DATA */ + 0x00000000, /* DENALI_PHY_244_DATA */ + 0x00000000, /* DENALI_PHY_245_DATA */ + 0x00000000, /* DENALI_PHY_246_DATA */ + 0x00000000, /* DENALI_PHY_247_DATA */ + 0x00000000, /* DENALI_PHY_248_DATA */ + 0x00000000, /* DENALI_PHY_249_DATA */ + 0x00000000, /* DENALI_PHY_250_DATA */ + 0x00000000, /* DENALI_PHY_251_DATA */ + 0x00000000, /* DENALI_PHY_252_DATA */ + 0x00000000, /* DENALI_PHY_253_DATA */ + 0x00000000, /* DENALI_PHY_254_DATA */ + 0x00000000, /* DENALI_PHY_255_DATA */ + 0x76543210, /* DENALI_PHY_256_DATA */ + 0x0004f008, /* DENALI_PHY_257_DATA */ + 0x00020119, /* DENALI_PHY_258_DATA */ + 0x00000000, /* DENALI_PHY_259_DATA */ + 0x00000000, /* DENALI_PHY_260_DATA */ + 0x00010000, /* DENALI_PHY_261_DATA */ + 0x01665555, /* DENALI_PHY_262_DATA */ + 0x03665555, /* DENALI_PHY_263_DATA */ + 0x00010f00, /* DENALI_PHY_264_DATA */ + 0x05010200, /* DENALI_PHY_265_DATA */ + 0x00000002, /* DENALI_PHY_266_DATA */ + 0x00170180, /* DENALI_PHY_267_DATA */ + 0x00cc0201, /* DENALI_PHY_268_DATA */ + 0x00030066, /* DENALI_PHY_269_DATA */ + 0x00000000, /* DENALI_PHY_270_DATA */ + 0x00000000, /* DENALI_PHY_271_DATA */ + 0x00000000, /* DENALI_PHY_272_DATA */ + 0x00000000, /* DENALI_PHY_273_DATA */ + 0x00000000, /* DENALI_PHY_274_DATA */ + 0x00000000, /* DENALI_PHY_275_DATA */ + 0x00000000, /* DENALI_PHY_276_DATA */ + 0x00000000, /* DENALI_PHY_277_DATA */ + 0x04080000, /* DENALI_PHY_278_DATA */ + 0x04080400, /* DENALI_PHY_279_DATA */ + 0x30000000, /* DENALI_PHY_280_DATA */ + 0x0c00c007, /* DENALI_PHY_281_DATA */ + 0x00000100, /* DENALI_PHY_282_DATA */ + 0x00000000, /* DENALI_PHY_283_DATA */ + 0xfd02fe01, /* DENALI_PHY_284_DATA */ + 0xf708fb04, /* DENALI_PHY_285_DATA */ + 0xdf20ef10, /* DENALI_PHY_286_DATA */ + 0x7f80bf40, /* DENALI_PHY_287_DATA */ + 0x0001aaaa, /* DENALI_PHY_288_DATA */ + 0x00000000, /* DENALI_PHY_289_DATA */ + 0x00000000, /* DENALI_PHY_290_DATA */ + 0x00000000, /* DENALI_PHY_291_DATA */ + 0x00000000, /* DENALI_PHY_292_DATA */ + 0x00000000, /* DENALI_PHY_293_DATA */ + 0x00000000, /* DENALI_PHY_294_DATA */ + 0x00000000, /* DENALI_PHY_295_DATA */ + 0x00000000, /* DENALI_PHY_296_DATA */ + 0x00000000, /* DENALI_PHY_297_DATA */ + 0x00000000, /* DENALI_PHY_298_DATA */ + 0x00000000, /* DENALI_PHY_299_DATA */ + 0x00000000, /* DENALI_PHY_300_DATA */ + 0x00000000, /* DENALI_PHY_301_DATA */ + 0x00000000, /* DENALI_PHY_302_DATA */ + 0x00000000, /* DENALI_PHY_303_DATA */ + 0x00000000, /* DENALI_PHY_304_DATA */ + 0x00000000, /* DENALI_PHY_305_DATA */ + 0x00000000, /* DENALI_PHY_306_DATA */ + 0x00000000, /* DENALI_PHY_307_DATA */ + 0x00200000, /* DENALI_PHY_308_DATA */ + 0x00000000, /* DENALI_PHY_309_DATA */ + 0x00000000, /* DENALI_PHY_310_DATA */ + 0x00000000, /* DENALI_PHY_311_DATA */ + 0x00000000, /* DENALI_PHY_312_DATA */ + 0x00000000, /* DENALI_PHY_313_DATA */ + 0x00000000, /* DENALI_PHY_314_DATA */ + 0x02800280, /* DENALI_PHY_315_DATA */ + 0x02800280, /* DENALI_PHY_316_DATA */ + 0x02800280, /* DENALI_PHY_317_DATA */ + 0x02800280, /* DENALI_PHY_318_DATA */ + 0x00000280, /* DENALI_PHY_319_DATA */ + 0x00000000, /* DENALI_PHY_320_DATA */ + 0x00000000, /* DENALI_PHY_321_DATA */ + 0x00000000, /* DENALI_PHY_322_DATA */ + 0x00000000, /* DENALI_PHY_323_DATA */ + 0x00800000, /* DENALI_PHY_324_DATA */ + 0x00800080, /* DENALI_PHY_325_DATA */ + 0x00800080, /* DENALI_PHY_326_DATA */ + 0x00800080, /* DENALI_PHY_327_DATA */ + 0x00800080, /* DENALI_PHY_328_DATA */ + 0x00800080, /* DENALI_PHY_329_DATA */ + 0x00800080, /* DENALI_PHY_330_DATA */ + 0x00800080, /* DENALI_PHY_331_DATA */ + 0x00800080, /* DENALI_PHY_332_DATA */ + 0x01190080, /* DENALI_PHY_333_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ + 0x00000000, /* DENALI_PHY_335_DATA */ + 0x00000000, /* DENALI_PHY_336_DATA */ + 0x00000200, /* DENALI_PHY_337_DATA */ + 0x00000000, /* DENALI_PHY_338_DATA */ + 0x51315152, /* DENALI_PHY_339_DATA */ + 0xc0013150, /* DENALI_PHY_340_DATA */ + 0x020000c0, /* DENALI_PHY_341_DATA */ + 0x00100001, /* DENALI_PHY_342_DATA */ + 0x07054204, /* DENALI_PHY_343_DATA */ + 0x000f0c18, /* DENALI_PHY_344_DATA */ + 0x01000140, /* DENALI_PHY_345_DATA */ + 0x00000c10, /* DENALI_PHY_346_DATA */ + 0x00000000, /* DENALI_PHY_347_DATA */ + 0x00000000, /* DENALI_PHY_348_DATA */ + 0x00000000, /* DENALI_PHY_349_DATA */ + 0x00000000, /* DENALI_PHY_350_DATA */ + 0x00000000, /* DENALI_PHY_351_DATA */ + 0x00000000, /* DENALI_PHY_352_DATA */ + 0x00000000, /* DENALI_PHY_353_DATA */ + 0x00000000, /* DENALI_PHY_354_DATA */ + 0x00000000, /* DENALI_PHY_355_DATA */ + 0x00000000, /* DENALI_PHY_356_DATA */ + 0x00000000, /* DENALI_PHY_357_DATA */ + 0x00000000, /* DENALI_PHY_358_DATA */ + 0x00000000, /* DENALI_PHY_359_DATA */ + 0x00000000, /* DENALI_PHY_360_DATA */ + 0x00000000, /* DENALI_PHY_361_DATA */ + 0x00000000, /* DENALI_PHY_362_DATA */ + 0x00000000, /* DENALI_PHY_363_DATA */ + 0x00000000, /* DENALI_PHY_364_DATA */ + 0x00000000, /* DENALI_PHY_365_DATA */ + 0x00000000, /* DENALI_PHY_366_DATA */ + 0x00000000, /* DENALI_PHY_367_DATA */ + 0x00000000, /* DENALI_PHY_368_DATA */ + 0x00000000, /* DENALI_PHY_369_DATA */ + 0x00000000, /* DENALI_PHY_370_DATA */ + 0x00000000, /* DENALI_PHY_371_DATA */ + 0x00000000, /* DENALI_PHY_372_DATA */ + 0x00000000, /* DENALI_PHY_373_DATA */ + 0x00000000, /* DENALI_PHY_374_DATA */ + 0x00000000, /* DENALI_PHY_375_DATA */ + 0x00000000, /* DENALI_PHY_376_DATA */ + 0x00000000, /* DENALI_PHY_377_DATA */ + 0x00000000, /* DENALI_PHY_378_DATA */ + 0x00000000, /* DENALI_PHY_379_DATA */ + 0x00000000, /* DENALI_PHY_380_DATA */ + 0x00000000, /* DENALI_PHY_381_DATA */ + 0x00000000, /* DENALI_PHY_382_DATA */ + 0x00000000, /* DENALI_PHY_383_DATA */ + 0x76543210, /* DENALI_PHY_384_DATA */ + 0x0004f008, /* DENALI_PHY_385_DATA */ + 0x00020119, /* DENALI_PHY_386_DATA */ + 0x00000000, /* DENALI_PHY_387_DATA */ + 0x00000000, /* DENALI_PHY_388_DATA */ + 0x00010000, /* DENALI_PHY_389_DATA */ + 0x01665555, /* DENALI_PHY_390_DATA */ + 0x03665555, /* DENALI_PHY_391_DATA */ + 0x00010f00, /* DENALI_PHY_392_DATA */ + 0x05010200, /* DENALI_PHY_393_DATA */ + 0x00000002, /* DENALI_PHY_394_DATA */ + 0x00170180, /* DENALI_PHY_395_DATA */ + 0x00cc0201, /* DENALI_PHY_396_DATA */ + 0x00030066, /* DENALI_PHY_397_DATA */ + 0x00000000, /* DENALI_PHY_398_DATA */ + 0x00000000, /* DENALI_PHY_399_DATA */ + 0x00000000, /* DENALI_PHY_400_DATA */ + 0x00000000, /* DENALI_PHY_401_DATA */ + 0x00000000, /* DENALI_PHY_402_DATA */ + 0x00000000, /* DENALI_PHY_403_DATA */ + 0x00000000, /* DENALI_PHY_404_DATA */ + 0x00000000, /* DENALI_PHY_405_DATA */ + 0x04080000, /* DENALI_PHY_406_DATA */ + 0x04080400, /* DENALI_PHY_407_DATA */ + 0x30000000, /* DENALI_PHY_408_DATA */ + 0x0c00c007, /* DENALI_PHY_409_DATA */ + 0x00000100, /* DENALI_PHY_410_DATA */ + 0x00000000, /* DENALI_PHY_411_DATA */ + 0xfd02fe01, /* DENALI_PHY_412_DATA */ + 0xf708fb04, /* DENALI_PHY_413_DATA */ + 0xdf20ef10, /* DENALI_PHY_414_DATA */ + 0x7f80bf40, /* DENALI_PHY_415_DATA */ + 0x0000aaaa, /* DENALI_PHY_416_DATA */ + 0x00000000, /* DENALI_PHY_417_DATA */ + 0x00000000, /* DENALI_PHY_418_DATA */ + 0x00000000, /* DENALI_PHY_419_DATA */ + 0x00000000, /* DENALI_PHY_420_DATA */ + 0x00000000, /* DENALI_PHY_421_DATA */ + 0x00000000, /* DENALI_PHY_422_DATA */ + 0x00000000, /* DENALI_PHY_423_DATA */ + 0x00000000, /* DENALI_PHY_424_DATA */ + 0x00000000, /* DENALI_PHY_425_DATA */ + 0x00000000, /* DENALI_PHY_426_DATA */ + 0x00000000, /* DENALI_PHY_427_DATA */ + 0x00000000, /* DENALI_PHY_428_DATA */ + 0x00000000, /* DENALI_PHY_429_DATA */ + 0x00000000, /* DENALI_PHY_430_DATA */ + 0x00000000, /* DENALI_PHY_431_DATA */ + 0x00000000, /* DENALI_PHY_432_DATA */ + 0x00000000, /* DENALI_PHY_433_DATA */ + 0x00000000, /* DENALI_PHY_434_DATA */ + 0x00000000, /* DENALI_PHY_435_DATA */ + 0x00200000, /* DENALI_PHY_436_DATA */ + 0x00000000, /* DENALI_PHY_437_DATA */ + 0x00000000, /* DENALI_PHY_438_DATA */ + 0x00000000, /* DENALI_PHY_439_DATA */ + 0x00000000, /* DENALI_PHY_440_DATA */ + 0x00000000, /* DENALI_PHY_441_DATA */ + 0x00000000, /* DENALI_PHY_442_DATA */ + 0x02800280, /* DENALI_PHY_443_DATA */ + 0x02800280, /* DENALI_PHY_444_DATA */ + 0x02800280, /* DENALI_PHY_445_DATA */ + 0x02800280, /* DENALI_PHY_446_DATA */ + 0x00000280, /* DENALI_PHY_447_DATA */ + 0x00000000, /* DENALI_PHY_448_DATA */ + 0x00000000, /* DENALI_PHY_449_DATA */ + 0x00000000, /* DENALI_PHY_450_DATA */ + 0x00000000, /* DENALI_PHY_451_DATA */ + 0x00800000, /* DENALI_PHY_452_DATA */ + 0x00800080, /* DENALI_PHY_453_DATA */ + 0x00800080, /* DENALI_PHY_454_DATA */ + 0x00800080, /* DENALI_PHY_455_DATA */ + 0x00800080, /* DENALI_PHY_456_DATA */ + 0x00800080, /* DENALI_PHY_457_DATA */ + 0x00800080, /* DENALI_PHY_458_DATA */ + 0x00800080, /* DENALI_PHY_459_DATA */ + 0x00800080, /* DENALI_PHY_460_DATA */ + 0x01190080, /* DENALI_PHY_461_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ + 0x00000000, /* DENALI_PHY_463_DATA */ + 0x00000000, /* DENALI_PHY_464_DATA */ + 0x00000200, /* DENALI_PHY_465_DATA */ + 0x00000000, /* DENALI_PHY_466_DATA */ + 0x51315152, /* DENALI_PHY_467_DATA */ + 0xc0013150, /* DENALI_PHY_468_DATA */ + 0x020000c0, /* DENALI_PHY_469_DATA */ + 0x00100001, /* DENALI_PHY_470_DATA */ + 0x07054204, /* DENALI_PHY_471_DATA */ + 0x000f0c18, /* DENALI_PHY_472_DATA */ + 0x01000140, /* DENALI_PHY_473_DATA */ + 0x00000c10, /* DENALI_PHY_474_DATA */ + 0x00000000, /* DENALI_PHY_475_DATA */ + 0x00000000, /* DENALI_PHY_476_DATA */ + 0x00000000, /* DENALI_PHY_477_DATA */ + 0x00000000, /* DENALI_PHY_478_DATA */ + 0x00000000, /* DENALI_PHY_479_DATA */ + 0x00000000, /* DENALI_PHY_480_DATA */ + 0x00000000, /* DENALI_PHY_481_DATA */ + 0x00000000, /* DENALI_PHY_482_DATA */ + 0x00000000, /* DENALI_PHY_483_DATA */ + 0x00000000, /* DENALI_PHY_484_DATA */ + 0x00000000, /* DENALI_PHY_485_DATA */ + 0x00000000, /* DENALI_PHY_486_DATA */ + 0x00000000, /* DENALI_PHY_487_DATA */ + 0x00000000, /* DENALI_PHY_488_DATA */ + 0x00000000, /* DENALI_PHY_489_DATA */ + 0x00000000, /* DENALI_PHY_490_DATA */ + 0x00000000, /* DENALI_PHY_491_DATA */ + 0x00000000, /* DENALI_PHY_492_DATA */ + 0x00000000, /* DENALI_PHY_493_DATA */ + 0x00000000, /* DENALI_PHY_494_DATA */ + 0x00000000, /* DENALI_PHY_495_DATA */ + 0x00000000, /* DENALI_PHY_496_DATA */ + 0x00000000, /* DENALI_PHY_497_DATA */ + 0x00000000, /* DENALI_PHY_498_DATA */ + 0x00000000, /* DENALI_PHY_499_DATA */ + 0x00000000, /* DENALI_PHY_500_DATA */ + 0x00000000, /* DENALI_PHY_501_DATA */ + 0x00000000, /* DENALI_PHY_502_DATA */ + 0x00000000, /* DENALI_PHY_503_DATA */ + 0x00000000, /* DENALI_PHY_504_DATA */ + 0x00000000, /* DENALI_PHY_505_DATA */ + 0x00000000, /* DENALI_PHY_506_DATA */ + 0x00000000, /* DENALI_PHY_507_DATA */ + 0x00000000, /* DENALI_PHY_508_DATA */ + 0x00000000, /* DENALI_PHY_509_DATA */ + 0x00000000, /* DENALI_PHY_510_DATA */ + 0x00000000, /* DENALI_PHY_511_DATA */ + 0x00000000, /* DENALI_PHY_512_DATA */ + 0x00000000, /* DENALI_PHY_513_DATA */ + 0x00000000, /* DENALI_PHY_514_DATA */ + 0x00000000, /* DENALI_PHY_515_DATA */ + 0x00000000, /* DENALI_PHY_516_DATA */ + 0x00000000, /* DENALI_PHY_517_DATA */ + 0x00000000, /* DENALI_PHY_518_DATA */ + 0x00000002, /* DENALI_PHY_519_DATA */ + 0x00000000, /* DENALI_PHY_520_DATA */ + 0x00000000, /* DENALI_PHY_521_DATA */ + 0x00000000, /* DENALI_PHY_522_DATA */ + 0x00400320, /* DENALI_PHY_523_DATA */ + 0x00000040, /* DENALI_PHY_524_DATA */ + 0x00dcba98, /* DENALI_PHY_525_DATA */ + 0x00000000, /* DENALI_PHY_526_DATA */ + 0x00dcba98, /* DENALI_PHY_527_DATA */ + 0x01000000, /* DENALI_PHY_528_DATA */ + 0x00020003, /* DENALI_PHY_529_DATA */ + 0x00000000, /* DENALI_PHY_530_DATA */ + 0x00000000, /* DENALI_PHY_531_DATA */ + 0x00000000, /* DENALI_PHY_532_DATA */ + 0x0000002a, /* DENALI_PHY_533_DATA */ + 0x00000015, /* DENALI_PHY_534_DATA */ + 0x00000015, /* DENALI_PHY_535_DATA */ + 0x0000002a, /* DENALI_PHY_536_DATA */ + 0x00000033, /* DENALI_PHY_537_DATA */ + 0x0000000c, /* DENALI_PHY_538_DATA */ + 0x0000000c, /* DENALI_PHY_539_DATA */ + 0x00000033, /* DENALI_PHY_540_DATA */ + 0x0a418820, /* DENALI_PHY_541_DATA */ + 0x003f0000, /* DENALI_PHY_542_DATA */ + 0x0000003f, /* DENALI_PHY_543_DATA */ + 0x00030055, /* DENALI_PHY_544_DATA */ + 0x03000300, /* DENALI_PHY_545_DATA */ + 0x03000300, /* DENALI_PHY_546_DATA */ + 0x00000300, /* DENALI_PHY_547_DATA */ + 0x42080010, /* DENALI_PHY_548_DATA */ + 0x00000003, /* DENALI_PHY_549_DATA */ + 0x00000000, /* DENALI_PHY_550_DATA */ + 0x00000000, /* DENALI_PHY_551_DATA */ + 0x00000000, /* DENALI_PHY_552_DATA */ + 0x00000000, /* DENALI_PHY_553_DATA */ + 0x00000000, /* DENALI_PHY_554_DATA */ + 0x00000000, /* DENALI_PHY_555_DATA */ + 0x00000000, /* DENALI_PHY_556_DATA */ + 0x00000000, /* DENALI_PHY_557_DATA */ + 0x00000000, /* DENALI_PHY_558_DATA */ + 0x00000000, /* DENALI_PHY_559_DATA */ + 0x00000000, /* DENALI_PHY_560_DATA */ + 0x00000000, /* DENALI_PHY_561_DATA */ + 0x00000000, /* DENALI_PHY_562_DATA */ + 0x00000000, /* DENALI_PHY_563_DATA */ + 0x00000000, /* DENALI_PHY_564_DATA */ + 0x00000000, /* DENALI_PHY_565_DATA */ + 0x00000000, /* DENALI_PHY_566_DATA */ + 0x00000000, /* DENALI_PHY_567_DATA */ + 0x00000000, /* DENALI_PHY_568_DATA */ + 0x00000000, /* DENALI_PHY_569_DATA */ + 0x00000000, /* DENALI_PHY_570_DATA */ + 0x00000000, /* DENALI_PHY_571_DATA */ + 0x00000000, /* DENALI_PHY_572_DATA */ + 0x00000000, /* DENALI_PHY_573_DATA */ + 0x00000000, /* DENALI_PHY_574_DATA */ + 0x00000000, /* DENALI_PHY_575_DATA */ + 0x00000000, /* DENALI_PHY_576_DATA */ + 0x00000000, /* DENALI_PHY_577_DATA */ + 0x00000000, /* DENALI_PHY_578_DATA */ + 0x00000000, /* DENALI_PHY_579_DATA */ + 0x00000000, /* DENALI_PHY_580_DATA */ + 0x00000000, /* DENALI_PHY_581_DATA */ + 0x00000000, /* DENALI_PHY_582_DATA */ + 0x00000000, /* DENALI_PHY_583_DATA */ + 0x00000000, /* DENALI_PHY_584_DATA */ + 0x00000000, /* DENALI_PHY_585_DATA */ + 0x00000000, /* DENALI_PHY_586_DATA */ + 0x00000000, /* DENALI_PHY_587_DATA */ + 0x00000000, /* DENALI_PHY_588_DATA */ + 0x00000000, /* DENALI_PHY_589_DATA */ + 0x00000000, /* DENALI_PHY_590_DATA */ + 0x00000000, /* DENALI_PHY_591_DATA */ + 0x00000000, /* DENALI_PHY_592_DATA */ + 0x00000000, /* DENALI_PHY_593_DATA */ + 0x00000000, /* DENALI_PHY_594_DATA */ + 0x00000000, /* DENALI_PHY_595_DATA */ + 0x00000000, /* DENALI_PHY_596_DATA */ + 0x00000000, /* DENALI_PHY_597_DATA */ + 0x00000000, /* DENALI_PHY_598_DATA */ + 0x00000000, /* DENALI_PHY_599_DATA */ + 0x00000000, /* DENALI_PHY_600_DATA */ + 0x00000000, /* DENALI_PHY_601_DATA */ + 0x00000000, /* DENALI_PHY_602_DATA */ + 0x00000000, /* DENALI_PHY_603_DATA */ + 0x00000000, /* DENALI_PHY_604_DATA */ + 0x00000000, /* DENALI_PHY_605_DATA */ + 0x00000000, /* DENALI_PHY_606_DATA */ + 0x00000000, /* DENALI_PHY_607_DATA */ + 0x00000000, /* DENALI_PHY_608_DATA */ + 0x00000000, /* DENALI_PHY_609_DATA */ + 0x00000000, /* DENALI_PHY_610_DATA */ + 0x00000000, /* DENALI_PHY_611_DATA */ + 0x00000000, /* DENALI_PHY_612_DATA */ + 0x00000000, /* DENALI_PHY_613_DATA */ + 0x00000000, /* DENALI_PHY_614_DATA */ + 0x00000000, /* DENALI_PHY_615_DATA */ + 0x00000000, /* DENALI_PHY_616_DATA */ + 0x00000000, /* DENALI_PHY_617_DATA */ + 0x00000000, /* DENALI_PHY_618_DATA */ + 0x00000000, /* DENALI_PHY_619_DATA */ + 0x00000000, /* DENALI_PHY_620_DATA */ + 0x00000000, /* DENALI_PHY_621_DATA */ + 0x00000000, /* DENALI_PHY_622_DATA */ + 0x00000000, /* DENALI_PHY_623_DATA */ + 0x00000000, /* DENALI_PHY_624_DATA */ + 0x00000000, /* DENALI_PHY_625_DATA */ + 0x00000000, /* DENALI_PHY_626_DATA */ + 0x00000000, /* DENALI_PHY_627_DATA */ + 0x00000000, /* DENALI_PHY_628_DATA */ + 0x00000000, /* DENALI_PHY_629_DATA */ + 0x00000000, /* DENALI_PHY_630_DATA */ + 0x00000000, /* DENALI_PHY_631_DATA */ + 0x00000000, /* DENALI_PHY_632_DATA */ + 0x00000000, /* DENALI_PHY_633_DATA */ + 0x00000000, /* DENALI_PHY_634_DATA */ + 0x00000000, /* DENALI_PHY_635_DATA */ + 0x00000000, /* DENALI_PHY_636_DATA */ + 0x00000000, /* DENALI_PHY_637_DATA */ + 0x00000000, /* DENALI_PHY_638_DATA */ + 0x00000000, /* DENALI_PHY_639_DATA */ + 0x00000000, /* DENALI_PHY_640_DATA */ + 0x00000000, /* DENALI_PHY_641_DATA */ + 0x00000000, /* DENALI_PHY_642_DATA */ + 0x00000000, /* DENALI_PHY_643_DATA */ + 0x00000000, /* DENALI_PHY_644_DATA */ + 0x00000000, /* DENALI_PHY_645_DATA */ + 0x00000000, /* DENALI_PHY_646_DATA */ + 0x00000002, /* DENALI_PHY_647_DATA */ + 0x00000000, /* DENALI_PHY_648_DATA */ + 0x00000000, /* DENALI_PHY_649_DATA */ + 0x00000000, /* DENALI_PHY_650_DATA */ + 0x00400320, /* DENALI_PHY_651_DATA */ + 0x00000040, /* DENALI_PHY_652_DATA */ + 0x00000000, /* DENALI_PHY_653_DATA */ + 0x00000000, /* DENALI_PHY_654_DATA */ + 0x00000000, /* DENALI_PHY_655_DATA */ + 0x01000000, /* DENALI_PHY_656_DATA */ + 0x00020003, /* DENALI_PHY_657_DATA */ + 0x00000000, /* DENALI_PHY_658_DATA */ + 0x00000000, /* DENALI_PHY_659_DATA */ + 0x00000000, /* DENALI_PHY_660_DATA */ + 0x0000002a, /* DENALI_PHY_661_DATA */ + 0x00000015, /* DENALI_PHY_662_DATA */ + 0x00000015, /* DENALI_PHY_663_DATA */ + 0x0000002a, /* DENALI_PHY_664_DATA */ + 0x00000033, /* DENALI_PHY_665_DATA */ + 0x0000000c, /* DENALI_PHY_666_DATA */ + 0x0000000c, /* DENALI_PHY_667_DATA */ + 0x00000033, /* DENALI_PHY_668_DATA */ + 0x00000000, /* DENALI_PHY_669_DATA */ + 0x00000000, /* DENALI_PHY_670_DATA */ + 0x00000000, /* DENALI_PHY_671_DATA */ + 0x00030055, /* DENALI_PHY_672_DATA */ + 0x03000300, /* DENALI_PHY_673_DATA */ + 0x03000300, /* DENALI_PHY_674_DATA */ + 0x00000300, /* DENALI_PHY_675_DATA */ + 0x42080010, /* DENALI_PHY_676_DATA */ + 0x00000003, /* DENALI_PHY_677_DATA */ + 0x00000000, /* DENALI_PHY_678_DATA */ + 0x00000000, /* DENALI_PHY_679_DATA */ + 0x00000000, /* DENALI_PHY_680_DATA */ + 0x00000000, /* DENALI_PHY_681_DATA */ + 0x00000000, /* DENALI_PHY_682_DATA */ + 0x00000000, /* DENALI_PHY_683_DATA */ + 0x00000000, /* DENALI_PHY_684_DATA */ + 0x00000000, /* DENALI_PHY_685_DATA */ + 0x00000000, /* DENALI_PHY_686_DATA */ + 0x00000000, /* DENALI_PHY_687_DATA */ + 0x00000000, /* DENALI_PHY_688_DATA */ + 0x00000000, /* DENALI_PHY_689_DATA */ + 0x00000000, /* DENALI_PHY_690_DATA */ + 0x00000000, /* DENALI_PHY_691_DATA */ + 0x00000000, /* DENALI_PHY_692_DATA */ + 0x00000000, /* DENALI_PHY_693_DATA */ + 0x00000000, /* DENALI_PHY_694_DATA */ + 0x00000000, /* DENALI_PHY_695_DATA */ + 0x00000000, /* DENALI_PHY_696_DATA */ + 0x00000000, /* DENALI_PHY_697_DATA */ + 0x00000000, /* DENALI_PHY_698_DATA */ + 0x00000000, /* DENALI_PHY_699_DATA */ + 0x00000000, /* DENALI_PHY_700_DATA */ + 0x00000000, /* DENALI_PHY_701_DATA */ + 0x00000000, /* DENALI_PHY_702_DATA */ + 0x00000000, /* DENALI_PHY_703_DATA */ + 0x00000000, /* DENALI_PHY_704_DATA */ + 0x00000000, /* DENALI_PHY_705_DATA */ + 0x00000000, /* DENALI_PHY_706_DATA */ + 0x00000000, /* DENALI_PHY_707_DATA */ + 0x00000000, /* DENALI_PHY_708_DATA */ + 0x00000000, /* DENALI_PHY_709_DATA */ + 0x00000000, /* DENALI_PHY_710_DATA */ + 0x00000000, /* DENALI_PHY_711_DATA */ + 0x00000000, /* DENALI_PHY_712_DATA */ + 0x00000000, /* DENALI_PHY_713_DATA */ + 0x00000000, /* DENALI_PHY_714_DATA */ + 0x00000000, /* DENALI_PHY_715_DATA */ + 0x00000000, /* DENALI_PHY_716_DATA */ + 0x00000000, /* DENALI_PHY_717_DATA */ + 0x00000000, /* DENALI_PHY_718_DATA */ + 0x00000000, /* DENALI_PHY_719_DATA */ + 0x00000000, /* DENALI_PHY_720_DATA */ + 0x00000000, /* DENALI_PHY_721_DATA */ + 0x00000000, /* DENALI_PHY_722_DATA */ + 0x00000000, /* DENALI_PHY_723_DATA */ + 0x00000000, /* DENALI_PHY_724_DATA */ + 0x00000000, /* DENALI_PHY_725_DATA */ + 0x00000000, /* DENALI_PHY_726_DATA */ + 0x00000000, /* DENALI_PHY_727_DATA */ + 0x00000000, /* DENALI_PHY_728_DATA */ + 0x00000000, /* DENALI_PHY_729_DATA */ + 0x00000000, /* DENALI_PHY_730_DATA */ + 0x00000000, /* DENALI_PHY_731_DATA */ + 0x00000000, /* DENALI_PHY_732_DATA */ + 0x00000000, /* DENALI_PHY_733_DATA */ + 0x00000000, /* DENALI_PHY_734_DATA */ + 0x00000000, /* DENALI_PHY_735_DATA */ + 0x00000000, /* DENALI_PHY_736_DATA */ + 0x00000000, /* DENALI_PHY_737_DATA */ + 0x00000000, /* DENALI_PHY_738_DATA */ + 0x00000000, /* DENALI_PHY_739_DATA */ + 0x00000000, /* DENALI_PHY_740_DATA */ + 0x00000000, /* DENALI_PHY_741_DATA */ + 0x00000000, /* DENALI_PHY_742_DATA */ + 0x00000000, /* DENALI_PHY_743_DATA */ + 0x00000000, /* DENALI_PHY_744_DATA */ + 0x00000000, /* DENALI_PHY_745_DATA */ + 0x00000000, /* DENALI_PHY_746_DATA */ + 0x00000000, /* DENALI_PHY_747_DATA */ + 0x00000000, /* DENALI_PHY_748_DATA */ + 0x00000000, /* DENALI_PHY_749_DATA */ + 0x00000000, /* DENALI_PHY_750_DATA */ + 0x00000000, /* DENALI_PHY_751_DATA */ + 0x00000000, /* DENALI_PHY_752_DATA */ + 0x00000000, /* DENALI_PHY_753_DATA */ + 0x00000000, /* DENALI_PHY_754_DATA */ + 0x00000000, /* DENALI_PHY_755_DATA */ + 0x00000000, /* DENALI_PHY_756_DATA */ + 0x00000000, /* DENALI_PHY_757_DATA */ + 0x00000000, /* DENALI_PHY_758_DATA */ + 0x00000000, /* DENALI_PHY_759_DATA */ + 0x00000000, /* DENALI_PHY_760_DATA */ + 0x00000000, /* DENALI_PHY_761_DATA */ + 0x00000000, /* DENALI_PHY_762_DATA */ + 0x00000000, /* DENALI_PHY_763_DATA */ + 0x00000000, /* DENALI_PHY_764_DATA */ + 0x00000000, /* DENALI_PHY_765_DATA */ + 0x00000000, /* DENALI_PHY_766_DATA */ + 0x00000000, /* DENALI_PHY_767_DATA */ + 0x00000000, /* DENALI_PHY_768_DATA */ + 0x00000000, /* DENALI_PHY_769_DATA */ + 0x00000000, /* DENALI_PHY_770_DATA */ + 0x00000000, /* DENALI_PHY_771_DATA */ + 0x00000000, /* DENALI_PHY_772_DATA */ + 0x00000000, /* DENALI_PHY_773_DATA */ + 0x00000000, /* DENALI_PHY_774_DATA */ + 0x00000002, /* DENALI_PHY_775_DATA */ + 0x00000000, /* DENALI_PHY_776_DATA */ + 0x00000000, /* DENALI_PHY_777_DATA */ + 0x00000000, /* DENALI_PHY_778_DATA */ + 0x00400320, /* DENALI_PHY_779_DATA */ + 0x00000040, /* DENALI_PHY_780_DATA */ + 0x00000000, /* DENALI_PHY_781_DATA */ + 0x00000000, /* DENALI_PHY_782_DATA */ + 0x00000000, /* DENALI_PHY_783_DATA */ + 0x01000000, /* DENALI_PHY_784_DATA */ + 0x00020003, /* DENALI_PHY_785_DATA */ + 0x00000000, /* DENALI_PHY_786_DATA */ + 0x00000000, /* DENALI_PHY_787_DATA */ + 0x00000000, /* DENALI_PHY_788_DATA */ + 0x0000002a, /* DENALI_PHY_789_DATA */ + 0x00000015, /* DENALI_PHY_790_DATA */ + 0x00000015, /* DENALI_PHY_791_DATA */ + 0x0000002a, /* DENALI_PHY_792_DATA */ + 0x00000033, /* DENALI_PHY_793_DATA */ + 0x0000000c, /* DENALI_PHY_794_DATA */ + 0x0000000c, /* DENALI_PHY_795_DATA */ + 0x00000033, /* DENALI_PHY_796_DATA */ + 0x1ee6b16a, /* DENALI_PHY_797_DATA */ + 0x10000000, /* DENALI_PHY_798_DATA */ + 0x00000000, /* DENALI_PHY_799_DATA */ + 0x00030055, /* DENALI_PHY_800_DATA */ + 0x03000300, /* DENALI_PHY_801_DATA */ + 0x03000300, /* DENALI_PHY_802_DATA */ + 0x00000300, /* DENALI_PHY_803_DATA */ + 0x42080010, /* DENALI_PHY_804_DATA */ + 0x00000003, /* DENALI_PHY_805_DATA */ + 0x00000000, /* DENALI_PHY_806_DATA */ + 0x00000000, /* DENALI_PHY_807_DATA */ + 0x00000000, /* DENALI_PHY_808_DATA */ + 0x00000000, /* DENALI_PHY_809_DATA */ + 0x00000000, /* DENALI_PHY_810_DATA */ + 0x00000000, /* DENALI_PHY_811_DATA */ + 0x00000000, /* DENALI_PHY_812_DATA */ + 0x00000000, /* DENALI_PHY_813_DATA */ + 0x00000000, /* DENALI_PHY_814_DATA */ + 0x00000000, /* DENALI_PHY_815_DATA */ + 0x00000000, /* DENALI_PHY_816_DATA */ + 0x00000000, /* DENALI_PHY_817_DATA */ + 0x00000000, /* DENALI_PHY_818_DATA */ + 0x00000000, /* DENALI_PHY_819_DATA */ + 0x00000000, /* DENALI_PHY_820_DATA */ + 0x00000000, /* DENALI_PHY_821_DATA */ + 0x00000000, /* DENALI_PHY_822_DATA */ + 0x00000000, /* DENALI_PHY_823_DATA */ + 0x00000000, /* DENALI_PHY_824_DATA */ + 0x00000000, /* DENALI_PHY_825_DATA */ + 0x00000000, /* DENALI_PHY_826_DATA */ + 0x00000000, /* DENALI_PHY_827_DATA */ + 0x00000000, /* DENALI_PHY_828_DATA */ + 0x00000000, /* DENALI_PHY_829_DATA */ + 0x00000000, /* DENALI_PHY_830_DATA */ + 0x00000000, /* DENALI_PHY_831_DATA */ + 0x00000000, /* DENALI_PHY_832_DATA */ + 0x00000000, /* DENALI_PHY_833_DATA */ + 0x00000000, /* DENALI_PHY_834_DATA */ + 0x00000000, /* DENALI_PHY_835_DATA */ + 0x00000000, /* DENALI_PHY_836_DATA */ + 0x00000000, /* DENALI_PHY_837_DATA */ + 0x00000000, /* DENALI_PHY_838_DATA */ + 0x00000000, /* DENALI_PHY_839_DATA */ + 0x00000000, /* DENALI_PHY_840_DATA */ + 0x00000000, /* DENALI_PHY_841_DATA */ + 0x00000000, /* DENALI_PHY_842_DATA */ + 0x00000000, /* DENALI_PHY_843_DATA */ + 0x00000000, /* DENALI_PHY_844_DATA */ + 0x00000000, /* DENALI_PHY_845_DATA */ + 0x00000000, /* DENALI_PHY_846_DATA */ + 0x00000000, /* DENALI_PHY_847_DATA */ + 0x00000000, /* DENALI_PHY_848_DATA */ + 0x00000000, /* DENALI_PHY_849_DATA */ + 0x00000000, /* DENALI_PHY_850_DATA */ + 0x00000000, /* DENALI_PHY_851_DATA */ + 0x00000000, /* DENALI_PHY_852_DATA */ + 0x00000000, /* DENALI_PHY_853_DATA */ + 0x00000000, /* DENALI_PHY_854_DATA */ + 0x00000000, /* DENALI_PHY_855_DATA */ + 0x00000000, /* DENALI_PHY_856_DATA */ + 0x00000000, /* DENALI_PHY_857_DATA */ + 0x00000000, /* DENALI_PHY_858_DATA */ + 0x00000000, /* DENALI_PHY_859_DATA */ + 0x00000000, /* DENALI_PHY_860_DATA */ + 0x00000000, /* DENALI_PHY_861_DATA */ + 0x00000000, /* DENALI_PHY_862_DATA */ + 0x00000000, /* DENALI_PHY_863_DATA */ + 0x00000000, /* DENALI_PHY_864_DATA */ + 0x00000000, /* DENALI_PHY_865_DATA */ + 0x00000000, /* DENALI_PHY_866_DATA */ + 0x00000000, /* DENALI_PHY_867_DATA */ + 0x00000000, /* DENALI_PHY_868_DATA */ + 0x00000000, /* DENALI_PHY_869_DATA */ + 0x00000000, /* DENALI_PHY_870_DATA */ + 0x00000000, /* DENALI_PHY_871_DATA */ + 0x00000000, /* DENALI_PHY_872_DATA */ + 0x00000000, /* DENALI_PHY_873_DATA */ + 0x00000000, /* DENALI_PHY_874_DATA */ + 0x00000000, /* DENALI_PHY_875_DATA */ + 0x00000000, /* DENALI_PHY_876_DATA */ + 0x00000000, /* DENALI_PHY_877_DATA */ + 0x00000000, /* DENALI_PHY_878_DATA */ + 0x00000000, /* DENALI_PHY_879_DATA */ + 0x00000000, /* DENALI_PHY_880_DATA */ + 0x00000000, /* DENALI_PHY_881_DATA */ + 0x00000000, /* DENALI_PHY_882_DATA */ + 0x00000000, /* DENALI_PHY_883_DATA */ + 0x00000000, /* DENALI_PHY_884_DATA */ + 0x00000000, /* DENALI_PHY_885_DATA */ + 0x00000000, /* DENALI_PHY_886_DATA */ + 0x00000000, /* DENALI_PHY_887_DATA */ + 0x00000000, /* DENALI_PHY_888_DATA */ + 0x00000000, /* DENALI_PHY_889_DATA */ + 0x00000000, /* DENALI_PHY_890_DATA */ + 0x00000000, /* DENALI_PHY_891_DATA */ + 0x00000000, /* DENALI_PHY_892_DATA */ + 0x00000000, /* DENALI_PHY_893_DATA */ + 0x00000000, /* DENALI_PHY_894_DATA */ + 0x00000000, /* DENALI_PHY_895_DATA */ + 0x00000000, /* DENALI_PHY_896_DATA */ + 0x00000000, /* DENALI_PHY_897_DATA */ + 0x00000005, /* DENALI_PHY_898_DATA */ + 0x04000f01, /* DENALI_PHY_899_DATA */ + 0x00020040, /* DENALI_PHY_900_DATA */ + 0x00020055, /* DENALI_PHY_901_DATA */ + 0x00000000, /* DENALI_PHY_902_DATA */ + 0x00000000, /* DENALI_PHY_903_DATA */ + 0x00000000, /* DENALI_PHY_904_DATA */ + 0x00000050, /* DENALI_PHY_905_DATA */ + 0x00000000, /* DENALI_PHY_906_DATA */ + 0x01010100, /* DENALI_PHY_907_DATA */ + 0x00000600, /* DENALI_PHY_908_DATA */ + 0x00000000, /* DENALI_PHY_909_DATA */ + 0x00006400, /* DENALI_PHY_910_DATA */ + 0x01221102, /* DENALI_PHY_911_DATA */ + 0x00000000, /* DENALI_PHY_912_DATA */ + 0x000d1f00, /* DENALI_PHY_913_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_914_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_915_DATA */ + 0x00030003, /* DENALI_PHY_916_DATA */ + 0x03000300, /* DENALI_PHY_917_DATA */ + 0x00000300, /* DENALI_PHY_918_DATA */ + 0x01221102, /* DENALI_PHY_919_DATA */ + 0x00000000, /* DENALI_PHY_920_DATA */ + 0x00000000, /* DENALI_PHY_921_DATA */ + 0x03020000, /* DENALI_PHY_922_DATA */ + 0x00000001, /* DENALI_PHY_923_DATA */ + 0x00000411, /* DENALI_PHY_924_DATA */ + 0x00000411, /* DENALI_PHY_925_DATA */ + 0x00000040, /* DENALI_PHY_926_DATA */ + 0x00000040, /* DENALI_PHY_927_DATA */ + 0x00000411, /* DENALI_PHY_928_DATA */ + 0x00000411, /* DENALI_PHY_929_DATA */ + 0x00004410, /* DENALI_PHY_930_DATA */ + 0x00004410, /* DENALI_PHY_931_DATA */ + 0x00004410, /* DENALI_PHY_932_DATA */ + 0x00004410, /* DENALI_PHY_933_DATA */ + 0x00004410, /* DENALI_PHY_934_DATA */ + 0x00000411, /* DENALI_PHY_935_DATA */ + 0x00004410, /* DENALI_PHY_936_DATA */ + 0x00000411, /* DENALI_PHY_937_DATA */ + 0x00004410, /* DENALI_PHY_938_DATA */ + 0x00000411, /* DENALI_PHY_939_DATA */ + 0x00004410, /* DENALI_PHY_940_DATA */ + 0x00000000, /* DENALI_PHY_941_DATA */ + 0x00000000, /* DENALI_PHY_942_DATA */ + 0x00000000, /* DENALI_PHY_943_DATA */ + 0x64000000, /* DENALI_PHY_944_DATA */ + 0x00000000, /* DENALI_PHY_945_DATA */ + 0x00000000, /* DENALI_PHY_946_DATA */ + 0x00000508, /* DENALI_PHY_947_DATA */ + 0x00000000, /* DENALI_PHY_948_DATA */ + 0x00000000, /* DENALI_PHY_949_DATA */ + 0x00000000, /* DENALI_PHY_950_DATA */ + 0x00000000, /* DENALI_PHY_951_DATA */ + 0x00000000, /* DENALI_PHY_952_DATA */ + 0x00000000, /* DENALI_PHY_953_DATA */ + 0xe4000000, /* DENALI_PHY_954_DATA */ + 0x00000000, /* DENALI_PHY_955_DATA */ + 0x00000000, /* DENALI_PHY_956_DATA */ + 0x01010000, /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + } + }, +}, diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_common.c b/roms/u-boot/drivers/ram/rockchip/sdram_common.c new file mode 100644 index 000000000..b3e7421d0 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_common.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_RAM_ROCKCHIP_DEBUG +void sdram_print_dram_type(unsigned char dramtype) +{ + switch (dramtype) { + case DDR3: + printascii("DDR3"); + break; + case DDR4: + printascii("DDR4"); + break; + case LPDDR2: + printascii("LPDDR2"); + break; + case LPDDR3: + printascii("LPDDR3"); + break; + case LPDDR4: + printascii("LPDDR4"); + break; + default: + printascii("Unknown Device"); + break; + } +} + +void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base) +{ + u64 cap; + u32 bg; + + bg = (cap_info->dbw == 0) ? 2 : 1; + + sdram_print_dram_type(base->dramtype); + + printascii(", "); + printdec(base->ddr_freq); + printascii("MHz\n"); + + printascii("BW="); + printdec(8 << cap_info->bw); + printascii(" Col="); + printdec(cap_info->col); + printascii(" Bk="); + printdec(0x1 << cap_info->bk); + if (base->dramtype == DDR4) { + printascii(" BG="); + printdec(1 << bg); + } + printascii(" CS0 Row="); + printdec(cap_info->cs0_row); + if (cap_info->cs0_high16bit_row != + cap_info->cs0_row) { + printascii("/"); + printdec(cap_info->cs0_high16bit_row); + } + if (cap_info->rank > 1) { + printascii(" CS1 Row="); + printdec(cap_info->cs1_row); + if (cap_info->cs1_high16bit_row != + cap_info->cs1_row) { + printascii("/"); + printdec(cap_info->cs1_high16bit_row); + } + } + printascii(" CS="); + printdec(cap_info->rank); + printascii(" Die BW="); + printdec(8 << cap_info->dbw); + + cap = sdram_get_cs_cap(cap_info, 3, base->dramtype); + if (cap_info->row_3_4) + cap = cap * 3 / 4; + + printascii(" Size="); + printdec(cap >> 20); + printascii("MB\n"); +} + +void sdram_print_stride(unsigned int stride) +{ + switch (stride) { + case 0xc: + printf("128B stride\n"); + break; + case 5: + case 9: + case 0xd: + case 0x11: + case 0x19: + printf("256B stride\n"); + break; + case 0xa: + case 0xe: + case 0x12: + printf("512B stride\n"); + break; + case 0xf: + printf("4K stride\n"); + break; + case 0x1f: + printf("32MB + 256B stride\n"); + break; + default: + printf("no stride\n"); + } +} +#else +inline void sdram_print_dram_type(unsigned char dramtype) +{ +} + +inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base) +{ +} + +inline void sdram_print_stride(unsigned int stride) +{ +} +#endif + +/* + * cs: 0:cs0 + * 1:cs1 + * else cs0+cs1 + * note: it didn't consider about row_3_4 + */ +u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type) +{ + u32 bg; + u64 cap[2]; + + if (dram_type == DDR4) + /* DDR4 8bit dram BG = 2(4bank groups), + * 16bit dram BG = 1 (2 bank groups) + */ + bg = (cap_info->dbw == 0) ? 2 : 1; + else + bg = 0; + cap[0] = 1llu << (cap_info->bw + cap_info->col + + bg + cap_info->bk + cap_info->cs0_row); + + if (cap_info->rank == 2) + cap[1] = 1llu << (cap_info->bw + cap_info->col + + bg + cap_info->bk + cap_info->cs1_row); + else + cap[1] = 0; + + if (cs == 0) + return cap[0]; + else if (cs == 1) + return cap[1]; + else + return (cap[0] + cap[1]); +} + +/* n: Unit bytes */ +void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +void sdram_org_config(struct sdram_cap_info *cap_info, + struct sdram_base_params *base, + u32 *p_os_reg2, u32 *p_os_reg3, u32 channel) +{ + *p_os_reg2 |= SYS_REG_ENC_DDRTYPE(base->dramtype); + *p_os_reg2 |= SYS_REG_ENC_NUM_CH(base->num_channels); + + *p_os_reg2 |= SYS_REG_ENC_ROW_3_4(cap_info->row_3_4, channel); + *p_os_reg2 |= SYS_REG_ENC_CHINFO(channel); + *p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel); + *p_os_reg2 |= SYS_REG_ENC_COL(cap_info->col, channel); + *p_os_reg2 |= SYS_REG_ENC_BK(cap_info->bk, channel); + *p_os_reg2 |= SYS_REG_ENC_BW(cap_info->bw, channel); + *p_os_reg2 |= SYS_REG_ENC_DBW(cap_info->dbw, channel); + + SYS_REG_ENC_CS0_ROW(cap_info->cs0_row, *p_os_reg2, *p_os_reg3, channel); + if (cap_info->cs1_row) + SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, *p_os_reg2, + *p_os_reg3, channel); + *p_os_reg3 |= SYS_REG_ENC_CS1_COL(cap_info->col, channel); + *p_os_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION); +} + +int sdram_detect_bw(struct sdram_cap_info *cap_info) +{ + return 0; +} + +int sdram_detect_cs(struct sdram_cap_info *cap_info) +{ + return 0; +} + +int sdram_detect_col(struct sdram_cap_info *cap_info, + u32 coltmp) +{ + void __iomem *test_addr; + u32 col; + u32 bw = cap_info->bw; + + for (col = coltmp; col >= 9; col -= 1) { + writel(0, CONFIG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + (1ul << (col + bw - 1ul))); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + printascii("col error\n"); + return -1; + } + + cap_info->col = col; + + return 0; +} + +int sdram_detect_bank(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp) +{ + void __iomem *test_addr; + u32 bk; + u32 bw = cap_info->bw; + + test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + (1ul << (coltmp + bktmp + bw - 1ul))); + writel(0, CONFIG_SYS_SDRAM_BASE); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + bk = 3; + else + bk = 2; + + cap_info->bk = bk; + + return 0; +} + +/* detect bg for ddr4 */ +int sdram_detect_bg(struct sdram_cap_info *cap_info, + u32 coltmp) +{ + void __iomem *test_addr; + u32 dbw; + u32 bw = cap_info->bw; + + test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + (1ul << (coltmp + bw + 1ul))); + writel(0, CONFIG_SYS_SDRAM_BASE); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + dbw = 0; + else + dbw = 1; + + cap_info->dbw = dbw; + + return 0; +} + +/* detect dbw for ddr3,lpddr2,lpddr3,lpddr4 */ +int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type) +{ + u32 row, col, bk, bw, cs_cap, cs; + u32 die_bw_0 = 0, die_bw_1 = 0; + + if (dram_type == DDR3 || dram_type == LPDDR4) { + cap_info->dbw = 1; + } else if (dram_type == LPDDR3 || dram_type == LPDDR2) { + row = cap_info->cs0_row; + col = cap_info->col; + bk = cap_info->bk; + cs = cap_info->rank; + bw = cap_info->bw; + cs_cap = (1 << (row + col + bk + bw - 20)); + if (bw == 2) { + if (cs_cap <= 0x2000000) /* 256Mb */ + die_bw_0 = (col < 9) ? 2 : 1; + else if (cs_cap <= 0x10000000) /* 2Gb */ + die_bw_0 = (col < 10) ? 2 : 1; + else if (cs_cap <= 0x40000000) /* 8Gb */ + die_bw_0 = (col < 11) ? 2 : 1; + else + die_bw_0 = (col < 12) ? 2 : 1; + if (cs > 1) { + row = cap_info->cs1_row; + cs_cap = (1 << (row + col + bk + bw - 20)); + if (cs_cap <= 0x2000000) /* 256Mb */ + die_bw_0 = (col < 9) ? 2 : 1; + else if (cs_cap <= 0x10000000) /* 2Gb */ + die_bw_0 = (col < 10) ? 2 : 1; + else if (cs_cap <= 0x40000000) /* 8Gb */ + die_bw_0 = (col < 11) ? 2 : 1; + else + die_bw_0 = (col < 12) ? 2 : 1; + } + } else { + die_bw_1 = 1; + die_bw_0 = 1; + } + cap_info->dbw = (die_bw_0 > die_bw_1) ? die_bw_0 : die_bw_1; + } + + return 0; +} + +int sdram_detect_row(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp, u32 rowtmp) +{ + u32 row; + u32 bw = cap_info->bw; + void __iomem *test_addr; + + for (row = rowtmp; row > 12; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + (1ul << (row + bktmp + coltmp + bw - 1ul))); + writel(PATTERN, test_addr); + if ((readl(test_addr) == PATTERN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 12) { + printascii("row error"); + return -1; + } + + cap_info->cs0_row = row; + + return 0; +} + +int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp) +{ + u32 row_3_4; + u32 bw = cap_info->bw; + u32 row = cap_info->cs0_row; + void __iomem *test_addr, *test_addr1; + + test_addr = CONFIG_SYS_SDRAM_BASE; + test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul))); + + writel(0, test_addr); + writel(PATTERN, test_addr1); + if ((readl(test_addr) == 0) && (readl(test_addr1) == PATTERN)) + row_3_4 = 0; + else + row_3_4 = 1; + + cap_info->row_3_4 = row_3_4; + + return 0; +} + +int sdram_detect_high_row(struct sdram_cap_info *cap_info) +{ + cap_info->cs0_high16bit_row = cap_info->cs0_row; + cap_info->cs1_high16bit_row = cap_info->cs1_row; + + return 0; +} + +int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type) +{ + void __iomem *test_addr; + u32 row = 0, bktmp, coltmp, bw; + ulong cs0_cap; + u32 byte_mask; + + if (cap_info->rank == 2) { + cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type); + + if (dram_type == DDR4) { + if (cap_info->dbw == 0) + bktmp = cap_info->bk + 2; + else + bktmp = cap_info->bk + 1; + } else { + bktmp = cap_info->bk; + } + bw = cap_info->bw; + coltmp = cap_info->col; + + /* + * because px30 support axi split,min bandwidth + * is 8bit. if cs0 is 32bit, cs1 may 32bit or 16bit + * so we check low 16bit data when detect cs1 row. + * if cs0 is 16bit/8bit, we check low 8bit data. + */ + if (bw == 2) + byte_mask = 0xFFFF; + else + byte_mask = 0xFF; + + /* detect cs1 row */ + for (row = cap_info->cs0_row; row > 12; row--) { + test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + cs0_cap + + (1ul << (row + bktmp + coltmp + bw - 1ul))); + writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap); + writel(PATTERN, test_addr); + + if (((readl(test_addr) & byte_mask) == + (PATTERN & byte_mask)) && + ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) & + byte_mask) == 0)) { + break; + } + } + } + + cap_info->cs1_row = row; + + return 0; +} diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_pctl_px30.c b/roms/u-boot/drivers/ram/rockchip/sdram_pctl_px30.c new file mode 100644 index 000000000..331d85fba --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_pctl_px30.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include + +/* + * rank = 1: cs0 + * rank = 2: cs1 + */ +void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num) +{ + writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0); + writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1); + setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); + while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) + continue; + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + continue; +} + +/* rank = 1: cs0 + * rank = 2: cs1 + * rank = 3: cs0 & cs1 + * note: be careful of keep mr original val + */ +int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, + u32 dramtype) +{ + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + continue; + if (dramtype == DDR3 || dramtype == DDR4) { + writel((mr_num << 12) | (rank << 4) | (0 << 0), + pctl_base + DDR_PCTL2_MRCTRL0); + writel(arg, pctl_base + DDR_PCTL2_MRCTRL1); + } else { + writel((rank << 4) | (0 << 0), + pctl_base + DDR_PCTL2_MRCTRL0); + writel((mr_num << 8) | (arg & 0xff), + pctl_base + DDR_PCTL2_MRCTRL1); + } + + setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31); + while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31)) + continue; + while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY) + continue; + + return 0; +} + +/* + * rank : 1:cs0, 2:cs1, 3:cs0&cs1 + * vrefrate: 4500: 45%, + */ +int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, + u32 dramtype) +{ + u32 tccd_l, value; + u32 dis_auto_zq = 0; + + if (dramtype != DDR4 || vrefrate < 4500 || + vrefrate > 9200) + return (-1); + + tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf; + tccd_l = (tccd_l - 4) << 10; + + if (vrefrate > 7500) { + /* range 1 */ + value = ((vrefrate - 6000) / 65) | tccd_l; + } else { + /* range 2 */ + value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6); + } + + dis_auto_zq = pctl_dis_zqcs_aref(pctl_base); + + /* enable vrefdq calibratin */ + pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); + udelay(1);/* tvrefdqe */ + /* write vrefdq value */ + pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); + udelay(1);/* tvref_time */ + pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype); + udelay(1);/* tvrefdqx */ + + pctl_rest_zqcs_aref(pctl_base, dis_auto_zq); + + return 0; +} + +static int upctl2_update_ref_reg(void __iomem *pctl_base) +{ + u32 ret; + + ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1); + writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3); + + return 0; +} + +u32 pctl_dis_zqcs_aref(void __iomem *pctl_base) +{ + u32 dis_auto_zq = 0; + + /* disable zqcs */ + if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) & + (1ul << 31))) { + dis_auto_zq = 1; + setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); + } + + /* disable auto refresh */ + setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); + + upctl2_update_ref_reg(pctl_base); + + return dis_auto_zq; +} + +void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq) +{ + /* restore zqcs */ + if (dis_auto_zq) + clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31); + + /* restore auto refresh */ + clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1); + + upctl2_update_ref_reg(pctl_base); +} + +u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs, + struct sdram_cap_info *cap_info, + u32 dram_type) +{ + u32 tmp = 0, tmp_adr = 0, i; + + for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) { + if (pctl_regs->pctl[i][0] == 0) { + tmp = pctl_regs->pctl[i][1];/* MSTR */ + tmp_adr = i; + } + } + + tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12)); + + switch (cap_info->dbw) { + case 2: + tmp |= (3ul << 30); + break; + case 1: + tmp |= (2ul << 30); + break; + case 0: + default: + tmp |= (1ul << 30); + break; + } + + /* + * If DDR3 or DDR4 MSTR.active_ranks=1, + * it will gate memory clock when enter power down. + * Force set active_ranks to 3 to workaround it. + */ + if (cap_info->rank == 2 || dram_type == DDR3 || + dram_type == DDR4) + tmp |= 3 << 24; + else + tmp |= 1 << 24; + + tmp |= (2 - cap_info->bw) << 12; + + pctl_regs->pctl[tmp_adr][1] = tmp; + + return 0; +} + +int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs, + u32 sr_idle, u32 pd_idle) +{ + u32 i; + + for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) { + writel(pctl_regs->pctl[i][1], + pctl_base + pctl_regs->pctl[i][0]); + } + clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG, + (0xff << 16) | 0x1f, + ((sr_idle & 0xff) << 16) | (pd_idle & 0x1f)); + + clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL, + 0xfff << 16, + 5 << 16); + /* disable zqcs */ + setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31); + + return 0; +} diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_phy_px30.c b/roms/u-boot/drivers/ram/rockchip/sdram_phy_px30.c new file mode 100644 index 000000000..f7f6de1ba --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_phy_px30.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void sdram_phy_dll_bypass_set(void __iomem *phy_base, u32 freq) +{ + u32 tmp; + u32 i, j; + u32 dqs_dll_freq; + + setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); + clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); + for (i = 0; i < 4; i++) { + j = 0x26 + i * 0x10; + setbits_le32(PHY_REG(phy_base, j), 1 << 4); + clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); + } + + if (freq <= 400) + /* DLL bypass */ + setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); + else + clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); + + #ifdef CONFIG_ROCKCHIP_RK3328 + dqs_dll_freq = 680; + #else + dqs_dll_freq = 801; + #endif + + if (freq <= dqs_dll_freq) + tmp = 2; + else + tmp = 1; + + for (i = 0; i < 4; i++) { + j = 0x28 + i * 0x10; + writel(tmp, PHY_REG(phy_base, j)); + } +} + +static void sdram_phy_set_ds_odt(void __iomem *phy_base, + u32 dram_type) +{ + u32 cmd_drv, clk_drv, dqs_drv, dqs_odt; + u32 i, j; + + if (dram_type == DDR3) { + cmd_drv = PHY_DDR3_RON_RTT_34ohm; + clk_drv = PHY_DDR3_RON_RTT_45ohm; + dqs_drv = PHY_DDR3_RON_RTT_34ohm; + dqs_odt = PHY_DDR3_RON_RTT_225ohm; + } else { + cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm; + clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm; + dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm; + if (dram_type == LPDDR2) + dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_DISABLE; + else + dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm; + } + /* DS */ + writel(cmd_drv, PHY_REG(phy_base, 0x11)); + clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3); + writel(clk_drv, PHY_REG(phy_base, 0x16)); + writel(clk_drv, PHY_REG(phy_base, 0x18)); + + for (i = 0; i < 4; i++) { + j = 0x20 + i * 0x10; + writel(dqs_drv, PHY_REG(phy_base, j)); + writel(dqs_drv, PHY_REG(phy_base, j + 0xf)); + /* ODT */ + writel(dqs_odt, PHY_REG(phy_base, j + 0x1)); + writel(dqs_odt, PHY_REG(phy_base, j + 0xe)); + } +} + +void phy_soft_reset(void __iomem *phy_base) +{ + clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2); + udelay(1); + setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET); + udelay(5); + setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET); + udelay(1); +} + +void phy_dram_set_bw(void __iomem *phy_base, u32 bw) +{ + if (bw == 2) { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); + setbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); + setbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); + } else if (bw == 1) { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); + clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); + clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); + } else if (bw == 0) { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4); + clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3); + clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); + clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); + } + + phy_soft_reset(phy_base); +} + +int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype) +{ + u32 ret; + u32 odt_val; + u32 i, j; + + odt_val = readl(PHY_REG(phy_base, 0x2e)); + + for (i = 0; i < 4; i++) { + j = 0x20 + i * 0x10; + writel(PHY_DDR3_RON_RTT_225ohm, PHY_REG(phy_base, j + 0x1)); + writel(0, PHY_REG(phy_base, j + 0xe)); + } + + if (dramtype == DDR4) { + clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0); + clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0); + clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0); + clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0); + } + /* choose training cs */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); + /* enable gate training */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); + udelay(50); + ret = readl(PHY_REG(phy_base, 0xff)); + /* disable gate training */ + clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0); + #ifndef CONFIG_ROCKCHIP_RK3328 + clrbits_le32(PHY_REG(phy_base, 2), 0x30); + #endif + + if (dramtype == DDR4) { + clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2); + clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2); + clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2); + clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2); + } + + if (ret & 0x10) { + ret = -1; + } else { + ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4); + ret = (ret == 0) ? 0 : -1; + } + + for (i = 0; i < 4; i++) { + j = 0x20 + i * 0x10; + writel(odt_val, PHY_REG(phy_base, j + 0x1)); + writel(odt_val, PHY_REG(phy_base, j + 0xe)); + } + return ret; +} + +void phy_cfg(void __iomem *phy_base, + struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, + struct sdram_base_params *base, u32 bw) +{ + u32 i; + + sdram_phy_dll_bypass_set(phy_base, base->ddr_freq); + for (i = 0; phy_regs->phy[i][0] != 0xFFFFFFFF; i++) { + writel(phy_regs->phy[i][1], + phy_base + phy_regs->phy[i][0]); + } + if (bw == 2) { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); + } else if (bw == 1) { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); + /* disable DQS2,DQS3 tx dll for saving power */ + clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); + clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); + } else { + clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4); + /* disable DQS2,DQS3 tx dll for saving power */ + clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3); + clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); + clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); + } + sdram_phy_set_ds_odt(phy_base, base->dramtype); + + /* deskew */ + setbits_le32(PHY_REG(phy_base, 2), 8); + sdram_copy_to_reg(PHY_REG(phy_base, 0xb0), + &skew->a0_a1_skew[0], 15 * 4); + sdram_copy_to_reg(PHY_REG(phy_base, 0x70), + &skew->cs0_dm0_skew[0], 44 * 4); + sdram_copy_to_reg(PHY_REG(phy_base, 0xc0), + &skew->cs1_dm0_skew[0], 44 * 4); +} diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_px30.c b/roms/u-boot/drivers/ram/rockchip/sdram_px30.c new file mode 100644 index 000000000..c024a0cd6 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_px30.c @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct dram_info { +#ifdef CONFIG_TPL_BUILD + struct ddr_pctl_regs *pctl; + struct ddr_phy_regs *phy; + struct px30_cru *cru; + struct msch_regs *msch; + struct px30_ddr_grf_regs *ddr_grf; + struct px30_grf *grf; +#endif + struct ram_info info; + struct px30_pmugrf *pmugrf; +}; + +#ifdef CONFIG_TPL_BUILD + +u8 ddr_cfg_2_rbc[] = { + /* + * [6:4] max row: 13+n + * [3] bank(0:4bank,1:8bank) + * [2:0] col(10+n) + */ + ((5 << 4) | (1 << 3) | 0), /* 0 */ + ((5 << 4) | (1 << 3) | 1), /* 1 */ + ((4 << 4) | (1 << 3) | 2), /* 2 */ + ((3 << 4) | (1 << 3) | 3), /* 3 */ + ((2 << 4) | (1 << 3) | 4), /* 4 */ + ((5 << 4) | (0 << 3) | 2), /* 5 */ + ((4 << 4) | (1 << 3) | 2), /* 6 */ + /*((0<<3)|3),*/ /* 12 for ddr4 */ + /*((1<<3)|1),*/ /* 13 B,C exchange for rkvdec */ +}; + +/* + * for ddr4 if ddrconfig=7, upctl should set 7 and noc should + * set to 1 for more efficient. + * noc ddrconf, upctl addrmap + * 1 7 + * 2 8 + * 3 9 + * 12 10 + * 5 11 + */ +u8 d4_rbc_2_d3_rbc[] = { + 1, /* 7 */ + 2, /* 8 */ + 3, /* 9 */ + 12, /* 10 */ + 5, /* 11 */ +}; + +/* + * row higher than cs should be disabled by set to 0xf + * rank addrmap calculate by real cap. + */ +u32 addrmap[][8] = { + /* map0 map1, map2, map3, map4, map5 + * map6, map7, map8 + * ------------------------------------------------------- + * bk2-0 col 5-2 col 9-6 col 11-10 row 11-0 + * row 15-12 row 17-16 bg1,0 + * ------------------------------------------------------- + * 4,3,2 5-2 9-6 6 + * 3,2 + */ + {0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505, + 0x05050505, 0x00000505, 0x3f3f}, /* 0 */ + {0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x06060606, 0x3f3f}, /* 1 */ + {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f3f}, /* 2 */ + {0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, + 0x08080808, 0x00000f0f, 0x3f3f}, /* 3 */ + {0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, + 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */ + {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000606, 0x3f3f}, /* 5 */ + {0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f0f, 0x3f3f}, /* 6 */ + {0x003f0808, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000606, 0x0600}, /* 7 */ + {0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x0700}, /* 8 */ + {0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, + 0x08080808, 0x00000f0f, 0x0801}, /* 9 */ + {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ + {0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000606, 0x3f00}, /* 11 */ + /* when ddr4 12 map to 10, when ddr3 12 unused */ + {0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, + 0x07070707, 0x00000f07, 0x3f01}, /* 10 */ + {0x00070706, 0x00000000, 0x1f010000, 0x00001f1f, 0x06060606, + 0x06060606, 0x00000606, 0x3f3f}, /* 13 */ +}; + +#define PMUGRF_BASE_ADDR 0xFF010000 +#define CRU_BASE_ADDR 0xFF2B0000 +#define GRF_BASE_ADDR 0xFF140000 +#define DDRC_BASE_ADDR 0xFF600000 +#define DDR_PHY_BASE_ADDR 0xFF2A0000 +#define SERVER_MSCH0_BASE_ADDR 0xFF530000 +#define DDR_GRF_BASE_ADDR 0xff630000 + +struct dram_info dram_info; + +struct px30_sdram_params sdram_configs[] = { +#if defined(CONFIG_RAM_PX30_DDR4) +#include "sdram-px30-ddr4-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR2) +#include "sdram-px30-lpddr2-detect-333.inc" +#elif defined(CONFIG_RAM_PX30_LPDDR3) +#include "sdram-px30-lpddr3-detect-333.inc" +#else +#include "sdram-px30-ddr3-detect-333.inc" +#endif +}; + +struct ddr_phy_skew skew = { +#include "sdram-px30-ddr_skew.inc" +}; + +static void rkclk_ddr_reset(struct dram_info *dram, + u32 ctl_srstn, u32 ctl_psrstn, + u32 phy_srstn, u32 phy_psrstn) +{ + writel(upctl2_srstn_req(ctl_srstn) | upctl2_psrstn_req(ctl_psrstn) | + upctl2_asrstn_req(ctl_srstn), + &dram->cru->softrst_con[1]); + writel(ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn), + &dram->cru->softrst_con[2]); +} + +static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) +{ + unsigned int refdiv, postdiv1, postdiv2, fbdiv; + int delay = 1000; + u32 mhz = hz / MHz; + + refdiv = 1; + if (mhz <= 300) { + postdiv1 = 4; + postdiv2 = 2; + } else if (mhz <= 400) { + postdiv1 = 6; + postdiv2 = 1; + } else if (mhz <= 600) { + postdiv1 = 4; + postdiv2 = 1; + } else if (mhz <= 800) { + postdiv1 = 3; + postdiv2 = 1; + } else if (mhz <= 1600) { + postdiv1 = 2; + postdiv2 = 1; + } else { + postdiv1 = 1; + postdiv2 = 1; + } + fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; + + writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); + + writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); + writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), + &dram->cru->pll[1].con1); + + while (delay > 0) { + udelay(1); + if (LOCK(readl(&dram->cru->pll[1].con1))) + break; + delay--; + } + + writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); +} + +static void rkclk_configure_ddr(struct dram_info *dram, + struct px30_sdram_params *sdram_params) +{ + /* for inno ddr phy need 2*freq */ + rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHz * 2); +} + +/* return ddrconfig value + * (-1), find ddrconfig fail + * other, the ddrconfig value + * only support cs0_row >= cs1_row + */ +static unsigned int calculate_ddrconfig(struct px30_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 bw, die_bw, col, bank; + u32 i, tmp; + u32 ddrconf = -1; + + bw = cap_info->bw; + die_bw = cap_info->dbw; + col = cap_info->col; + bank = cap_info->bk; + + if (sdram_params->base.dramtype == DDR4) { + if (die_bw == 0) + ddrconf = 7 + bw; + else + ddrconf = 12 - bw; + ddrconf = d4_rbc_2_d3_rbc[ddrconf - 7]; + } else { + tmp = ((bank - 2) << 3) | (col + bw - 10); + for (i = 0; i < 7; i++) + if ((ddr_cfg_2_rbc[i] & 0xf) == tmp) { + ddrconf = i; + break; + } + if (i > 6) + printascii("calculate ddrconfig error\n"); + } + + return ddrconf; +} + +/* + * calculate controller dram address map, and setting to register. + * argument sdram_params->ch.ddrconf must be right value before + * call this function. + */ +static void set_ctl_address_map(struct dram_info *dram, + struct px30_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *pctl_base = dram->pctl; + u32 cs_pst, bg, max_row, ddrconf; + u32 i; + + if (sdram_params->base.dramtype == DDR4) + /* + * DDR4 8bit dram BG = 2(4bank groups), + * 16bit dram BG = 1 (2 bank groups) + */ + bg = (cap_info->dbw == 0) ? 2 : 1; + else + bg = 0; + + cs_pst = cap_info->bw + cap_info->col + + bg + cap_info->bk + cap_info->cs0_row; + if (cs_pst >= 32 || cap_info->rank == 1) + writel(0x1f, pctl_base + DDR_PCTL2_ADDRMAP0); + else + writel(cs_pst - 8, pctl_base + DDR_PCTL2_ADDRMAP0); + + ddrconf = cap_info->ddrconfig; + if (sdram_params->base.dramtype == DDR4) { + for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc); i++) { + if (d4_rbc_2_d3_rbc[i] == ddrconf) { + ddrconf = 7 + i; + break; + } + } + } + + sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP1), + &addrmap[ddrconf][0], 8 * 4); + max_row = cs_pst - 1 - 8 - (addrmap[ddrconf][5] & 0xf); + + if (max_row < 12) + printascii("set addrmap fail\n"); + /* need to disable row ahead of rank by set to 0xf */ + for (i = 17; i > max_row; i--) + clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + + ((i - 12) * 8 / 32) * 4, + 0xf << ((i - 12) * 8 % 32), + 0xf << ((i - 12) * 8 % 32)); + + if ((sdram_params->base.dramtype == LPDDR3 || + sdram_params->base.dramtype == LPDDR2) && + cap_info->row_3_4) + setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); + if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) + setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); +} + +/* + * rank = 1: cs0 + * rank = 2: cs1 + */ +int read_mr(struct dram_info *dram, u32 rank, u32 mr_num) +{ + void __iomem *ddr_grf_base = dram->ddr_grf; + + pctl_read_mr(dram->pctl, rank, mr_num); + + return (readl(ddr_grf_base + DDR_GRF_STATUS(0)) & 0xff); +} + +#define MIN(a, b) (((a) > (b)) ? (b) : (a)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +static u32 check_rd_gate(struct dram_info *dram) +{ + void __iomem *phy_base = dram->phy; + + u32 max_val = 0; + u32 min_val = 0xff; + u32 gate[4]; + u32 i, bw; + + bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; + switch (bw) { + case 0x1: + bw = 1; + break; + case 0x3: + bw = 2; + break; + case 0xf: + default: + bw = 4; + break; + } + + for (i = 0; i < bw; i++) { + gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); + max_val = MAX(max_val, gate[i]); + min_val = MIN(min_val, gate[i]); + } + + if (max_val > 0x80 || min_val < 0x20) + return -1; + else + return 0; +} + +static int data_training(struct dram_info *dram, u32 cs, u32 dramtype) +{ + void __iomem *pctl_base = dram->pctl; + u32 dis_auto_zq = 0; + u32 pwrctl; + u32 ret; + + /* disable auto low-power */ + pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); + writel(0, pctl_base + DDR_PCTL2_PWRCTL); + + dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); + + ret = phy_data_training(dram->phy, cs, dramtype); + + pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); + + /* restore auto low-power */ + writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); + + return ret; +} + +static void dram_set_bw(struct dram_info *dram, u32 bw) +{ + phy_dram_set_bw(dram->phy, bw); +} + +static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) +{ + writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf); + rk_clrsetreg(&dram->grf->soc_noc_con[1], 0x3 << 14, 0 << 14); +} + +static void sdram_msch_config(struct msch_regs *msch, + struct sdram_msch_timings *noc_timings, + struct sdram_cap_info *cap_info, + struct sdram_base_params *base) +{ + u64 cs_cap[2]; + + cs_cap[0] = sdram_get_cs_cap(cap_info, 0, base->dramtype); + cs_cap[1] = sdram_get_cs_cap(cap_info, 1, base->dramtype); + writel(((((cs_cap[1] >> 20) / 64) & 0xff) << 8) | + (((cs_cap[0] >> 20) / 64) & 0xff), + &msch->devicesize); + + writel(noc_timings->ddrtiminga0.d32, + &msch->ddrtiminga0); + writel(noc_timings->ddrtimingb0.d32, + &msch->ddrtimingb0); + writel(noc_timings->ddrtimingc0.d32, + &msch->ddrtimingc0); + writel(noc_timings->devtodev0.d32, + &msch->devtodev0); + writel(noc_timings->ddrmode.d32, &msch->ddrmode); + writel(noc_timings->ddr4timing.d32, + &msch->ddr4timing); + writel(noc_timings->agingx0, &msch->agingx0); + writel(noc_timings->agingx0, &msch->aging0); + writel(noc_timings->agingx0, &msch->aging1); + writel(noc_timings->agingx0, &msch->aging2); + writel(noc_timings->agingx0, &msch->aging3); +} + +static void dram_all_config(struct dram_info *dram, + struct px30_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 sys_reg2 = 0; + u32 sys_reg3 = 0; + + set_ddrconfig(dram, cap_info->ddrconfig); + sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, + &sys_reg3, 0); + writel(sys_reg2, &dram->pmugrf->os_reg[2]); + writel(sys_reg3, &dram->pmugrf->os_reg[3]); + sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info, + &sdram_params->base); +} + +static void enable_low_power(struct dram_info *dram, + struct px30_sdram_params *sdram_params) +{ + void __iomem *pctl_base = dram->pctl; + void __iomem *phy_base = dram->phy; + void __iomem *ddr_grf_base = dram->ddr_grf; + u32 grf_lp_con; + + /* + * bit0: grf_upctl_axi_cg_en = 1 enable upctl2 axi clk auto gating + * bit1: grf_upctl_apb_cg_en = 1 ungated axi,core clk for apb access + * bit2: grf_upctl_core_cg_en = 1 enable upctl2 core clk auto gating + * bit3: grf_selfref_type2_en = 0 disable core clk gating when type2 sr + * bit4: grf_upctl_syscreq_cg_en = 1 + * ungating coreclk when c_sysreq assert + * bit8-11: grf_auto_sr_dly = 6 + */ + writel(0x1f1f0617, &dram->ddr_grf->ddr_grf_con[1]); + + if (sdram_params->base.dramtype == DDR4) + grf_lp_con = (0x7 << 16) | (1 << 1); + else if (sdram_params->base.dramtype == DDR3) + grf_lp_con = (0x7 << 16) | (1 << 0); + else + grf_lp_con = (0x7 << 16) | (1 << 2); + + /* en lpckdis_en */ + grf_lp_con = grf_lp_con | (0x1 << (9 + 16)) | (0x1 << 9); + writel(grf_lp_con, ddr_grf_base + DDR_GRF_LP_CON); + + /* off digit module clock when enter power down */ + setbits_le32(PHY_REG(phy_base, 7), 1 << 7); + + /* enable sr, pd */ + if (PD_IDLE == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + if (SR_IDLE == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); +} + +/* + * pre_init: 0: pre init for dram cap detect + * 1: detect correct cap(except cs1 row)info, than reinit + * 2: after reinit, we detect cs1_row, if cs1_row not equal + * to cs0_row and cs is in middle on ddrconf map, we need + * to reinit dram, than set the correct ddrconf. + */ +static int sdram_init_(struct dram_info *dram, + struct px30_sdram_params *sdram_params, u32 pre_init) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *pctl_base = dram->pctl; + + rkclk_ddr_reset(dram, 1, 1, 1, 1); + udelay(10); + /* + * dereset ddr phy psrstn to config pll, + * if using phy pll psrstn must be dereset + * before config pll + */ + rkclk_ddr_reset(dram, 1, 1, 1, 0); + rkclk_configure_ddr(dram, sdram_params); + + /* release phy srst to provide clk to ctrl */ + rkclk_ddr_reset(dram, 1, 1, 0, 0); + udelay(10); + phy_soft_reset(dram->phy); + /* release ctrl presetn, and config ctl registers */ + rkclk_ddr_reset(dram, 1, 0, 0, 0); + pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); + cap_info->ddrconfig = calculate_ddrconfig(sdram_params); + set_ctl_address_map(dram, sdram_params); + phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew, + &sdram_params->base, cap_info->bw); + + /* enable dfi_init_start to init phy after ctl srstn deassert */ + setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); + + rkclk_ddr_reset(dram, 0, 0, 0, 0); + /* wait for dfi_init_done and dram init complete */ + while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) + continue; + + if (sdram_params->base.dramtype == LPDDR3) + pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3); + + /* do ddr gate training */ +redo_cs0_training: + if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { + if (pre_init != 0) + printascii("DTT cs0 error\n"); + return -1; + } + if (check_rd_gate(dram)) { + printascii("re training cs0"); + goto redo_cs0_training; + } + + if (sdram_params->base.dramtype == LPDDR3) { + if ((read_mr(dram, 1, 8) & 0x3) != 0x3) + return -1; + } else if (sdram_params->base.dramtype == LPDDR2) { + if ((read_mr(dram, 1, 8) & 0x3) != 0x0) + return -1; + } + /* for px30: when 2cs, both 2 cs should be training */ + if (pre_init != 0 && cap_info->rank == 2) { +redo_cs1_training: + if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { + printascii("DTT cs1 error\n"); + return -1; + } + if (check_rd_gate(dram)) { + printascii("re training cs1"); + goto redo_cs1_training; + } + } + + if (sdram_params->base.dramtype == DDR4) + pctl_write_vrefdq(dram->pctl, 0x3, 5670, + sdram_params->base.dramtype); + + dram_all_config(dram, sdram_params); + enable_low_power(dram, sdram_params); + + return 0; +} + +static int dram_detect_cap(struct dram_info *dram, + struct px30_sdram_params *sdram_params, + unsigned char channel) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + + /* + * for ddr3: ddrconf = 3 + * for ddr4: ddrconf = 12 + * for lpddr3: ddrconf = 3 + * default bw = 1 + */ + u32 bk, bktmp; + u32 col, coltmp; + u32 rowtmp; + u32 cs; + u32 bw = 1; + u32 dram_type = sdram_params->base.dramtype; + + if (dram_type != DDR4) { + /* detect col and bk for ddr3/lpddr3 */ + coltmp = 12; + bktmp = 3; + if (dram_type == LPDDR2) + rowtmp = 15; + else + rowtmp = 16; + + if (sdram_detect_col(cap_info, coltmp) != 0) + goto cap_err; + sdram_detect_bank(cap_info, coltmp, bktmp); + sdram_detect_dbw(cap_info, dram_type); + } else { + /* detect bg for ddr4 */ + coltmp = 10; + bktmp = 4; + rowtmp = 17; + + col = 10; + bk = 2; + cap_info->col = col; + cap_info->bk = bk; + sdram_detect_bg(cap_info, coltmp); + } + + /* detect row */ + if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0) + goto cap_err; + + /* detect row_3_4 */ + sdram_detect_row_3_4(cap_info, coltmp, bktmp); + + /* bw and cs detect using data training */ + if (data_training(dram, 1, dram_type) == 0) + cs = 1; + else + cs = 0; + cap_info->rank = cs + 1; + + dram_set_bw(dram, 2); + if (data_training(dram, 0, dram_type) == 0) + bw = 2; + else + bw = 1; + cap_info->bw = bw; + + cap_info->cs0_high16bit_row = cap_info->cs0_row; + if (cs) { + cap_info->cs1_row = cap_info->cs0_row; + cap_info->cs1_high16bit_row = cap_info->cs0_row; + } else { + cap_info->cs1_row = 0; + cap_info->cs1_high16bit_row = 0; + } + + return 0; +cap_err: + return -1; +} + +/* return: 0 = success, other = fail */ +static int sdram_init_detect(struct dram_info *dram, + struct px30_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 ret; + u32 sys_reg = 0; + u32 sys_reg3 = 0; + + if (sdram_init_(dram, sdram_params, 0) != 0) + return -1; + + if (dram_detect_cap(dram, sdram_params, 0) != 0) + return -1; + + /* modify bw, cs related timing */ + pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, + sdram_params->base.dramtype); + /* reinit sdram by real dram cap */ + ret = sdram_init_(dram, sdram_params, 1); + if (ret != 0) + goto out; + + /* redetect cs1 row */ + sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); + if (cap_info->cs1_row) { + sys_reg = readl(&dram->pmugrf->os_reg[2]); + sys_reg3 = readl(&dram->pmugrf->os_reg[3]); + SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, + sys_reg, sys_reg3, 0); + writel(sys_reg, &dram->pmugrf->os_reg[2]); + writel(sys_reg3, &dram->pmugrf->os_reg[3]); + } + + ret = sdram_detect_high_row(cap_info); + +out: + return ret; +} + +struct px30_sdram_params + *get_default_sdram_config(void) +{ + sdram_configs[0].skew = &skew; + + return &sdram_configs[0]; +} + +/* return: 0 = success, other = fail */ +int sdram_init(void) +{ + struct px30_sdram_params *sdram_params; + int ret = 0; + + dram_info.phy = (void *)DDR_PHY_BASE_ADDR; + dram_info.pctl = (void *)DDRC_BASE_ADDR; + dram_info.grf = (void *)GRF_BASE_ADDR; + dram_info.cru = (void *)CRU_BASE_ADDR; + dram_info.msch = (void *)SERVER_MSCH0_BASE_ADDR; + dram_info.ddr_grf = (void *)DDR_GRF_BASE_ADDR; + dram_info.pmugrf = (void *)PMUGRF_BASE_ADDR; + + sdram_params = get_default_sdram_config(); + ret = sdram_init_detect(&dram_info, sdram_params); + + if (ret) + goto error; + + sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base); + + printascii("out\n"); + return ret; +error: + return (-1); +} +#else + +static int px30_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: grf=%p\n", __func__, priv->pmugrf); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); + + return 0; +} + +static int px30_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops px30_dmc_ops = { + .get_info = px30_dmc_get_info, +}; + +static const struct udevice_id px30_dmc_ids[] = { + { .compatible = "rockchip,px30-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_px30) = { + .name = "rockchip_px30_dmc", + .id = UCLASS_RAM, + .of_match = px30_dmc_ids, + .ops = &px30_dmc_ops, + .probe = px30_dmc_probe, + .priv_auto = sizeof(struct dram_info), +}; +#endif /* CONFIG_TPL_BUILD */ diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_rk3128.c b/roms/u-boot/drivers/ram/rockchip/sdram_rk3128.c new file mode 100644 index 000000000..16cfbf947 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_rk3128.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct dram_info { + struct ram_info info; + struct rk3128_grf *grf; +}; + +static int rk3128_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->grf->os_reg[1]); + + return 0; +} + +static int rk3128_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3128_dmc_ops = { + .get_info = rk3128_dmc_get_info, +}; + +static const struct udevice_id rk3128_dmc_ids[] = { + { .compatible = "rockchip,rk3128-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3128) = { + .name = "rockchip_rk3128_dmc", + .id = UCLASS_RAM, + .of_match = rk3128_dmc_ids, + .ops = &rk3128_dmc_ops, + .probe = rk3128_dmc_probe, + .priv_auto = sizeof(struct dram_info), +}; diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_rk3188.c b/roms/u-boot/drivers/ram/rockchip/sdram_rk3188.c new file mode 100644 index 000000000..25ae69e9a --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_rk3188.c @@ -0,0 +1,960 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * Adapted from the very similar rk3288 ddr init. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct chan_info { + struct rk3288_ddr_pctl *pctl; + struct rk3288_ddr_publ *publ; + struct rk3188_msch *msch; +}; + +struct dram_info { + struct chan_info chan[1]; + struct ram_info info; + struct clk ddr_clk; + struct rk3188_cru *cru; + struct rk3188_grf *grf; + struct rk3188_sgrf *sgrf; + struct rk3188_pmu *pmu; +}; + +struct rk3188_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3188_dmc of_plat; +#endif + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + struct rk3288_base_params base; + int num_channels; + struct regmap *map; +}; + +const int ddrconf_table[] = { + /* + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + * row col,bw + */ + 0, + ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#define TEST_PATTEN 0x5aa5f00f +#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) +#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) + +#ifdef CONFIG_SPL_BUILD +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) +{ + u32 phy_ctl_srstn_shift = 13; + u32 ctl_psrstn_shift = 11; + u32 ctl_srstn_shift = 10; + u32 phy_psrstn_shift = 9; + u32 phy_srstn_shift = 8; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | + 1 << phy_srstn_shift, + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | + ctl << ctl_srstn_shift | phy << phy_psrstn_shift | + phy << phy_srstn_shift); +} + +static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n) +{ + u32 phy_ctl_srstn_shift = 13; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); +} + +static void phy_pctrl_reset(struct rk3188_cru *cru, + struct rk3288_ddr_publ *publ, + int channel) +{ + int i; + + ddr_reset(cru, channel, 1, 1); + udelay(1); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + ddr_reset(cru, channel, 1, 0); + udelay(10); + ddr_reset(cru, channel, 0, 0); + udelay(10); +} + +static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, + u32 freq) +{ + int i; + + if (freq <= 250000000) { + if (freq <= 150000000) + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + else + setbits_le32(&publ->dllgcr, SBIAS_BYPASS); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + + setbits_le32(&publ->pir, PIR_DLLBYP); + } else { + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) { + clrbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + } + + clrbits_le32(&publ->pir, PIR_DLLBYP); + } +} + +static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) +{ + writel(DFI_INIT_START, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); + writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); + writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); + writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); + writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); + writel(1, &pctl->dfitphyupdtype0); + + /* cs0 and cs1 write odt enable */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + /* odt write length */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + /* phyupd and ctrlupd disabled */ + writel(0, &pctl->dfiupdcfg); +} + +static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable) +{ + uint val = 0; + + if (enable) + val = 1 << DDR_16BIT_EN_SHIFT; + + rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val); +} + +static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel, + bool ddr3_mode) +{ + uint mask, val; + + mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; + val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable) +{ + uint mask, val; + + mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; + val = enable << RANK_TO_ROW15_EN_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, + struct rk3188_sdram_params *sdram_params, + struct rk3188_grf *grf) +{ + copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, + sizeof(sdram_params->pctl_timing)); + switch (sdram_params->base.dramtype) { + case DDR3: + if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { + writel(sdram_params->pctl_timing.tcl - 3, + &pctl->dfitrddataen); + } else { + writel(sdram_params->pctl_timing.tcl - 2, + &pctl->dfitrddataen); + } + writel(sdram_params->pctl_timing.tcwl - 1, + &pctl->dfitphywrlat); + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + ddr_set_ddr3_mode(grf, channel, true); + ddr_set_enable(grf, channel, true); + break; + } + + setbits_le32(&pctl->scfg, 1); +} + +static void phy_cfg(const struct chan_info *chan, int channel, + struct rk3188_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; + u32 dinit2; + int i; + + dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); + /* DDR PHY Timing */ + copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, + sizeof(sdram_params->phy_timing)); + writel(sdram_params->base.noc_timing, &msch->ddrtiming); + writel(0x3f, &msch->readlatency); + writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | + 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); + writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, + &publ->ptr[1]); + writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, + &publ->ptr[2]); + + switch (sdram_params->base.dramtype) { + case DDR3: + clrbits_le32(&publ->pgcr, 0x1f); + clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, + DDRMD_DDR3 << DDRMD_SHIFT); + break; + } + if (sdram_params->base.odt) { + /*dynamic RTT enable */ + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } else { + /*dynamic RTT disable */ + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } +} + +static void phy_init(struct rk3288_ddr_publ *publ) +{ + setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST + | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); + udelay(1); + while ((readl(&publ->pgsr) & + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) + ; +} + +static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, + u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static inline void send_command_op(struct rk3288_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 ma, u32 op) +{ + send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | + (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); +} + +static void memory_init(struct rk3288_ddr_publ *publ, + u32 dramtype) +{ + setbits_le32(&publ->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + udelay(1); + while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) + != (PGSR_IDONE | PGSR_DLDONE)) + ; +} + +static void move_to_config_state(struct rk3288_ddr_publ *publ, + struct rk3288_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) + != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + /* + * if at low power state,need wakeup first, + * and then enter the config, so + * fallthrough + */ + case ACCESS: + /* fallthrough */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void set_bandwidth_ratio(const struct chan_info *chan, int channel, + u32 n, struct rk3188_grf *grf) +{ + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + + if (n == 1) { + setbits_le32(&pctl->ppcfg, 1); + ddr_set_enable(grf, channel, 1); + setbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte disable*/ + clrbits_le32(&publ->datx8[2].dxgcr, 1); + clrbits_le32(&publ->datx8[3].dxgcr, 1); + /* disable DLL */ + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + } else { + clrbits_le32(&pctl->ppcfg, 1); + ddr_set_enable(grf, channel, 0); + clrbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte enable*/ + setbits_le32(&publ->datx8[2].dxgcr, 1); + setbits_le32(&publ->datx8[3].dxgcr, 1); + + /* enable DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + /* reset DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + udelay(10); + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + } + setbits_le32(&pctl->dfistcfg0, 1 << 2); +} + +static int data_training(const struct chan_info *chan, int channel, + struct rk3188_sdram_params *sdram_params) +{ + unsigned int j; + int ret = 0; + u32 rank; + int i; + u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + + /* disable auto refresh */ + writel(0, &pctl->trefi); + + if (sdram_params->base.dramtype != LPDDR3) + setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + rank = sdram_params->ch[channel].rank | 1; + for (j = 0; j < ARRAY_SIZE(step); j++) { + /* + * trigger QSTRN and RVTRN + * clear DTDONE status + */ + setbits_le32(&publ->pir, PIR_CLRSR); + + /* trigger DTT */ + setbits_le32(&publ->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); + udelay(1); + /* wait echo byte DTDONE */ + while ((readl(&publ->datx8[0].dxgsr[0]) & rank) + != rank) + ; + while ((readl(&publ->datx8[1].dxgsr[0]) & rank) + != rank) + ; + if (!(readl(&pctl->ppcfg) & 1)) { + while ((readl(&publ->datx8[2].dxgsr[0]) + & rank) != rank) + ; + while ((readl(&publ->datx8[3].dxgsr[0]) + & rank) != rank) + ; + } + if (readl(&publ->pgsr) & + (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { + ret = -1; + break; + } + } + /* send some auto refresh to complement the lost while DTT */ + for (i = 0; i < (rank > 1 ? 8 : 4); i++) + send_command(pctl, rank, REF_CMD, 0); + + if (sdram_params->base.dramtype != LPDDR3) + clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + + /* resume auto refresh */ + writel(sdram_params->pctl_timing.trefi, &pctl->trefi); + + return ret; +} + +static void move_to_access_state(const struct chan_info *chan) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, + struct rk3188_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + + if (sdram_params->ch[chnum].bk == 3) + clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, + 1 << PDQ_SHIFT); + else + clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); + + writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); +} + +static void dram_all_config(const struct dram_info *dram, + struct rk3188_sdram_params *sdram_params) +{ + unsigned int chan; + u32 sys_reg = 0; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (chan = 0; chan < sdram_params->num_channels; chan++) { + const struct rk3288_sdram_channel *info = + &sdram_params->ch[chan]; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); + } + if (sdram_params->ch[0].rank == 2) + ddr_rank_2_row15en(dram->grf, 0); + else + ddr_rank_2_row15en(dram->grf, 1); + + writel(sys_reg, &dram->pmu->sys_reg[2]); +} + +static int sdram_rank_bw_detect(struct dram_info *dram, int channel, + struct rk3188_sdram_params *sdram_params) +{ + int reg; + int need_trainig = 0; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_publ *publ = chan->publ; + + ddr_rank_2_row15en(dram->grf, 0); + + if (data_training(chan, channel, sdram_params) < 0) { + printf("first data training fail!\n"); + reg = readl(&publ->datx8[0].dxgsr[0]); + /* Check the result for rank 0 */ + if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { + printf("data training fail!\n"); + return -EIO; + } + + /* Check the result for rank 1 */ + if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { + sdram_params->ch[channel].rank = 1; + clrsetbits_le32(&publ->pgcr, 0xF << 18, + sdram_params->ch[channel].rank << 18); + need_trainig = 1; + } + reg = readl(&publ->datx8[2].dxgsr[0]); + if (reg & (1 << 4)) { + sdram_params->ch[channel].bw = 1; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, + dram->grf); + need_trainig = 1; + } + } + /* Assume the Die bit width are the same with the chip bit width */ + sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; + + if (need_trainig && + (data_training(chan, channel, sdram_params) < 0)) { + if (sdram_params->base.dramtype == LPDDR3) { + ddr_phy_ctl_reset(dram->cru, channel, 1); + udelay(10); + ddr_phy_ctl_reset(dram->cru, channel, 0); + udelay(10); + } + printf("2nd data training failed!"); + return -EIO; + } + + return 0; +} + +/* + * Detect ram columns and rows. + * @dram: dram info struct + * @channel: channel number to handle + * @sdram_params: sdram parameters, function will fill in col and row values + * + * Returns 0 or negative on error. + */ +static int sdram_col_row_detect(struct dram_info *dram, int channel, + struct rk3188_sdram_params *sdram_params) +{ + int row, col; + unsigned int addr; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + int ret = 0; + + /* Detect col */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + sdram_params->ch[channel].bw - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + printf("Col detect error\n"); + ret = -EINVAL; + goto out; + } else { + sdram_params->ch[channel].col = col; + } + + ddr_rank_2_row15en(dram->grf, 1); + move_to_config_state(publ, pctl); + writel(1, &chan->msch->ddrconf); + move_to_access_state(chan); + /* Detect row, max 15,min13 in rk3188*/ + for (row = 16; row >= 13; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 12) { + printf("Row detect error\n"); + ret = -EINVAL; + } else { + sdram_params->ch[channel].cs1_row = row; + sdram_params->ch[channel].row_3_4 = 0; + debug("chn %d col %d, row %d\n", channel, col, row); + sdram_params->ch[channel].cs0_row = row; + } + +out: + return ret; +} + +static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params) +{ + int i, tmp, size, row, ret = 0; + + row = sdram_params->ch[0].cs0_row; + /* + * RK3188 share the rank and row bit15, we use same ddr config for 15bit + * and 16bit row + */ + if (row == 16) + row = 15; + tmp = sdram_params->ch[0].col - 9; + tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; + tmp |= ((row - 13) << 4); + size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); + for (i = 0; i < size; i++) + if (tmp == ddrconf_table[i]) + break; + if (i >= size) { + printf("niu config not found\n"); + ret = -EINVAL; + } else { + debug("niu config %d\n", i); + sdram_params->base.ddrconfig = i; + } + + return ret; +} + +static int sdram_init(struct dram_info *dram, + struct rk3188_sdram_params *sdram_params) +{ + int channel; + int zqcr; + int ret; + + if ((sdram_params->base.dramtype == DDR3 && + sdram_params->base.ddr_freq > 800000000)) { + printf("SDRAM frequency is too high!"); + return -E2BIG; + } + + ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); + if (ret) { + printf("Could not set DDR clock\n"); + return ret; + } + + for (channel = 0; channel < 1; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + + phy_pctrl_reset(dram->cru, publ, channel); + phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); + + dfi_cfg(pctl, sdram_params->base.dramtype); + + pctl_cfg(channel, pctl, sdram_params, dram->grf); + + phy_cfg(chan, channel, sdram_params); + + phy_init(publ); + + writel(POWER_UP_START, &pctl->powctl); + while (!(readl(&pctl->powstat) & POWER_UP_DONE)) + ; + + memory_init(publ, sdram_params->base.dramtype); + move_to_config_state(publ, pctl); + + /* Using 32bit bus width for detect */ + sdram_params->ch[channel].bw = 2; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, dram->grf); + /* + * set cs, using n=3 for detect + * CS0, n=1 + * CS1, n=2 + * CS0 & CS1, n = 3 + */ + sdram_params->ch[channel].rank = 2, + clrsetbits_le32(&publ->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); + + /* DS=40ohm,ODT=155ohm */ + zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | + 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | + 0x19 << PD_OUTPUT_SHIFT; + writel(zqcr, &publ->zq1cr[0]); + writel(zqcr, &publ->zq0cr[0]); + + /* Detect the rank and bit-width with data-training */ + writel(1, &chan->msch->ddrconf); + sdram_rank_bw_detect(dram, channel, sdram_params); + + if (sdram_params->base.dramtype == LPDDR3) { + u32 i; + writel(0, &pctl->mrrcfg0); + for (i = 0; i < 17; i++) + send_command_op(pctl, 1, MRR_CMD, i, 0); + } + writel(4, &chan->msch->ddrconf); + move_to_access_state(chan); + /* DDR3 and LPDDR3 are always 8 bank, no need detect */ + sdram_params->ch[channel].bk = 3; + /* Detect Col and Row number*/ + ret = sdram_col_row_detect(dram, channel, sdram_params); + if (ret) + goto error; + } + /* Find NIU DDR configuration */ + ret = sdram_get_niu_config(sdram_params); + if (ret) + goto error; + + dram_all_config(dram, sdram_params); + debug("%s done\n", __func__); + + return 0; +error: + printf("DRAM init failed!\n"); + hang(); +} + +static int setup_sdram(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3188_sdram_params *params = dev_get_plat(dev); + + return sdram_init(priv, params); +} + +static int rk3188_dmc_of_to_plat(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_sdram_params *params = dev_get_plat(dev); + int ret; + + /* rk3188 supports only one-channel */ + params->num_channels = 1; + ret = dev_read_u32_array(dev, "rockchip,pctl-timing", + (u32 *)¶ms->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,pctl-timing\n", __func__); + return -EINVAL; + } + ret = dev_read_u32_array(dev, "rockchip,phy-timing", + (u32 *)¶ms->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,phy-timing\n", __func__); + return -EINVAL; + } + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)¶ms->base, + sizeof(params->base) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params\n", __func__); + return -EINVAL; + } + ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); + if (ret) + return ret; +#endif + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_plat(struct udevice *dev) +{ + struct rk3188_sdram_params *plat = dev_get_plat(dev); + struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat; + int ret; + + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + /* rk3188 supports dual-channel, set default channel num to 2 */ + plat->num_channels = 1; + ret = regmap_init_mem_plat(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static int rk3188_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_SPL_BUILD + struct rk3188_sdram_params *plat = dev_get_plat(dev); + struct regmap *map; + struct udevice *dev_clk; + int ret; +#endif + struct dram_info *priv = dev_get_priv(dev); + + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + +#ifdef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_plat(dev); + if (ret) + return ret; +#endif + map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); + if (IS_ERR(map)) + return PTR_ERR(map); + priv->chan[0].msch = regmap_get_range(map, 0); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].publ = regmap_get_range(plat->map, 1); + + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + priv->cru = rockchip_get_cru(); + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); + ret = setup_sdram(dev); + if (ret) + return ret; +#else + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmu->sys_reg[2]); +#endif + + return 0; +} + +static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3188_dmc_ops = { + .get_info = rk3188_dmc_get_info, +}; + +static const struct udevice_id rk3188_dmc_ids[] = { + { .compatible = "rockchip,rk3188-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3188_dmc) = { + .name = "rockchip_rk3188_dmc", + .id = UCLASS_RAM, + .of_match = rk3188_dmc_ids, + .ops = &rk3188_dmc_ops, +#ifdef CONFIG_SPL_BUILD + .of_to_plat = rk3188_dmc_of_to_plat, +#endif + .probe = rk3188_dmc_probe, + .priv_auto = sizeof(struct dram_info), +#ifdef CONFIG_SPL_BUILD + .plat_auto = sizeof(struct rk3188_sdram_params), +#endif +}; diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_rk322x.c b/roms/u-boot/drivers/ram/rockchip/sdram_rk322x.c new file mode 100644 index 000000000..9057ccacd --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_rk322x.c @@ -0,0 +1,855 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +struct chan_info { + struct rk322x_ddr_pctl *pctl; + struct rk322x_ddr_phy *phy; + struct rk322x_service_sys *msch; +}; + +struct dram_info { + struct chan_info chan[1]; + struct ram_info info; + struct clk ddr_clk; + struct rk322x_cru *cru; + struct rk322x_grf *grf; +}; + +struct rk322x_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3228_dmc of_plat; +#endif + struct rk322x_sdram_channel ch[1]; + struct rk322x_pctl_timing pctl_timing; + struct rk322x_phy_timing phy_timing; + struct rk322x_base_params base; + int num_channels; + struct regmap *map; +}; + +#ifdef CONFIG_TPL_BUILD +/* + * [7:6] bank(n:n bit bank) + * [5:4] row(13+n) + * [3] cs(0:1 cs, 1:2 cs) + * [2:1] bank(n:n bit bank) + * [0] col(10+n) + */ +const char ddr_cfg_2_rbc[] = { + ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 1), + ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 1), + ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 1), + ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 1), + ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 2), + ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 2), + ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 2), + ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 0), + ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 0), + ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 0), + ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 0), + ((0 << 6) | (2 << 4) | (0 << 3) | (0 << 2) | 1), + ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 2), + ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 1), + ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 1), + ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 0), +}; + +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +void phy_pctrl_reset(struct rk322x_cru *cru, + struct rk322x_ddr_phy *ddr_phy) +{ + rk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | + 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | + 1 << DDRPHY_SRST_SHIFT, + 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | + 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); + + udelay(10); + + rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | + 1 << DDRPHY_SRST_SHIFT); + udelay(10); + + rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | + 1 << DDRCTRL_SRST_SHIFT); + udelay(10); + + clrbits_le32(&ddr_phy->ddrphy_reg[0], + SOFT_RESET_MASK << SOFT_RESET_SHIFT); + udelay(10); + setbits_le32(&ddr_phy->ddrphy_reg[0], + SOFT_DERESET_ANALOG); + udelay(5); + setbits_le32(&ddr_phy->ddrphy_reg[0], + SOFT_DERESET_DIGITAL); + + udelay(1); +} + +void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) +{ + u32 tmp; + + setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10); + setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10); + setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10); + setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10); + setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10); + + clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8); + clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8); + clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8); + clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8); + clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8); + + if (freq <= 400) + setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); + else + clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); + + if (freq <= 680) + tmp = 3; + else + tmp = 2; + + writel(tmp, &ddr_phy->ddrphy_reg[0x28]); + writel(tmp, &ddr_phy->ddrphy_reg[0x38]); + writel(tmp, &ddr_phy->ddrphy_reg[0x48]); + writel(tmp, &ddr_phy->ddrphy_reg[0x58]); +} + +static void send_command(struct rk322x_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static void memory_init(struct chan_info *chan, + struct rk322x_sdram_params *sdram_params) +{ + struct rk322x_ddr_pctl *pctl = chan->pctl; + u32 dramtype = sdram_params->base.dramtype; + + if (dramtype == DDR3) { + send_command(pctl, 3, DESELECT_CMD, 0); + udelay(1); + send_command(pctl, 3, PREA_CMD, 0); + send_command(pctl, 3, MRS_CMD, + (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + ((sdram_params->phy_timing.mr[0] | + DDR3_DLL_RESET) & + CMD_ADDR_MASK) << CMD_ADDR_SHIFT); + + send_command(pctl, 3, ZQCL_CMD, 0); + } else { + send_command(pctl, 3, MRS_CMD, + (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | + (0 & LPDDR23_OP_MASK) << + LPDDR23_OP_SHIFT); + udelay(10); + send_command(pctl, 3, MRS_CMD, + (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | + (0xff & LPDDR23_OP_MASK) << + LPDDR23_OP_SHIFT); + udelay(1); + send_command(pctl, 3, MRS_CMD, + (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | + (0xff & LPDDR23_OP_MASK) << + LPDDR23_OP_SHIFT); + udelay(1); + send_command(pctl, 3, MRS_CMD, + (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | + (sdram_params->phy_timing.mr[1] & + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); + send_command(pctl, 3, MRS_CMD, + (2 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | + (sdram_params->phy_timing.mr[2] & + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); + send_command(pctl, 3, MRS_CMD, + (3 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | + (sdram_params->phy_timing.mr[3] & + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); + if (dramtype == LPDDR3) + send_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) << + LPDDR23_MA_SHIFT | + (sdram_params->phy_timing.mr11 & + LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); + } +} + +static u32 data_training(struct chan_info *chan) +{ + struct rk322x_ddr_phy *ddr_phy = chan->phy; + struct rk322x_ddr_pctl *pctl = chan->pctl; + u32 value; + u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf; + u32 ret; + + /* disable auto refresh */ + value = readl(&pctl->trefi) | (1 << 31); + writel(1 << 31, &pctl->trefi); + + clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30, + DQS_SQU_CAL_SEL_CS0); + setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); + + udelay(30); + ret = readl(&ddr_phy->ddrphy_reg[0xff]); + + clrbits_le32(&ddr_phy->ddrphy_reg[2], + DQS_SQU_CAL_START); + + /* + * since data training will take about 20us, so send some auto + * refresh(about 7.8us) to complement the lost time + */ + send_command(pctl, 3, PREA_CMD, 0); + send_command(pctl, 3, REF_CMD, 0); + + writel(value, &pctl->trefi); + + if (ret & 0x10) { + ret = -1; + } else { + ret = (ret & 0xf) ^ bw; + ret = (ret == 0) ? 0 : -1; + } + return ret; +} + +static void move_to_config_state(struct rk322x_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MASK; + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) + != ACCESS) + ; + /* + * If at low power state, need wakeup first, and then + * enter the config, so fallthrough + */ + case ACCESS: + /* fallthrough */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void move_to_access_state(struct rk322x_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MASK; + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MASK; + switch (state) { + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) + ; + break; + case ACCESS: + writel(SLEEP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != + LOW_POWER) + ; + break; + case LOW_POWER: + return; + default: + break; + } + } +} + +/* pctl should in low power mode when call this function */ +static void phy_softreset(struct dram_info *dram) +{ + struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; + struct rk322x_grf *grf = dram->grf; + + writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); + clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); + udelay(1); + setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); + udelay(5); + setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); + writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); +} + +/* bw: 2: 32bit, 1:16bit */ +static void set_bw(struct dram_info *dram, u32 bw) +{ + struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; + struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; + struct rk322x_grf *grf = dram->grf; + + if (bw == 1) { + setbits_le32(&pctl->ppcfg, 1); + clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4); + writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]); + clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); + clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); + } else { + clrbits_le32(&pctl->ppcfg, 1); + setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4); + writel(GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN, + &grf->soc_con[0]); + setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); + setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); + } +} + +static void pctl_cfg(struct rk322x_ddr_pctl *pctl, + struct rk322x_sdram_params *sdram_params, + struct rk322x_grf *grf) +{ + u32 burst_len; + u32 bw; + u32 dramtype = sdram_params->base.dramtype; + + if (sdram_params->ch[0].bw == 2) + bw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN; + else + bw = GRF_MSCH_NOC_16BIT_EN; + + writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(0x51010, &pctl->dfilpcfg0); + + writel(1, &pctl->dfitphyupdtype0); + writel(0x0d, &pctl->dfitphyrdlat); + writel(0, &pctl->dfitphywrdata); + + writel(0, &pctl->dfiupdcfg); + copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, + sizeof(struct rk322x_pctl_timing)); + if (dramtype == DDR3) { + writel((1 << 3) | (1 << 11), + &pctl->dfiodtcfg); + writel(7 << 16, &pctl->dfiodtcfg1); + writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen); + writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat); + writel(500, &pctl->trsth); + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + writel(bw | GRF_DDR3_EN, &grf->soc_con[0]); + } else { + if (sdram_params->phy_timing.bl & PHT_BL_8) + burst_len = MDDR_LPDDR2_BL_8; + else + burst_len = MDDR_LPDDR2_BL_4; + + writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen); + writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat); + writel(0, &pctl->trsth); + if (dramtype == LPDDR2) { + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | + LPDDR2_S4 | LPDDR2_EN | burst_len | + (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + writel(0, &pctl->dfiodtcfg); + writel(0, &pctl->dfiodtcfg1); + } else { + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | + LPDDR2_S4 | LPDDR3_EN | burst_len | + (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + writel((1 << 3) | (1 << 2), &pctl->dfiodtcfg); + writel((7 << 16) | 4, &pctl->dfiodtcfg1); + } + writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]); + } + setbits_le32(&pctl->scfg, 1); +} + +static void phy_cfg(struct chan_info *chan, + struct rk322x_sdram_params *sdram_params) +{ + struct rk322x_ddr_phy *ddr_phy = chan->phy; + struct rk322x_service_sys *axi_bus = chan->msch; + struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing; + struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing; + struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing; + u32 cmd_drv, clk_drv, dqs_drv, dqs_odt; + + writel(noc_timing->ddrtiming, &axi_bus->ddrtiming); + writel(noc_timing->ddrmode, &axi_bus->ddrmode); + writel(noc_timing->readlatency, &axi_bus->readlatency); + writel(noc_timing->activate, &axi_bus->activate); + writel(noc_timing->devtodev, &axi_bus->devtodev); + + switch (sdram_params->base.dramtype) { + case DDR3: + writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); + break; + case LPDDR2: + writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); + break; + default: + writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); + break; + } + + writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]); + writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]); + + cmd_drv = PHY_RON_RTT_34OHM; + clk_drv = PHY_RON_RTT_45OHM; + dqs_drv = PHY_RON_RTT_34OHM; + if (sdram_params->base.dramtype == LPDDR2) + dqs_odt = PHY_RON_RTT_DISABLE; + else + dqs_odt = PHY_RON_RTT_225OHM; + + writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]); + clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3); + writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]); + writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]); + + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]); + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]); + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]); + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]); + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]); + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]); + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]); + writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]); + + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]); + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]); + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]); + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]); + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]); + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]); + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]); + writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]); +} + +void dram_cfg_rbc(struct chan_info *chan, + struct rk322x_sdram_params *sdram_params) +{ + char noc_config; + int i = 0; + struct rk322x_sdram_channel *config = &sdram_params->ch[0]; + struct rk322x_service_sys *axi_bus = chan->msch; + + move_to_config_state(chan->pctl); + + if ((config->rank == 2) && (config->cs1_row == config->cs0_row)) { + if ((config->col + config->bw) == 12) { + i = 14; + goto finish; + } else if ((config->col + config->bw) == 11) { + i = 15; + goto finish; + } + } + noc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) | + (config->col + config->bw - 11); + for (i = 0; i < 11; i++) { + if (noc_config == ddr_cfg_2_rbc[i]) + break; + } + + if (i < 11) + goto finish; + + noc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) | + (config->col + config->bw - 11); + + for (i = 11; i < 14; i++) { + if (noc_config == ddr_cfg_2_rbc[i]) + break; + } + if (i < 14) + goto finish; + else + i = 0; + +finish: + writel(i, &axi_bus->ddrconf); + move_to_access_state(chan->pctl); +} + +static void dram_all_config(const struct dram_info *dram, + struct rk322x_sdram_params *sdram_params) +{ + struct rk322x_sdram_channel *info = &sdram_params->ch[0]; + u32 sys_reg = 0; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (1 - 1) << SYS_REG_NUM_CH_SHIFT; + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(0); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(0); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(0); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(0); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(0); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(0); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(0); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0); + + writel(sys_reg, &dram->grf->os_reg[2]); +} + +#define TEST_PATTEN 0x5aa5f00f + +static int dram_cap_detect(struct dram_info *dram, + struct rk322x_sdram_params *sdram_params) +{ + u32 bw, row, col, addr; + u32 ret = 0; + struct rk322x_service_sys *axi_bus = dram->chan[0].msch; + + if (sdram_params->base.dramtype == DDR3) + sdram_params->ch[0].dbw = 1; + else + sdram_params->ch[0].dbw = 2; + + move_to_config_state(dram->chan[0].pctl); + /* bw detect */ + set_bw(dram, 2); + if (data_training(&dram->chan[0]) == 0) { + bw = 2; + } else { + bw = 1; + set_bw(dram, 1); + move_to_lowpower_state(dram->chan[0].pctl); + phy_softreset(dram); + move_to_config_state(dram->chan[0].pctl); + if (data_training(&dram->chan[0])) { + printf("BW detect error\n"); + ret = -EINVAL; + } + } + sdram_params->ch[0].bw = bw; + sdram_params->ch[0].bk = 3; + + if (bw == 2) + writel(6, &axi_bus->ddrconf); + else + writel(3, &axi_bus->ddrconf); + move_to_access_state(dram->chan[0].pctl); + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + bw - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + printf("Col detect error\n"); + ret = -EINVAL; + goto out; + } else { + sdram_params->ch[0].col = col; + } + + writel(10, &axi_bus->ddrconf); + + /* Detect row*/ + for (row = 16; row >= 12; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 11) { + printf("Row detect error\n"); + ret = -EINVAL; + } else { + sdram_params->ch[0].cs1_row = row; + sdram_params->ch[0].row_3_4 = 0; + sdram_params->ch[0].cs0_row = row; + } + /* cs detect */ + writel(0, CONFIG_SYS_SDRAM_BASE); + writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30)); + writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4); + if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + sdram_params->ch[0].rank = 2; + else + sdram_params->ch[0].rank = 1; +out: + return ret; +} + +static int sdram_init(struct dram_info *dram, + struct rk322x_sdram_params *sdram_params) +{ + int ret; + + ret = clk_set_rate(&dram->ddr_clk, + sdram_params->base.ddr_freq * MHz * 2); + if (ret < 0) { + printf("Could not set DDR clock\n"); + return ret; + } + + phy_pctrl_reset(dram->cru, dram->chan[0].phy); + phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq); + pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf); + phy_cfg(&dram->chan[0], sdram_params); + writel(POWER_UP_START, &dram->chan[0].pctl->powctl); + while (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE)) + ; + memory_init(&dram->chan[0], sdram_params); + move_to_access_state(dram->chan[0].pctl); + ret = dram_cap_detect(dram, sdram_params); + if (ret) + goto out; + dram_cfg_rbc(&dram->chan[0], sdram_params); + dram_all_config(dram, sdram_params); +out: + return ret; +} + +static int rk322x_dmc_of_to_plat(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk322x_sdram_params *params = dev_get_plat(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + int ret; + + params->num_channels = 1; + + ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", + (u32 *)¶ms->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,pctl-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", + (u32 *)¶ms->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,phy-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", + (u32 *)¶ms->base, + sizeof(params->base) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params\n", __func__); + return -EINVAL; + } + ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); + if (ret) + return ret; +#endif + + return 0; +} +#endif /* CONFIG_TPL_BUILD */ + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_plat(struct udevice *dev) +{ + struct rk322x_sdram_params *plat = dev_get_plat(dev); + struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat; + int ret; + + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + + plat->num_channels = 1; + ret = regmap_init_mem_plat(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static int rk322x_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD + struct rk322x_sdram_params *plat = dev_get_plat(dev); + int ret; + struct udevice *dev_clk; +#endif + struct dram_info *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); +#ifdef CONFIG_TPL_BUILD +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_plat(dev); + if (ret) + return ret; +#endif + + priv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].phy = regmap_get_range(plat->map, 1); + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + priv->cru = rockchip_get_cru(); + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); + ret = sdram_init(priv, plat); + if (ret) + return ret; +#else + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->grf->os_reg[2]); +#endif + + return 0; +} + +static int rk322x_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk322x_dmc_ops = { + .get_info = rk322x_dmc_get_info, +}; + +static const struct udevice_id rk322x_dmc_ids[] = { + { .compatible = "rockchip,rk3228-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk322x) = { + .name = "rockchip_rk322x_dmc", + .id = UCLASS_RAM, + .of_match = rk322x_dmc_ids, + .ops = &rk322x_dmc_ops, +#ifdef CONFIG_TPL_BUILD + .of_to_plat = rk322x_dmc_of_to_plat, +#endif + .probe = rk322x_dmc_probe, + .priv_auto = sizeof(struct dram_info), +#ifdef CONFIG_TPL_BUILD + .plat_auto = sizeof(struct rk322x_sdram_params), +#endif +}; + diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_rk3288.c b/roms/u-boot/drivers/ram/rockchip/sdram_rk3288.c new file mode 100644 index 000000000..a933abf0d --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_rk3288.c @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * Adapted from coreboot. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct chan_info { + struct rk3288_ddr_pctl *pctl; + struct rk3288_ddr_publ *publ; + struct rk3288_msch *msch; +}; + +struct dram_info { + struct chan_info chan[2]; + struct ram_info info; + struct clk ddr_clk; + struct rockchip_cru *cru; + struct rk3288_grf *grf; + struct rk3288_sgrf *sgrf; + struct rk3288_pmu *pmu; + bool is_veyron; +}; + +struct rk3288_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3288_dmc of_plat; +#endif + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + struct rk3288_base_params base; + int num_channels; + struct regmap *map; +}; + +const int ddrconf_table[] = { + /* row col,bw */ + 0, + ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + 0, + 0, + 0, + 0, + ((4 << 4) | 2), +}; + +#define TEST_PATTEN 0x5aa5f00f +#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) +#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) + +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy) +{ + u32 phy_ctl_srstn_shift = 4 + 5 * ch; + u32 ctl_psrstn_shift = 3 + 5 * ch; + u32 ctl_srstn_shift = 2 + 5 * ch; + u32 phy_psrstn_shift = 1 + 5 * ch; + u32 phy_srstn_shift = 5 * ch; + + rk_clrsetreg(&cru->cru_softrst_con[10], + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | + 1 << phy_srstn_shift, + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | + ctl << ctl_srstn_shift | phy << phy_psrstn_shift | + phy << phy_srstn_shift); +} + +static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n) +{ + u32 phy_ctl_srstn_shift = 4 + 5 * ch; + + rk_clrsetreg(&cru->cru_softrst_con[10], + 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); +} + +static void phy_pctrl_reset(struct rockchip_cru *cru, + struct rk3288_ddr_publ *publ, + int channel) +{ + int i; + + ddr_reset(cru, channel, 1, 1); + udelay(1); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + ddr_reset(cru, channel, 1, 0); + udelay(10); + ddr_reset(cru, channel, 0, 0); + udelay(10); +} + +static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, + u32 freq) +{ + int i; + + if (freq <= 250000000) { + if (freq <= 150000000) + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + else + setbits_le32(&publ->dllgcr, SBIAS_BYPASS); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + + setbits_le32(&publ->pir, PIR_DLLBYP); + } else { + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) { + clrbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + } + + clrbits_le32(&publ->pir, PIR_DLLBYP); + } +} + +static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) +{ + writel(DFI_INIT_START, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); + writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); + writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); + writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); + writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); + writel(1, &pctl->dfitphyupdtype0); + + /* cs0 and cs1 write odt enable */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + /* odt write length */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + /* phyupd and ctrlupd disabled */ + writel(0, &pctl->dfiupdcfg); +} + +static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable) +{ + uint val = 0; + + if (enable) { + val = 1 << (channel ? DDR1_16BIT_EN_SHIFT : + DDR0_16BIT_EN_SHIFT); + } + rk_clrsetreg(&grf->soc_con0, + 1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT), + val); +} + +static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel, + bool ddr3_mode) +{ + uint mask, val; + + mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT); + val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT : + MSCH0_MAINDDR3_SHIFT); + rk_clrsetreg(&grf->soc_con0, mask, val); +} + +static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel, + bool enable, bool enable_bst, bool enable_odt) +{ + uint mask; + bool disable_bst = !enable_bst; + + mask = channel ? + (1 << LPDDR3_EN1_SHIFT | 1 << UPCTL1_BST_DIABLE_SHIFT | + 1 << UPCTL1_LPDDR3_ODT_EN_SHIFT) : + (1 << LPDDR3_EN0_SHIFT | 1 << UPCTL0_BST_DIABLE_SHIFT | + 1 << UPCTL0_LPDDR3_ODT_EN_SHIFT); + rk_clrsetreg(&grf->soc_con2, mask, + enable << (channel ? LPDDR3_EN1_SHIFT : LPDDR3_EN0_SHIFT) | + disable_bst << (channel ? UPCTL1_BST_DIABLE_SHIFT : + UPCTL0_BST_DIABLE_SHIFT) | + enable_odt << (channel ? UPCTL1_LPDDR3_ODT_EN_SHIFT : + UPCTL0_LPDDR3_ODT_EN_SHIFT)); +} + +static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, + struct rk3288_sdram_params *sdram_params, + struct rk3288_grf *grf) +{ + unsigned int burstlen; + + burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; + copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, + sizeof(sdram_params->pctl_timing)); + switch (sdram_params->base.dramtype) { + case LPDDR3: + writel(sdram_params->pctl_timing.tcl - 1, + &pctl->dfitrddataen); + writel(sdram_params->pctl_timing.tcwl, + &pctl->dfitphywrlat); + burstlen >>= 1; + writel(LPDDR2_S4 | 0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | + LPDDR2_EN | burstlen << BURSTLENGTH_SHIFT | + (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + ddr_set_ddr3_mode(grf, channel, false); + ddr_set_enable(grf, channel, true); + ddr_set_en_bst_odt(grf, channel, true, false, + sdram_params->base.odt); + break; + case DDR3: + if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { + writel(sdram_params->pctl_timing.tcl - 3, + &pctl->dfitrddataen); + } else { + writel(sdram_params->pctl_timing.tcl - 2, + &pctl->dfitrddataen); + } + writel(sdram_params->pctl_timing.tcwl - 1, + &pctl->dfitphywrlat); + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + ddr_set_ddr3_mode(grf, channel, true); + ddr_set_enable(grf, channel, true); + + ddr_set_en_bst_odt(grf, channel, false, true, false); + break; + } + + setbits_le32(&pctl->scfg, 1); +} + +static void phy_cfg(const struct chan_info *chan, int channel, + struct rk3288_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_msch *msch = chan->msch; + uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; + u32 dinit2, tmp; + int i; + + dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); + /* DDR PHY Timing */ + copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, + sizeof(sdram_params->phy_timing)); + writel(sdram_params->base.noc_timing, &msch->ddrtiming); + writel(0x3f, &msch->readlatency); + writel(sdram_params->base.noc_activate, &msch->activate); + writel(2 << BUSWRTORD_SHIFT | 2 << BUSRDTOWR_SHIFT | + 1 << BUSRDTORD_SHIFT, &msch->devtodev); + writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | + 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); + writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, + &publ->ptr[1]); + writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, + &publ->ptr[2]); + + switch (sdram_params->base.dramtype) { + case LPDDR3: + clrsetbits_le32(&publ->pgcr, 0x1F, + 0 << PGCR_DFTLMT_SHIFT | + 0 << PGCR_DFTCMP_SHIFT | + 1 << PGCR_DQSCFG_SHIFT | + 0 << PGCR_ITMDMD_SHIFT); + /* DDRMODE select LPDDR3 */ + clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, + DDRMD_LPDDR2_LPDDR3 << DDRMD_SHIFT); + clrsetbits_le32(&publ->dxccr, + DQSNRES_MASK << DQSNRES_SHIFT | + DQSRES_MASK << DQSRES_SHIFT, + 4 << DQSRES_SHIFT | 0xc << DQSNRES_SHIFT); + tmp = readl(&publ->dtpr[1]); + tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) - + ((tmp >> TDQSCK_SHIFT) & TDQSCK_MASK); + clrsetbits_le32(&publ->dsgcr, + DQSGE_MASK << DQSGE_SHIFT | + DQSGX_MASK << DQSGX_SHIFT, + tmp << DQSGE_SHIFT | tmp << DQSGX_SHIFT); + break; + case DDR3: + clrbits_le32(&publ->pgcr, 0x1f); + clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, + DDRMD_DDR3 << DDRMD_SHIFT); + break; + } + if (sdram_params->base.odt) { + /*dynamic RTT enable */ + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } else { + /*dynamic RTT disable */ + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } +} + +static void phy_init(struct rk3288_ddr_publ *publ) +{ + setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST + | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); + udelay(1); + while ((readl(&publ->pgsr) & + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) + ; +} + +static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, + u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static inline void send_command_op(struct rk3288_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 ma, u32 op) +{ + send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | + (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); +} + +static void memory_init(struct rk3288_ddr_publ *publ, + u32 dramtype) +{ + setbits_le32(&publ->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + udelay(1); + while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) + != (PGSR_IDONE | PGSR_DLDONE)) + ; +} + +static void move_to_config_state(struct rk3288_ddr_publ *publ, + struct rk3288_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) + != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + /* + * if at low power state,need wakeup first, + * and then enter the config + * so here no break. + */ + case ACCESS: + /* no break */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void set_bandwidth_ratio(const struct chan_info *chan, int channel, + u32 n, struct rk3288_grf *grf) +{ + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_msch *msch = chan->msch; + + if (n == 1) { + setbits_le32(&pctl->ppcfg, 1); + rk_setreg(&grf->soc_con0, 1 << (8 + channel)); + setbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte disable*/ + clrbits_le32(&publ->datx8[2].dxgcr, 1); + clrbits_le32(&publ->datx8[3].dxgcr, 1); + /* disable DLL */ + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + } else { + clrbits_le32(&pctl->ppcfg, 1); + rk_clrreg(&grf->soc_con0, 1 << (8 + channel)); + clrbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte enable*/ + setbits_le32(&publ->datx8[2].dxgcr, 1); + setbits_le32(&publ->datx8[3].dxgcr, 1); + + /* enable DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + /* reset DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + udelay(10); + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + } + setbits_le32(&pctl->dfistcfg0, 1 << 2); +} + +static int data_training(const struct chan_info *chan, int channel, + struct rk3288_sdram_params *sdram_params) +{ + unsigned int j; + int ret = 0; + u32 rank; + int i; + u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + + /* disable auto refresh */ + writel(0, &pctl->trefi); + + if (sdram_params->base.dramtype != LPDDR3) + setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + rank = sdram_params->ch[channel].rank | 1; + for (j = 0; j < ARRAY_SIZE(step); j++) { + /* + * trigger QSTRN and RVTRN + * clear DTDONE status + */ + setbits_le32(&publ->pir, PIR_CLRSR); + + /* trigger DTT */ + setbits_le32(&publ->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); + udelay(1); + /* wait echo byte DTDONE */ + while ((readl(&publ->datx8[0].dxgsr[0]) & rank) + != rank) + ; + while ((readl(&publ->datx8[1].dxgsr[0]) & rank) + != rank) + ; + if (!(readl(&pctl->ppcfg) & 1)) { + while ((readl(&publ->datx8[2].dxgsr[0]) + & rank) != rank) + ; + while ((readl(&publ->datx8[3].dxgsr[0]) + & rank) != rank) + ; + } + if (readl(&publ->pgsr) & + (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { + ret = -1; + break; + } + } + /* send some auto refresh to complement the lost while DTT */ + for (i = 0; i < (rank > 1 ? 8 : 4); i++) + send_command(pctl, rank, REF_CMD, 0); + + if (sdram_params->base.dramtype != LPDDR3) + clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + + /* resume auto refresh */ + writel(sdram_params->pctl_timing.trefi, &pctl->trefi); + + return ret; +} + +static void move_to_access_state(const struct chan_info *chan) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, + struct rk3288_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + + if (sdram_params->ch[chnum].bk == 3) + clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, + 1 << PDQ_SHIFT); + else + clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); + + writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); +} + +static void dram_all_config(const struct dram_info *dram, + struct rk3288_sdram_params *sdram_params) +{ + unsigned int chan; + u32 sys_reg = 0; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (chan = 0; chan < sdram_params->num_channels; chan++) { + const struct rk3288_sdram_channel *info = + &sdram_params->ch[chan]; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); + } + writel(sys_reg, &dram->pmu->sys_reg[2]); + rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); +} + +static int sdram_rank_bw_detect(struct dram_info *dram, int channel, + struct rk3288_sdram_params *sdram_params) +{ + int reg; + int need_trainig = 0; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_publ *publ = chan->publ; + + if (data_training(chan, channel, sdram_params) < 0) { + reg = readl(&publ->datx8[0].dxgsr[0]); + /* Check the result for rank 0 */ + if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { + debug("data training fail!\n"); + return -EIO; + } else if ((channel == 1) && + (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { + sdram_params->num_channels = 1; + } + + /* Check the result for rank 1 */ + if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { + sdram_params->ch[channel].rank = 1; + clrsetbits_le32(&publ->pgcr, 0xF << 18, + sdram_params->ch[channel].rank << 18); + need_trainig = 1; + } + reg = readl(&publ->datx8[2].dxgsr[0]); + if (reg & (1 << 4)) { + sdram_params->ch[channel].bw = 1; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, + dram->grf); + need_trainig = 1; + } + } + /* Assume the Die bit width are the same with the chip bit width */ + sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; + + if (need_trainig && + (data_training(chan, channel, sdram_params) < 0)) { + if (sdram_params->base.dramtype == LPDDR3) { + ddr_phy_ctl_reset(dram->cru, channel, 1); + udelay(10); + ddr_phy_ctl_reset(dram->cru, channel, 0); + udelay(10); + } + debug("2nd data training failed!"); + return -EIO; + } + + return 0; +} + +static int sdram_col_row_detect(struct dram_info *dram, int channel, + struct rk3288_sdram_params *sdram_params) +{ + int row, col; + unsigned int addr; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + int ret = 0; + + /* Detect col */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + sdram_params->ch[channel].bw - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + printf("Col detect error\n"); + ret = -EINVAL; + goto out; + } else { + sdram_params->ch[channel].col = col; + } + + move_to_config_state(publ, pctl); + writel(4, &chan->msch->ddrconf); + move_to_access_state(chan); + /* Detect row*/ + for (row = 16; row >= 12; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 11) { + printf("Row detect error\n"); + ret = -EINVAL; + } else { + sdram_params->ch[channel].cs1_row = row; + sdram_params->ch[channel].row_3_4 = 0; + debug("chn %d col %d, row %d\n", channel, col, row); + sdram_params->ch[channel].cs0_row = row; + } + +out: + return ret; +} + +static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params) +{ + int i, tmp, size, ret = 0; + + tmp = sdram_params->ch[0].col - 9; + tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; + tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4); + size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); + for (i = 0; i < size; i++) + if (tmp == ddrconf_table[i]) + break; + if (i >= size) { + printf("niu config not found\n"); + ret = -EINVAL; + } else { + sdram_params->base.ddrconfig = i; + } + + return ret; +} + +static int sdram_get_stride(struct rk3288_sdram_params *sdram_params) +{ + int stride = -1; + int ret = 0; + long cap = sdram_params->num_channels * (1u << + (sdram_params->ch[0].cs0_row + + sdram_params->ch[0].col + + (sdram_params->ch[0].rank - 1) + + sdram_params->ch[0].bw + + 3 - 20)); + + switch (cap) { + case 512: + stride = 0; + break; + case 1024: + stride = 5; + break; + case 2048: + stride = 9; + break; + case 4096: + stride = 0xd; + break; + default: + stride = -1; + printf("could not find correct stride, cap error!\n"); + ret = -EINVAL; + break; + } + sdram_params->base.stride = stride; + + return ret; +} + +static int sdram_init(struct dram_info *dram, + struct rk3288_sdram_params *sdram_params) +{ + int channel; + int zqcr; + int ret; + + debug("%s start\n", __func__); + if ((sdram_params->base.dramtype == DDR3 && + sdram_params->base.ddr_freq > 800000000) || + (sdram_params->base.dramtype == LPDDR3 && + sdram_params->base.ddr_freq > 533000000)) { + debug("SDRAM frequency is too high!"); + return -E2BIG; + } + + debug("ddr clk dpll\n"); + ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); + debug("ret=%d\n", ret); + if (ret) { + debug("Could not set DDR clock\n"); + return ret; + } + + for (channel = 0; channel < 2; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + + /* map all the 4GB space to the current channel */ + if (channel) + rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17); + else + rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a); + phy_pctrl_reset(dram->cru, publ, channel); + phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); + + dfi_cfg(pctl, sdram_params->base.dramtype); + + pctl_cfg(channel, pctl, sdram_params, dram->grf); + + phy_cfg(chan, channel, sdram_params); + + phy_init(publ); + + writel(POWER_UP_START, &pctl->powctl); + while (!(readl(&pctl->powstat) & POWER_UP_DONE)) + ; + + memory_init(publ, sdram_params->base.dramtype); + move_to_config_state(publ, pctl); + + if (sdram_params->base.dramtype == LPDDR3) { + send_command(pctl, 3, DESELECT_CMD, 0); + udelay(1); + send_command(pctl, 3, PREA_CMD, 0); + udelay(1); + send_command_op(pctl, 3, MRS_CMD, 63, 0xfc); + udelay(1); + send_command_op(pctl, 3, MRS_CMD, 1, + sdram_params->phy_timing.mr[1]); + udelay(1); + send_command_op(pctl, 3, MRS_CMD, 2, + sdram_params->phy_timing.mr[2]); + udelay(1); + send_command_op(pctl, 3, MRS_CMD, 3, + sdram_params->phy_timing.mr[3]); + udelay(1); + } + + /* Using 32bit bus width for detect */ + sdram_params->ch[channel].bw = 2; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, dram->grf); + /* + * set cs, using n=3 for detect + * CS0, n=1 + * CS1, n=2 + * CS0 & CS1, n = 3 + */ + sdram_params->ch[channel].rank = 2, + clrsetbits_le32(&publ->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); + + /* DS=40ohm,ODT=155ohm */ + zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | + 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | + 0x19 << PD_OUTPUT_SHIFT; + writel(zqcr, &publ->zq1cr[0]); + writel(zqcr, &publ->zq0cr[0]); + + if (sdram_params->base.dramtype == LPDDR3) { + /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ + udelay(10); + send_command_op(pctl, + sdram_params->ch[channel].rank | 1, + MRS_CMD, 11, + sdram_params->base.odt ? 3 : 0); + if (channel == 0) { + writel(0, &pctl->mrrcfg0); + send_command_op(pctl, 1, MRR_CMD, 8, 0); + /* S8 */ + if ((readl(&pctl->mrrstat0) & 0x3) != 3) { + debug("failed!"); + return -EREMOTEIO; + } + } + } + + /* Detect the rank and bit-width with data-training */ + sdram_rank_bw_detect(dram, channel, sdram_params); + + if (sdram_params->base.dramtype == LPDDR3) { + u32 i; + writel(0, &pctl->mrrcfg0); + for (i = 0; i < 17; i++) + send_command_op(pctl, 1, MRR_CMD, i, 0); + } + writel(15, &chan->msch->ddrconf); + move_to_access_state(chan); + /* DDR3 and LPDDR3 are always 8 bank, no need detect */ + sdram_params->ch[channel].bk = 3; + /* Detect Col and Row number*/ + ret = sdram_col_row_detect(dram, channel, sdram_params); + if (ret) + goto error; + } + /* Find NIU DDR configuration */ + ret = sdram_get_niu_config(sdram_params); + if (ret) + goto error; + /* Find stride setting */ + ret = sdram_get_stride(sdram_params); + if (ret) + goto error; + + dram_all_config(dram, sdram_params); + debug("%s done\n", __func__); + + return 0; +error: + printf("DRAM init failed!\n"); + hang(); +} + +# ifdef CONFIG_ROCKCHIP_FAST_SPL +static int veyron_init(struct dram_info *priv) +{ + struct udevice *pmic; + int ret; + + ret = uclass_first_device_err(UCLASS_PMIC, &pmic); + if (ret) + return ret; + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = rk8xx_spl_configure_buck(pmic, 1, 1200000); + if (ret) + return ret; + udelay(175);/* Must wait for voltage to stabilize, 2mV/us */ + ret = rk8xx_spl_configure_buck(pmic, 1, 1400000); + if (ret) + return ret; + udelay(100);/* Must wait for voltage to stabilize, 2mV/us */ + + rk3288_clk_configure_cpu(priv->cru, priv->grf); + + return 0; +} +# endif + +static int setup_sdram(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3288_sdram_params *params = dev_get_plat(dev); + +# ifdef CONFIG_ROCKCHIP_FAST_SPL + if (priv->is_veyron) { + int ret; + + ret = veyron_init(priv); + if (ret) + return ret; + } +# endif + + return sdram_init(priv, params); +} + +static int rk3288_dmc_of_to_plat(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3288_sdram_params *params = dev_get_plat(dev); + int ret; + + /* Rk3288 supports dual-channel, set default channel num to 2 */ + params->num_channels = 2; + ret = dev_read_u32_array(dev, "rockchip,pctl-timing", + (u32 *)¶ms->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); + if (ret) { + debug("%s: Cannot read rockchip,pctl-timing\n", __func__); + return -EINVAL; + } + ret = dev_read_u32_array(dev, "rockchip,phy-timing", + (u32 *)¶ms->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); + if (ret) { + debug("%s: Cannot read rockchip,phy-timing\n", __func__); + return -EINVAL; + } + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)¶ms->base, + sizeof(params->base) / sizeof(u32)); + if (ret) { + debug("%s: Cannot read rockchip,sdram-params\n", __func__); + return -EINVAL; + } +#ifdef CONFIG_ROCKCHIP_FAST_SPL + struct dram_info *priv = dev_get_priv(dev); + + priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron"); +#endif + ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); + if (ret) + return ret; +#endif + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_plat(struct udevice *dev) +{ + struct rk3288_sdram_params *plat = dev_get_plat(dev); + struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat; + int ret; + + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + /* Rk3288 supports dual-channel, set default channel num to 2 */ + plat->num_channels = 2; + ret = regmap_init_mem_plat(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static int rk3288_dmc_probe(struct udevice *dev) +{ +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + struct rk3288_sdram_params *plat = dev_get_plat(dev); + struct udevice *dev_clk; + struct regmap *map; + int ret; +#endif + struct dram_info *priv = dev_get_priv(dev); + + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_plat(dev); + if (ret) + return ret; +#endif + map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); + if (IS_ERR(map)) + return PTR_ERR(map); + priv->chan[0].msch = regmap_get_range(map, 0); + priv->chan[1].msch = (struct rk3288_msch *) + (regmap_get_range(map, 0) + 0x80); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].publ = regmap_get_range(plat->map, 1); + priv->chan[1].pctl = regmap_get_range(plat->map, 2); + priv->chan[1].publ = regmap_get_range(plat->map, 3); + + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + priv->cru = rockchip_get_cru(); + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); + ret = setup_sdram(dev); + if (ret) + return ret; +#else + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmu->sys_reg[2]); +#endif + + return 0; +} + +static int rk3288_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3288_dmc_ops = { + .get_info = rk3288_dmc_get_info, +}; + +static const struct udevice_id rk3288_dmc_ids[] = { + { .compatible = "rockchip,rk3288-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3288_dmc) = { + .name = "rockchip_rk3288_dmc", + .id = UCLASS_RAM, + .of_match = rk3288_dmc_ids, + .ops = &rk3288_dmc_ops, +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + .of_to_plat = rk3288_dmc_of_to_plat, +#endif + .probe = rk3288_dmc_probe, + .priv_auto = sizeof(struct dram_info), +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + .plat_auto = sizeof(struct rk3288_sdram_params), +#endif +}; diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_rk3308.c b/roms/u-boot/drivers/ram/rockchip/sdram_rk3308.c new file mode 100644 index 000000000..44d7d8a0d --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_rk3308.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct dram_info { + struct ram_info info; + struct rk3308_grf *grf; +}; + +static int rk3308_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2); + + return 0; +} + +static int rk3308_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3308_dmc_ops = { + .get_info = rk3308_dmc_get_info, +}; + +static const struct udevice_id rk3308_dmc_ids[] = { + { .compatible = "rockchip,rk3308-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3308) = { + .name = "rockchip_rk3308_dmc", + .id = UCLASS_RAM, + .of_match = rk3308_dmc_ids, + .ops = &rk3308_dmc_ops, + .probe = rk3308_dmc_probe, + .priv_auto = sizeof(struct dram_info), +}; diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_rk3328.c b/roms/u-boot/drivers/ram/rockchip/sdram_rk3328.c new file mode 100644 index 000000000..9af4c372d --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_rk3328.c @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct dram_info { +#ifdef CONFIG_TPL_BUILD + struct ddr_pctl_regs *pctl; + struct ddr_phy_regs *phy; + struct clk ddr_clk; + struct rk3328_cru *cru; + struct msch_regs *msch; + struct rk3328_ddr_grf_regs *ddr_grf; +#endif + struct ram_info info; + struct rk3328_grf_regs *grf; +}; + +#ifdef CONFIG_TPL_BUILD + +struct rk3328_sdram_channel sdram_ch; + +struct rockchip_dmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3328_dmc dtplat; +#else + struct rk3328_sdram_params sdram_params; +#endif + struct regmap *map; +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_plat(struct udevice *dev) +{ + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; + int ret; + + ret = regmap_init_mem_plat(dev, dtplat->reg, + ARRAY_SIZE(dtplat->reg) / 2, &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static void rkclk_ddr_reset(struct dram_info *dram, + u32 ctl_srstn, u32 ctl_psrstn, + u32 phy_srstn, u32 phy_psrstn) +{ + writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) | + ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn), + &dram->cru->softrst_con[5]); + writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]); +} + +static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) +{ + unsigned int refdiv, postdiv1, postdiv2, fbdiv; + int delay = 1000; + u32 mhz = hz / MHZ; + + refdiv = 1; + if (mhz <= 300) { + postdiv1 = 4; + postdiv2 = 2; + } else if (mhz <= 400) { + postdiv1 = 6; + postdiv2 = 1; + } else if (mhz <= 600) { + postdiv1 = 4; + postdiv2 = 1; + } else if (mhz <= 800) { + postdiv1 = 3; + postdiv2 = 1; + } else if (mhz <= 1600) { + postdiv1 = 2; + postdiv2 = 1; + } else { + postdiv1 = 1; + postdiv2 = 1; + } + fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; + + writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con); + writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); + writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), + &dram->cru->dpll_con[1]); + + while (delay > 0) { + udelay(1); + if (LOCK(readl(&dram->cru->dpll_con[1]))) + break; + delay--; + } + + writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con); +} + +static void rkclk_configure_ddr(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + void __iomem *phy_base = dram->phy; + + /* choose DPLL for ddr clk source */ + clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); + + /* for inno ddr phy need 2*freq */ + rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2); +} + +/* return ddrconfig value + * (-1), find ddrconfig fail + * other, the ddrconfig value + * only support cs0_row >= cs1_row + */ +static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 cs, bw, die_bw, col, row, bank; + u32 cs1_row; + u32 i, tmp; + u32 ddrconf = -1; + + cs = cap_info->rank; + bw = cap_info->bw; + die_bw = cap_info->dbw; + col = cap_info->col; + row = cap_info->cs0_row; + cs1_row = cap_info->cs1_row; + bank = cap_info->bk; + + if (sdram_params->base.dramtype == DDR4) { + /* when DDR_TEST, CS always at MSB position for easy test */ + if (cs == 2 && row == cs1_row) { + /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */ + tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) | + die_bw; + for (i = 17; i < 21; i++) { + if (((tmp & 0x7) == + (ddr4_cfg_2_rbc[i - 10] & 0x7)) && + ((tmp & 0x3c) <= + (ddr4_cfg_2_rbc[i - 10] & 0x3c))) { + ddrconf = i; + goto out; + } + } + } + + tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw; + for (i = 10; i < 17; i++) { + if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) && + ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) && + ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) { + ddrconf = i; + goto out; + } + } + } else { + if (bank == 2) { + ddrconf = 8; + goto out; + } + + /* when DDR_TEST, CS always at MSB position for easy test */ + if (cs == 2 && row == cs1_row) { + /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */ + for (i = 5; i < 8; i++) { + if ((bw + col - 11) == (ddr_cfg_2_rbc[i] & + 0x3)) { + ddrconf = i; + goto out; + } + } + } + + tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0); + for (i = 0; i < 5; i++) + if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) && + ((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) { + ddrconf = i; + goto out; + } + } + +out: + if (ddrconf > 20) + printf("calculate ddrconfig error\n"); + + return ddrconf; +} + +/******* + * calculate controller dram address map, and setting to register. + * argument sdram_ch.ddrconf must be right value before + * call this function. + *******/ +static void set_ctl_address_map(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *pctl_base = dram->pctl; + + sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), + &addrmap[cap_info->ddrconfig][0], 9 * 4); + if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) + setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); + if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) + setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); + + if (cap_info->rank == 1) + clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); +} + +static int data_training(struct dram_info *dram, u32 cs, u32 dramtype) +{ + void __iomem *pctl_base = dram->pctl; + u32 dis_auto_zq = 0; + u32 pwrctl; + u32 ret; + + /* disable auto low-power */ + pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); + writel(0, pctl_base + DDR_PCTL2_PWRCTL); + + dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); + + ret = phy_data_training(dram->phy, cs, dramtype); + + pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); + + /* restore auto low-power */ + writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); + + return ret; +} + +static void rx_deskew_switch_adjust(struct dram_info *dram) +{ + u32 i, deskew_val; + u32 gate_val = 0; + void __iomem *phy_base = dram->phy; + + for (i = 0; i < 4; i++) + gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); + + deskew_val = (gate_val >> 3) + 1; + deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val; + clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); + clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, + (deskew_val & 0x1c) << 2); +} + +static void tx_deskew_switch_adjust(struct dram_info *dram) +{ + void __iomem *phy_base = dram->phy; + + clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); +} + +static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) +{ + writel(ddrconfig, &dram->msch->ddrconf); +} + +static void sdram_msch_config(struct msch_regs *msch, + struct sdram_msch_timings *noc_timings) +{ + writel(noc_timings->ddrtiming.d32, &msch->ddrtiming); + + writel(noc_timings->ddrmode.d32, &msch->ddrmode); + writel(noc_timings->readlatency, &msch->readlatency); + + writel(noc_timings->activate.d32, &msch->activate); + writel(noc_timings->devtodev.d32, &msch->devtodev); + writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing); + writel(noc_timings->agingx0, &msch->aging0); + writel(noc_timings->agingx0, &msch->aging1); + writel(noc_timings->agingx0, &msch->aging2); + writel(noc_timings->agingx0, &msch->aging3); + writel(noc_timings->agingx0, &msch->aging4); + writel(noc_timings->agingx0, &msch->aging5); +} + +static void dram_all_config(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + u32 sys_reg2 = 0; + u32 sys_reg3 = 0; + + set_ddrconfig(dram, cap_info->ddrconfig); + sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, + &sys_reg3, 0); + writel(sys_reg2, &dram->grf->os_reg[2]); + writel(sys_reg3, &dram->grf->os_reg[3]); + + sdram_msch_config(dram->msch, &sdram_ch.noc_timings); +} + +static void enable_low_power(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + void __iomem *pctl_base = dram->pctl; + + /* enable upctl2 axi clock auto gating */ + writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]); + writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]); + /* enable upctl2 core clock auto gating */ + writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]); + /* enable sr, pd */ + if (PD_IDLE == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); + if (SR_IDLE == 0) + clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + else + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); + setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); +} + +static int sdram_init(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params, u32 pre_init) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + void __iomem *pctl_base = dram->pctl; + + rkclk_ddr_reset(dram, 1, 1, 1, 1); + udelay(10); + /* + * dereset ddr phy psrstn to config pll, + * if using phy pll psrstn must be dereset + * before config pll + */ + rkclk_ddr_reset(dram, 1, 1, 1, 0); + rkclk_configure_ddr(dram, sdram_params); + + /* release phy srst to provide clk to ctrl */ + rkclk_ddr_reset(dram, 1, 1, 0, 0); + udelay(10); + phy_soft_reset(dram->phy); + /* release ctrl presetn, and config ctl registers */ + rkclk_ddr_reset(dram, 1, 0, 0, 0); + pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); + cap_info->ddrconfig = calculate_ddrconfig(sdram_params); + set_ctl_address_map(dram, sdram_params); + phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew, + &sdram_params->base, cap_info->bw); + + /* enable dfi_init_start to init phy after ctl srstn deassert */ + setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); + rkclk_ddr_reset(dram, 0, 0, 0, 0); + /* wait for dfi_init_done and dram init complete */ + while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) + continue; + + /* do ddr gate training */ + if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { + printf("data training error\n"); + return -1; + } + + if (sdram_params->base.dramtype == DDR4) + pctl_write_vrefdq(dram->pctl, 0x3, 5670, + sdram_params->base.dramtype); + + if (pre_init != 0) { + rx_deskew_switch_adjust(dram); + tx_deskew_switch_adjust(dram); + } + + dram_all_config(dram, sdram_params); + enable_low_power(dram, sdram_params); + + return 0; +} + +static u64 dram_detect_cap(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params, + unsigned char channel) +{ + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + + /* + * for ddr3: ddrconf = 3 + * for ddr4: ddrconf = 12 + * for lpddr3: ddrconf = 3 + * default bw = 1 + */ + u32 bk, bktmp; + u32 col, coltmp; + u32 rowtmp; + u32 cs; + u32 bw = 1; + u32 dram_type = sdram_params->base.dramtype; + + if (dram_type != DDR4) { + /* detect col and bk for ddr3/lpddr3 */ + coltmp = 12; + bktmp = 3; + rowtmp = 16; + + if (sdram_detect_col(cap_info, coltmp) != 0) + goto cap_err; + sdram_detect_bank(cap_info, coltmp, bktmp); + sdram_detect_dbw(cap_info, dram_type); + } else { + /* detect bg for ddr4 */ + coltmp = 10; + bktmp = 4; + rowtmp = 17; + + col = 10; + bk = 2; + cap_info->col = col; + cap_info->bk = bk; + sdram_detect_bg(cap_info, coltmp); + } + + /* detect row */ + if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0) + goto cap_err; + + /* detect row_3_4 */ + sdram_detect_row_3_4(cap_info, coltmp, bktmp); + + /* bw and cs detect using data training */ + if (data_training(dram, 1, dram_type) == 0) + cs = 1; + else + cs = 0; + cap_info->rank = cs + 1; + + bw = 2; + cap_info->bw = bw; + + cap_info->cs0_high16bit_row = cap_info->cs0_row; + if (cs) { + cap_info->cs1_row = cap_info->cs0_row; + cap_info->cs1_high16bit_row = cap_info->cs0_row; + } else { + cap_info->cs1_row = 0; + cap_info->cs1_high16bit_row = 0; + } + + return 0; +cap_err: + return -1; +} + +static int sdram_init_detect(struct dram_info *dram, + struct rk3328_sdram_params *sdram_params) +{ + u32 sys_reg = 0; + u32 sys_reg3 = 0; + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; + + debug("Starting SDRAM initialization...\n"); + + memcpy(&sdram_ch, &sdram_params->ch, + sizeof(struct rk3328_sdram_channel)); + + sdram_init(dram, sdram_params, 0); + dram_detect_cap(dram, sdram_params, 0); + + /* modify bw, cs related timing */ + pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, + sdram_params->base.dramtype); + + if (cap_info->bw == 2) + sdram_ch.noc_timings.ddrtiming.b.bwratio = 0; + else + sdram_ch.noc_timings.ddrtiming.b.bwratio = 1; + + /* reinit sdram by real dram cap */ + sdram_init(dram, sdram_params, 1); + + /* redetect cs1 row */ + sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); + if (cap_info->cs1_row) { + sys_reg = readl(&dram->grf->os_reg[2]); + sys_reg3 = readl(&dram->grf->os_reg[3]); + SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, + sys_reg, sys_reg3, 0); + writel(sys_reg, &dram->grf->os_reg[2]); + writel(sys_reg3, &dram->grf->os_reg[3]); + } + + sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base); + + return 0; +} + +static int rk3328_dmc_init(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3328_sdram_params *params = &plat->sdram_params; +#else + struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; + struct rk3328_sdram_params *params = + (void *)dtplat->rockchip_sdram_params; + + ret = conv_of_plat(dev); + if (ret) + return ret; +#endif + priv->phy = regmap_get_range(plat->map, 0); + priv->pctl = regmap_get_range(plat->map, 1); + priv->grf = regmap_get_range(plat->map, 2); + priv->cru = regmap_get_range(plat->map, 3); + priv->msch = regmap_get_range(plat->map, 4); + priv->ddr_grf = regmap_get_range(plat->map, 5); + + debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n", + __func__, priv->phy, priv->pctl, priv->grf, priv->cru, + priv->msch, priv->ddr_grf); + ret = sdram_init_detect(priv, params); + if (ret < 0) { + printf("%s DRAM init failed%d\n", __func__, ret); + return ret; + } + + return 0; +} + +static int rk3328_dmc_of_to_plat(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; + + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)&plat->sdram_params, + sizeof(plat->sdram_params) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params %d\n", + __func__, ret); + return ret; + } + ret = regmap_init_mem(dev, &plat->map); + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); +#endif + return 0; +} + +#endif + +static int rk3328_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD + if (rk3328_dmc_init(dev)) + return 0; +#else + struct dram_info *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->grf->os_reg[2]); +#endif + return 0; +} + +static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3328_dmc_ops = { + .get_info = rk3328_dmc_get_info, +}; + +static const struct udevice_id rk3328_dmc_ids[] = { + { .compatible = "rockchip,rk3328-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3328_dmc) = { + .name = "rockchip_rk3328_dmc", + .id = UCLASS_RAM, + .of_match = rk3328_dmc_ids, + .ops = &rk3328_dmc_ops, +#ifdef CONFIG_TPL_BUILD + .of_to_plat = rk3328_dmc_of_to_plat, +#endif + .probe = rk3328_dmc_probe, + .priv_auto = sizeof(struct dram_info), +#ifdef CONFIG_TPL_BUILD + .plat_auto = sizeof(struct rockchip_dmc_plat), +#endif +}; diff --git a/roms/u-boot/drivers/ram/rockchip/sdram_rk3399.c b/roms/u-boot/drivers/ram/rockchip/sdram_rk3399.c new file mode 100644 index 000000000..a83a670b3 --- /dev/null +++ b/roms/u-boot/drivers/ram/rockchip/sdram_rk3399.c @@ -0,0 +1,3185 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2016-2017 Rockchip Inc. + * + * Adapted from coreboot. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) +#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) +#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) + +#define PHY_DRV_ODT_HI_Z 0x0 +#define PHY_DRV_ODT_240 0x1 +#define PHY_DRV_ODT_120 0x8 +#define PHY_DRV_ODT_80 0x9 +#define PHY_DRV_ODT_60 0xc +#define PHY_DRV_ODT_48 0xd +#define PHY_DRV_ODT_40 0xe +#define PHY_DRV_ODT_34_3 0xf + +#define PHY_BOOSTP_EN 0x1 +#define PHY_BOOSTN_EN 0x1 +#define PHY_SLEWP_EN 0x1 +#define PHY_SLEWN_EN 0x1 +#define PHY_RX_CM_INPUT 0x1 +#define CS0_MR22_VAL 0 +#define CS1_MR22_VAL 3 + +/* LPDDR3 DRAM DS */ +#define LPDDR3_DS_34 0x1 +#define LPDDR3_DS_40 0x2 +#define LPDDR3_DS_48 0x3 + +#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ + ((n) << (8 + (ch) * 4))) +#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ + ((n) << (9 + (ch) * 4))) +struct chan_info { + struct rk3399_ddr_pctl_regs *pctl; + struct rk3399_ddr_pi_regs *pi; + struct rk3399_ddr_publ_regs *publ; + struct msch_regs *msch; +}; + +struct dram_info { +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + u32 pwrup_srefresh_exit[2]; + struct chan_info chan[2]; + struct clk ddr_clk; + struct rockchip_cru *cru; + struct rk3399_grf_regs *grf; + struct rk3399_pmu_regs *pmu; + struct rk3399_pmucru *pmucru; + struct rk3399_pmusgrf_regs *pmusgrf; + struct rk3399_ddr_cic_regs *cic; + const struct sdram_rk3399_ops *ops; +#endif + struct ram_info info; + struct rk3399_pmugrf_regs *pmugrf; +}; + +struct sdram_rk3399_ops { + int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *sdram); + int (*set_rate_index)(struct dram_info *dram, + struct rk3399_sdram_params *params); + void (*modify_param)(const struct chan_info *chan, + struct rk3399_sdram_params *params); + struct rk3399_sdram_params * + (*get_phy_index_params)(u32 phy_fn, + struct rk3399_sdram_params *params); +}; + +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + +struct rockchip_dmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3399_dmc dtplat; +#else + struct rk3399_sdram_params sdram_params; +#endif + struct regmap *map; +}; + +struct io_setting { + u32 mhz; + u32 mr5; + /* dram side */ + u32 dq_odt; + u32 ca_odt; + u32 pdds; + u32 dq_vref; + u32 ca_vref; + /* phy side */ + u32 rd_odt; + u32 wr_dq_drv; + u32 wr_ca_drv; + u32 wr_ckcs_drv; + u32 rd_odt_en; + u32 rd_vref; +} lpddr4_io_setting[] = { + { + 50 * MHz, + 0, + /* dram side */ + 0, /* dq_odt; */ + 0, /* ca_odt; */ + 6, /* pdds; */ + 0x72, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_HI_Z, /* rd_odt; */ + PHY_DRV_ODT_40, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 0, /* rd_odt_en;*/ + 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, + { + 600 * MHz, + 0, + /* dram side */ + 1, /* dq_odt; */ + 0, /* ca_odt; */ + 6, /* pdds; */ + 0x72, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_HI_Z, /* rd_odt; */ + PHY_DRV_ODT_48, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 0, /* rd_odt_en; */ + 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, + { + 933 * MHz, + 0, + /* dram side */ + 1, /* dq_odt; */ + 0, /* ca_odt; */ + 3, /* pdds; */ + 0x72, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_80, /* rd_odt; */ + PHY_DRV_ODT_40, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 1, /* rd_odt_en; */ + 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, + { + 1066 * MHz, + 0, + /* dram side */ + 6, /* dq_odt; */ + 0, /* ca_odt; */ + 3, /* pdds; */ + 0x10, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_80, /* rd_odt; */ + PHY_DRV_ODT_60, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 1, /* rd_odt_en; */ + 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, +}; + +static struct io_setting * +lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5) +{ + struct io_setting *io = NULL; + u32 n; + + for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) { + io = &lpddr4_io_setting[n]; + + if (io->mr5 != 0) { + if (io->mhz >= params->base.ddr_freq && + io->mr5 == mr5) + break; + } else { + if (io->mhz >= params->base.ddr_freq) + break; + } + } + + return io; +} + +static void *get_denali_ctl(const struct chan_info *chan, + struct rk3399_sdram_params *params, bool reg) +{ + return reg ? &chan->pctl->denali_ctl : ¶ms->pctl_regs.denali_ctl; +} + +static void *get_denali_phy(const struct chan_info *chan, + struct rk3399_sdram_params *params, bool reg) +{ + return reg ? &chan->publ->denali_phy : ¶ms->phy_regs.denali_phy; +} + +static void *get_ddrc0_con(struct dram_info *dram, u8 channel) +{ + return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0; +} + +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl, + u32 phy) +{ + channel &= 0x1; + ctl &= 0x1; + phy &= 0x1; + writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | + CRU_SFTRST_DDR_PHY(channel, phy), + &cru->softrst_con[4]); +} + +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel) +{ + rkclk_ddr_reset(cru, channel, 1, 1); + udelay(10); + + rkclk_ddr_reset(cru, channel, 1, 0); + udelay(10); + + rkclk_ddr_reset(cru, channel, 0, 0); + udelay(10); +} + +static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, + u32 freq) +{ + u32 *denali_phy = ddr_publ_regs->denali_phy; + + /* From IP spec, only freq small than 125 can enter dll bypass mode */ + if (freq <= 125) { + /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ + setbits_le32(&denali_phy[86], (0x3 << 2) << 8); + setbits_le32(&denali_phy[214], (0x3 << 2) << 8); + setbits_le32(&denali_phy[342], (0x3 << 2) << 8); + setbits_le32(&denali_phy[470], (0x3 << 2) << 8); + + /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ + setbits_le32(&denali_phy[547], (0x3 << 2) << 16); + setbits_le32(&denali_phy[675], (0x3 << 2) << 16); + setbits_le32(&denali_phy[803], (0x3 << 2) << 16); + } else { + /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ + clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); + clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); + clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); + clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); + + /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ + clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); + clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); + clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); + } +} + +static void set_memory_map(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *params) +{ + const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel]; + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_pi = chan->pi->denali_pi; + u32 cs_map; + u32 reduc; + u32 row; + + /* Get row number from ddrconfig setting */ + if (sdram_ch->cap_info.ddrconfig < 2 || + sdram_ch->cap_info.ddrconfig == 4) + row = 16; + else if (sdram_ch->cap_info.ddrconfig == 3 || + sdram_ch->cap_info.ddrconfig == 5) + row = 14; + else + row = 15; + + cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; + reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; + + /* Set the dram configuration to ctrl */ + clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); + clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->cap_info.bk) << 16) | + ((16 - row) << 24)); + + clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), + cs_map | (reduc << 16)); + + /* PI_199 PI_COL_DIFF:RW:0:4 */ + clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); + + /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ + clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->cap_info.bk) << 16) | + ((16 - row) << 24)); + + if (params->base.dramtype == LPDDR4) { + if (cs_map == 1) + cs_map = 0x5; + else if (cs_map == 2) + cs_map = 0xa; + else + cs_map = 0xF; + } + + /* PI_41 PI_CS_MAP:RW:24:4 */ + clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); + if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3) + writel(0x2EC7FFFF, &denali_pi[34]); +} + +static int phy_io_config(u32 *denali_phy, u32 *denali_ctl, + const struct rk3399_sdram_params *params, u32 mr5) +{ + u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; + u32 mode_sel; + u32 speed; + u32 reg_value; + u32 ds_value, odt_value; + + /* vref setting & mode setting */ + if (params->base.dramtype == LPDDR4) { + struct io_setting *io = lpddr4_get_io_settings(params, mr5); + u32 rd_vref = io->rd_vref * 1000; + + if (rd_vref < 36700) { + /* MODE_LV[2:0] = LPDDR4 (Range 2)*/ + vref_mode_dq = 0x7; + /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */ + mode_sel = 0x5; + vref_value_dq = (rd_vref - 3300) / 521; + } else { + /* MODE_LV[2:0] = LPDDR4 (Range 1)*/ + vref_mode_dq = 0x6; + /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */ + mode_sel = 0x4; + vref_value_dq = (rd_vref - 15300) / 521; + } + vref_mode_ac = 0x6; + /* VDDQ/3/2=16.8% */ + vref_value_ac = 0x3; + } else if (params->base.dramtype == LPDDR3) { + if (params->base.odt == 1) { + vref_mode_dq = 0x5; /* LPDDR3 ODT */ + ds_value = readl(&denali_ctl[138]) & 0xf; + odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; + if (ds_value == LPDDR3_DS_48) { + switch (odt_value) { + case PHY_DRV_ODT_240: + vref_value_dq = 0x1B; + break; + case PHY_DRV_ODT_120: + vref_value_dq = 0x26; + break; + case PHY_DRV_ODT_60: + vref_value_dq = 0x36; + break; + default: + debug("Invalid ODT value.\n"); + return -EINVAL; + } + } else if (ds_value == LPDDR3_DS_40) { + switch (odt_value) { + case PHY_DRV_ODT_240: + vref_value_dq = 0x19; + break; + case PHY_DRV_ODT_120: + vref_value_dq = 0x23; + break; + case PHY_DRV_ODT_60: + vref_value_dq = 0x31; + break; + default: + debug("Invalid ODT value.\n"); + return -EINVAL; + } + } else if (ds_value == LPDDR3_DS_34) { + switch (odt_value) { + case PHY_DRV_ODT_240: + vref_value_dq = 0x17; + break; + case PHY_DRV_ODT_120: + vref_value_dq = 0x20; + break; + case PHY_DRV_ODT_60: + vref_value_dq = 0x2e; + break; + default: + debug("Invalid ODT value.\n"); + return -EINVAL; + } + } else { + debug("Invalid DRV value.\n"); + return -EINVAL; + } + } else { + vref_mode_dq = 0x2; /* LPDDR3 */ + vref_value_dq = 0x1f; + } + vref_mode_ac = 0x2; + vref_value_ac = 0x1f; + mode_sel = 0x0; + } else if (params->base.dramtype == DDR3) { + /* DDR3L */ + vref_mode_dq = 0x1; + vref_value_dq = 0x1f; + vref_mode_ac = 0x1; + vref_value_ac = 0x1f; + mode_sel = 0x1; + } else { + debug("Unknown DRAM type.\n"); + return -EINVAL; + } + + reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; + + /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ + clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); + /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ + clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); + /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ + clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); + /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ + clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); + + reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; + + /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ + clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); + + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + + if (params->base.dramtype == LPDDR4) { + /* BOOSTP_EN & BOOSTN_EN */ + reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN); + /* PHY_925 PHY_PAD_FDBK_DRIVE2 */ + clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20); + + /* SLEWP_EN & SLEWN_EN */ + reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN); + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x3f, reg_value); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x3f, reg_value); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8); + } + + /* speed setting */ + speed = 0x2; + + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + + if (params->base.dramtype == LPDDR4) { + /* RX_CM_INPUT */ + reg_value = PHY_RX_CM_INPUT; + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19); + } + + return 0; +} + +static void set_ds_odt(const struct chan_info *chan, + struct rk3399_sdram_params *params, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg); + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; + u32 tsel_idle_select_p, tsel_rd_select_p; + u32 tsel_idle_select_n, tsel_rd_select_n; + u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; + u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + u32 tsel_ckcs_select_p, tsel_ckcs_select_n; + struct io_setting *io = NULL; + u32 soc_odt = 0; + u32 reg_value; + + if (params->base.dramtype == LPDDR4) { + io = lpddr4_get_io_settings(params, mr5); + + tsel_rd_select_p = PHY_DRV_ODT_HI_Z; + tsel_rd_select_n = io->rd_odt; + + tsel_idle_select_p = PHY_DRV_ODT_HI_Z; + tsel_idle_select_n = PHY_DRV_ODT_HI_Z; + + tsel_wr_select_dq_p = io->wr_dq_drv; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = io->wr_ca_drv; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_ckcs_select_p = io->wr_ckcs_drv; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; + + switch (tsel_rd_select_n) { + case PHY_DRV_ODT_240: + soc_odt = 1; + break; + case PHY_DRV_ODT_120: + soc_odt = 2; + break; + case PHY_DRV_ODT_80: + soc_odt = 3; + break; + case PHY_DRV_ODT_60: + soc_odt = 4; + break; + case PHY_DRV_ODT_48: + soc_odt = 5; + break; + case PHY_DRV_ODT_40: + soc_odt = 6; + break; + case PHY_DRV_ODT_34_3: + soc_odt = 6; + printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n", + __func__); + break; + case PHY_DRV_ODT_HI_Z: + default: + soc_odt = 0; + break; + } + } else if (params->base.dramtype == LPDDR3) { + tsel_rd_select_p = PHY_DRV_ODT_240; + tsel_rd_select_n = PHY_DRV_ODT_HI_Z; + + tsel_idle_select_p = PHY_DRV_ODT_240; + tsel_idle_select_n = PHY_DRV_ODT_HI_Z; + + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; + } else { + tsel_rd_select_p = PHY_DRV_ODT_240; + tsel_rd_select_n = PHY_DRV_ODT_240; + + tsel_idle_select_p = PHY_DRV_ODT_240; + tsel_idle_select_n = PHY_DRV_ODT_240; + + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; + } + + if (params->base.odt == 1) { + tsel_rd_en = 1; + + if (params->base.dramtype == LPDDR4) + tsel_rd_en = io->rd_odt_en; + } else { + tsel_rd_en = 0; + } + + tsel_wr_en = 0; + tsel_idle_en = 0; + + /* F0_0 */ + clrsetbits_le32(&denali_ctl[145], 0xFF << 16, + (soc_odt | (CS0_MR22_VAL << 3)) << 16); + /* F2_0, F1_0 */ + clrsetbits_le32(&denali_ctl[146], 0xFF00FF, + ((soc_odt | (CS0_MR22_VAL << 3)) << 16) | + (soc_odt | (CS0_MR22_VAL << 3))); + /* F0_1 */ + clrsetbits_le32(&denali_ctl[159], 0xFF << 16, + (soc_odt | (CS1_MR22_VAL << 3)) << 16); + /* F2_1, F1_1 */ + clrsetbits_le32(&denali_ctl[160], 0xFF00FF, + ((soc_odt | (CS1_MR22_VAL << 3)) << 16) | + (soc_odt | (CS1_MR22_VAL << 3))); + + /* + * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 + * sets termination values for read/idle cycles and drive strength + * for write cycles for DQ/DM + */ + reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | + (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | + (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); + clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); + + /* + * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 + * sets termination values for read/idle cycles and drive strength + * for write cycles for DQS + */ + clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); + + /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ + reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); + if (params->base.dramtype == LPDDR4) { + /* LPDDR4 these register read always return 0, so + * can not use clrsetbits_le32(), need to write32 + */ + writel((0x300 << 8) | reg_value, &denali_phy[544]); + writel((0x300 << 8) | reg_value, &denali_phy[672]); + writel((0x300 << 8) | reg_value, &denali_phy[800]); + } else { + clrsetbits_le32(&denali_phy[544], 0xff, reg_value); + clrsetbits_le32(&denali_phy[672], 0xff, reg_value); + clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + } + + /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ + clrsetbits_le32(&denali_phy[928], 0xff, reg_value); + + /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ + if (!ctl_phy_reg) + clrsetbits_le32(&denali_phy[937], 0xff, reg_value); + + /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ + clrsetbits_le32(&denali_phy[935], 0xff, reg_value); + + /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ + clrsetbits_le32(&denali_phy[939], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); + + /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ + clrsetbits_le32(&denali_phy[929], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); + + /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ + clrsetbits_le32(&denali_phy[924], 0xff, + tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 4)); + clrsetbits_le32(&denali_phy[925], 0xff, + tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4)); + + /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ + reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) + << 16; + clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); + + /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ + reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) + << 24; + clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); + + /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ + reg_value = tsel_wr_en << 8; + clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); + clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); + clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); + + /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ + reg_value = tsel_wr_en << 17; + clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); + /* + * pad_rst/cke/cs/clk_term tsel 1bits + * DENALI_PHY_938/936/940/934 offset_17 + */ + clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); + + /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ + clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); + + phy_io_config(denali_phy, denali_ctl, params, mr5); +} + +static void pctl_start(struct dram_info *dram, + struct rk3399_sdram_params *params, + u32 channel_mask) +{ + const struct chan_info *chan_0 = &dram->chan[0]; + const struct chan_info *chan_1 = &dram->chan[1]; + + u32 *denali_ctl_0 = chan_0->pctl->denali_ctl; + u32 *denali_phy_0 = chan_0->publ->denali_phy; + u32 *ddrc0_con_0 = get_ddrc0_con(dram, 0); + u32 *denali_ctl_1 = chan_1->pctl->denali_ctl; + u32 *denali_phy_1 = chan_1->publ->denali_phy; + u32 *ddrc1_con_0 = get_ddrc0_con(dram, 1); + u32 count = 0; + u32 byte, tmp; + + /* PHY_DLL_RST_EN */ + if (channel_mask & 1) { + writel(0x01000000, &ddrc0_con_0); + clrsetbits_le32(&denali_phy_0[957], 0x3 << 24, 0x2 << 24); + } + + if (channel_mask & 1) { + count = 0; + while (!(readl(&denali_ctl_0[203]) & (1 << 3))) { + if (count > 1000) { + printf("%s: Failed to init pctl channel 0\n", + __func__); + while (1) + ; + } + udelay(1); + count++; + } + + writel(0x01000100, &ddrc0_con_0); + for (byte = 0; byte < 4; byte++) { + tmp = 0x820; + writel((tmp << 16) | tmp, + &denali_phy_0[53 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_0[54 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_0[55 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_0[56 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_0[57 + (128 * byte)]); + clrsetbits_le32(&denali_phy_0[58 + (128 * byte)], + 0xffff, tmp); + } + clrsetbits_le32(&denali_ctl_0[68], PWRUP_SREFRESH_EXIT, + dram->pwrup_srefresh_exit[0]); + } + + if (channel_mask & 2) { + writel(0x01000000, &ddrc1_con_0); + clrsetbits_le32(&denali_phy_1[957], 0x3 << 24, 0x2 << 24); + } + if (channel_mask & 2) { + count = 0; + while (!(readl(&denali_ctl_1[203]) & (1 << 3))) { + if (count > 1000) { + printf("%s: Failed to init pctl channel 1\n", + __func__); + while (1) + ; + } + udelay(1); + count++; + } + + writel(0x01000100, &ddrc1_con_0); + for (byte = 0; byte < 4; byte++) { + tmp = 0x820; + writel((tmp << 16) | tmp, + &denali_phy_1[53 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_1[54 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_1[55 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_1[56 + (128 * byte)]); + writel((tmp << 16) | tmp, + &denali_phy_1[57 + (128 * byte)]); + clrsetbits_le32(&denali_phy_1[58 + (128 * byte)], + 0xffff, tmp); + } + + clrsetbits_le32(&denali_ctl_1[68], PWRUP_SREFRESH_EXIT, + dram->pwrup_srefresh_exit[1]); + + /* + * restore channel 1 RESET original setting + * to avoid 240ohm too weak to prevent ESD test + */ + if (params->base.dramtype == LPDDR4) + clrsetbits_le32(&denali_phy_1[937], 0xff, + params->phy_regs.denali_phy[937] & + 0xFF); + } +} + +static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, + u32 channel, struct rk3399_sdram_params *params) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + const u32 *params_ctl = params->pctl_regs.denali_ctl; + const u32 *params_phy = params->phy_regs.denali_phy; + u32 tmp, tmp1, tmp2; + struct rk3399_sdram_params *params_cfg; + u32 byte; + + dram->ops->modify_param(chan, params); + /* + * work around controller bug: + * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed + */ + sdram_copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], + sizeof(struct rk3399_ddr_pctl_regs) - 4); + writel(params_ctl[0], &denali_ctl[0]); + + /* + * two channel init at the same time, then ZQ Cal Start + * at the same time, it will use the same RZQ, but cannot + * start at the same time. + * + * So, increase tINIT3 for channel 1, will avoid two + * channel ZQ Cal Start at the same time + */ + if (params->base.dramtype == LPDDR4 && channel == 1) { + tmp = ((params->base.ddr_freq * MHz + 999) / 1000); + tmp1 = readl(&denali_ctl[14]); + writel(tmp + tmp1, &denali_ctl[14]); + } + + sdram_copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], + sizeof(struct rk3399_ddr_pi_regs)); + + /* rank count need to set for init */ + set_memory_map(chan, channel, params); + + writel(params->phy_regs.denali_phy[910], &denali_phy[910]); + writel(params->phy_regs.denali_phy[911], &denali_phy[911]); + writel(params->phy_regs.denali_phy[912], &denali_phy[912]); + + if (params->base.dramtype == LPDDR4) { + writel(params->phy_regs.denali_phy[898], &denali_phy[898]); + writel(params->phy_regs.denali_phy[919], &denali_phy[919]); + } + + dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & + PWRUP_SREFRESH_EXIT; + clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); + + /* PHY_DLL_RST_EN */ + clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); + + setbits_le32(&denali_pi[0], START); + setbits_le32(&denali_ctl[0], START); + + /** + * LPDDR4 use PLL bypass mode for init + * not need to wait for the PLL to lock + */ + if (params->base.dramtype != LPDDR4) { + /* Waiting for phy DLL lock */ + while (1) { + tmp = readl(&denali_phy[920]); + tmp1 = readl(&denali_phy[921]); + tmp2 = readl(&denali_phy[922]); + if ((((tmp >> 16) & 0x1) == 0x1) && + (((tmp1 >> 16) & 0x1) == 0x1) && + (((tmp1 >> 0) & 0x1) == 0x1) && + (((tmp2 >> 0) & 0x1) == 0x1)) + break; + } + } + + sdram_copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); + sdram_copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); + sdram_copy_to_reg(&denali_phy[128], ¶ms_phy[128], + (218 - 128 + 1) * 4); + sdram_copy_to_reg(&denali_phy[256], ¶ms_phy[256], + (346 - 256 + 1) * 4); + sdram_copy_to_reg(&denali_phy[384], ¶ms_phy[384], + (474 - 384 + 1) * 4); + sdram_copy_to_reg(&denali_phy[512], ¶ms_phy[512], + (549 - 512 + 1) * 4); + sdram_copy_to_reg(&denali_phy[640], ¶ms_phy[640], + (677 - 640 + 1) * 4); + sdram_copy_to_reg(&denali_phy[768], ¶ms_phy[768], + (805 - 768 + 1) * 4); + + if (params->base.dramtype == LPDDR4) + params_cfg = dram->ops->get_phy_index_params(1, params); + else + params_cfg = dram->ops->get_phy_index_params(0, params); + + clrsetbits_le32(¶ms_cfg->phy_regs.denali_phy[896], 0x3 << 8, + 0 << 8); + writel(params_cfg->phy_regs.denali_phy[896], &denali_phy[896]); + + writel(params->phy_regs.denali_phy[83] + (0x10 << 16), + &denali_phy[83]); + writel(params->phy_regs.denali_phy[84] + (0x10 << 8), + &denali_phy[84]); + writel(params->phy_regs.denali_phy[211] + (0x10 << 16), + &denali_phy[211]); + writel(params->phy_regs.denali_phy[212] + (0x10 << 8), + &denali_phy[212]); + writel(params->phy_regs.denali_phy[339] + (0x10 << 16), + &denali_phy[339]); + writel(params->phy_regs.denali_phy[340] + (0x10 << 8), + &denali_phy[340]); + writel(params->phy_regs.denali_phy[467] + (0x10 << 16), + &denali_phy[467]); + writel(params->phy_regs.denali_phy[468] + (0x10 << 8), + &denali_phy[468]); + + if (params->base.dramtype == LPDDR4) { + /* + * to improve write dqs and dq phase from 1.5ns to 3.5ns + * at 50MHz. this's the measure result from oscilloscope + * of dqs and dq write signal. + */ + for (byte = 0; byte < 4; byte++) { + tmp = 0x680; + clrsetbits_le32(&denali_phy[1 + (128 * byte)], + 0xfff << 8, tmp << 8); + } + /* + * to workaround 366ball two channel's RESET connect to + * one RESET signal of die + */ + if (channel == 1) + clrsetbits_le32(&denali_phy[937], 0xff, + PHY_DRV_ODT_240 | + (PHY_DRV_ODT_240 << 0x4)); + } + + return 0; +} + +static void select_per_cs_training_index(const struct chan_info *chan, + u32 rank) +{ + u32 *denali_phy = chan->publ->denali_phy; + + /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ + if ((readl(&denali_phy[84]) >> 16) & 1) { + /* + * PHY_8/136/264/392 + * phy_per_cs_training_index_X 1bit offset_24 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); + clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); + clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); + clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); + } +} + +static void override_write_leveling_value(const struct chan_info *chan) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_phy = chan->publ->denali_phy; + u32 byte; + + /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ + setbits_le32(&denali_phy[896], 1); + + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); + + for (byte = 0; byte < 4; byte++) + clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, + 0x200 << 16); + + /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ + clrbits_le32(&denali_phy[896], 1); + + /* CTL_200 ctrlupd_req 1bit offset_8 */ + clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); +} + +static int data_training_ca(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + u32 i, tmp; + u32 obs_0, obs_1, obs_2, obs_err = 0; + u32 rank = params->ch[channel].cap_info.rank; + u32 rank_mask; + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + + if (params->base.dramtype == LPDDR4) + rank_mask = (rank == 1) ? 0x5 : 0xf; + else + rank_mask = (rank == 1) ? 0x1 : 0x3; + + for (i = 0; i < 4; i++) { + if (!(rank_mask & (1 << i))) + continue; + + select_per_cs_training_index(chan, i); + + /* PI_100 PI_CALVL_EN:RW:8:2 */ + clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); + + /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ + clrsetbits_le32(&denali_pi[92], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + /* + * check status obs + * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 + */ + obs_0 = readl(&denali_phy[532]); + obs_1 = readl(&denali_phy[660]); + obs_2 = readl(&denali_phy[788]); + if (((obs_0 >> 30) & 0x3) || + ((obs_1 >> 30) & 0x3) || + ((obs_2 >> 30) & 0x3)) + obs_err = 1; + if ((((tmp >> 11) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 5) & 0x1) == 0x0) && + obs_err == 0) + break; + else if ((((tmp >> 5) & 0x1) == 0x1) || + (obs_err == 1)) + return -EIO; + } + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + + clrbits_le32(&denali_pi[100], 0x3 << 8); + + return 0; +} + +static int data_training_wl(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + u32 i, tmp; + u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; + u32 rank = params->ch[channel].cap_info.rank; + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + + /* PI_60 PI_WRLVL_EN:RW:8:2 */ + clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); + + /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ + clrsetbits_le32(&denali_pi[59], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + + /* + * check status obs, if error maybe can not + * get leveling done PHY_40/168/296/424 + * phy_wrlvl_status_obs_X:0:13 + */ + obs_0 = readl(&denali_phy[40]); + obs_1 = readl(&denali_phy[168]); + obs_2 = readl(&denali_phy[296]); + obs_3 = readl(&denali_phy[424]); + if (((obs_0 >> 12) & 0x1) || + ((obs_1 >> 12) & 0x1) || + ((obs_2 >> 12) & 0x1) || + ((obs_3 >> 12) & 0x1)) + obs_err = 1; + if ((((tmp >> 10) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 4) & 0x1) == 0x0) && + obs_err == 0) + break; + else if ((((tmp >> 4) & 0x1) == 0x1) || + (obs_err == 1)) + return -EIO; + } + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + + override_write_leveling_value(chan); + clrbits_le32(&denali_pi[60], 0x3 << 8); + + return 0; +} + +static int data_training_rg(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + u32 i, tmp; + u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; + u32 rank = params->ch[channel].cap_info.rank; + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + + /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ + clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); + + /* + * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 + * PI_RDLVL_CS:RW:24:2 + */ + clrsetbits_le32(&denali_pi[74], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + + /* + * check status obs + * PHY_43/171/299/427 + * PHY_GTLVL_STATUS_OBS_x:16:8 + */ + obs_0 = readl(&denali_phy[43]); + obs_1 = readl(&denali_phy[171]); + obs_2 = readl(&denali_phy[299]); + obs_3 = readl(&denali_phy[427]); + if (((obs_0 >> (16 + 6)) & 0x3) || + ((obs_1 >> (16 + 6)) & 0x3) || + ((obs_2 >> (16 + 6)) & 0x3) || + ((obs_3 >> (16 + 6)) & 0x3)) + obs_err = 1; + if ((((tmp >> 9) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 3) & 0x1) == 0x0) && + obs_err == 0) + break; + else if ((((tmp >> 3) & 0x1) == 0x1) || + (obs_err == 1)) + return -EIO; + } + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + + clrbits_le32(&denali_pi[80], 0x3 << 24); + + return 0; +} + +static int data_training_rl(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 i, tmp; + u32 rank = params->ch[channel].cap_info.rank; + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + + /* PI_80 PI_RDLVL_EN:RW:16:2 */ + clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); + + /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ + clrsetbits_le32(&denali_pi[74], + (0x1 << 8) | (0x3 << 24), + (0x1 << 8) | (i << 24)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + + /* + * make sure status obs not report error bit + * PHY_46/174/302/430 + * phy_rdlvl_status_obs_X:16:8 + */ + if ((((tmp >> 8) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 2) & 0x1) == 0x0)) + break; + else if (((tmp >> 2) & 0x1) == 0x1) + return -EIO; + } + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + + clrbits_le32(&denali_pi[80], 0x3 << 16); + + return 0; +} + +static int data_training_wdql(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 i, tmp; + u32 rank = params->ch[channel].cap_info.rank; + u32 rank_mask; + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + + if (params->base.dramtype == LPDDR4) + rank_mask = (rank == 1) ? 0x5 : 0xf; + else + rank_mask = (rank == 1) ? 0x1 : 0x3; + + for (i = 0; i < 4; i++) { + if (!(rank_mask & (1 << i))) + continue; + + select_per_cs_training_index(chan, i); + + /* + * disable PI_WDQLVL_VREF_EN before wdq leveling? + * PI_117 PI_WDQLVL_VREF_EN:RW:8:1 + */ + clrbits_le32(&denali_pi[117], 0x1 << 8); + /* PI_124 PI_WDQLVL_EN:RW:16:2 */ + clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); + + /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ + clrsetbits_le32(&denali_pi[121], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + if ((((tmp >> 12) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 6) & 0x1) == 0x0)) + break; + else if (((tmp >> 6) & 0x1) == 0x1) + return -EIO; + } + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + + clrbits_le32(&denali_pi[124], 0x3 << 16); + + return 0; +} + +static int data_training(struct dram_info *dram, u32 channel, + const struct rk3399_sdram_params *params, + u32 training_flag) +{ + struct chan_info *chan = &dram->chan[channel]; + u32 *denali_phy = chan->publ->denali_phy; + int ret; + + /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ + setbits_le32(&denali_phy[927], (1 << 22)); + + if (training_flag == PI_FULL_TRAINING) { + if (params->base.dramtype == LPDDR4) { + training_flag = PI_WRITE_LEVELING | + PI_READ_GATE_TRAINING | + PI_READ_LEVELING | PI_WDQ_LEVELING; + } else if (params->base.dramtype == LPDDR3) { + training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | + PI_READ_GATE_TRAINING; + } else if (params->base.dramtype == DDR3) { + training_flag = PI_WRITE_LEVELING | + PI_READ_GATE_TRAINING | + PI_READ_LEVELING; + } + } + + /* ca training(LPDDR4,LPDDR3 support) */ + if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { + ret = data_training_ca(chan, channel, params); + if (ret < 0) { + debug("%s: data training ca failed\n", __func__); + return ret; + } + } + + /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ + if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { + ret = data_training_wl(chan, channel, params); + if (ret < 0) { + debug("%s: data training wl failed\n", __func__); + return ret; + } + } + + /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ + if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { + ret = data_training_rg(chan, channel, params); + if (ret < 0) { + debug("%s: data training rg failed\n", __func__); + return ret; + } + } + + /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ + if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { + ret = data_training_rl(chan, channel, params); + if (ret < 0) { + debug("%s: data training rl failed\n", __func__); + return ret; + } + } + + /* wdq leveling(LPDDR4 support) */ + if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { + ret = data_training_wdql(chan, channel, params); + if (ret < 0) { + debug("%s: data training wdql failed\n", __func__); + return ret; + } + } + + /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ + clrbits_le32(&denali_phy[927], (1 << 22)); + + return 0; +} + +static void set_ddrconfig(const struct chan_info *chan, + const struct rk3399_sdram_params *params, + unsigned char channel, u32 ddrconfig) +{ + /* only need to set ddrconfig */ + struct msch_regs *ddr_msch_regs = chan->msch; + unsigned int cs0_cap = 0; + unsigned int cs1_cap = 0; + + cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row + + params->ch[channel].cap_info.col + + params->ch[channel].cap_info.bk + + params->ch[channel].cap_info.bw - 20)); + if (params->ch[channel].cap_info.rank > 1) + cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row + - params->ch[channel].cap_info.cs1_row); + if (params->ch[channel].cap_info.row_3_4) { + cs0_cap = cs0_cap * 3 / 4; + cs1_cap = cs1_cap * 3 / 4; + } + + writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); + writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), + &ddr_msch_regs->ddrsize); +} + +static void sdram_msch_config(struct msch_regs *msch, + struct sdram_msch_timings *noc_timings) +{ + writel(noc_timings->ddrtiminga0.d32, + &msch->ddrtiminga0.d32); + writel(noc_timings->ddrtimingb0.d32, + &msch->ddrtimingb0.d32); + writel(noc_timings->ddrtimingc0.d32, + &msch->ddrtimingc0.d32); + writel(noc_timings->devtodev0.d32, + &msch->devtodev0.d32); + writel(noc_timings->ddrmode.d32, + &msch->ddrmode.d32); +} + +static void dram_all_config(struct dram_info *dram, + struct rk3399_sdram_params *params) +{ + u32 sys_reg2 = 0; + u32 sys_reg3 = 0; + unsigned int channel, idx; + + for (channel = 0, idx = 0; + (idx < params->base.num_channels) && (channel < 2); + channel++) { + struct msch_regs *ddr_msch_regs; + struct sdram_msch_timings *noc_timing; + + if (params->ch[channel].cap_info.col == 0) + continue; + idx++; + sdram_org_config(¶ms->ch[channel].cap_info, + ¶ms->base, &sys_reg2, + &sys_reg3, channel); + ddr_msch_regs = dram->chan[channel].msch; + noc_timing = ¶ms->ch[channel].noc_timings; + sdram_msch_config(ddr_msch_regs, noc_timing); + + /** + * rank 1 memory clock disable (dfi_dram_clk_disable = 1) + * + * The hardware for LPDDR4 with + * - CLK0P/N connect to lower 16-bits + * - CLK1P/N connect to higher 16-bits + * + * dfi dram clk is configured via CLK1P/N, so disabling + * dfi dram clk will disable the CLK1P/N as well for lpddr4. + */ + if (params->ch[channel].cap_info.rank == 1 && + params->base.dramtype != LPDDR4) + setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], + 1 << 17); + } + + writel(sys_reg2, &dram->pmugrf->os_reg2); + writel(sys_reg3, &dram->pmugrf->os_reg3); + rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, + params->base.stride << 10); + + /* reboot hold register set */ + writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | + PRESET_GPIO1_HOLD(1), + &dram->pmucru->pmucru_rstnhold_con[1]); + clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); +} + +static void set_cap_relate_config(const struct chan_info *chan, + struct rk3399_sdram_params *params, + unsigned int channel) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 tmp; + struct sdram_msch_timings *noc_timing; + + if (params->base.dramtype == LPDDR3) { + tmp = (8 << params->ch[channel].cap_info.bw) / + (8 << params->ch[channel].cap_info.dbw); + + /** + * memdata_ratio + * 1 -> 0, 2 -> 1, 4 -> 2 + */ + clrsetbits_le32(&denali_ctl[197], 0x7, + (tmp >> 1)); + clrsetbits_le32(&denali_ctl[198], 0x7 << 8, + (tmp >> 1) << 8); + } + + noc_timing = ¶ms->ch[channel].noc_timings; + + /* + * noc timing bw relate timing is 32 bit, and real bw is 16bit + * actually noc reg is setting at function dram_all_config + */ + if (params->ch[channel].cap_info.bw == 16 && + noc_timing->ddrmode.b.mwrsize == 2) { + if (noc_timing->ddrmode.b.burstsize) + noc_timing->ddrmode.b.burstsize -= 1; + noc_timing->ddrmode.b.mwrsize -= 1; + noc_timing->ddrtimingc0.b.burstpenalty *= 2; + noc_timing->ddrtimingc0.b.wrtomwr *= 2; + } +} + +static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel) +{ + unsigned int cs0_row = params->ch[channel].cap_info.cs0_row; + unsigned int col = params->ch[channel].cap_info.col; + unsigned int bw = params->ch[channel].cap_info.bw; + u16 ddr_cfg_2_rbc[] = { + /* + * [6] highest bit col + * [5:3] max row(14+n) + * [2] insertion row + * [1:0] col(9+n),col, data bus 32bit + * + * highbitcol, max_row, insertion_row, col + */ + ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ + ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ + ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ + ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ + ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ + ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ + ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ + ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ + }; + u32 i; + + col -= (bw == 2) ? 0 : 1; + col -= 9; + + for (i = 0; i < 4; i++) { + if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && + (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) + break; + } + + if (i >= 4) + i = -EINVAL; + + return i; +} + +static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) +{ + rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); +} + +#if !defined(CONFIG_RAM_RK3399_LPDDR4) +static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *params) +{ + u8 training_flag = PI_READ_GATE_TRAINING; + + /* + * LPDDR3 CA training msut be trigger before + * other training. + * DDR3 is not have CA training. + */ + + if (params->base.dramtype == LPDDR3) + training_flag |= PI_CA_TRAINING; + + return data_training(dram, channel, params, training_flag); +} + +static int switch_to_phy_index1(struct dram_info *dram, + struct rk3399_sdram_params *params) +{ + u32 channel; + u32 *denali_phy; + u32 ch_count = params->base.num_channels; + int ret; + int i = 0; + + writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, + 1 << 4 | 1 << 2 | 1), + &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { + mdelay(10); + i++; + if (i > 10) { + debug("index1 frequency change overtime\n"); + return -ETIME; + } + } + + i = 0; + writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { + mdelay(10); + i++; + if (i > 10) { + debug("index1 frequency done overtime\n"); + return -ETIME; + } + } + + for (channel = 0; channel < ch_count; channel++) { + denali_phy = dram->chan[channel].publ->denali_phy; + clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); + ret = data_training(dram, channel, params, PI_FULL_TRAINING); + if (ret < 0) { + debug("index1 training failed\n"); + return ret; + } + } + + return 0; +} + +struct rk3399_sdram_params + *get_phy_index_params(u32 phy_fn, + struct rk3399_sdram_params *params) +{ + if (phy_fn == 0) + return params; + else + return NULL; +} + +void modify_param(const struct chan_info *chan, + struct rk3399_sdram_params *params) +{ + struct rk3399_sdram_params *params_cfg; + u32 *denali_pi_params; + + denali_pi_params = params->pi_regs.denali_pi; + + /* modify PHY F0/F1/F2 params */ + params_cfg = get_phy_index_params(0, params); + set_ds_odt(chan, params_cfg, false, 0); + + clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); +} +#else + +struct rk3399_sdram_params dfs_cfgs_lpddr4[] = { +#include "sdram-rk3399-lpddr4-400.inc" +#include "sdram-rk3399-lpddr4-800.inc" +}; + +static struct rk3399_sdram_params + *lpddr4_get_phy_index_params(u32 phy_fn, + struct rk3399_sdram_params *params) +{ + if (phy_fn == 0) + return params; + else if (phy_fn == 1) + return &dfs_cfgs_lpddr4[1]; + else if (phy_fn == 2) + return &dfs_cfgs_lpddr4[0]; + else + return NULL; +} + +static void *get_denali_pi(const struct chan_info *chan, + struct rk3399_sdram_params *params, bool reg) +{ + return reg ? &chan->pi->denali_pi : ¶ms->pi_regs.denali_pi; +} + +static u32 lpddr4_get_phy_fn(struct rk3399_sdram_params *params, u32 ctl_fn) +{ + u32 lpddr4_phy_fn[] = {1, 0, 0xb}; + + return lpddr4_phy_fn[ctl_fn]; +} + +static u32 lpddr4_get_ctl_fn(struct rk3399_sdram_params *params, u32 phy_fn) +{ + u32 lpddr4_ctl_fn[] = {1, 0, 2}; + + return lpddr4_ctl_fn[phy_fn]; +} + +static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf) +{ + return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F); +} + +/* + * read mr_num mode register + * rank = 1: cs0 + * rank = 2: cs1 + */ +static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank, + u32 mr_num, u32 *buf) +{ + s32 timeout = 100; + + writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8, + &ddr_pctl_regs->denali_ctl[118]); + + while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) & + ((1 << 21) | (1 << 12)))) { + udelay(1); + + if (timeout <= 0) { + printf("%s: pctl timeout!\n", __func__); + return -ETIMEDOUT; + } + + timeout--; + } + + if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) { + *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF; + } else { + printf("%s: read mr failed with 0x%x status\n", __func__, + readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3); + *buf = 0; + } + + setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12)); + + return 0; +} + +static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *params) +{ + u64 cs0_cap; + u32 stride; + u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0; + u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0; + u32 mr5, mr12, mr14; + struct chan_info *chan = &dram->chan[channel]; + struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl; + void __iomem *addr = NULL; + int ret = 0; + u32 val; + + stride = get_ddr_stride(dram->pmusgrf); + + if (params->ch[channel].cap_info.col == 0) { + ret = -EPERM; + goto end; + } + + cs = params->ch[channel].cap_info.rank; + col = params->ch[channel].cap_info.col; + bk = params->ch[channel].cap_info.bk; + bw = params->ch[channel].cap_info.bw; + row_3_4 = params->ch[channel].cap_info.row_3_4; + cs0_row = params->ch[channel].cap_info.cs0_row; + cs1_row = params->ch[channel].cap_info.cs1_row; + ddrconfig = params->ch[channel].cap_info.ddrconfig; + + /* 2GB */ + params->ch[channel].cap_info.rank = 2; + params->ch[channel].cap_info.col = 10; + params->ch[channel].cap_info.bk = 3; + params->ch[channel].cap_info.bw = 2; + params->ch[channel].cap_info.row_3_4 = 0; + params->ch[channel].cap_info.cs0_row = 15; + params->ch[channel].cap_info.cs1_row = 15; + params->ch[channel].cap_info.ddrconfig = 1; + + set_memory_map(chan, channel, params); + params->ch[channel].cap_info.ddrconfig = + calculate_ddrconfig(params, channel); + set_ddrconfig(chan, params, channel, + params->ch[channel].cap_info.ddrconfig); + set_cap_relate_config(chan, params, channel); + + cs0_cap = (1 << (params->ch[channel].cap_info.bw + + params->ch[channel].cap_info.col + + params->ch[channel].cap_info.bk + + params->ch[channel].cap_info.cs0_row)); + + if (params->ch[channel].cap_info.row_3_4) + cs0_cap = cs0_cap * 3 / 4; + + if (channel == 0) + set_ddr_stride(dram->pmusgrf, 0x17); + else + set_ddr_stride(dram->pmusgrf, 0x18); + + /* read and write data to DRAM, avoid be optimized by compiler. */ + if (rank == 1) + addr = (void __iomem *)0x100; + else if (rank == 2) + addr = (void __iomem *)(cs0_cap + 0x100); + + val = readl(addr); + writel(val + 1, addr); + + read_mr(ddr_pctl_regs, rank, 5, &mr5); + read_mr(ddr_pctl_regs, rank, 12, &mr12); + read_mr(ddr_pctl_regs, rank, 14, &mr14); + + if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) { + ret = -EINVAL; + goto end; + } +end: + params->ch[channel].cap_info.rank = cs; + params->ch[channel].cap_info.col = col; + params->ch[channel].cap_info.bk = bk; + params->ch[channel].cap_info.bw = bw; + params->ch[channel].cap_info.row_3_4 = row_3_4; + params->ch[channel].cap_info.cs0_row = cs0_row; + params->ch[channel].cap_info.cs1_row = cs1_row; + params->ch[channel].cap_info.ddrconfig = ddrconfig; + + set_ddr_stride(dram->pmusgrf, stride); + + return ret; +} + +static void set_lpddr4_dq_odt(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl_fn, + bool en, bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + if (en) + reg_value = io->dq_odt; + else + reg_value = 0; + + switch (ctl_fn) { + case 0: + clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24); + clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24); + + clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16)); + break; + case 1: + clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0); + clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0); + + clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0)); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8)); + clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8)); + + clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16)); + break; + } +} + +static void set_lpddr4_ca_odt(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl_fn, + bool en, bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + if (en) + reg_value = io->ca_odt; + else + reg_value = 0; + + switch (ctl_fn) { + case 0: + clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28); + clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28); + + clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20); + break; + case 1: + clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4); + + clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12)); + clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12)); + + clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20); + break; + } +} + +static void set_lpddr4_MR3(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl_fn, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = ((io->pdds << 3) | 1); + + switch (ctl_fn) { + case 0: + clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value); + break; + case 1: + clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value); + break; + } +} + +static void set_lpddr4_MR12(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl_fn, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = io->ca_vref; + + switch (ctl_fn) { + case 0: + clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24); + break; + case 1: + clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24); + break; + } +} + +static void set_lpddr4_MR14(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl_fn, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = io->dq_vref; + + switch (ctl_fn) { + case 0: + clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0); + break; + case 1: + clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0); + break; + } +} + +void lpddr4_modify_param(const struct chan_info *chan, + struct rk3399_sdram_params *params) +{ + struct rk3399_sdram_params *params_cfg; + u32 *denali_ctl_params; + u32 *denali_pi_params; + u32 *denali_phy_params; + + denali_ctl_params = params->pctl_regs.denali_ctl; + denali_pi_params = params->pi_regs.denali_pi; + denali_phy_params = params->phy_regs.denali_phy; + + set_lpddr4_dq_odt(chan, params, 2, true, false, 0); + set_lpddr4_ca_odt(chan, params, 2, true, false, 0); + set_lpddr4_MR3(chan, params, 2, false, 0); + set_lpddr4_MR12(chan, params, 2, false, 0); + set_lpddr4_MR14(chan, params, 2, false, 0); + params_cfg = lpddr4_get_phy_index_params(0, params); + set_ds_odt(chan, params_cfg, false, 0); + /* read two cycle preamble */ + clrsetbits_le32(&denali_ctl_params[200], 0x3 << 24, 0x3 << 24); + clrsetbits_le32(&denali_phy_params[7], 0x3 << 24, 0x3 << 24); + clrsetbits_le32(&denali_phy_params[135], 0x3 << 24, 0x3 << 24); + clrsetbits_le32(&denali_phy_params[263], 0x3 << 24, 0x3 << 24); + clrsetbits_le32(&denali_phy_params[391], 0x3 << 24, 0x3 << 24); + + /* boot frequency two cycle preamble */ + clrsetbits_le32(&denali_phy_params[2], 0x3 << 16, 0x3 << 16); + clrsetbits_le32(&denali_phy_params[130], 0x3 << 16, 0x3 << 16); + clrsetbits_le32(&denali_phy_params[258], 0x3 << 16, 0x3 << 16); + clrsetbits_le32(&denali_phy_params[386], 0x3 << 16, 0x3 << 16); + + clrsetbits_le32(&denali_pi_params[45], 0x3 << 8, 0x3 << 8); + clrsetbits_le32(&denali_pi_params[58], 0x1, 0x1); + + /* + * bypass mode need PHY_SLICE_PWR_RDC_DISABLE_x = 1, + * boot frequency mode use bypass mode + */ + setbits_le32(&denali_phy_params[10], 1 << 16); + setbits_le32(&denali_phy_params[138], 1 << 16); + setbits_le32(&denali_phy_params[266], 1 << 16); + setbits_le32(&denali_phy_params[394], 1 << 16); + + clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); +} + +static void lpddr4_copy_phy(struct dram_info *dram, + struct rk3399_sdram_params *params, u32 phy_fn, + struct rk3399_sdram_params *params_cfg, + u32 channel) +{ + u32 *denali_ctl, *denali_phy; + u32 *denali_phy_params; + u32 speed = 0; + u32 ctl_fn, mr5; + + denali_ctl = dram->chan[channel].pctl->denali_ctl; + denali_phy = dram->chan[channel].publ->denali_phy; + denali_phy_params = params_cfg->phy_regs.denali_phy; + + /* switch index */ + clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, + phy_fn << 8); + writel(denali_phy_params[896], &denali_phy[896]); + + /* phy_pll_ctrl_ca, phy_pll_ctrl */ + writel(denali_phy_params[911], &denali_phy[911]); + + /* phy_low_freq_sel */ + clrsetbits_le32(&denali_phy[913], 0x1, + denali_phy_params[913] & 0x1); + + /* phy_grp_slave_delay_x, phy_cslvl_dly_step */ + writel(denali_phy_params[916], &denali_phy[916]); + writel(denali_phy_params[917], &denali_phy[917]); + writel(denali_phy_params[918], &denali_phy[918]); + + /* phy_adrz_sw_wraddr_shift_x */ + writel(denali_phy_params[512], &denali_phy[512]); + clrsetbits_le32(&denali_phy[513], 0xffff, + denali_phy_params[513] & 0xffff); + writel(denali_phy_params[640], &denali_phy[640]); + clrsetbits_le32(&denali_phy[641], 0xffff, + denali_phy_params[641] & 0xffff); + writel(denali_phy_params[768], &denali_phy[768]); + clrsetbits_le32(&denali_phy[769], 0xffff, + denali_phy_params[769] & 0xffff); + + writel(denali_phy_params[544], &denali_phy[544]); + writel(denali_phy_params[545], &denali_phy[545]); + writel(denali_phy_params[546], &denali_phy[546]); + writel(denali_phy_params[547], &denali_phy[547]); + + writel(denali_phy_params[672], &denali_phy[672]); + writel(denali_phy_params[673], &denali_phy[673]); + writel(denali_phy_params[674], &denali_phy[674]); + writel(denali_phy_params[675], &denali_phy[675]); + + writel(denali_phy_params[800], &denali_phy[800]); + writel(denali_phy_params[801], &denali_phy[801]); + writel(denali_phy_params[802], &denali_phy[802]); + writel(denali_phy_params[803], &denali_phy[803]); + + /* + * phy_adr_master_delay_start_x + * phy_adr_master_delay_step_x + * phy_adr_master_delay_wait_x + */ + writel(denali_phy_params[548], &denali_phy[548]); + writel(denali_phy_params[676], &denali_phy[676]); + writel(denali_phy_params[804], &denali_phy[804]); + + /* phy_adr_calvl_dly_step_x */ + writel(denali_phy_params[549], &denali_phy[549]); + writel(denali_phy_params[677], &denali_phy[677]); + writel(denali_phy_params[805], &denali_phy[805]); + + /* + * phy_clk_wrdm_slave_delay_x + * phy_clk_wrdqz_slave_delay_x + * phy_clk_wrdqs_slave_delay_x + */ + sdram_copy_to_reg((u32 *)&denali_phy[59], + (u32 *)&denali_phy_params[59], (63 - 58) * 4); + sdram_copy_to_reg((u32 *)&denali_phy[187], + (u32 *)&denali_phy_params[187], (191 - 186) * 4); + sdram_copy_to_reg((u32 *)&denali_phy[315], + (u32 *)&denali_phy_params[315], (319 - 314) * 4); + sdram_copy_to_reg((u32 *)&denali_phy[443], + (u32 *)&denali_phy_params[443], (447 - 442) * 4); + + /* + * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8 + * dqs_tsel_wr_end[7:4] add half cycle + * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8 + * dq_tsel_wr_end[7:4] add half cycle + */ + writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]); + writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]); + writel(denali_phy_params[85], &denali_phy[85]); + + writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]); + writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]); + writel(denali_phy_params[213], &denali_phy[213]); + + writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]); + writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]); + writel(denali_phy_params[341], &denali_phy[341]); + + writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]); + writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]); + writel(denali_phy_params[469], &denali_phy[469]); + + /* + * phy_gtlvl_resp_wait_cnt_x + * phy_gtlvl_dly_step_x + * phy_wrlvl_resp_wait_cnt_x + * phy_gtlvl_final_step_x + * phy_gtlvl_back_step_x + * phy_rdlvl_dly_step_x + * + * phy_master_delay_step_x + * phy_master_delay_wait_x + * phy_wrlvl_dly_step_x + * phy_rptr_update_x + * phy_wdqlvl_dly_step_x + */ + writel(denali_phy_params[87], &denali_phy[87]); + writel(denali_phy_params[88], &denali_phy[88]); + writel(denali_phy_params[89], &denali_phy[89]); + writel(denali_phy_params[90], &denali_phy[90]); + + writel(denali_phy_params[215], &denali_phy[215]); + writel(denali_phy_params[216], &denali_phy[216]); + writel(denali_phy_params[217], &denali_phy[217]); + writel(denali_phy_params[218], &denali_phy[218]); + + writel(denali_phy_params[343], &denali_phy[343]); + writel(denali_phy_params[344], &denali_phy[344]); + writel(denali_phy_params[345], &denali_phy[345]); + writel(denali_phy_params[346], &denali_phy[346]); + + writel(denali_phy_params[471], &denali_phy[471]); + writel(denali_phy_params[472], &denali_phy[472]); + writel(denali_phy_params[473], &denali_phy[473]); + writel(denali_phy_params[474], &denali_phy[474]); + + /* + * phy_gtlvl_lat_adj_start_x + * phy_gtlvl_rddqs_slv_dly_start_x + * phy_rdlvl_rddqs_dq_slv_dly_start_x + * phy_wdqlvl_dqdm_slv_dly_start_x + */ + writel(denali_phy_params[80], &denali_phy[80]); + writel(denali_phy_params[81], &denali_phy[81]); + + writel(denali_phy_params[208], &denali_phy[208]); + writel(denali_phy_params[209], &denali_phy[209]); + + writel(denali_phy_params[336], &denali_phy[336]); + writel(denali_phy_params[337], &denali_phy[337]); + + writel(denali_phy_params[464], &denali_phy[464]); + writel(denali_phy_params[465], &denali_phy[465]); + + /* + * phy_master_delay_start_x + * phy_sw_master_mode_x + * phy_rddata_en_tsel_dly_x + */ + writel(denali_phy_params[86], &denali_phy[86]); + writel(denali_phy_params[214], &denali_phy[214]); + writel(denali_phy_params[342], &denali_phy[342]); + writel(denali_phy_params[470], &denali_phy[470]); + + /* + * phy_rddqz_slave_delay_x + * phy_rddqs_dqz_fall_slave_delay_x + * phy_rddqs_dqz_rise_slave_delay_x + * phy_rddqs_dm_fall_slave_delay_x + * phy_rddqs_dm_rise_slave_delay_x + * phy_rddqs_gate_slave_delay_x + * phy_wrlvl_delay_early_threshold_x + * phy_write_path_lat_add_x + * phy_rddqs_latency_adjust_x + * phy_wrlvl_delay_period_threshold_x + * phy_wrlvl_early_force_zero_x + */ + sdram_copy_to_reg((u32 *)&denali_phy[64], + (u32 *)&denali_phy_params[64], (67 - 63) * 4); + clrsetbits_le32(&denali_phy[68], 0xfffffc00, + denali_phy_params[68] & 0xfffffc00); + sdram_copy_to_reg((u32 *)&denali_phy[69], + (u32 *)&denali_phy_params[69], (79 - 68) * 4); + sdram_copy_to_reg((u32 *)&denali_phy[192], + (u32 *)&denali_phy_params[192], (195 - 191) * 4); + clrsetbits_le32(&denali_phy[196], 0xfffffc00, + denali_phy_params[196] & 0xfffffc00); + sdram_copy_to_reg((u32 *)&denali_phy[197], + (u32 *)&denali_phy_params[197], (207 - 196) * 4); + sdram_copy_to_reg((u32 *)&denali_phy[320], + (u32 *)&denali_phy_params[320], (323 - 319) * 4); + clrsetbits_le32(&denali_phy[324], 0xfffffc00, + denali_phy_params[324] & 0xfffffc00); + sdram_copy_to_reg((u32 *)&denali_phy[325], + (u32 *)&denali_phy_params[325], (335 - 324) * 4); + sdram_copy_to_reg((u32 *)&denali_phy[448], + (u32 *)&denali_phy_params[448], (451 - 447) * 4); + clrsetbits_le32(&denali_phy[452], 0xfffffc00, + denali_phy_params[452] & 0xfffffc00); + sdram_copy_to_reg((u32 *)&denali_phy[453], + (u32 *)&denali_phy_params[453], (463 - 452) * 4); + + /* phy_two_cyc_preamble_x */ + clrsetbits_le32(&denali_phy[7], 0x3 << 24, + denali_phy_params[7] & (0x3 << 24)); + clrsetbits_le32(&denali_phy[135], 0x3 << 24, + denali_phy_params[135] & (0x3 << 24)); + clrsetbits_le32(&denali_phy[263], 0x3 << 24, + denali_phy_params[263] & (0x3 << 24)); + clrsetbits_le32(&denali_phy[391], 0x3 << 24, + denali_phy_params[391] & (0x3 << 24)); + + /* speed */ + if (params_cfg->base.ddr_freq < 400) + speed = 0x0; + else if (params_cfg->base.ddr_freq < 800) + speed = 0x1; + else if (params_cfg->base.ddr_freq < 1200) + speed = 0x2; + + /* phy_924 phy_pad_fdbk_drive */ + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); + /* phy_926 phy_pad_data_drive */ + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); + /* phy_927 phy_pad_dqs_drive */ + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); + /* phy_928 phy_pad_addr_drive */ + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); + /* phy_929 phy_pad_clk_drive */ + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); + /* phy_935 phy_pad_cke_drive */ + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); + /* phy_937 phy_pad_rst_drive */ + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); + /* phy_939 phy_pad_cs_drive */ + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + + if (params_cfg->base.dramtype == LPDDR4) { + read_mr(dram->chan[channel].pctl, 1, 5, &mr5); + set_ds_odt(&dram->chan[channel], params_cfg, true, mr5); + + ctl_fn = lpddr4_get_ctl_fn(params_cfg, phy_fn); + set_lpddr4_dq_odt(&dram->chan[channel], params_cfg, + ctl_fn, true, true, mr5); + set_lpddr4_ca_odt(&dram->chan[channel], params_cfg, + ctl_fn, true, true, mr5); + set_lpddr4_MR3(&dram->chan[channel], params_cfg, + ctl_fn, true, mr5); + set_lpddr4_MR12(&dram->chan[channel], params_cfg, + ctl_fn, true, mr5); + set_lpddr4_MR14(&dram->chan[channel], params_cfg, + ctl_fn, true, mr5); + + /* + * if phy_sw_master_mode_x not bypass mode, + * clear phy_slice_pwr_rdc_disable. + * note: need use timings, not ddr_publ_regs + */ + if (!((denali_phy_params[86] >> 8) & (1 << 2))) { + clrbits_le32(&denali_phy[10], 1 << 16); + clrbits_le32(&denali_phy[138], 1 << 16); + clrbits_le32(&denali_phy[266], 1 << 16); + clrbits_le32(&denali_phy[394], 1 << 16); + } + + /* + * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't + * smaller than 8 + * NOTE: need use timings, not ddr_publ_regs + */ + if ((denali_phy_params[84] >> 16) & 1) { + if (((readl(&denali_ctl[217 + ctl_fn]) >> + 16) & 0x1f) < 8) + clrsetbits_le32(&denali_ctl[217 + ctl_fn], + 0x1f << 16, + 8 << 16); + } + } +} + +static void lpddr4_set_phy(struct dram_info *dram, + struct rk3399_sdram_params *params, u32 phy_fn, + struct rk3399_sdram_params *params_cfg) +{ + u32 channel; + + for (channel = 0; channel < 2; channel++) + lpddr4_copy_phy(dram, params, phy_fn, params_cfg, + channel); +} + +static int lpddr4_set_ctl(struct dram_info *dram, + struct rk3399_sdram_params *params, + u32 fn, u32 hz) +{ + u32 channel; + int ret_clk, ret; + + /* cci idle req stall */ + writel(0x70007, &dram->grf->soc_con0); + + /* enable all clk */ + setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); + + /* idle */ + setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); + while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) + != (0x3 << 18)) + ; + + /* change freq */ + writel((((0x3 << 4) | (1 << 2) | 1) << 16) | + (fn << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 2))) + ; + + ret_clk = clk_set_rate(&dram->ddr_clk, hz); + if (ret_clk < 0) { + printf("%s clk set failed %d\n", __func__, ret_clk); + return ret_clk; + } + + writel(0x20002, &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 0))) + ; + + /* deidle */ + clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); + while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) + ; + + /* clear enable all clk */ + clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); + + /* lpddr4 ctl2 can not do training, all training will fail */ + if (!(params->base.dramtype == LPDDR4 && fn == 2)) { + for (channel = 0; channel < 2; channel++) { + if (!(params->ch[channel].cap_info.col)) + continue; + ret = data_training(dram, channel, params, + PI_FULL_TRAINING); + if (ret) + printf("%s: channel %d training failed!\n", + __func__, channel); + else + debug("%s: channel %d training pass\n", + __func__, channel); + } + } + + return 0; +} + +static int lpddr4_set_rate(struct dram_info *dram, + struct rk3399_sdram_params *params) +{ + u32 ctl_fn; + u32 phy_fn; + + for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) { + phy_fn = lpddr4_get_phy_fn(params, ctl_fn); + + lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); + lpddr4_set_ctl(dram, params, ctl_fn, + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); + + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) + printf("%s: change freq to %d mhz %d, %d\n", __func__, + dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, + ctl_fn, phy_fn); + } + + return 0; +} +#endif /* CONFIG_RAM_RK3399_LPDDR4 */ + +/* CS0,n=1 + * CS1,n=2 + * CS0 & CS1, n=3 + * cs0_cap: MB unit + */ +static void dram_set_cs(const struct chan_info *chan, u32 cs_map, u32 cs0_cap, + unsigned char dramtype) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_pi = chan->pi->denali_pi; + struct msch_regs *ddr_msch_regs = chan->msch; + + clrsetbits_le32(&denali_ctl[196], 0x3, cs_map); + writel((cs0_cap / 32) | (((4096 - cs0_cap) / 32) << 8), + &ddr_msch_regs->ddrsize); + if (dramtype == LPDDR4) { + if (cs_map == 1) + cs_map = 0x5; + else if (cs_map == 2) + cs_map = 0xa; + else + cs_map = 0xF; + } + /*PI_41 PI_CS_MAP:RW:24:4*/ + clrsetbits_le32(&denali_pi[41], + 0xf << 24, cs_map << 24); + if (cs_map == 1 && dramtype == DDR3) + writel(0x2EC7FFFF, &denali_pi[34]); +} + +static void dram_set_bw(const struct chan_info *chan, u32 bw) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + + if (bw == 2) + clrbits_le32(&denali_ctl[196], 1 << 16); + else + setbits_le32(&denali_ctl[196], 1 << 16); +} + +static void dram_set_max_col(const struct chan_info *chan, u32 bw, u32 *pcol) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + struct msch_regs *ddr_msch_regs = chan->msch; + u32 *denali_pi = chan->pi->denali_pi; + u32 ddrconfig; + + clrbits_le32(&denali_ctl[191], 0xf); + clrsetbits_le32(&denali_ctl[190], + (7 << 24), + ((16 - ((bw == 2) ? 14 : 15)) << 24)); + /*PI_199 PI_COL_DIFF:RW:0:4*/ + clrbits_le32(&denali_pi[199], 0xf); + /*PI_155 PI_ROW_DIFF:RW:24:3*/ + clrsetbits_le32(&denali_pi[155], + (7 << 24), + ((16 - 12) << 24)); + ddrconfig = (bw == 2) ? 3 : 2; + writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); + /* set max cs0 size */ + writel((4096 / 32) | ((0 / 32) << 8), + &ddr_msch_regs->ddrsize); + + *pcol = 12; +} + +static void dram_set_max_bank(const struct chan_info *chan, u32 bw, u32 *pbank, + u32 *pcol) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_pi = chan->pi->denali_pi; + + clrbits_le32(&denali_ctl[191], 0xf); + clrbits_le32(&denali_ctl[190], (3 << 16)); + /*PI_199 PI_COL_DIFF:RW:0:4*/ + clrbits_le32(&denali_pi[199], 0xf); + /*PI_155 PI_BANK_DIFF:RW:16:2*/ + clrbits_le32(&denali_pi[155], (3 << 16)); + + *pbank = 3; + *pcol = 12; +} + +static void dram_set_max_row(const struct chan_info *chan, u32 bw, u32 *prow, + u32 *pbank, u32 *pcol) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_pi = chan->pi->denali_pi; + struct msch_regs *ddr_msch_regs = chan->msch; + + clrsetbits_le32(&denali_ctl[191], 0xf, 12 - 10); + clrbits_le32(&denali_ctl[190], + (0x3 << 16) | (0x7 << 24)); + /*PI_199 PI_COL_DIFF:RW:0:4*/ + clrsetbits_le32(&denali_pi[199], 0xf, 12 - 10); + /*PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2*/ + clrbits_le32(&denali_pi[155], + (0x3 << 16) | (0x7 << 24)); + writel(1 | (1 << 8), &ddr_msch_regs->ddrconf); + /* set max cs0 size */ + writel((4096 / 32) | ((0 / 32) << 8), + &ddr_msch_regs->ddrsize); + + *prow = 16; + *pbank = 3; + *pcol = (bw == 2) ? 10 : 11; +} + +static u64 dram_detect_cap(struct dram_info *dram, + struct rk3399_sdram_params *params, + unsigned char channel) +{ + const struct chan_info *chan = &dram->chan[channel]; + struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info; + u32 bw; + u32 col_tmp; + u32 bk_tmp; + u32 row_tmp; + u32 cs0_cap; + u32 training_flag; + u32 ddrconfig; + + /* detect bw */ + bw = 2; + if (params->base.dramtype != LPDDR4) { + dram_set_bw(chan, bw); + cap_info->bw = bw; + if (data_training(dram, channel, params, + PI_READ_GATE_TRAINING)) { + bw = 1; + dram_set_bw(chan, 1); + cap_info->bw = bw; + if (data_training(dram, channel, params, + PI_READ_GATE_TRAINING)) { + printf("16bit error!!!\n"); + goto error; + } + } + } + /* + * LPDDR3 CA training msut be trigger before other training. + * DDR3 is not have CA training. + */ + if (params->base.dramtype == LPDDR3) + training_flag = PI_WRITE_LEVELING; + else + training_flag = PI_FULL_TRAINING; + + if (params->base.dramtype != LPDDR4) { + if (data_training(dram, channel, params, training_flag)) { + printf("full training error!!!\n"); + goto error; + } + } + + /* detect col */ + dram_set_max_col(chan, bw, &col_tmp); + if (sdram_detect_col(cap_info, col_tmp) != 0) + goto error; + + /* detect bank */ + dram_set_max_bank(chan, bw, &bk_tmp, &col_tmp); + sdram_detect_bank(cap_info, col_tmp, bk_tmp); + + /* detect row */ + dram_set_max_row(chan, bw, &row_tmp, &bk_tmp, &col_tmp); + if (sdram_detect_row(cap_info, col_tmp, bk_tmp, row_tmp) != 0) + goto error; + + /* detect row_3_4 */ + sdram_detect_row_3_4(cap_info, col_tmp, bk_tmp); + + /* set ddrconfig */ + cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + cap_info->bk + + cap_info->bw - 20)); + if (cap_info->row_3_4) + cs0_cap = cs0_cap * 3 / 4; + + cap_info->cs1_row = cap_info->cs0_row; + set_memory_map(chan, channel, params); + ddrconfig = calculate_ddrconfig(params, channel); + if (-1 == ddrconfig) + goto error; + set_ddrconfig(chan, params, channel, + cap_info->ddrconfig); + + /* detect cs1 row */ + sdram_detect_cs1_row(cap_info, params->base.dramtype); + + /* detect die bw */ + sdram_detect_dbw(cap_info, params->base.dramtype); + + return 0; +error: + return (-1); +} + +static unsigned char calculate_stride(struct rk3399_sdram_params *params) +{ + unsigned int gstride_type; + unsigned int channel; + unsigned int chinfo = 0; + unsigned int cap = 0; + unsigned int stride = -1; + unsigned int ch_cap[2] = {0, 0}; + + gstride_type = STRIDE_256B; + + for (channel = 0; channel < 2; channel++) { + unsigned int cs0_cap = 0; + unsigned int cs1_cap = 0; + struct sdram_cap_info *cap_info = + ¶ms->ch[channel].cap_info; + + if (cap_info->col == 0) + continue; + + cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + + cap_info->bk + cap_info->bw - 20)); + if (cap_info->rank > 1) + cs1_cap = cs0_cap >> (cap_info->cs0_row + - cap_info->cs1_row); + if (cap_info->row_3_4) { + cs0_cap = cs0_cap * 3 / 4; + cs1_cap = cs1_cap * 3 / 4; + } + ch_cap[channel] = cs0_cap + cs1_cap; + chinfo |= 1 << channel; + } + + cap = ch_cap[0] + ch_cap[1]; + if (params->base.num_channels == 1) { + if (chinfo & 1) /* channel a only */ + stride = 0x17; + else /* channel b only */ + stride = 0x18; + } else {/* 2 channel */ + if (ch_cap[0] == ch_cap[1]) { + /* interleaved */ + if (gstride_type == PART_STRIDE) { + /* + * first 64MB no interleaved other 256B interleaved + * if 786M+768M.useful space from 0-1280MB and + * 1536MB-1792MB + * if 1.5G+1.5G(continuous).useful space from 0-2560MB + * and 3072MB-3584MB + */ + stride = 0x1F; + } else { + switch (cap) { + /* 512MB */ + case 512: + stride = 0; + break; + /* 1GB unstride or 256B stride*/ + case 1024: + stride = (gstride_type == UN_STRIDE) ? + 0x1 : 0x5; + break; + /* + * 768MB + 768MB same as total 2GB memory + * useful space: 0-768MB 1GB-1792MB + */ + case 1536: + /* 2GB unstride or 256B or 512B stride */ + case 2048: + stride = (gstride_type == UN_STRIDE) ? + 0x2 : + ((gstride_type == STRIDE_512B) ? + 0xA : 0x9); + break; + /* 1536MB + 1536MB */ + case 3072: + stride = (gstride_type == UN_STRIDE) ? + 0x3 : + ((gstride_type == STRIDE_512B) ? + 0x12 : 0x11); + break; + /* 4GB unstride or 128B,256B,512B,4KB stride */ + case 4096: + stride = (gstride_type == UN_STRIDE) ? + 0x3 : (0xC + gstride_type); + break; + } + } + } + if (ch_cap[0] == 2048 && ch_cap[1] == 1024) { + /* 2GB + 1GB */ + stride = (gstride_type == UN_STRIDE) ? 0x3 : 0x19; + } + /* + * remain two channel capability not equal OR capability + * power function of 2 + */ + if (stride == (-1)) { + switch ((ch_cap[0] > ch_cap[1]) ? + ch_cap[0] : ch_cap[1]) { + case 256: /* 256MB + 128MB */ + stride = 0; + break; + case 512: /* 512MB + 256MB */ + stride = 1; + break; + case 1024:/* 1GB + 128MB/256MB/384MB/512MB/768MB */ + stride = 2; + break; + case 2048: /* 2GB + 128MB/256MB/384MB/512MB/768MB/1GB */ + stride = 3; + break; + default: + break; + } + } + if (stride == (-1)) + goto error; + } + + sdram_print_stride(stride); + + return stride; +error: + printf("Cap not support!\n"); + return (-1); +} + +static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel) +{ + params->ch[channel].cap_info.rank = 0; + params->ch[channel].cap_info.col = 0; + params->ch[channel].cap_info.bk = 0; + params->ch[channel].cap_info.bw = 32; + params->ch[channel].cap_info.dbw = 32; + params->ch[channel].cap_info.row_3_4 = 0; + params->ch[channel].cap_info.cs0_row = 0; + params->ch[channel].cap_info.cs1_row = 0; + params->ch[channel].cap_info.ddrconfig = 0; +} + +static int sdram_init(struct dram_info *dram, + struct rk3399_sdram_params *params) +{ + unsigned char dramtype = params->base.dramtype; + unsigned int ddr_freq = params->base.ddr_freq; + int channel, ch, rank; + u32 tmp, ret; + + debug("Starting SDRAM initialization...\n"); + + if ((dramtype == DDR3 && ddr_freq > 933) || + (dramtype == LPDDR3 && ddr_freq > 933) || + (dramtype == LPDDR4 && ddr_freq > 800)) { + debug("SDRAM frequency is to high!"); + return -E2BIG; + } + + /* detect rank */ + for (ch = 0; ch < 2; ch++) { + params->ch[ch].cap_info.rank = 2; + for (rank = 2; rank != 0; rank--) { + for (channel = 0; channel < 2; channel++) { + const struct chan_info *chan = + &dram->chan[channel]; + struct rockchip_cru *cru = dram->cru; + struct rk3399_ddr_publ_regs *publ = chan->publ; + + phy_pctrl_reset(cru, channel); + phy_dll_bypass_set(publ, ddr_freq); + pctl_cfg(dram, chan, channel, params); + } + + /* start to trigger initialization */ + pctl_start(dram, params, 3); + + /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ + if (dramtype == LPDDR3) + udelay(10); + + tmp = (rank == 2) ? 3 : 1; + dram_set_cs(&dram->chan[ch], tmp, 2048, + params->base.dramtype); + params->ch[ch].cap_info.rank = rank; + + ret = dram->ops->data_training_first(dram, ch, + rank, params); + if (!ret) { + debug("%s: data trained for rank %d, ch %d\n", + __func__, rank, ch); + break; + } + } + /* Computed rank with associated channel number */ + params->ch[ch].cap_info.rank = rank; + } + + params->base.num_channels = 0; + for (channel = 0; channel < 2; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct sdram_cap_info *cap_info = + ¶ms->ch[channel].cap_info; + + if (cap_info->rank == 0) { + clear_channel_params(params, 1); + continue; + } else { + params->base.num_channels++; + } + + if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) { + printf("Channel "); + printf(channel ? "1: " : "0: "); + } + + if (channel == 0) + set_ddr_stride(dram->pmusgrf, 0x17); + else + set_ddr_stride(dram->pmusgrf, 0x18); + + if (dram_detect_cap(dram, params, channel)) { + printf("Cap error!\n"); + continue; + } + + sdram_print_ddr_info(cap_info, ¶ms->base); + set_memory_map(chan, channel, params); + cap_info->ddrconfig = + calculate_ddrconfig(params, channel); + if (-1 == cap_info->ddrconfig) { + printf("no ddrconfig find, Cap not support!\n"); + continue; + } + set_ddrconfig(chan, params, channel, cap_info->ddrconfig); + set_cap_relate_config(chan, params, channel); + } + + if (params->base.num_channels == 0) { + printf("%s: ", __func__); + sdram_print_dram_type(params->base.dramtype); + printf(" - %dMHz failed!\n", params->base.ddr_freq); + return -EINVAL; + } + + params->base.stride = calculate_stride(params); + dram_all_config(dram, params); + + dram->ops->set_rate_index(dram, params); + + debug("Finish SDRAM initialization...\n"); + return 0; +} + +static int rk3399_dmc_of_to_plat(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; + + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)&plat->sdram_params, + sizeof(plat->sdram_params) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params %d\n", + __func__, ret); + return ret; + } + ret = regmap_init_mem(dev_ofnode(dev), &plat->map); + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); + +#endif + return 0; +} + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_plat(struct udevice *dev) +{ + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; + int ret; + + ret = regmap_init_mem_plat(dev, dtplat->reg, + ARRAY_SIZE(dtplat->reg) / 2, &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static const struct sdram_rk3399_ops rk3399_ops = { +#if !defined(CONFIG_RAM_RK3399_LPDDR4) + .data_training_first = data_training_first, + .set_rate_index = switch_to_phy_index1, + .modify_param = modify_param, + .get_phy_index_params = get_phy_index_params, +#else + .data_training_first = lpddr4_mr_detect, + .set_rate_index = lpddr4_set_rate, + .modify_param = lpddr4_modify_param, + .get_phy_index_params = lpddr4_get_phy_index_params, +#endif +}; + +static int rk3399_dmc_init(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rockchip_dmc_plat *plat = dev_get_plat(dev); + int ret; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3399_sdram_params *params = &plat->sdram_params; +#else + struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; + struct rk3399_sdram_params *params = + (void *)dtplat->rockchip_sdram_params; + + ret = conv_of_plat(dev); + if (ret) + return ret; +#endif + + priv->ops = &rk3399_ops; + priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); + priv->pmucru = rockchip_get_pmucru(); + priv->cru = rockchip_get_cru(); + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].pi = regmap_get_range(plat->map, 1); + priv->chan[0].publ = regmap_get_range(plat->map, 2); + priv->chan[0].msch = regmap_get_range(plat->map, 3); + priv->chan[1].pctl = regmap_get_range(plat->map, 4); + priv->chan[1].pi = regmap_get_range(plat->map, 5); + priv->chan[1].publ = regmap_get_range(plat->map, 6); + priv->chan[1].msch = regmap_get_range(plat->map, 7); + + debug("con reg %p %p %p %p %p %p %p %p\n", + priv->chan[0].pctl, priv->chan[0].pi, + priv->chan[0].publ, priv->chan[0].msch, + priv->chan[1].pctl, priv->chan[1].pi, + priv->chan[1].publ, priv->chan[1].msch); + debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru, + priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu); + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->ddr_clk); +#else + ret = clk_get_by_index(dev, 0, &priv->ddr_clk); +#endif + if (ret) { + printf("%s clk get failed %d\n", __func__, ret); + return ret; + } + + ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); + if (ret < 0) { + printf("%s clk set failed %d\n", __func__, ret); + return ret; + } + + ret = sdram_init(priv, params); + if (ret < 0) { + printf("%s DRAM init failed %d\n", __func__, ret); + return ret; + } + + return 0; +} +#endif + +static int rk3399_dmc_probe(struct udevice *dev) +{ +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + if (rk3399_dmc_init(dev)) + return 0; +#else + struct dram_info *priv = dev_get_priv(dev); + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); +#endif + return 0; +} + +static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3399_dmc_ops = { + .get_info = rk3399_dmc_get_info, +}; + +static const struct udevice_id rk3399_dmc_ids[] = { + { .compatible = "rockchip,rk3399-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3399) = { + .name = "rockchip_rk3399_dmc", + .id = UCLASS_RAM, + .of_match = rk3399_dmc_ids, + .ops = &rk3399_dmc_ops, +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + .of_to_plat = rk3399_dmc_of_to_plat, +#endif + .probe = rk3399_dmc_probe, + .priv_auto = sizeof(struct dram_info), +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + .plat_auto = sizeof(struct rockchip_dmc_plat), +#endif +}; diff --git a/roms/u-boot/drivers/ram/sandbox_ram.c b/roms/u-boot/drivers/ram/sandbox_ram.c new file mode 100644 index 000000000..910dce623 --- /dev/null +++ b/roms/u-boot/drivers/ram/sandbox_ram.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int sandbox_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = 0; + info->size = gd->ram_size; + + return 0; +} + +static const struct ram_ops sandbox_ram_ops = { + .get_info = sandbox_get_info, +}; + +static const struct udevice_id sandbox_ram_ids[] = { + { .compatible = "sandbox,ram" }, + { } +}; + +U_BOOT_DRIVER(warm_ram_sandbox) = { + .name = "ram_sandbox", + .id = UCLASS_RAM, + .of_match = sandbox_ram_ids, + .ops = &sandbox_ram_ops, +}; diff --git a/roms/u-boot/drivers/ram/sifive/Kconfig b/roms/u-boot/drivers/ram/sifive/Kconfig new file mode 100644 index 000000000..0aaac0265 --- /dev/null +++ b/roms/u-boot/drivers/ram/sifive/Kconfig @@ -0,0 +1,13 @@ +config RAM_SIFIVE + bool "Ram drivers support for SiFive SoCs" + depends on RAM && RISCV + default y + help + This enables support for ram drivers of SiFive SoCs. + +config SIFIVE_DDR + bool "SiFive DDR driver" + depends on RAM_SIFIVE + default y if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED + help + This enables DDR support for the platforms based on SiFive SoC. diff --git a/roms/u-boot/drivers/ram/sifive/Makefile b/roms/u-boot/drivers/ram/sifive/Makefile new file mode 100644 index 000000000..4ef89f85b --- /dev/null +++ b/roms/u-boot/drivers/ram/sifive/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2020 SiFive, Inc +# + +obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o diff --git a/roms/u-boot/drivers/ram/sifive/sifive_ddr.c b/roms/u-boot/drivers/ram/sifive/sifive_ddr.c new file mode 100644 index 000000000..ba1846603 --- /dev/null +++ b/roms/u-boot/drivers/ram/sifive/sifive_ddr.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * (C) Copyright 2020-2021 SiFive, Inc. + * + * Authors: + * Pragnesh Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DENALI_CTL_0 0 +#define DENALI_CTL_21 21 +#define DENALI_CTL_120 120 +#define DENALI_CTL_132 132 +#define DENALI_CTL_136 136 +#define DENALI_CTL_170 170 +#define DENALI_CTL_181 181 +#define DENALI_CTL_182 182 +#define DENALI_CTL_184 184 +#define DENALI_CTL_208 208 +#define DENALI_CTL_209 209 +#define DENALI_CTL_210 210 +#define DENALI_CTL_212 212 +#define DENALI_CTL_214 214 +#define DENALI_CTL_216 216 +#define DENALI_CTL_224 224 +#define DENALI_CTL_225 225 +#define DENALI_CTL_260 260 + +#define DENALI_PHY_1152 1152 +#define DENALI_PHY_1214 1214 + +#define DRAM_CLASS_OFFSET 8 +#define DRAM_CLASS_DDR4 0xA +#define OPTIMAL_RMODW_EN_OFFSET 0 +#define DISABLE_RD_INTERLEAVE_OFFSET 16 +#define OUT_OF_RANGE_OFFSET 1 +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2 +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7 +#define MC_INIT_COMPLETE_OFFSET 8 +#define LEVELING_OPERATION_COMPLETED_OFFSET 22 +#define DFI_PHY_WRLELV_MODE_OFFSET 24 +#define DFI_PHY_RDLVL_MODE_OFFSET 24 +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0 +#define VREF_EN_OFFSET 24 +#define PORT_ADDR_PROTECTION_EN_OFFSET 0 +#define AXI0_ADDRESS_RANGE_ENABLE 8 +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24 +#define RDLVL_EN_OFFSET 16 +#define RDLVL_GATE_EN_OFFSET 24 +#define WRLVL_EN_OFFSET 0 + +#define PHY_RX_CAL_DQ0_0_OFFSET 0 +#define PHY_RX_CAL_DQ1_0_OFFSET 16 + +DECLARE_GLOBAL_DATA_PTR; + +struct sifive_ddrctl { + volatile u32 denali_ctl[265]; +}; + +struct sifive_ddrphy { + volatile u32 denali_phy[1215]; +}; + +/** + * struct sifive_ddr_info + * + * @dev : pointer for the device + * @info : UCLASS RAM information + * @ctl : DDR controller base address + * @phy : DDR PHY base address + * @ctrl : DDR control base address + * @physical_filter_ctrl : DDR physical filter control base address + */ +struct sifive_ddr_info { + struct udevice *dev; + struct ram_info info; + struct sifive_ddrctl *ctl; + struct sifive_ddrphy *phy; + struct clk ddr_clk; + u32 *physical_filter_ctrl; +}; + +#if defined(CONFIG_SPL_BUILD) +struct sifive_ddr_params { + struct sifive_ddrctl pctl_regs; + struct sifive_ddrphy phy_regs; +}; + +struct sifive_dmc_plat { + struct sifive_ddr_params ddr_params; +}; + +/* + * TODO : It can be possible to use common sdram_copy_to_reg() API + * n: Unit bytes + */ +static void sdram_copy_to_reg(volatile u32 *dest, + volatile u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void sifive_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr) +{ + u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1; + + writel(0x0, DENALI_CTL_209 + ctl); + writel(end_addr_16kblocks, DENALI_CTL_210 + ctl); + writel(0x0, DENALI_CTL_212 + ctl); + writel(0x0, DENALI_CTL_214 + ctl); + writel(0x0, DENALI_CTL_216 + ctl); + setbits_le32(DENALI_CTL_224 + ctl, + 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); + writel(0xFFFFFFFF, DENALI_CTL_225 + ctl); + setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE); + setbits_le32(DENALI_CTL_208 + ctl, + 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET); +} + +static void sifive_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, + u64 ddr_end) +{ + volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl; + + setbits_le32(DENALI_CTL_0 + ctl, 0x1); + + wait_for_bit_le32((void *)ctl + DENALI_CTL_132, + BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false); + + /* Disable the BusBlocker in front of the controller AXI slave ports */ + filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2); +} + +static void sifive_ddr_check_errata(u32 regbase, u32 updownreg) +{ + u64 fails = 0; + u32 dq = 0; + u32 down, up; + u8 failc0, failc1; + u32 phy_rx_cal_dqn_0_offset; + + for (u32 bit = 0; bit < 2; bit++) { + if (bit == 0) { + phy_rx_cal_dqn_0_offset = + PHY_RX_CAL_DQ0_0_OFFSET; + } else { + phy_rx_cal_dqn_0_offset = + PHY_RX_CAL_DQ1_0_OFFSET; + } + + down = (updownreg >> + phy_rx_cal_dqn_0_offset) & 0x3F; + up = (updownreg >> + (phy_rx_cal_dqn_0_offset + 6)) & + 0x3F; + + failc0 = ((down == 0) && (up == 0x3F)); + failc1 = ((up == 0) && (down == 0x3F)); + + /* print error message on failure */ + if (failc0 || failc1) { + if (fails == 0) + printf("DDR error in fixing up\n"); + + fails |= (1 << dq); + + char slicelsc = '0'; + char slicemsc = '0'; + + slicelsc += (dq % 10); + slicemsc += (dq / 10); + printf("S "); + printf("%c", slicemsc); + printf("%c", slicelsc); + + if (failc0) + printf("U"); + else + printf("D"); + + printf("\n"); + } + dq++; + } +} + +static u64 sifive_ddr_phy_fixup(volatile u32 *ddrphyreg) +{ + u32 slicebase = 0; + + /* check errata condition */ + for (u32 slice = 0; slice < 8; slice++) { + u32 regbase = slicebase + 34; + + for (u32 reg = 0; reg < 4; reg++) { + u32 updownreg = readl(regbase + reg + ddrphyreg); + + sifive_ddr_check_errata(regbase, updownreg); + } + slicebase += 128; + } + + return(0); +} + +static u32 sifive_ddr_get_dram_class(volatile u32 *ctl) +{ + u32 reg = readl(DENALI_CTL_0 + ctl); + + return ((reg >> DRAM_CLASS_OFFSET) & 0xF); +} + +static int sifive_ddr_setup(struct udevice *dev) +{ + struct sifive_ddr_info *priv = dev_get_priv(dev); + struct sifive_dmc_plat *plat = dev_get_plat(dev); + struct sifive_ddr_params *params = &plat->ddr_params; + volatile u32 *denali_ctl = priv->ctl->denali_ctl; + volatile u32 *denali_phy = priv->phy->denali_phy; + const u64 ddr_size = priv->info.size; + const u64 ddr_end = priv->info.base + ddr_size; + int ret, i; + u32 physet; + + ret = dev_read_u32_array(dev, "sifive,ddr-params", + (u32 *)&plat->ddr_params, + sizeof(plat->ddr_params) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read sifive,ddr-params %d\n", + __func__, ret); + return ret; + } + + sdram_copy_to_reg(priv->ctl->denali_ctl, + params->pctl_regs.denali_ctl, + sizeof(struct sifive_ddrctl)); + + /* phy reset */ + for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) { + physet = params->phy_regs.denali_phy[i]; + priv->phy->denali_phy[i] = physet; + } + + for (i = 0; i < DENALI_PHY_1152; i++) { + physet = params->phy_regs.denali_phy[i]; + priv->phy->denali_phy[i] = physet; + } + + /* Disable read interleave DENALI_CTL_120 */ + setbits_le32(DENALI_CTL_120 + denali_ctl, + 1 << DISABLE_RD_INTERLEAVE_OFFSET); + + /* Disable optimal read/modify/write logic DENALI_CTL_21 */ + clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET); + + /* Enable write Leveling DENALI_CTL_170 */ + setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET) + | (1 << DFI_PHY_WRLELV_MODE_OFFSET)); + + /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */ + setbits_le32(DENALI_CTL_181 + denali_ctl, + 1 << DFI_PHY_RDLVL_MODE_OFFSET); + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET); + + /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */ + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET); + setbits_le32(DENALI_CTL_182 + denali_ctl, + 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET); + + if (sifive_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) { + /* Enable vref training DENALI_CTL_184 */ + setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET); + } + + /* Mask off leveling completion interrupt DENALI_CTL_136 */ + setbits_le32(DENALI_CTL_136 + denali_ctl, + 1 << LEVELING_OPERATION_COMPLETED_OFFSET); + + /* Mask off MC init complete interrupt DENALI_CTL_136 */ + setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET); + + /* Mask off out of range interrupts DENALI_CTL_136 */ + setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET) + | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET)); + + /* set up range protection */ + sifive_ddr_setup_range_protection(denali_ctl, priv->info.size); + + /* Mask off port command error interrupt DENALI_CTL_136 */ + setbits_le32(DENALI_CTL_136 + denali_ctl, + 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET); + + sifive_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end); + + sifive_ddr_phy_fixup(denali_phy); + + /* check size */ + priv->info.size = get_ram_size((long *)priv->info.base, + ddr_size); + + debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size); + + /* check memory access for all memory */ + if (priv->info.size != ddr_size) { + printf("DDR invalid size : 0x%lx, expected 0x%lx\n", + (uintptr_t)priv->info.size, (uintptr_t)ddr_size); + return -EINVAL; + } + + return 0; +} +#endif + +static int sifive_ddr_probe(struct udevice *dev) +{ + struct sifive_ddr_info *priv = dev_get_priv(dev); + + /* Read memory base and size from DT */ + fdtdec_setup_mem_size_base(); + priv->info.base = gd->ram_base; + priv->info.size = gd->ram_size; + +#if defined(CONFIG_SPL_BUILD) + int ret; + u32 clock = 0; + + debug("sifive DDR probe\n"); + priv->dev = dev; + + ret = clk_get_by_index(dev, 0, &priv->ddr_clk); + if (ret) { + debug("clk get failed %d\n", ret); + return ret; + } + + ret = dev_read_u32(dev, "clock-frequency", &clock); + if (ret) { + debug("clock-frequency not found in dt %d\n", ret); + return ret; + } else { + ret = clk_set_rate(&priv->ddr_clk, clock); + if (ret < 0) { + debug("Could not set DDR clock\n"); + return ret; + } + } + + ret = clk_enable(&priv->ddr_clk); + if (ret < 0) { + debug("Could not enable DDR clock\n"); + return ret; + } + + priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0); + priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1); + priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2); + + return sifive_ddr_setup(dev); +#endif + + return 0; +} + +static int sifive_ddr_get_info(struct udevice *dev, struct ram_info *info) +{ + struct sifive_ddr_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops sifive_ddr_ops = { + .get_info = sifive_ddr_get_info, +}; + +static const struct udevice_id sifive_ddr_ids[] = { + { .compatible = "sifive,fu540-c000-ddr" }, + { .compatible = "sifive,fu740-c000-ddr" }, + { } +}; + +U_BOOT_DRIVER(sifive_ddr) = { + .name = "sifive_ddr", + .id = UCLASS_RAM, + .of_match = sifive_ddr_ids, + .ops = &sifive_ddr_ops, + .probe = sifive_ddr_probe, + .priv_auto = sizeof(struct sifive_ddr_info), +#if defined(CONFIG_SPL_BUILD) + .plat_auto = sizeof(struct sifive_dmc_plat), +#endif +}; diff --git a/roms/u-boot/drivers/ram/stm32_sdram.c b/roms/u-boot/drivers/ram/stm32_sdram.c new file mode 100644 index 000000000..3e25cc7a0 --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32_sdram.c @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, for STMicroelectronics. + */ + +#define LOG_CATEGORY UCLASS_RAM + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MEM_MODE_MASK GENMASK(2, 0) +#define SWP_FMC_OFFSET 10 +#define SWP_FMC_MASK GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET) +#define NOT_FOUND 0xff + +struct stm32_fmc_regs { + /* 0x0 */ + u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ + u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ + u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ + u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ + u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ + u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ + u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ + u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ + u32 reserved1[24]; + + /* 0x80 */ + u32 pcr; /* NAND Flash control register */ + u32 sr; /* FIFO status and interrupt register */ + u32 pmem; /* Common memory space timing register */ + u32 patt; /* Attribute memory space timing registers */ + u32 reserved2[1]; + u32 eccr; /* ECC result registers */ + u32 reserved3[27]; + + /* 0x104 */ + u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ + u32 reserved4[1]; + u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ + u32 reserved5[1]; + u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ + u32 reserved6[1]; + u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ + u32 reserved7[8]; + + /* 0x140 */ + u32 sdcr1; /* SDRAM Control register 1 */ + u32 sdcr2; /* SDRAM Control register 2 */ + u32 sdtr1; /* SDRAM Timing register 1 */ + u32 sdtr2; /* SDRAM Timing register 2 */ + u32 sdcmr; /* SDRAM Mode register */ + u32 sdrtr; /* SDRAM Refresh timing register */ + u32 sdsr; /* SDRAM Status register */ +}; + +/* + * NOR/PSRAM Control register BCR1 + * FMC controller Enable, only availabe for H7 + */ +#define FMC_BCR1_FMCEN BIT(31) + +/* Control register SDCR */ +#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ +#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ +#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ +#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ +#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ +#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ +#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ +#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ +#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ + +/* Timings register SDTR */ +#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ +#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ +#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ +#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ +#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ +#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ +#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ + +#define FMC_SDCMR_NRFS_SHIFT 5 + +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_START_CLOCK 1 +#define FMC_SDCMR_MODE_PRECHARGE 2 +#define FMC_SDCMR_MODE_AUTOREFRESH 3 +#define FMC_SDCMR_MODE_WRITE_MODE 4 +#define FMC_SDCMR_MODE_SELFREFRESH 5 +#define FMC_SDCMR_MODE_POWERDOWN 6 + +#define FMC_SDCMR_BANK_1 BIT(4) +#define FMC_SDCMR_BANK_2 BIT(3) + +#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 + +#define FMC_SDSR_BUSY BIT(5) + +#define FMC_BUSY_WAIT(regs) do { \ + __asm__ __volatile__ ("dsb" : : : "memory"); \ + while (regs->sdsr & FMC_SDSR_BUSY) \ + ; \ + } while (0) + +struct stm32_sdram_control { + u8 no_columns; + u8 no_rows; + u8 memory_width; + u8 no_banks; + u8 cas_latency; + u8 sdclk; + u8 rd_burst; + u8 rd_pipe_delay; +}; + +struct stm32_sdram_timing { + u8 tmrd; + u8 txsr; + u8 tras; + u8 trc; + u8 trp; + u8 twr; + u8 trcd; +}; +enum stm32_fmc_bank { + SDRAM_BANK1, + SDRAM_BANK2, + MAX_SDRAM_BANK, +}; + +enum stm32_fmc_family { + STM32F7_FMC, + STM32H7_FMC, +}; + +struct bank_params { + struct stm32_sdram_control *sdram_control; + struct stm32_sdram_timing *sdram_timing; + u32 sdram_ref_count; + enum stm32_fmc_bank target_bank; +}; + +struct stm32_sdram_params { + struct stm32_fmc_regs *base; + u8 no_sdram_banks; + struct bank_params bank_params[MAX_SDRAM_BANK]; + enum stm32_fmc_family family; +}; + +#define SDRAM_MODE_BL_SHIFT 0 +#define SDRAM_MODE_CAS_SHIFT 4 +#define SDRAM_MODE_BL 0 + +int stm32_sdram_init(struct udevice *dev) +{ + struct stm32_sdram_params *params = dev_get_plat(dev); + struct stm32_sdram_control *control; + struct stm32_sdram_timing *timing; + struct stm32_fmc_regs *regs = params->base; + enum stm32_fmc_bank target_bank; + u32 ctb; /* SDCMR register: Command Target Bank */ + u32 ref_count; + u8 i; + + /* disable the FMC controller */ + if (params->family == STM32H7_FMC) + clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); + + for (i = 0; i < params->no_sdram_banks; i++) { + control = params->bank_params[i].sdram_control; + timing = params->bank_params[i].sdram_timing; + target_bank = params->bank_params[i].target_bank; + ref_count = params->bank_params[i].sdram_ref_count; + + writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT + | control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT + | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | control->rd_burst << FMC_SDCR_RBURST_SHIFT, + ®s->sdcr1); + + if (target_bank == SDRAM_BANK2) + writel(control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT, + ®s->sdcr2); + + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr1); + + if (target_bank == SDRAM_BANK2) + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr2); + + if (target_bank == SDRAM_BANK1) + ctb = FMC_SDCMR_BANK_1; + else + ctb = FMC_SDCMR_BANK_2; + + writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | control->cas_latency << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); + FMC_BUSY_WAIT(regs); + + /* Refresh timer */ + writel(ref_count << 1, ®s->sdrtr); + } + + /* enable the FMC controller */ + if (params->family == STM32H7_FMC) + setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); + + return 0; +} + +static int stm32_fmc_of_to_plat(struct udevice *dev) +{ + struct stm32_sdram_params *params = dev_get_plat(dev); + struct bank_params *bank_params; + struct ofnode_phandle_args args; + u32 *syscfg_base; + u32 mem_remap; + u32 swp_fmc; + ofnode bank_node; + char *bank_name; + char _bank_name[128] = {0}; + u8 bank = 0; + int ret; + + ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, + &args); + if (ret) { + dev_dbg(dev, "can't find syscon device (%d)\n", ret); + } else { + syscfg_base = (u32 *)ofnode_get_addr(args.node); + + mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND); + if (mem_remap != NOT_FOUND) { + /* set memory mapping selection */ + clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap); + } else { + dev_dbg(dev, "cannot find st,mem_remap property\n"); + } + + swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND); + if (swp_fmc != NOT_FOUND) { + /* set fmc swapping selection */ + clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET); + } else { + dev_dbg(dev, "cannot find st,swp_fmc property\n"); + } + + dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base); + } + + dev_for_each_subnode(bank_node, dev) { + /* extract the bank index from DT */ + bank_name = (char *)ofnode_get_name(bank_node); + strlcpy(_bank_name, bank_name, sizeof(_bank_name)); + bank_name = (char *)_bank_name; + strsep(&bank_name, "@"); + if (!bank_name) { + pr_err("missing sdram bank index"); + return -EINVAL; + } + + bank_params = ¶ms->bank_params[bank]; + strict_strtoul(bank_name, 10, + (long unsigned int *)&bank_params->target_bank); + + if (bank_params->target_bank >= MAX_SDRAM_BANK) { + pr_err("Found bank %d , but only bank 0 and 1 are supported", + bank_params->target_bank); + return -EINVAL; + } + + debug("Find bank %s %u\n", bank_name, bank_params->target_bank); + + params->bank_params[bank].sdram_control = + (struct stm32_sdram_control *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-control", + sizeof(struct stm32_sdram_control)); + + if (!params->bank_params[bank].sdram_control) { + pr_err("st,sdram-control not found for %s", + ofnode_get_name(bank_node)); + return -EINVAL; + } + + + params->bank_params[bank].sdram_timing = + (struct stm32_sdram_timing *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-timing", + sizeof(struct stm32_sdram_timing)); + + if (!params->bank_params[bank].sdram_timing) { + pr_err("st,sdram-timing not found for %s", + ofnode_get_name(bank_node)); + return -EINVAL; + } + + + bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, + "st,sdram-refcount", 8196); + bank++; + } + + params->no_sdram_banks = bank; + dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks); + + return 0; +} + +static int stm32_fmc_probe(struct udevice *dev) +{ + struct stm32_sdram_params *params = dev_get_plat(dev); + int ret; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + params->base = (struct stm32_fmc_regs *)addr; + params->family = dev_get_driver_data(dev); + +#ifdef CONFIG_CLK + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } +#endif + ret = stm32_sdram_init(dev); + if (ret) + return ret; + + return 0; +} + +static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) +{ + return 0; +} + +static struct ram_ops stm32_fmc_ops = { + .get_info = stm32_fmc_get_info, +}; + +static const struct udevice_id stm32_fmc_ids[] = { + { .compatible = "st,stm32-fmc", .data = STM32F7_FMC }, + { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC }, + { } +}; + +U_BOOT_DRIVER(stm32_fmc) = { + .name = "stm32_fmc", + .id = UCLASS_RAM, + .of_match = stm32_fmc_ids, + .ops = &stm32_fmc_ops, + .of_to_plat = stm32_fmc_of_to_plat, + .probe = stm32_fmc_probe, + .plat_auto = sizeof(struct stm32_sdram_params), +}; diff --git a/roms/u-boot/drivers/ram/stm32mp1/Kconfig b/roms/u-boot/drivers/ram/stm32mp1/Kconfig new file mode 100644 index 000000000..2fd8c7b7e --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/Kconfig @@ -0,0 +1,49 @@ + +config STM32MP1_DDR + bool "STM32MP1 DDR driver" + depends on DM && OF_CONTROL && ARCH_STM32MP + select RAM + select SPL_RAM if SPL + default y + help + activate STM32MP1 DDR controller driver for STM32MP1 soc + family: support for LPDDR2, LPDDR3 and DDR3 + the SDRAM parameters for controleur and phy need to be provided + in device tree (computed by DDR tuning tools) + +config STM32MP1_DDR_INTERACTIVE + bool "STM32MP1 DDR driver : interactive support" + depends on STM32MP1_DDR + help + activate interactive support in STM32MP1 DDR controller driver + used for DDR tuning tools + to enter in intercative mode type 'd' during SPL DDR driver + initialisation + +config STM32MP1_DDR_INTERACTIVE_FORCE + bool "STM32MP1 DDR driver : force interactive mode" + depends on STM32MP1_DDR_INTERACTIVE + default n + help + force interactive mode in STM32MP1 DDR controller driver + skip the polling of character 'd' in console + useful when SPL is loaded in sysram + directly by programmer + +config STM32MP1_DDR_TESTS + bool "STM32MP1 DDR driver : tests support" + depends on STM32MP1_DDR_INTERACTIVE + default y + help + activate test support for interactive support in + STM32MP1 DDR controller driver: command test + +config STM32MP1_DDR_TUNING + bool "STM32MP1 DDR driver : support of tuning" + depends on STM32MP1_DDR_INTERACTIVE + default y + help + activate tuning command in STM32MP1 DDR interactive mode + used for DDR tuning tools + - DQ Deskew algorithm + - DQS Trimming diff --git a/roms/u-boot/drivers/ram/stm32mp1/Makefile b/roms/u-boot/drivers/ram/stm32mp1/Makefile new file mode 100644 index 000000000..e1e913560 --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += stm32mp1_ram.o +obj-y += stm32mp1_ddr.o + +obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += stm32mp1_interactive.o +obj-$(CONFIG_STM32MP1_DDR_TESTS) += stm32mp1_tests.o +obj-$(CONFIG_STM32MP1_DDR_TUNING) += stm32mp1_tuning.o + +ifneq ($(DDR_INTERACTIVE),) +CFLAGS_stm32mp1_interactive.o += -DCONFIG_STM32MP1_DDR_INTERACTIVE_FORCE=y +endif diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.c b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.c new file mode 100644 index 000000000..0457166b1 --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_RAM + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp1_ddr.h" +#include "stm32mp1_ddr_regs.h" + +#define RCC_DDRITFCR 0xD8 + +#define RCC_DDRITFCR_DDRCAPBRST (BIT(14)) +#define RCC_DDRITFCR_DDRCAXIRST (BIT(15)) +#define RCC_DDRITFCR_DDRCORERST (BIT(16)) +#define RCC_DDRITFCR_DPHYAPBRST (BIT(17)) +#define RCC_DDRITFCR_DPHYRST (BIT(18)) +#define RCC_DDRITFCR_DPHYCTLRST (BIT(19)) + +struct reg_desc { + const char *name; + u16 offset; /* offset for base address */ + u8 par_offset; /* offset for parameter array */ +}; + +#define INVALID_OFFSET 0xFF + +#define DDRCTL_REG(x, y) \ + {#x,\ + offsetof(struct stm32mp1_ddrctl, x),\ + offsetof(struct y, x)} + +#define DDRPHY_REG(x, y) \ + {#x,\ + offsetof(struct stm32mp1_ddrphy, x),\ + offsetof(struct y, x)} + +#define DDR_REG_DYN(x) \ + {#x,\ + offsetof(struct stm32mp1_ddrctl, x),\ + INVALID_OFFSET} + +#define DDRPHY_REG_DYN(x) \ + {#x,\ + offsetof(struct stm32mp1_ddrphy, x),\ + INVALID_OFFSET} + +/*********************************************************** + * PARAMETERS: value get from device tree : + * size / order need to be aligned with binding + * modification NOT ALLOWED !!! + ***********************************************************/ +#define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */ +#define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */ +#define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */ +#define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */ + +#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */ +#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */ +#define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */ + +#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg) +static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = { + DDRCTL_REG_REG(mstr), + DDRCTL_REG_REG(mrctrl0), + DDRCTL_REG_REG(mrctrl1), + DDRCTL_REG_REG(derateen), + DDRCTL_REG_REG(derateint), + DDRCTL_REG_REG(pwrctl), + DDRCTL_REG_REG(pwrtmg), + DDRCTL_REG_REG(hwlpctl), + DDRCTL_REG_REG(rfshctl0), + DDRCTL_REG_REG(rfshctl3), + DDRCTL_REG_REG(crcparctl0), + DDRCTL_REG_REG(zqctl0), + DDRCTL_REG_REG(dfitmg0), + DDRCTL_REG_REG(dfitmg1), + DDRCTL_REG_REG(dfilpcfg0), + DDRCTL_REG_REG(dfiupd0), + DDRCTL_REG_REG(dfiupd1), + DDRCTL_REG_REG(dfiupd2), + DDRCTL_REG_REG(dfiphymstr), + DDRCTL_REG_REG(odtmap), + DDRCTL_REG_REG(dbg0), + DDRCTL_REG_REG(dbg1), + DDRCTL_REG_REG(dbgcmd), + DDRCTL_REG_REG(poisoncfg), + DDRCTL_REG_REG(pccfg), +}; + +#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing) +static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = { + DDRCTL_REG_TIMING(rfshtmg), + DDRCTL_REG_TIMING(dramtmg0), + DDRCTL_REG_TIMING(dramtmg1), + DDRCTL_REG_TIMING(dramtmg2), + DDRCTL_REG_TIMING(dramtmg3), + DDRCTL_REG_TIMING(dramtmg4), + DDRCTL_REG_TIMING(dramtmg5), + DDRCTL_REG_TIMING(dramtmg6), + DDRCTL_REG_TIMING(dramtmg7), + DDRCTL_REG_TIMING(dramtmg8), + DDRCTL_REG_TIMING(dramtmg14), + DDRCTL_REG_TIMING(odtcfg), +}; + +#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map) +static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = { + DDRCTL_REG_MAP(addrmap1), + DDRCTL_REG_MAP(addrmap2), + DDRCTL_REG_MAP(addrmap3), + DDRCTL_REG_MAP(addrmap4), + DDRCTL_REG_MAP(addrmap5), + DDRCTL_REG_MAP(addrmap6), + DDRCTL_REG_MAP(addrmap9), + DDRCTL_REG_MAP(addrmap10), + DDRCTL_REG_MAP(addrmap11), +}; + +#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf) +static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = { + DDRCTL_REG_PERF(sched), + DDRCTL_REG_PERF(sched1), + DDRCTL_REG_PERF(perfhpr1), + DDRCTL_REG_PERF(perflpr1), + DDRCTL_REG_PERF(perfwr1), + DDRCTL_REG_PERF(pcfgr_0), + DDRCTL_REG_PERF(pcfgw_0), + DDRCTL_REG_PERF(pcfgqos0_0), + DDRCTL_REG_PERF(pcfgqos1_0), + DDRCTL_REG_PERF(pcfgwqos0_0), + DDRCTL_REG_PERF(pcfgwqos1_0), + DDRCTL_REG_PERF(pcfgr_1), + DDRCTL_REG_PERF(pcfgw_1), + DDRCTL_REG_PERF(pcfgqos0_1), + DDRCTL_REG_PERF(pcfgqos1_1), + DDRCTL_REG_PERF(pcfgwqos0_1), + DDRCTL_REG_PERF(pcfgwqos1_1), +}; + +#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg) +static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = { + DDRPHY_REG_REG(pgcr), + DDRPHY_REG_REG(aciocr), + DDRPHY_REG_REG(dxccr), + DDRPHY_REG_REG(dsgcr), + DDRPHY_REG_REG(dcr), + DDRPHY_REG_REG(odtcr), + DDRPHY_REG_REG(zq0cr1), + DDRPHY_REG_REG(dx0gcr), + DDRPHY_REG_REG(dx1gcr), + DDRPHY_REG_REG(dx2gcr), + DDRPHY_REG_REG(dx3gcr), +}; + +#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing) +static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = { + DDRPHY_REG_TIMING(ptr0), + DDRPHY_REG_TIMING(ptr1), + DDRPHY_REG_TIMING(ptr2), + DDRPHY_REG_TIMING(dtpr0), + DDRPHY_REG_TIMING(dtpr1), + DDRPHY_REG_TIMING(dtpr2), + DDRPHY_REG_TIMING(mr0), + DDRPHY_REG_TIMING(mr1), + DDRPHY_REG_TIMING(mr2), + DDRPHY_REG_TIMING(mr3), +}; + +#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal) +static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = { + DDRPHY_REG_CAL(dx0dllcr), + DDRPHY_REG_CAL(dx0dqtr), + DDRPHY_REG_CAL(dx0dqstr), + DDRPHY_REG_CAL(dx1dllcr), + DDRPHY_REG_CAL(dx1dqtr), + DDRPHY_REG_CAL(dx1dqstr), + DDRPHY_REG_CAL(dx2dllcr), + DDRPHY_REG_CAL(dx2dqtr), + DDRPHY_REG_CAL(dx2dqstr), + DDRPHY_REG_CAL(dx3dllcr), + DDRPHY_REG_CAL(dx3dqtr), + DDRPHY_REG_CAL(dx3dqstr), +}; + +/************************************************************** + * DYNAMIC REGISTERS: only used for debug purpose (read/modify) + **************************************************************/ +#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE +static const struct reg_desc ddr_dyn[] = { + DDR_REG_DYN(stat), + DDR_REG_DYN(init0), + DDR_REG_DYN(dfimisc), + DDR_REG_DYN(dfistat), + DDR_REG_DYN(swctl), + DDR_REG_DYN(swstat), + DDR_REG_DYN(pctrl_0), + DDR_REG_DYN(pctrl_1), +}; + +#define DDR_REG_DYN_SIZE ARRAY_SIZE(ddr_dyn) + +static const struct reg_desc ddrphy_dyn[] = { + DDRPHY_REG_DYN(pir), + DDRPHY_REG_DYN(pgsr), + DDRPHY_REG_DYN(zq0sr0), + DDRPHY_REG_DYN(zq0sr1), + DDRPHY_REG_DYN(dx0gsr0), + DDRPHY_REG_DYN(dx0gsr1), + DDRPHY_REG_DYN(dx1gsr0), + DDRPHY_REG_DYN(dx1gsr1), + DDRPHY_REG_DYN(dx2gsr0), + DDRPHY_REG_DYN(dx2gsr1), + DDRPHY_REG_DYN(dx3gsr0), + DDRPHY_REG_DYN(dx3gsr1), +}; + +#define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn) + +#endif + +/***************************************************************** + * REGISTERS ARRAY: used to parse device tree and interactive mode + *****************************************************************/ +enum reg_type { + REG_REG, + REG_TIMING, + REG_PERF, + REG_MAP, + REGPHY_REG, + REGPHY_TIMING, + REGPHY_CAL, +#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE +/* dynamic registers => managed in driver or not changed, + * can be dumped in interactive mode + */ + REG_DYN, + REGPHY_DYN, +#endif + REG_TYPE_NB +}; + +enum base_type { + DDR_BASE, + DDRPHY_BASE, + NONE_BASE +}; + +struct ddr_reg_info { + const char *name; + const struct reg_desc *desc; + u8 size; + enum base_type base; +}; + +#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal) + +const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = { +[REG_REG] = { + "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE}, +[REG_TIMING] = { + "timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE}, +[REG_PERF] = { + "perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE}, +[REG_MAP] = { + "map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE}, +[REGPHY_REG] = { + "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE}, +[REGPHY_TIMING] = { + "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE}, +[REGPHY_CAL] = { + "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE}, +#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE +[REG_DYN] = { + "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE}, +[REGPHY_DYN] = { + "dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE}, +#endif + +}; + +const char *base_name[] = { + [DDR_BASE] = "ctl", + [DDRPHY_BASE] = "phy", +}; + +static u32 get_base_addr(const struct ddr_info *priv, enum base_type base) +{ + if (base == DDRPHY_BASE) + return (u32)priv->phy; + else + return (u32)priv->ctl; +} + +static void set_reg(const struct ddr_info *priv, + enum reg_type type, + const void *param) +{ + unsigned int i; + unsigned int *ptr, value; + enum base_type base = ddr_registers[type].base; + u32 base_addr = get_base_addr(priv, base); + const struct reg_desc *desc = ddr_registers[type].desc; + + log_debug("init %s\n", ddr_registers[type].name); + for (i = 0; i < ddr_registers[type].size; i++) { + ptr = (unsigned int *)(base_addr + desc[i].offset); + if (desc[i].par_offset == INVALID_OFFSET) { + log_err("invalid parameter offset for %s", desc[i].name); + } else { + value = *((u32 *)((u32)param + + desc[i].par_offset)); + writel(value, ptr); + log_debug("[0x%x] %s= 0x%08x\n", + (u32)ptr, desc[i].name, value); + } + } +} + +#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE +static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc) +{ + unsigned int *ptr; + + ptr = (unsigned int *)(base_addr + desc->offset); + printf("%s= 0x%08x\n", desc->name, readl(ptr)); +} + +static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc) +{ + unsigned int *ptr; + + ptr = (unsigned int *)(par_addr + desc->par_offset); + printf("%s= 0x%08x\n", desc->name, readl(ptr)); +} + +static const struct reg_desc *found_reg(const char *name, enum reg_type *type) +{ + unsigned int i, j; + const struct reg_desc *desc; + + for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) { + desc = ddr_registers[i].desc; + for (j = 0; j < ddr_registers[i].size; j++) { + if (strcmp(name, desc[j].name) == 0) { + *type = i; + return &desc[j]; + } + } + } + *type = REG_TYPE_NB; + return NULL; +} + +int stm32mp1_dump_reg(const struct ddr_info *priv, + const char *name) +{ + unsigned int i, j; + const struct reg_desc *desc; + u32 base_addr; + enum base_type p_base; + enum reg_type type; + const char *p_name; + enum base_type filter = NONE_BASE; + int result = -1; + + if (name) { + if (strcmp(name, base_name[DDR_BASE]) == 0) + filter = DDR_BASE; + else if (strcmp(name, base_name[DDRPHY_BASE]) == 0) + filter = DDRPHY_BASE; + } + + for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) { + p_base = ddr_registers[i].base; + p_name = ddr_registers[i].name; + if (!name || (filter == p_base || !strcmp(name, p_name))) { + result = 0; + desc = ddr_registers[i].desc; + base_addr = get_base_addr(priv, p_base); + printf("==%s.%s==\n", base_name[p_base], p_name); + for (j = 0; j < ddr_registers[i].size; j++) + stm32mp1_dump_reg_desc(base_addr, &desc[j]); + } + } + if (result) { + desc = found_reg(name, &type); + if (desc) { + p_base = ddr_registers[type].base; + base_addr = get_base_addr(priv, p_base); + stm32mp1_dump_reg_desc(base_addr, desc); + result = 0; + } + } + return result; +} + +void stm32mp1_edit_reg(const struct ddr_info *priv, + char *name, char *string) +{ + unsigned long *ptr, value; + enum reg_type type; + enum base_type base; + const struct reg_desc *desc; + u32 base_addr; + + desc = found_reg(name, &type); + + if (!desc) { + printf("%s not found\n", name); + return; + } + if (strict_strtoul(string, 16, &value) < 0) { + printf("invalid value %s\n", string); + return; + } + base = ddr_registers[type].base; + base_addr = get_base_addr(priv, base); + ptr = (unsigned long *)(base_addr + desc->offset); + writel(value, ptr); + printf("%s= 0x%08x\n", desc->name, readl(ptr)); +} + +static u32 get_par_addr(const struct stm32mp1_ddr_config *config, + enum reg_type type) +{ + u32 par_addr = 0x0; + + switch (type) { + case REG_REG: + par_addr = (u32)&config->c_reg; + break; + case REG_TIMING: + par_addr = (u32)&config->c_timing; + break; + case REG_PERF: + par_addr = (u32)&config->c_perf; + break; + case REG_MAP: + par_addr = (u32)&config->c_map; + break; + case REGPHY_REG: + par_addr = (u32)&config->p_reg; + break; + case REGPHY_TIMING: + par_addr = (u32)&config->p_timing; + break; + case REGPHY_CAL: + par_addr = (u32)&config->p_cal; + break; + case REG_DYN: + case REGPHY_DYN: + case REG_TYPE_NB: + par_addr = (u32)NULL; + break; + } + + return par_addr; +} + +int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config, + const char *name) +{ + unsigned int i, j; + const struct reg_desc *desc; + u32 par_addr; + enum base_type p_base; + enum reg_type type; + const char *p_name; + enum base_type filter = NONE_BASE; + int result = -EINVAL; + + if (name) { + if (strcmp(name, base_name[DDR_BASE]) == 0) + filter = DDR_BASE; + else if (strcmp(name, base_name[DDRPHY_BASE]) == 0) + filter = DDRPHY_BASE; + } + + for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) { + par_addr = get_par_addr(config, i); + if (!par_addr) + continue; + p_base = ddr_registers[i].base; + p_name = ddr_registers[i].name; + if (!name || (filter == p_base || !strcmp(name, p_name))) { + result = 0; + desc = ddr_registers[i].desc; + printf("==%s.%s==\n", base_name[p_base], p_name); + for (j = 0; j < ddr_registers[i].size; j++) + stm32mp1_dump_param_desc(par_addr, &desc[j]); + } + } + if (result) { + desc = found_reg(name, &type); + if (desc) { + par_addr = get_par_addr(config, type); + if (par_addr) { + stm32mp1_dump_param_desc(par_addr, desc); + result = 0; + } + } + } + return result; +} + +void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config, + char *name, char *string) +{ + unsigned long *ptr, value; + enum reg_type type; + const struct reg_desc *desc; + u32 par_addr; + + desc = found_reg(name, &type); + if (!desc) { + printf("%s not found\n", name); + return; + } + if (strict_strtoul(string, 16, &value) < 0) { + printf("invalid value %s\n", string); + return; + } + par_addr = get_par_addr(config, type); + if (!par_addr) { + printf("no parameter %s\n", name); + return; + } + ptr = (unsigned long *)(par_addr + desc->par_offset); + writel(value, ptr); + printf("%s= 0x%08x\n", desc->name, readl(ptr)); +} +#endif + +__weak bool stm32mp1_ddr_interactive(void *priv, + enum stm32mp1_ddr_interact_step step, + const struct stm32mp1_ddr_config *config) +{ + return false; +} + +#define INTERACTIVE(step)\ + stm32mp1_ddr_interactive(priv, step, config) + +static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy) +{ + u32 pgsr; + int ret; + + ret = readl_poll_timeout(&phy->pgsr, pgsr, + pgsr & (DDRPHYC_PGSR_IDONE | + DDRPHYC_PGSR_DTERR | + DDRPHYC_PGSR_DTIERR | + DDRPHYC_PGSR_DFTERR | + DDRPHYC_PGSR_RVERR | + DDRPHYC_PGSR_RVEIRR), + 1000000); + log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n", + (u32)&phy->pgsr, pgsr, ret); +} + +void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) +{ + pir |= DDRPHYC_PIR_INIT; + writel(pir, &phy->pir); + log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n", + (u32)&phy->pir, pir, readl(&phy->pir)); + + /* need to wait 10 configuration clock before start polling */ + udelay(10); + + /* Wait DRAM initialization and Gate Training Evaluation complete */ + ddrphy_idone_wait(phy); +} + +/* start quasi dynamic register update */ +static void start_sw_done(struct stm32mp1_ddrctl *ctl) +{ + clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); +} + +/* wait quasi dynamic register update */ +static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl) +{ + int ret; + u32 swstat; + + setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); + + ret = readl_poll_timeout(&ctl->swstat, swstat, + swstat & DDRCTRL_SWSTAT_SW_DONE_ACK, + 1000000); + if (ret) + panic("Timeout initialising DRAM : DDR->swstat = %x\n", + swstat); + + log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat); +} + +/* wait quasi dynamic register update */ +static void wait_operating_mode(struct ddr_info *priv, int mode) +{ + u32 stat, val, mask, val2 = 0, mask2 = 0; + int ret; + + mask = DDRCTRL_STAT_OPERATING_MODE_MASK; + val = mode; + /* self-refresh due to software => check also STAT.selfref_type */ + if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { + mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK; + val |= DDRCTRL_STAT_SELFREF_TYPE_SR; + } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) { + /* normal mode: handle also automatic self refresh */ + mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK | + DDRCTRL_STAT_SELFREF_TYPE_MASK; + val2 = DDRCTRL_STAT_OPERATING_MODE_SR | + DDRCTRL_STAT_SELFREF_TYPE_ASR; + } + + ret = readl_poll_timeout(&priv->ctl->stat, stat, + ((stat & mask) == val) || + (mask2 && ((stat & mask2) == val2)), + 1000000); + + if (ret) + panic("Timeout DRAM : DDR->stat = %x\n", stat); + + log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat); +} + +void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) +{ + start_sw_done(ctl); + /* quasi-dynamic register update*/ + setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); + clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN | + DDRCTRL_PWRCTL_SELFREF_EN); + clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(ctl); +} + +void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, + u32 rfshctl3, u32 pwrctl) +{ + start_sw_done(ctl); + if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH)) + clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); + if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); + if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN)) + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(ctl); +} + +/* board-specific DDR power initializations. */ +__weak int board_ddr_power_init(enum ddr_type ddr_type) +{ + return 0; +} + +__maybe_unused +void stm32mp1_ddr_init(struct ddr_info *priv, + const struct stm32mp1_ddr_config *config) +{ + u32 pir; + int ret = -EINVAL; + char bus_width; + + switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { + case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER: + bus_width = 8; + break; + case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF: + bus_width = 16; + break; + default: + bus_width = 32; + break; + } + + + if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) + ret = board_ddr_power_init(STM32MP_DDR3); + else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) { + if (bus_width == 32) + ret = board_ddr_power_init(STM32MP_LPDDR2_32); + else + ret = board_ddr_power_init(STM32MP_LPDDR2_16); + } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) { + if (bus_width == 32) + ret = board_ddr_power_init(STM32MP_LPDDR3_32); + else + ret = board_ddr_power_init(STM32MP_LPDDR3_16); + } + if (ret) + panic("ddr power init failed\n"); + +start: + log_debug("name = %s\n", config->info.name); + log_debug("speed = %d kHz\n", config->info.speed); + log_debug("size = 0x%x\n", config->info.size); +/* + * 1. Program the DWC_ddr_umctl2 registers + * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn + */ + /* Assert All DDR part */ + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); + +/* 1.2. start CLOCK */ + if (stm32mp1_ddr_clk_enable(priv, config->info.speed)) + panic("invalid DRAM clock : %d kHz\n", + config->info.speed); + +/* 1.3. deassert reset */ + /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */ + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); + /* De-assert presetn once the clocks are active + * and stable via DDRCAPBRST bit + */ + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); + +/* 1.4. wait 128 cycles to permit initialization of end logic */ + udelay(2); + /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */ + + if (INTERACTIVE(STEP_DDR_RESET)) + goto start; + +/* 1.5. initialize registers ddr_umctl2 */ + /* Stop uMCTL2 before PHY is ready */ + clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + log_debug("[0x%08x] dfimisc = 0x%08x\n", + (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc)); + + set_reg(priv, REG_REG, &config->c_reg); + set_reg(priv, REG_TIMING, &config->c_timing); + set_reg(priv, REG_MAP, &config->c_map); + + /* skip CTRL init, SDRAM init is done by PHY PUBL */ + clrsetbits_le32(&priv->ctl->init0, + DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK, + DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL); + + set_reg(priv, REG_PERF, &config->c_perf); + + if (INTERACTIVE(STEP_CTL_INIT)) + goto start; + +/* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */ + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); + +/* 3. start PHY init by accessing relevant PUBL registers + * (DXGCR, DCR, PTR*, MR*, DTPR*) + */ + set_reg(priv, REGPHY_REG, &config->p_reg); + set_reg(priv, REGPHY_TIMING, &config->p_timing); + if (config->p_cal_present) + set_reg(priv, REGPHY_CAL, &config->p_cal); + + if (INTERACTIVE(STEP_PHY_INIT)) + goto start; + +/* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE + * Perform DDR PHY DRAM initialization and Gate Training Evaluation + */ + ddrphy_idone_wait(priv->phy); + +/* 5. Indicate to PUBL that controller performs SDRAM initialization + * by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE + * DRAM init is done by PHY, init0.skip_dram.init = 1 + */ + pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL | + DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC; + + if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) + pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */ + + stm32mp1_ddrphy_init(priv->phy, pir); + +/* 6. SET DFIMISC.dfi_init_complete_en to 1 */ + /* Enable quasi-dynamic register programming*/ + start_sw_done(priv->ctl); + setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(priv->ctl); + +/* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode + * by monitoring STAT.operating_mode signal + */ + /* wait uMCTL2 ready */ + + wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); + + if (config->p_cal_present) { + log_debug("DDR DQS training skipped.\n"); + } else { + log_debug("DDR DQS training : "); +/* 8. Disable Auto refresh and power down by setting + * - RFSHCTL3.dis_au_refresh = 1 + * - PWRCTL.powerdown_en = 0 + * - DFIMISC.dfiinit_complete_en = 0 + */ + stm32mp1_refresh_disable(priv->ctl); + +/* 9. Program PUBL PGCR to enable refresh during training and rank to train + * not done => keep the programed value in PGCR + */ + +/* 10. configure PUBL PIR register to specify which training step to run */ + /* warning : RVTRN is not supported by this PUBL */ + stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); + +/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ + ddrphy_idone_wait(priv->phy); + +/* 12. set back registers in step 8 to the orginal values if desidered */ + stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, + config->c_reg.pwrctl); + } /* if (config->p_cal_present) */ + + /* enable uMCTL2 AXI port 0 and 1 */ + setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); + setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN); + + if (INTERACTIVE(STEP_DDR_READY)) + goto start; +} diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.h b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.h new file mode 100644 index 000000000..4998f0443 --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _RAM_STM32MP1_DDR_H +#define _RAM_STM32MP1_DDR_H + +enum stm32mp1_ddr_interact_step { + STEP_DDR_RESET, + STEP_CTL_INIT, + STEP_PHY_INIT, + STEP_DDR_READY, + STEP_RUN, +}; + +/* DDR CTL and DDR PHY REGISTERS */ +struct stm32mp1_ddrctl; +struct stm32mp1_ddrphy; + +/** + * struct ddr_info + * + * @dev: pointer for the device + * @info: UCLASS RAM information + * @ctl: DDR controleur base address + * @clk: DDR clock + * @phy: DDR PHY base address + * @rcc: rcc base address + */ +struct ddr_info { + struct udevice *dev; + struct ram_info info; + struct clk clk; + struct stm32mp1_ddrctl *ctl; + struct stm32mp1_ddrphy *phy; + u32 rcc; +}; + +struct stm32mp1_ddrctrl_reg { + u32 mstr; + u32 mrctrl0; + u32 mrctrl1; + u32 derateen; + u32 derateint; + u32 pwrctl; + u32 pwrtmg; + u32 hwlpctl; + u32 rfshctl0; + u32 rfshctl3; + u32 crcparctl0; + u32 zqctl0; + u32 dfitmg0; + u32 dfitmg1; + u32 dfilpcfg0; + u32 dfiupd0; + u32 dfiupd1; + u32 dfiupd2; + u32 dfiphymstr; + u32 odtmap; + u32 dbg0; + u32 dbg1; + u32 dbgcmd; + u32 poisoncfg; + u32 pccfg; + +}; + +struct stm32mp1_ddrctrl_timing { + u32 rfshtmg; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg14; + u32 odtcfg; +}; + +struct stm32mp1_ddrctrl_map { + u32 addrmap1; + u32 addrmap2; + u32 addrmap3; + u32 addrmap4; + u32 addrmap5; + u32 addrmap6; + u32 addrmap9; + u32 addrmap10; + u32 addrmap11; +}; + +struct stm32mp1_ddrctrl_perf { + u32 sched; + u32 sched1; + u32 perfhpr1; + u32 perflpr1; + u32 perfwr1; + u32 pcfgr_0; + u32 pcfgw_0; + u32 pcfgqos0_0; + u32 pcfgqos1_0; + u32 pcfgwqos0_0; + u32 pcfgwqos1_0; + u32 pcfgr_1; + u32 pcfgw_1; + u32 pcfgqos0_1; + u32 pcfgqos1_1; + u32 pcfgwqos0_1; + u32 pcfgwqos1_1; +}; + +struct stm32mp1_ddrphy_reg { + u32 pgcr; + u32 aciocr; + u32 dxccr; + u32 dsgcr; + u32 dcr; + u32 odtcr; + u32 zq0cr1; + u32 dx0gcr; + u32 dx1gcr; + u32 dx2gcr; + u32 dx3gcr; +}; + +struct stm32mp1_ddrphy_timing { + u32 ptr0; + u32 ptr1; + u32 ptr2; + u32 dtpr0; + u32 dtpr1; + u32 dtpr2; + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; +}; + +struct stm32mp1_ddrphy_cal { + u32 dx0dllcr; + u32 dx0dqtr; + u32 dx0dqstr; + u32 dx1dllcr; + u32 dx1dqtr; + u32 dx1dqstr; + u32 dx2dllcr; + u32 dx2dqtr; + u32 dx2dqstr; + u32 dx3dllcr; + u32 dx3dqtr; + u32 dx3dqstr; +}; + +struct stm32mp1_ddr_info { + const char *name; + u32 speed; /* in kHZ */ + u32 size; /* memory size in byte = col * row * width */ +}; + +struct stm32mp1_ddr_config { + struct stm32mp1_ddr_info info; + struct stm32mp1_ddrctrl_reg c_reg; + struct stm32mp1_ddrctrl_timing c_timing; + struct stm32mp1_ddrctrl_map c_map; + struct stm32mp1_ddrctrl_perf c_perf; + struct stm32mp1_ddrphy_reg p_reg; + struct stm32mp1_ddrphy_timing p_timing; + struct stm32mp1_ddrphy_cal p_cal; + bool p_cal_present; +}; + +int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed); +void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir); +void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl); +void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, + u32 rfshctl3, + u32 pwrctl); + +void stm32mp1_ddr_init( + struct ddr_info *priv, + const struct stm32mp1_ddr_config *config); + +int stm32mp1_dump_reg(const struct ddr_info *priv, + const char *name); + +void stm32mp1_edit_reg(const struct ddr_info *priv, + char *name, + char *string); + +int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config, + const char *name); + +void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config, + char *name, + char *string); + +bool stm32mp1_ddr_interactive( + void *priv, + enum stm32mp1_ddr_interact_step step, + const struct stm32mp1_ddr_config *config); + +#endif diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h new file mode 100644 index 000000000..3c8885a96 --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -0,0 +1,369 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _RAM_STM32MP1_DDR_REGS_H +#define _RAM_STM32MP1_DDR_REGS_H + +/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ +#include +struct stm32mp1_ddrctl { + u32 mstr ; /* 0x0 Master*/ + u32 stat; /* 0x4 Operating Mode Status*/ + u8 reserved008[0x10 - 0x8]; + u32 mrctrl0; /* 0x10 Control 0.*/ + u32 mrctrl1; /* 0x14 Control 1*/ + u32 mrstat; /* 0x18 Status*/ + u32 reserved01c; /* 0x1c */ + u32 derateen; /* 0x20 Temperature Derate Enable*/ + u32 derateint; /* 0x24 Temperature Derate Interval*/ + u8 reserved028[0x30 - 0x28]; + u32 pwrctl; /* 0x30 Low Power Control*/ + u32 pwrtmg; /* 0x34 Low Power Timing*/ + u32 hwlpctl; /* 0x38 Hardware Low Power Control*/ + u8 reserved03c[0x50 - 0x3C]; + u32 rfshctl0; /* 0x50 Refresh Control 0*/ + u32 reserved054; /* 0x54 Refresh Control 1*/ + u32 reserved058; /* 0x58 Refresh Control 2*/ + u32 reserved05C; + u32 rfshctl3; /* 0x60 Refresh Control 0*/ + u32 rfshtmg; /* 0x64 Refresh Timing*/ + u8 reserved068[0xc0 - 0x68]; + u32 crcparctl0; /* 0xc0 CRC Parity Control0*/ + u32 reserved0c4; /* 0xc4 CRC Parity Control1*/ + u32 reserved0c8; /* 0xc8 CRC Parity Control2*/ + u32 crcparstat; /* 0xcc CRC Parity Status*/ + u32 init0; /* 0xd0 SDRAM Initialization 0*/ + u32 init1; /* 0xd4 SDRAM Initialization 1*/ + u32 init2; /* 0xd8 SDRAM Initialization 2*/ + u32 init3; /* 0xdc SDRAM Initialization 3*/ + u32 init4; /* 0xe0 SDRAM Initialization 4*/ + u32 init5; /* 0xe4 SDRAM Initialization 5*/ + u32 reserved0e8; + u32 reserved0ec; + u32 dimmctl; /* 0xf0 DIMM Control*/ + u8 reserved0f4[0x100 - 0xf4]; + u32 dramtmg0; /* 0x100 SDRAM Timing 0*/ + u32 dramtmg1; /* 0x104 SDRAM Timing 1*/ + u32 dramtmg2; /* 0x108 SDRAM Timing 2*/ + u32 dramtmg3; /* 0x10c SDRAM Timing 3*/ + u32 dramtmg4; /* 0x110 SDRAM Timing 4*/ + u32 dramtmg5; /* 0x114 SDRAM Timing 5*/ + u32 dramtmg6; /* 0x118 SDRAM Timing 6*/ + u32 dramtmg7; /* 0x11c SDRAM Timing 7*/ + u32 dramtmg8; /* 0x120 SDRAM Timing 8*/ + u8 reserved124[0x138 - 0x124]; + u32 dramtmg14; /* 0x138 SDRAM Timing 14*/ + u32 dramtmg15; /* 0x13C SDRAM Timing 15*/ + u8 reserved140[0x180 - 0x140]; + u32 zqctl0; /* 0x180 ZQ Control 0*/ + u32 zqctl1; /* 0x184 ZQ Control 1*/ + u32 zqctl2; /* 0x188 ZQ Control 2*/ + u32 zqstat; /* 0x18c ZQ Status*/ + u32 dfitmg0; /* 0x190 DFI Timing 0*/ + u32 dfitmg1; /* 0x194 DFI Timing 1*/ + u32 dfilpcfg0; /* 0x198 DFI Low Power Configuration 0*/ + u32 reserved19c; + u32 dfiupd0; /* 0x1a0 DFI Update 0*/ + u32 dfiupd1; /* 0x1a4 DFI Update 1*/ + u32 dfiupd2; /* 0x1a8 DFI Update 2*/ + u32 reserved1ac; + u32 dfimisc; /* 0x1b0 DFI Miscellaneous Control*/ + u8 reserved1b4[0x1bc - 0x1b4]; + u32 dfistat; /* 0x1bc DFI Miscellaneous Control*/ + u8 reserved1c0[0x1c4 - 0x1c0]; + u32 dfiphymstr; /* 0x1c4 DFI PHY Master interface*/ + u8 reserved1c8[0x204 - 0x1c8]; + u32 addrmap1; /* 0x204 Address Map 1*/ + u32 addrmap2; /* 0x208 Address Map 2*/ + u32 addrmap3; /* 0x20c Address Map 3*/ + u32 addrmap4; /* 0x210 Address Map 4*/ + u32 addrmap5; /* 0x214 Address Map 5*/ + u32 addrmap6; /* 0x218 Address Map 6*/ + u8 reserved21c[0x224 - 0x21c]; + u32 addrmap9; /* 0x224 Address Map 9*/ + u32 addrmap10; /* 0x228 Address Map 10*/ + u32 addrmap11; /* 0x22C Address Map 11*/ + u8 reserved230[0x240 - 0x230]; + u32 odtcfg; /* 0x240 ODT Configuration*/ + u32 odtmap; /* 0x244 ODT/Rank Map*/ + u8 reserved248[0x250 - 0x248]; + u32 sched; /* 0x250 Scheduler Control*/ + u32 sched1; /* 0x254 Scheduler Control 1*/ + u32 reserved258; + u32 perfhpr1; /* 0x25c High Priority Read CAM 1*/ + u32 reserved260; + u32 perflpr1; /* 0x264 Low Priority Read CAM 1*/ + u32 reserved268; + u32 perfwr1; /* 0x26c Write CAM 1*/ + u8 reserved27c[0x300 - 0x270]; + u32 dbg0; /* 0x300 Debug 0*/ + u32 dbg1; /* 0x304 Debug 1*/ + u32 dbgcam; /* 0x308 CAM Debug*/ + u32 dbgcmd; /* 0x30c Command Debug*/ + u32 dbgstat; /* 0x310 Status Debug*/ + u8 reserved314[0x320 - 0x314]; + u32 swctl; /* 0x320 Software Programming Control Enable*/ + u32 swstat; /* 0x324 Software Programming Control Status*/ + u8 reserved328[0x36c - 0x328]; + u32 poisoncfg; /* 0x36c AXI Poison Configuration Register*/ + u32 poisonstat; /* 0x370 AXI Poison Status Register*/ + u8 reserved374[0x3fc - 0x374]; + + /* Multi Port registers */ + u32 pstat; /* 0x3fc Port Status*/ + u32 pccfg; /* 0x400 Port Common Configuration*/ + + /* PORT 0 */ + u32 pcfgr_0; /* 0x404 Configuration Read*/ + u32 pcfgw_0; /* 0x408 Configuration Write*/ + u8 reserved40c[0x490 - 0x40c]; + u32 pctrl_0; /* 0x490 Port Control Register */ + u32 pcfgqos0_0; /* 0x494 Read QoS Configuration 0*/ + u32 pcfgqos1_0; /* 0x498 Read QoS Configuration 1*/ + u32 pcfgwqos0_0; /* 0x49c Write QoS Configuration 0*/ + u32 pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1*/ + u8 reserved4a4[0x4b4 - 0x4a4]; + + /* PORT 1 */ + u32 pcfgr_1; /* 0x4b4 Configuration Read*/ + u32 pcfgw_1; /* 0x4b8 Configuration Write*/ + u8 reserved4bc[0x540 - 0x4bc]; + u32 pctrl_1; /* 0x540 Port 2 Control Register */ + u32 pcfgqos0_1; /* 0x544 Read QoS Configuration 0*/ + u32 pcfgqos1_1; /* 0x548 Read QoS Configuration 1*/ + u32 pcfgwqos0_1; /* 0x54c Write QoS Configuration 0*/ + u32 pcfgwqos1_1; /* 0x550 Write QoS Configuration 1*/ +}; + +/* DDR Physical Interface Control (DDRPHYC) registers*/ +struct stm32mp1_ddrphy { + u32 ridr; /* 0x00 R Revision Identification*/ + u32 pir; /* 0x04 R/W PHY Initialization*/ + u32 pgcr; /* 0x08 R/W PHY General Configuration*/ + u32 pgsr; /* 0x0C PHY General Status*/ + u32 dllgcr; /* 0x10 R/W DLL General Control*/ + u32 acdllcr; /* 0x14 R/W AC DLL Control*/ + u32 ptr0; /* 0x18 R/W PHY Timing 0*/ + u32 ptr1; /* 0x1C R/W PHY Timing 1*/ + u32 ptr2; /* 0x20 R/W PHY Timing 2*/ + u32 aciocr; /* 0x24 AC I/O Configuration*/ + u32 dxccr; /* 0x28 DATX8 Common Configuration*/ + u32 dsgcr; /* 0x2C DDR System General Configuration*/ + u32 dcr; /* 0x30 DRAM Configuration*/ + u32 dtpr0; /* 0x34 DRAM Timing Parameters0*/ + u32 dtpr1; /* 0x38 DRAM Timing Parameters1*/ + u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/ + u32 mr0; /* 0x40 Mode 0*/ + u32 mr1; /* 0x44 Mode 1*/ + u32 mr2; /* 0x48 Mode 2*/ + u32 mr3; /* 0x4C Mode 3*/ + u32 odtcr; /* 0x50 ODT Configuration*/ + u32 dtar; /* 0x54 data training address*/ + u32 dtdr0; /* 0x58 */ + u32 dtdr1; /* 0x5c */ + u8 res1[0x0c0 - 0x060]; /* 0x60 */ + u32 dcuar; /* 0xc0 Address*/ + u32 dcudr; /* 0xc4 DCU Data*/ + u32 dcurr; /* 0xc8 DCU Run*/ + u32 dculr; /* 0xcc DCU Loop*/ + u32 dcugcr; /* 0xd0 DCU General Configuration*/ + u32 dcutpr; /* 0xd4 DCU Timing Parameters */ + u32 dcusr0; /* 0xd8 DCU Status 0*/ + u32 dcusr1; /* 0xdc DCU Status 1*/ + u8 res2[0x100 - 0xe0]; /* 0xe0 */ + u32 bistrr; /* 0x100 BIST Run*/ + u32 bistmskr0; /* 0x104 BIST Mask 0*/ + u32 bistmskr1; /* 0x108 BIST Mask 0*/ + u32 bistwcr; /* 0x10c BIST Word Count*/ + u32 bistlsr; /* 0x110 BIST LFSR Seed*/ + u32 bistar0; /* 0x114 BIST Address 0*/ + u32 bistar1; /* 0x118 BIST Address 1*/ + u32 bistar2; /* 0x11c BIST Address 2*/ + u32 bistupdr; /* 0x120 BIST User Data Pattern*/ + u32 bistgsr; /* 0x124 BIST General Status*/ + u32 bistwer; /* 0x128 BIST Word Error*/ + u32 bistber0; /* 0x12c BIST Bit Error 0*/ + u32 bistber1; /* 0x130 BIST Bit Error 1*/ + u32 bistber2; /* 0x134 BIST Bit Error 2*/ + u32 bistwcsr; /* 0x138 BIST Word Count Status*/ + u32 bistfwr0; /* 0x13c BIST Fail Word 0*/ + u32 bistfwr1; /* 0x140 BIST Fail Word 1*/ + u8 res3[0x178 - 0x144]; /* 0x144 */ + u32 gpr0; /* 0x178 General Purpose 0 (GPR0)*/ + u32 gpr1; /* 0x17C General Purpose 1 (GPR1)*/ + u32 zq0cr0; /* 0x180 zq 0 control 0 */ + u32 zq0cr1; /* 0x184 zq 0 control 1 */ + u32 zq0sr0; /* 0x188 zq 0 status 0 */ + u32 zq0sr1; /* 0x18C zq 0 status 1 */ + u8 res4[0x1C0 - 0x190]; /* 0x190 */ + u32 dx0gcr; /* 0x1c0 Byte lane 0 General Configuration*/ + u32 dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0*/ + u32 dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1*/ + u32 dx0dllcr; /* 0x1cc Byte lane 0 DLL Control*/ + u32 dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing*/ + u32 dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing*/ + u8 res5[0x200 - 0x1d8]; /* 0x1d8 */ + u32 dx1gcr; /* 0x200 Byte lane 1 General Configuration*/ + u32 dx1gsr0; /* 0x204 Byte lane 1 General Status 0*/ + u32 dx1gsr1; /* 0x208 Byte lane 1 General Status 1*/ + u32 dx1dllcr; /* 0x20c Byte lane 1 DLL Control*/ + u32 dx1dqtr; /* 0x210 Byte lane 1 DQ Timing*/ + u32 dx1dqstr; /* 0x214 Byte lane 1 QS Timing*/ + u8 res6[0x240 - 0x218]; /* 0x218 */ + u32 dx2gcr; /* 0x240 Byte lane 2 General Configuration*/ + u32 dx2gsr0; /* 0x244 Byte lane 2 General Status 0*/ + u32 dx2gsr1; /* 0x248 Byte lane 2 General Status 1*/ + u32 dx2dllcr; /* 0x24c Byte lane 2 DLL Control*/ + u32 dx2dqtr; /* 0x250 Byte lane 2 DQ Timing*/ + u32 dx2dqstr; /* 0x254 Byte lane 2 QS Timing*/ + u8 res7[0x280 - 0x258]; /* 0x258 */ + u32 dx3gcr; /* 0x280 Byte lane 3 General Configuration*/ + u32 dx3gsr0; /* 0x284 Byte lane 3 General Status 0*/ + u32 dx3gsr1; /* 0x288 Byte lane 3 General Status 1*/ + u32 dx3dllcr; /* 0x28c Byte lane 3 DLL Control*/ + u32 dx3dqtr; /* 0x290 Byte lane 3 DQ Timing*/ + u32 dx3dqstr; /* 0x294 Byte lane 3 QS Timing*/ +}; + +#define DXN(phy, offset, byte) ((u32)(phy) + (offset) + ((u32)(byte) * 0x40)) +#define DXNGCR(phy, byte) DXN(phy, 0x1c0, byte) +#define DXNDLLCR(phy, byte) DXN(phy, 0x1cc, byte) +#define DXNDQTR(phy, byte) DXN(phy, 0x1d0, byte) +#define DXNDQSTR(phy, byte) DXN(phy, 0x1d4, byte) + +/* DDRCTRL REGISTERS */ +#define DDRCTRL_MSTR_DDR3 BIT(0) +#define DDRCTRL_MSTR_LPDDR2 BIT(2) +#define DDRCTRL_MSTR_LPDDR3 BIT(3) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12) +#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15) + +#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) +#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 1 +#define DDRCTRL_STAT_OPERATING_MODE_SR 3 +#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) +#define DDRCTRL_STAT_SELFREF_TYPE_ASR (3 << 4) +#define DDRCTRL_STAT_SELFREF_TYPE_SR (2 << 4) + +#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE 0 +/* only one rank supported */ +#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRCTRL_MRCTRL0_MR_RANK_ALL \ + (0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT) +#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12) +#define DDRCTRL_MRCTRL0_MR_WR BIT(31) + +#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) + +#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) +#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) +#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) + +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) + +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 + +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL (BIT(30)) + +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) + +#define DDRCTRL_DBG1_DIS_HIF BIT(1) + +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) +#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ + (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ + DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) +#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ + (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ + DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ + DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) + +#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) + +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) + +#define DDRCTRL_SWCTL_SW_DONE BIT(0) + +#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) + +#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) + +/* DDRPHYC registers */ +#define DDRPHYC_PIR_INIT BIT(0) +#define DDRPHYC_PIR_DLLSRST BIT(1) +#define DDRPHYC_PIR_DLLLOCK BIT(2) +#define DDRPHYC_PIR_ZCAL BIT(3) +#define DDRPHYC_PIR_ITMSRST BIT(4) +#define DDRPHYC_PIR_DRAMRST BIT(5) +#define DDRPHYC_PIR_DRAMINIT BIT(6) +#define DDRPHYC_PIR_QSTRN BIT(7) +#define DDRPHYC_PIR_ICPC BIT(16) +#define DDRPHYC_PIR_ZCALBYP BIT(30) +#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) + +#define DDRPHYC_PGCR_DFTCMP BIT(2) +#define DDRPHYC_PGCR_PDDISDX BIT(24) +#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25) + +#define DDRPHYC_PGSR_IDONE BIT(0) +#define DDRPHYC_PGSR_DTERR BIT(5) +#define DDRPHYC_PGSR_DTIERR BIT(6) +#define DDRPHYC_PGSR_DFTERR BIT(7) +#define DDRPHYC_PGSR_RVERR BIT(8) +#define DDRPHYC_PGSR_RVEIRR BIT(9) + +#define DDRPHYC_DLLGCR_BPS200 BIT(23) + +#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) + +#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0) +#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0 +#define DDRPHYC_ZQ0CRN_ZDEN BIT(28) + +#define DDRPHYC_DXNGCR_DXEN BIT(0) + +#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30) +#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) +#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14) +#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14 + +#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit)) +#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0) +#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0) +#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2) + +#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20) +#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20 +#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23) +#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23 +#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0) +#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0 +#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12) +#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12 + +#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19) +#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19 + +#define DDRPHYC_BISTGSR_BDDONE BIT(0) +#define DDRPHYC_BISTGSR_BDXERR BIT(2) + +#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16 + +/* PWR registers */ +#define PWR_CR3 0x00C +#define PWR_CR3_DDRSRDIS BIT(11) +#define PWR_CR3_DDRRETEN BIT(12) + +#endif diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_interactive.c b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_interactive.c new file mode 100644 index 000000000..8c2310ac9 --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -0,0 +1,497 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_RAM + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp1_ddr.h" +#include "stm32mp1_tests.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum ddr_command { + DDR_CMD_HELP, + DDR_CMD_INFO, + DDR_CMD_FREQ, + DDR_CMD_RESET, + DDR_CMD_PARAM, + DDR_CMD_PRINT, + DDR_CMD_EDIT, + DDR_CMD_STEP, + DDR_CMD_NEXT, + DDR_CMD_GO, + DDR_CMD_TEST, + DDR_CMD_TUNING, + DDR_CMD_UNKNOWN, +}; + +const char *step_str[] = { + [STEP_DDR_RESET] = "DDR_RESET", + [STEP_CTL_INIT] = "DDR_CTRL_INIT_DONE", + [STEP_PHY_INIT] = "DDR PHY_INIT_DONE", + [STEP_DDR_READY] = "DDR_READY", + [STEP_RUN] = "RUN" +}; + +enum ddr_command stm32mp1_get_command(char *cmd, int argc) +{ + const char *cmd_string[DDR_CMD_UNKNOWN] = { + [DDR_CMD_HELP] = "help", + [DDR_CMD_INFO] = "info", + [DDR_CMD_FREQ] = "freq", + [DDR_CMD_RESET] = "reset", + [DDR_CMD_PARAM] = "param", + [DDR_CMD_PRINT] = "print", + [DDR_CMD_EDIT] = "edit", + [DDR_CMD_STEP] = "step", + [DDR_CMD_NEXT] = "next", + [DDR_CMD_GO] = "go", +#ifdef CONFIG_STM32MP1_DDR_TESTS + [DDR_CMD_TEST] = "test", +#endif +#ifdef CONFIG_STM32MP1_DDR_TUNING + [DDR_CMD_TUNING] = "tuning", +#endif + }; + /* min and max number of argument */ + const char cmd_arg[DDR_CMD_UNKNOWN][2] = { + [DDR_CMD_HELP] = { 0, 0 }, + [DDR_CMD_INFO] = { 0, 255 }, + [DDR_CMD_FREQ] = { 0, 1 }, + [DDR_CMD_RESET] = { 0, 0 }, + [DDR_CMD_PARAM] = { 0, 2 }, + [DDR_CMD_PRINT] = { 0, 1 }, + [DDR_CMD_EDIT] = { 2, 2 }, + [DDR_CMD_STEP] = { 0, 1 }, + [DDR_CMD_NEXT] = { 0, 0 }, + [DDR_CMD_GO] = { 0, 0 }, +#ifdef CONFIG_STM32MP1_DDR_TESTS + [DDR_CMD_TEST] = { 0, 255 }, +#endif +#ifdef CONFIG_STM32MP1_DDR_TUNING + [DDR_CMD_TUNING] = { 0, 255 }, +#endif + }; + int i; + + for (i = 0; i < DDR_CMD_UNKNOWN; i++) + if (!strcmp(cmd, cmd_string[i])) { + if (argc - 1 < cmd_arg[i][0]) { + printf("no enought argument (min=%d)\n", + cmd_arg[i][0]); + return DDR_CMD_UNKNOWN; + } else if (argc - 1 > cmd_arg[i][1]) { + printf("too many argument (max=%d)\n", + cmd_arg[i][1]); + return DDR_CMD_UNKNOWN; + } else { + return i; + } + } + + printf("unknown command %s\n", cmd); + return DDR_CMD_UNKNOWN; +} + +static void stm32mp1_do_usage(void) +{ + const char *usage = { + "commands:\n\n" + "help displays help\n" + "info displays DDR information\n" + "info changes DDR information\n" + " with = step, name, size, speed or cal\n" + "freq displays the DDR PHY frequency in kHz\n" + "freq changes the DDR PHY frequency\n" + "param [type|reg] prints input parameters\n" + "param edits parameters in step 0\n" + "print [type|reg] dumps registers\n" + "edit modifies one register\n" + "step lists the available step\n" + "step go to the step \n" + "next goes to the next step\n" + "go continues the U-Boot SPL execution\n" + "reset reboots machine\n" +#ifdef CONFIG_STM32MP1_DDR_TESTS + "test [help] | [...] lists (with help) or executes test \n" +#endif +#ifdef CONFIG_STM32MP1_DDR_TUNING + "tuning [help] | [...] lists (with help) or execute tuning \n" +#endif + "\nwith for [type|reg]:\n" + " all registers if absent\n" + " = ctl, phy\n" + " or one category (static, timing, map, perf, cal, dyn)\n" + " = name of the register\n" + }; + + puts(usage); +} + +static bool stm32mp1_check_step(enum stm32mp1_ddr_interact_step step, + enum stm32mp1_ddr_interact_step expected) +{ + if (step != expected) { + printf("invalid step %d:%s expecting %d:%s\n", + step, step_str[step], + expected, + step_str[expected]); + return false; + } + return true; +} + +static void stm32mp1_do_info(struct ddr_info *priv, + struct stm32mp1_ddr_config *config, + enum stm32mp1_ddr_interact_step step, + int argc, char *const argv[]) +{ + unsigned long value; + static char *ddr_name; + + if (argc == 1) { + printf("step = %d : %s\n", step, step_str[step]); + printf("name = %s\n", config->info.name); + printf("size = 0x%x\n", config->info.size); + printf("speed = %d kHz\n", config->info.speed); + printf("cal = %d\n", config->p_cal_present); + return; + } + + if (argc < 3) { + printf("no enought parameter\n"); + return; + } + if (!strcmp(argv[1], "name")) { + u32 i, name_len = 0; + + for (i = 2; i < argc; i++) + name_len += strlen(argv[i]) + 1; + if (ddr_name) + free(ddr_name); + ddr_name = malloc(name_len); + config->info.name = ddr_name; + if (!ddr_name) { + printf("alloc error, length %d\n", name_len); + return; + } + strcpy(ddr_name, argv[2]); + for (i = 3; i < argc; i++) { + strcat(ddr_name, " "); + strcat(ddr_name, argv[i]); + } + printf("name = %s\n", ddr_name); + return; + } + if (!strcmp(argv[1], "size")) { + if (strict_strtoul(argv[2], 16, &value) < 0) { + printf("invalid value %s\n", argv[2]); + } else { + config->info.size = value; + printf("size = 0x%x\n", config->info.size); + } + return; + } + if (!strcmp(argv[1], "speed")) { + if (strict_strtoul(argv[2], 10, &value) < 0) { + printf("invalid value %s\n", argv[2]); + } else { + config->info.speed = value; + printf("speed = %d kHz\n", config->info.speed); + value = clk_get_rate(&priv->clk); + printf("DDRPHY = %ld kHz\n", value / 1000); + } + return; + } + if (!strcmp(argv[1], "cal")) { + if (strict_strtoul(argv[2], 10, &value) < 0 || + (value != 0 && value != 1)) { + printf("invalid value %s\n", argv[2]); + } else { + config->p_cal_present = value; + printf("cal = %d\n", config->p_cal_present); + } + return; + } + printf("argument %s invalid\n", argv[1]); +} + +static bool stm32mp1_do_freq(struct ddr_info *priv, + int argc, char *const argv[]) +{ + unsigned long ddrphy_clk; + + if (argc == 2) { + if (strict_strtoul(argv[1], 0, &ddrphy_clk) < 0) { + printf("invalid argument %s", argv[1]); + return false; + } + if (clk_set_rate(&priv->clk, ddrphy_clk * 1000)) { + printf("ERROR: update failed!\n"); + return false; + } + } + ddrphy_clk = clk_get_rate(&priv->clk); + printf("DDRPHY = %ld kHz\n", ddrphy_clk / 1000); + if (argc == 2) + return true; + return false; +} + +static void stm32mp1_do_param(enum stm32mp1_ddr_interact_step step, + const struct stm32mp1_ddr_config *config, + int argc, char *const argv[]) +{ + switch (argc) { + case 1: + stm32mp1_dump_param(config, NULL); + break; + case 2: + if (stm32mp1_dump_param(config, argv[1])) + printf("invalid argument %s\n", + argv[1]); + break; + case 3: + if (!stm32mp1_check_step(step, STEP_DDR_RESET)) + return; + stm32mp1_edit_param(config, argv[1], argv[2]); + break; + } +} + +static void stm32mp1_do_print(struct ddr_info *priv, + int argc, char *const argv[]) +{ + switch (argc) { + case 1: + stm32mp1_dump_reg(priv, NULL); + break; + case 2: + if (stm32mp1_dump_reg(priv, argv[1])) + printf("invalid argument %s\n", + argv[1]); + break; + } +} + +static int stm32mp1_do_step(enum stm32mp1_ddr_interact_step step, + int argc, char *const argv[]) +{ + int i; + unsigned long value; + + switch (argc) { + case 1: + for (i = 0; i < ARRAY_SIZE(step_str); i++) + printf("%d:%s\n", i, step_str[i]); + break; + + case 2: + if ((strict_strtoul(argv[1], 0, + &value) < 0) || + value >= ARRAY_SIZE(step_str)) { + printf("invalid argument %s\n", + argv[1]); + goto end; + } + + if (value != STEP_DDR_RESET && + value <= step) { + printf("invalid target %d:%s, current step is %d:%s\n", + (int)value, step_str[value], + step, step_str[step]); + goto end; + } + printf("step to %d:%s\n", + (int)value, step_str[value]); + return (int)value; + }; + +end: + return step; +} + +#if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING) +static const char * const s_result[] = { + [TEST_PASSED] = "Pass", + [TEST_FAILED] = "Failed", + [TEST_ERROR] = "Error" +}; + +static void stm32mp1_ddr_subcmd(struct ddr_info *priv, + int argc, char *argv[], + const struct test_desc array[], + const int array_nb) +{ + int i; + unsigned long value; + int result; + char string[50] = ""; + + if (argc == 1) { + printf("%s:%d\n", argv[0], array_nb); + for (i = 0; i < array_nb; i++) + printf("%d:%s:%s\n", + i, array[i].name, array[i].usage); + return; + } + if (argc > 1 && !strcmp(argv[1], "help")) { + printf("%s:%d\n", argv[0], array_nb); + for (i = 0; i < array_nb; i++) + printf("%d:%s:%s:%s\n", i, + array[i].name, array[i].usage, array[i].help); + return; + } + + if ((strict_strtoul(argv[1], 0, &value) < 0) || + value >= array_nb) { + sprintf(string, "invalid argument %s", + argv[1]); + result = TEST_FAILED; + goto end; + } + + if (argc > (array[value].max_args + 2)) { + sprintf(string, "invalid nb of args %d, max %d", + argc - 2, array[value].max_args); + result = TEST_FAILED; + goto end; + } + + printf("execute %d:%s\n", (int)value, array[value].name); + clear_ctrlc(); + result = array[value].fct(priv->ctl, priv->phy, + string, argc - 2, &argv[2]); + +end: + printf("Result: %s [%s]\n", s_result[result], string); +} +#endif + +bool stm32mp1_ddr_interactive(void *priv, + enum stm32mp1_ddr_interact_step step, + const struct stm32mp1_ddr_config *config) +{ + char buffer[CONFIG_SYS_CBSIZE]; + char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ + int argc; + static int next_step = -1; + + if (next_step < 0 && step == STEP_DDR_RESET) { +#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE_FORCE + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + next_step = STEP_DDR_RESET; +#else + unsigned long start = get_timer(0); + + while (1) { + if (tstc() && (getchar() == 'd')) { + next_step = STEP_DDR_RESET; + break; + } + if (get_timer(start) > 100) + break; + } +#endif + } + + log_debug("** step %d ** %s / %d\n", step, step_str[step], next_step); + + if (next_step < 0) + return false; + + if (step < 0 || step > ARRAY_SIZE(step_str)) { + printf("** step %d ** INVALID\n", step); + return false; + } + + printf("%d:%s\n", step, step_str[step]); + + if (next_step > step) + return false; + + while (next_step == step) { + cli_readline_into_buffer("DDR>", buffer, 0); + argc = cli_simple_parse_line(buffer, argv); + if (!argc) + continue; + + switch (stm32mp1_get_command(argv[0], argc)) { + case DDR_CMD_HELP: + stm32mp1_do_usage(); + break; + + case DDR_CMD_INFO: + stm32mp1_do_info(priv, + (struct stm32mp1_ddr_config *)config, + step, argc, argv); + break; + + case DDR_CMD_FREQ: + if (stm32mp1_do_freq(priv, argc, argv)) + next_step = STEP_DDR_RESET; + break; + + case DDR_CMD_RESET: + do_reset(NULL, 0, 0, NULL); + break; + + case DDR_CMD_PARAM: + stm32mp1_do_param(step, config, argc, argv); + break; + + case DDR_CMD_PRINT: + stm32mp1_do_print(priv, argc, argv); + break; + + case DDR_CMD_EDIT: + stm32mp1_edit_reg(priv, argv[1], argv[2]); + break; + + case DDR_CMD_GO: + next_step = STEP_RUN; + break; + + case DDR_CMD_NEXT: + next_step = step + 1; + break; + + case DDR_CMD_STEP: + next_step = stm32mp1_do_step(step, argc, argv); + break; + +#ifdef CONFIG_STM32MP1_DDR_TESTS + case DDR_CMD_TEST: + if (!stm32mp1_check_step(step, STEP_DDR_READY)) + continue; + stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb); + break; +#endif + +#ifdef CONFIG_STM32MP1_DDR_TUNING + case DDR_CMD_TUNING: + if (!stm32mp1_check_step(step, STEP_DDR_READY)) + continue; + stm32mp1_ddr_subcmd(priv, argc, argv, + tuning, tuning_nb); + break; +#endif + + default: + break; + } + } + return next_step == STEP_DDR_RESET; +} diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ram.c b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ram.c new file mode 100644 index 000000000..26f0b4f1e --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_RAM + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp1_ddr.h" + +static const char *const clkname[] = { + "ddrc1", + "ddrc2", + "ddrcapb", + "ddrphycapb", + "ddrphyc" /* LAST clock => used for get_rate() */ +}; + +int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) +{ + unsigned long ddrphy_clk; + unsigned long ddr_clk; + struct clk clk; + int ret; + unsigned int idx; + + for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) { + ret = clk_get_by_name(priv->dev, clkname[idx], &clk); + + if (!ret) + ret = clk_enable(&clk); + + if (ret) { + log_err("error for %s : %d\n", clkname[idx], ret); + return ret; + } + } + + priv->clk = clk; + ddrphy_clk = clk_get_rate(&priv->clk); + + log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n", + mem_speed, (u32)(ddrphy_clk / 1000)); + /* max 10% frequency delta */ + ddr_clk = abs(ddrphy_clk - mem_speed * 1000); + if (ddr_clk > (mem_speed * 100)) { + log_err("DDR expected freq %d kHz, current is %d kHz\n", + mem_speed, (u32)(ddrphy_clk / 1000)); + return -EINVAL; + } + + return 0; +} + +__weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev, + const char *name) +{ + return 0; /* Always match */ +} + +static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev) +{ + const char *name; + ofnode node; + + dev_for_each_subnode(node, dev) { + name = ofnode_get_property(node, "compatible", NULL); + + if (!board_stm32mp1_ddr_config_name_match(dev, name)) + return node; + } + + return dev_ofnode(dev); +} + +static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) +{ + struct ddr_info *priv = dev_get_priv(dev); + int ret; + unsigned int idx; + struct clk axidcg; + struct stm32mp1_ddr_config config; + ofnode node = stm32mp1_ddr_get_ofnode(dev); + +#define PARAM(x, y, z) \ + { .name = x, \ + .offset = offsetof(struct stm32mp1_ddr_config, y), \ + .size = sizeof(config.y) / sizeof(u32), \ + .present = z, \ + } + +#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL) +#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL) +#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present) + + const struct { + const char *name; /* name in DT */ + const u32 offset; /* offset in config struct */ + const u32 size; /* size of parameters */ + bool * const present; /* presence indication for opt */ + } param[] = { + CTL_PARAM(reg), + CTL_PARAM(timing), + CTL_PARAM(map), + CTL_PARAM(perf), + PHY_PARAM(reg), + PHY_PARAM(timing), + PHY_PARAM_OPT(cal) + }; + + config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0); + config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0); + config.info.name = ofnode_read_string(node, "st,mem-name"); + if (!config.info.name) { + dev_dbg(dev, "no st,mem-name\n"); + return -EINVAL; + } + printf("RAM: %s\n", config.info.name); + + for (idx = 0; idx < ARRAY_SIZE(param); idx++) { + ret = ofnode_read_u32_array(node, param[idx].name, + (void *)((u32)&config + + param[idx].offset), + param[idx].size); + dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__, + param[idx].name, param[idx].size, ret); + if (ret && + (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) { + dev_err(dev, "Cannot read %s, error=%d\n", + param[idx].name, ret); + return -EINVAL; + } + if (param[idx].present) { + /* save presence of optional parameters */ + *param[idx].present = true; + if (ret == -FDT_ERR_NOTFOUND) { + *param[idx].present = false; +#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE + /* reset values if used later */ + memset((void *)((u32)&config + + param[idx].offset), + 0, param[idx].size * sizeof(u32)); +#endif + } + } + } + + ret = clk_get_by_name(dev, "axidcg", &axidcg); + if (ret) { + dev_dbg(dev, "%s: Cannot found axidcg\n", __func__); + return -EINVAL; + } + clk_disable(&axidcg); /* disable clock gating during init */ + + stm32mp1_ddr_init(priv, &config); + + clk_enable(&axidcg); /* enable clock gating */ + + /* check size */ + dev_dbg(dev, "get_ram_size(%x, %x)\n", + (u32)priv->info.base, (u32)STM32_DDR_SIZE); + + priv->info.size = get_ram_size((long *)priv->info.base, + STM32_DDR_SIZE); + + dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size); + + /* check memory access for all memory */ + if (config.info.size != priv->info.size) { + printf("DDR invalid size : 0x%x, expected 0x%x\n", + priv->info.size, config.info.size); + return -EINVAL; + } + return 0; +} + +static int stm32mp1_ddr_probe(struct udevice *dev) +{ + struct ddr_info *priv = dev_get_priv(dev); + struct regmap *map; + int ret; + + priv->dev = dev; + + ret = regmap_init_mem(dev_ofnode(dev), &map); + if (ret) + return log_ret(ret); + + priv->ctl = regmap_get_range(map, 0); + priv->phy = regmap_get_range(map, 1); + + priv->rcc = STM32_RCC_BASE; + + priv->info.base = STM32_DDR_BASE; + +#if !defined(CONFIG_TFABOOT) && \ + (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + priv->info.size = 0; + ret = stm32mp1_ddr_setup(dev); + + return log_ret(ret); +#else + ofnode node = stm32mp1_ddr_get_ofnode(dev); + priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0); + return 0; +#endif +} + +static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info) +{ + struct ddr_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops stm32mp1_ddr_ops = { + .get_info = stm32mp1_ddr_get_info, +}; + +static const struct udevice_id stm32mp1_ddr_ids[] = { + { .compatible = "st,stm32mp1-ddr" }, + { } +}; + +U_BOOT_DRIVER(ddr_stm32mp1) = { + .name = "stm32mp1_ddr", + .id = UCLASS_RAM, + .of_match = stm32mp1_ddr_ids, + .ops = &stm32mp1_ddr_ops, + .probe = stm32mp1_ddr_probe, + .priv_auto = sizeof(struct ddr_info), +}; diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.c b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.c new file mode 100644 index 000000000..64262f1aa --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -0,0 +1,1504 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_RAM + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp1_tests.h" + +#define ADDR_INVALID 0xFFFFFFFF + +#define PATTERN_DEFAULT "-" + +DECLARE_GLOBAL_DATA_PTR; + +static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, + size_t *bufsize, size_t default_size, size_t min_size) +{ + unsigned long value; + + if (argc > arg_nb) { + if (strict_strtoul(argv[arg_nb], 0, &value) < 0) { + sprintf(string, "invalid %d parameter %s", + arg_nb, argv[arg_nb]); + return -1; + } + if (value > STM32_DDR_SIZE || value < min_size) { + sprintf(string, "invalid size %s (min=%d)", + argv[arg_nb], min_size); + return -1; + } + if (value & (min_size - 1)) { + sprintf(string, "unaligned size %s (min=%d)", + argv[arg_nb], min_size); + return -1; + } + *bufsize = value; + } else { + if (default_size != STM32_DDR_SIZE) + *bufsize = default_size; + else + *bufsize = get_ram_size((long *)STM32_DDR_BASE, + STM32_DDR_SIZE); + } + return 0; +} + +static int get_nb_loop(char *string, int argc, char *argv[], int arg_nb, + u32 *nb_loop, u32 default_nb_loop) +{ + unsigned long value; + + if (argc > arg_nb) { + if (strict_strtoul(argv[arg_nb], 0, &value) < 0) { + sprintf(string, "invalid %d parameter %s", + arg_nb, argv[arg_nb]); + return -1; + } + if (value == 0) + printf("WARNING: infinite loop requested\n"); + *nb_loop = value; + } else { + *nb_loop = default_nb_loop; + } + + return 0; +} + +static int get_addr(char *string, int argc, char *argv[], int arg_nb, + u32 *addr) +{ + unsigned long value; + + if (argc > arg_nb) { + if (strict_strtoul(argv[arg_nb], 16, &value) < 0) { + sprintf(string, "invalid %d parameter %s", + arg_nb, argv[arg_nb]); + return -1; + } + if (value < STM32_DDR_BASE) { + sprintf(string, "too low address %s", argv[arg_nb]); + return -1; + } + if (value & 0x3 && value != ADDR_INVALID) { + sprintf(string, "unaligned address %s", + argv[arg_nb]); + return -1; + } + *addr = value; + } else { + *addr = STM32_DDR_BASE; + } + + return 0; +} + +static int get_pattern(char *string, int argc, char *argv[], int arg_nb, + u32 *pattern, u32 default_pattern) +{ + unsigned long value; + + if (argc > arg_nb) { + if (!strcmp(argv[arg_nb], PATTERN_DEFAULT)) { + *pattern = default_pattern; + return 0; + } + if (strict_strtoul(argv[arg_nb], 16, &value) < 0) { + sprintf(string, "invalid %d parameter %s", + arg_nb, argv[arg_nb]); + return -1; + } + *pattern = value; + } else { + *pattern = default_pattern; + } + + return 0; +} + +static u32 check_addr(u32 addr, u32 value) +{ + u32 data = readl(addr); + + if (value != data) { + printf("0x%08x: 0x%08x <=> 0x%08x", addr, data, value); + data = readl(addr); + printf("(2nd read: 0x%08x)", data); + if (value == data) + printf("- read error"); + else + printf("- write error"); + printf("\n"); + return -1; + } + return 0; +} + +static int progress(u32 offset) +{ + if (!(offset & 0xFFFFFF)) { + putc('.'); + if (ctrlc()) { + printf("\ntest interrupted!\n"); + return 1; + } + } + return 0; +} + +static int test_loop_end(u32 *loop, u32 nb_loop, u32 progress) +{ + (*loop)++; + if (nb_loop && *loop >= nb_loop) + return 1; + if ((*loop) % progress) + return 0; + /* allow to interrupt the test only for progress step */ + if (ctrlc()) { + printf("test interrupted!\n"); + return 1; + } + printf("loop #%d\n", *loop); + WATCHDOG_RESET(); + + return 0; +} + +/********************************************************************** + * + * Function: memTestDataBus() + * + * Description: Test the data bus wiring in a memory region by + * performing a walking 1's test at a fixed address + * within that region. The address is selected + * by the caller. + * + * Notes: + * + * Returns: 0 if the test succeeds. + * A non-zero result is the first pattern that failed. + * + **********************************************************************/ +static u32 databus(u32 *address) +{ + u32 pattern; + u32 read_value; + + /* Perform a walking 1's test at the given address. */ + for (pattern = 1; pattern != 0; pattern <<= 1) { + /* Write the test pattern. */ + writel(pattern, address); + + /* Read it back (immediately is okay for this test). */ + read_value = readl(address); + log_debug("%x: %x <=> %x\n", + (u32)address, read_value, pattern); + + if (read_value != pattern) + return pattern; + } + + return 0; +} + +/********************************************************************** + * + * Function: memTestAddressBus() + * + * Description: Test the address bus wiring in a memory region by + * performing a walking 1's test on the relevant bits + * of the address and checking for aliasing. This test + * will find single-bit address failures such as stuck + * -high, stuck-low, and shorted pins. The base address + * and size of the region are selected by the caller. + * + * Notes: For best results, the selected base address should + * have enough LSB 0's to guarantee single address bit + * changes. For example, to test a 64-Kbyte region, + * select a base address on a 64-Kbyte boundary. Also, + * select the region size as a power-of-two--if at all + * possible. + * + * Returns: NULL if the test succeeds. + * A non-zero result is the first address at which an + * aliasing problem was uncovered. By examining the + * contents of memory, it may be possible to gather + * additional information about the problem. + * + **********************************************************************/ +static u32 *addressbus(u32 *address, u32 nb_bytes) +{ + u32 mask = (nb_bytes / sizeof(u32) - 1); + u32 offset; + u32 test_offset; + u32 read_value; + + u32 pattern = 0xAAAAAAAA; + u32 antipattern = 0x55555555; + + /* Write the default pattern at each of the power-of-two offsets. */ + for (offset = 1; (offset & mask) != 0; offset <<= 1) + writel(pattern, &address[offset]); + + /* Check for address bits stuck high. */ + test_offset = 0; + writel(antipattern, &address[test_offset]); + + for (offset = 1; (offset & mask) != 0; offset <<= 1) { + read_value = readl(&address[offset]); + log_debug("%x: %x <=> %x\n", + (u32)&address[offset], read_value, pattern); + if (read_value != pattern) + return &address[offset]; + } + + writel(pattern, &address[test_offset]); + + /* Check for address bits stuck low or shorted. */ + for (test_offset = 1; (test_offset & mask) != 0; test_offset <<= 1) { + writel(antipattern, &address[test_offset]); + if (readl(&address[0]) != pattern) + return &address[test_offset]; + + for (offset = 1; (offset & mask) != 0; offset <<= 1) { + if (readl(&address[offset]) != pattern && + offset != test_offset) + return &address[test_offset]; + } + writel(pattern, &address[test_offset]); + } + + return NULL; +} + +/********************************************************************** + * + * Function: memTestDevice() + * + * Description: Test the integrity of a physical memory device by + * performing an increment/decrement test over the + * entire region. In the process every storage bit + * in the device is tested as a zero and a one. The + * base address and the size of the region are + * selected by the caller. + * + * Notes: + * + * Returns: NULL if the test succeeds. + * + * A non-zero result is the first address at which an + * incorrect value was read back. By examining the + * contents of memory, it may be possible to gather + * additional information about the problem. + * + **********************************************************************/ +static u32 *memdevice(u32 *address, u32 nb_bytes) +{ + u32 offset; + u32 nb_words = nb_bytes / sizeof(u32); + + u32 pattern; + u32 antipattern; + + puts("Fill with pattern"); + /* Fill memory with a known pattern. */ + for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) { + writel(pattern, &address[offset]); + if (progress(offset)) + return NULL; + } + + puts("\nCheck and invert pattern"); + /* Check each location and invert it for the second pass. */ + for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) { + if (readl(&address[offset]) != pattern) + return &address[offset]; + + antipattern = ~pattern; + writel(antipattern, &address[offset]); + if (progress(offset)) + return NULL; + } + + puts("\nCheck inverted pattern"); + /* Check each location for the inverted pattern and zero it. */ + for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) { + antipattern = ~pattern; + if (readl(&address[offset]) != antipattern) + return &address[offset]; + if (progress(offset)) + return NULL; + } + printf("\n"); + + return NULL; +} + +static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + int i; + u32 loop = 0, nb_loop; + u32 addr; + u32 error = 0; + u32 data; + + if (get_nb_loop(string, argc, argv, 0, &nb_loop, 100)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 1, &addr)) + return TEST_ERROR; + + printf("running %d loops at 0x%x\n", nb_loop, addr); + while (!error) { + for (i = 0; i < 32; i++) + writel(~(1 << i), addr + 4 * i); + for (i = 0; i < 32; i++) { + data = readl(addr + 4 * i); + if (~(1 << i) != data) { + error |= 1 << i; + log_debug("%x: error %x expected %x => error:%x\n", + addr + 4 * i, data, ~(1 << i), error); + } + } + if (test_loop_end(&loop, nb_loop, 1000)) + break; + for (i = 0; i < 32; i++) + writel(0, addr + 4 * i); + } + if (error) { + sprintf(string, "loop %d: error for bits 0x%x", + loop, error); + return TEST_FAILED; + } + sprintf(string, "no error for %d loops", loop); + return TEST_PASSED; +} + +static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + int i; + u32 loop = 0, nb_loop; + u32 addr; + u32 error = 0; + u32 data; + + if (get_nb_loop(string, argc, argv, 0, &nb_loop, 100)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 1, &addr)) + return TEST_ERROR; + printf("running %d loops at 0x%x\n", nb_loop, addr); + while (!error) { + for (i = 0; i < 32; i++) + writel(1 << i, addr + 4 * i); + for (i = 0; i < 32; i++) { + data = readl(addr + 4 * i); + if ((1 << i) != data) { + error |= 1 << i; + log_debug("%x: error %x expected %x => error:%x\n", + addr + 4 * i, data, (1 << i), error); + } + } + if (test_loop_end(&loop, nb_loop, 1000)) + break; + for (i = 0; i < 32; i++) + writel(0, addr + 4 * i); + } + if (error) { + sprintf(string, "loop %d: error for bits 0x%x", + loop, error); + return TEST_FAILED; + } + sprintf(string, "no error for %d loops", loop); + return TEST_PASSED; +} + +static enum test_result test_databus(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 addr; + u32 error; + + if (get_addr(string, argc, argv, 0, &addr)) + return TEST_ERROR; + error = databus((u32 *)addr); + if (error) { + sprintf(string, "0x%x: error for bits 0x%x", + addr, error); + return TEST_FAILED; + } + sprintf(string, "address 0x%x", addr); + return TEST_PASSED; +} + +static enum test_result test_addressbus(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 addr; + u32 bufsize; + u32 error; + + if (get_bufsize(string, argc, argv, 0, &bufsize, STM32_DDR_SIZE, 4)) + return TEST_ERROR; + if (!is_power_of_2(bufsize)) { + sprintf(string, "size 0x%x is not a power of 2", + (u32)bufsize); + return TEST_ERROR; + } + if (get_addr(string, argc, argv, 1, &addr)) + return TEST_ERROR; + + printf("running at 0x%08x length 0x%x\n", addr, bufsize); + error = (u32)addressbus((u32 *)addr, bufsize); + if (error) { + sprintf(string, "0x%x: error for address 0x%x", + addr, error); + return TEST_FAILED; + } + sprintf(string, "address 0x%x, size 0x%x", + addr, bufsize); + return TEST_PASSED; +} + +static enum test_result test_memdevice(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 addr; + size_t bufsize; + u32 error; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 1, &addr)) + return TEST_ERROR; + error = (u32)memdevice((u32 *)addr, (unsigned long)bufsize); + if (error) { + sprintf(string, "0x%x: error for address 0x%x", + addr, error); + return TEST_FAILED; + } + sprintf(string, "address 0x%x, size 0x%x", + addr, bufsize); + return TEST_PASSED; +} + +/********************************************************************** + * + * Function: sso + * + * Description: Test the Simultaneous Switching Output. + * Verifies succes sive reads and writes to the same memory word, + * holding one bit constant while toggling all other data bits + * simultaneously + * => stress the data bus over an address range + * + * The CPU writes to each address in the given range. + * For each bit, first the CPU holds the bit at 1 while + * toggling the other bits, and then the CPU holds the bit at 0 + * while toggling the other bits. + * After each write, the CPU reads the address that was written + * to verify that it contains the correct data + * + **********************************************************************/ +static enum test_result test_sso(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + int i, j; + u32 addr, bufsize, remaining, offset; + u32 error = 0; + u32 data; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 1, &addr)) + return TEST_ERROR; + + printf("running sso at 0x%x length 0x%x", addr, bufsize); + offset = addr; + remaining = bufsize; + while (remaining) { + for (i = 0; i < 32; i++) { + /* write pattern. */ + for (j = 0; j < 6; j++) { + switch (j) { + case 0: + case 2: + data = 1 << i; + break; + case 3: + case 5: + data = ~(1 << i); + break; + case 1: + data = ~0x0; + break; + case 4: + data = 0x0; + break; + } + + writel(data, offset); + error = check_addr(offset, data); + if (error) + goto end; + } + } + offset += 4; + remaining -= 4; + if (progress(offset << 7)) + goto end; + } + puts("\n"); + +end: + if (error) { + sprintf(string, "error for pattern 0x%x @0x%x", + data, offset); + return TEST_FAILED; + } + sprintf(string, "no error for sso at 0x%x length 0x%x", addr, bufsize); + return TEST_PASSED; +} + +/********************************************************************** + * + * Function: Random + * + * Description: Verifies r/w with pseudo-ramdom value on one region + * + write the region (individual access) + * + memcopy to the 2nd region (try to use burst) + * + verify the 2 regions + * + **********************************************************************/ +static enum test_result test_random(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 addr, offset, value = 0; + size_t bufsize; + u32 loop = 0, nb_loop; + u32 error = 0; + unsigned int seed; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 8)) + return TEST_ERROR; + if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + bufsize /= 2; + printf("running %d loops copy from 0x%x to 0x%x (buffer size=0x%x)\n", + nb_loop, addr, addr + bufsize, bufsize); + while (!error) { + seed = rand(); + for (offset = 0; offset < bufsize; offset += 4) + writel(rand(), addr + offset); + + memcpy((void *)addr + bufsize, (void *)addr, bufsize); + + srand(seed); + for (offset = 0; offset < 2 * bufsize; offset += 4) { + if (offset == bufsize) + srand(seed); + value = rand(); + error = check_addr(addr + offset, value); + if (error) + break; + if (progress(offset)) + return TEST_FAILED; + } + if (test_loop_end(&loop, nb_loop, 100)) + break; + } + putc('\n'); + + if (error) { + sprintf(string, + "loop %d: error for address 0x%x: 0x%x expected 0x%x", + loop, offset, readl(offset), value); + return TEST_FAILED; + } + sprintf(string, "no error for %d loops, size 0x%x", + loop, bufsize); + return TEST_PASSED; +} + +/********************************************************************** + * + * Function: noise + * + * Description: Verifies r/w while forcing switching of all data bus lines. + * optimised 4 iteration write/read/write/read cycles... + * for pattern and inversed pattern + * + **********************************************************************/ +void do_noise(u32 addr, u32 pattern, u32 *result) +{ + __asm__("push {R0-R11}"); + __asm__("mov r0, %0" : : "r" (addr)); + __asm__("mov r1, %0" : : "r" (pattern)); + __asm__("mov r11, %0" : : "r" (result)); + + __asm__("mvn r2, r1"); + + __asm__("str r1, [r0]"); + __asm__("ldr r3, [r0]"); + __asm__("str r2, [r0]"); + __asm__("ldr r4, [r0]"); + + __asm__("str r1, [r0]"); + __asm__("ldr r5, [r0]"); + __asm__("str r2, [r0]"); + __asm__("ldr r6, [r0]"); + + __asm__("str r1, [r0]"); + __asm__("ldr r7, [r0]"); + __asm__("str r2, [r0]"); + __asm__("ldr r8, [r0]"); + + __asm__("str r1, [r0]"); + __asm__("ldr r9, [r0]"); + __asm__("str r2, [r0]"); + __asm__("ldr r10, [r0]"); + + __asm__("stmia R11!, {R3-R10}"); + + __asm__("pop {R0-R11}"); +} + +static enum test_result test_noise(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 addr, pattern; + u32 result[8]; + int i; + enum test_result res = TEST_PASSED; + + if (get_pattern(string, argc, argv, 0, &pattern, 0xFFFFFFFF)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 1, &addr)) + return TEST_ERROR; + + printf("running noise for 0x%x at 0x%x\n", pattern, addr); + + do_noise(addr, pattern, result); + + for (i = 0; i < 0x8;) { + if (check_addr((u32)&result[i++], pattern)) + res = TEST_FAILED; + if (check_addr((u32)&result[i++], ~pattern)) + res = TEST_FAILED; + } + + return res; +} + +/********************************************************************** + * + * Function: noise_burst + * + * Description: Verifies r/w while forcing switching of all data bus lines. + * optimised write loop witrh store multiple to use burst + * for pattern and inversed pattern + * + **********************************************************************/ +void do_noise_burst(u32 addr, u32 pattern, size_t bufsize) +{ + __asm__("push {R0-R9}"); + __asm__("mov r0, %0" : : "r" (addr)); + __asm__("mov r1, %0" : : "r" (pattern)); + __asm__("mov r9, %0" : : "r" (bufsize)); + + __asm__("mvn r2, r1"); + __asm__("mov r3, r1"); + __asm__("mov r4, r2"); + __asm__("mov r5, r1"); + __asm__("mov r6, r2"); + __asm__("mov r7, r1"); + __asm__("mov r8, r2"); + + __asm__("loop1:"); + __asm__("stmia R0!, {R1-R8}"); + __asm__("stmia R0!, {R1-R8}"); + __asm__("stmia R0!, {R1-R8}"); + __asm__("stmia R0!, {R1-R8}"); + __asm__("subs r9, r9, #128"); + __asm__("bge loop1"); + __asm__("pop {R0-R9}"); +} + +/* chunk size enough to allow interruption with Ctrl-C*/ +#define CHUNK_SIZE 0x8000000 +static enum test_result test_noise_burst(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 addr, offset, pattern; + size_t bufsize, remaining, size; + int i; + enum test_result res = TEST_PASSED; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 128)) + return TEST_ERROR; + if (get_pattern(string, argc, argv, 1, &pattern, 0xFFFFFFFF)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + printf("running noise burst for 0x%x at 0x%x + 0x%x", + pattern, addr, bufsize); + + offset = addr; + remaining = bufsize; + size = CHUNK_SIZE; + while (remaining) { + if (remaining < size) + size = remaining; + do_noise_burst(offset, pattern, size); + remaining -= size; + offset += size; + if (progress(offset)) { + res = TEST_FAILED; + goto end; + } + } + puts("\ncheck buffer"); + for (i = 0; i < bufsize;) { + if (check_addr(addr + i, pattern)) + res = TEST_FAILED; + i += 4; + if (check_addr(addr + i, ~pattern)) + res = TEST_FAILED; + i += 4; + if (progress(i)) { + res = TEST_FAILED; + goto end; + } + } +end: + puts("\n"); + return res; +} + +/********************************************************************** + * + * Function: pattern test + * + * Description: optimized loop for read/write pattern (array of 8 u32) + * + **********************************************************************/ +#define PATTERN_SIZE 8 +static enum test_result test_loop(const u32 *pattern, u32 *address, + const u32 bufsize) +{ + int i; + int j; + enum test_result res = TEST_PASSED; + u32 offset, testsize, remaining; + + offset = (u32)address; + remaining = bufsize; + while (remaining) { + testsize = bufsize > 0x1000000 ? 0x1000000 : bufsize; + + __asm__("push {R0-R10}"); + __asm__("mov r0, %0" : : "r" (pattern)); + __asm__("mov r1, %0" : : "r" (offset)); + __asm__("mov r2, %0" : : "r" (testsize)); + __asm__("ldmia r0!, {R3-R10}"); + + __asm__("loop2:"); + __asm__("stmia r1!, {R3-R10}"); + __asm__("stmia r1!, {R3-R10}"); + __asm__("stmia r1!, {R3-R10}"); + __asm__("stmia r1!, {R3-R10}"); + __asm__("subs r2, r2, #128"); + __asm__("bge loop2"); + __asm__("pop {R0-R10}"); + + offset += testsize; + remaining -= testsize; + if (progress((u32)offset)) { + res = TEST_FAILED; + goto end; + } + } + + puts("\ncheck buffer"); + for (i = 0; i < bufsize; i += PATTERN_SIZE * 4) { + for (j = 0; j < PATTERN_SIZE; j++, address++) + if (check_addr((u32)address, pattern[j])) { + res = TEST_FAILED; + goto end; + } + if (progress(i)) { + res = TEST_FAILED; + goto end; + } + } + +end: + puts("\n"); + return res; +} + +const u32 pattern_div1_x16[PATTERN_SIZE] = { + 0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF, + 0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF +}; + +const u32 pattern_div2_x16[PATTERN_SIZE] = { + 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000, + 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000 +}; + +const u32 pattern_div4_x16[PATTERN_SIZE] = { + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000 +}; + +const u32 pattern_div4_x32[PATTERN_SIZE] = { + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +const u32 pattern_mostly_zero_x16[PATTERN_SIZE] = { + 0x00000000, 0x00000000, 0x00000000, 0x0000FFFF, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +const u32 pattern_mostly_zero_x32[PATTERN_SIZE] = { + 0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +const u32 pattern_mostly_one_x16[PATTERN_SIZE] = { + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000FFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF +}; + +const u32 pattern_mostly_one_x32[PATTERN_SIZE] = { + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF +}; + +#define NB_PATTERN 5 +static enum test_result test_freq_pattern(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + const u32 * const patterns_x16[NB_PATTERN] = { + pattern_div1_x16, + pattern_div2_x16, + pattern_div4_x16, + pattern_mostly_zero_x16, + pattern_mostly_one_x16, + }; + const u32 * const patterns_x32[NB_PATTERN] = { + pattern_div2_x16, + pattern_div4_x16, + pattern_div4_x32, + pattern_mostly_zero_x32, + pattern_mostly_one_x32 + }; + const char *patterns_comments[NB_PATTERN] = { + "switching at frequency F/1", + "switching at frequency F/2", + "switching at frequency F/4", + "mostly zero", + "mostly one" + }; + + enum test_result res = TEST_PASSED, pattern_res; + int i, bus_width; + const u32 **patterns; + u32 bufsize, addr; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 128)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 1, &addr)) + return TEST_ERROR; + + switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { + case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF: + case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER: + bus_width = 16; + break; + default: + bus_width = 32; + break; + } + + printf("running test pattern at 0x%08x length 0x%x width = %d\n", + addr, bufsize, bus_width); + + patterns = + (const u32 **)(bus_width == 16 ? patterns_x16 : patterns_x32); + + for (i = 0; i < NB_PATTERN; i++) { + printf("test data pattern %s:", patterns_comments[i]); + pattern_res = test_loop(patterns[i], (u32 *)addr, bufsize); + if (pattern_res != TEST_PASSED) { + printf("Failed\n"); + return pattern_res; + } + printf("Passed\n"); + } + + return res; +} + +/********************************************************************** + * + * Function: pattern test with size + * + * Description: loop for write pattern + * + **********************************************************************/ + +static enum test_result test_loop_size(const u32 *pattern, u32 size, + u32 *address, + const u32 bufsize) +{ + int i, j; + enum test_result res = TEST_PASSED; + u32 *p = address; + + for (i = 0; i < bufsize; i += size * 4) { + for (j = 0; j < size ; j++, p++) + *p = pattern[j]; + if (progress(i)) { + res = TEST_FAILED; + goto end; + } + } + + puts("\ncheck buffer"); + p = address; + for (i = 0; i < bufsize; i += size * 4) { + for (j = 0; j < size; j++, p++) + if (check_addr((u32)p, pattern[j])) { + res = TEST_FAILED; + goto end; + } + if (progress(i)) { + res = TEST_FAILED; + goto end; + } + } + +end: + puts("\n"); + return res; +} + +static enum test_result test_checkboard(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + enum test_result res = TEST_PASSED; + u32 bufsize, nb_loop, loop = 0, addr; + int i; + + u32 checkboard[2] = {0x55555555, 0xAAAAAAAA}; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 8)) + return TEST_ERROR; + if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + printf("running %d loops at 0x%08x length 0x%x\n", + nb_loop, addr, bufsize); + while (1) { + for (i = 0; i < 2; i++) { + res = test_loop_size(checkboard, 2, (u32 *)addr, + bufsize); + if (res) + return res; + checkboard[0] = ~checkboard[0]; + checkboard[1] = ~checkboard[1]; + } + if (test_loop_end(&loop, nb_loop, 1)) + break; + } + sprintf(string, "no error for %d loops at 0x%08x length 0x%x", + loop, addr, bufsize); + + return res; +} + +static enum test_result test_blockseq(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + enum test_result res = TEST_PASSED; + u32 bufsize, nb_loop, loop = 0, addr, value; + int i; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) + return TEST_ERROR; + if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + printf("running %d loops at 0x%08x length 0x%x\n", + nb_loop, addr, bufsize); + while (1) { + for (i = 0; i < 256; i++) { + value = i | i << 8 | i << 16 | i << 24; + printf("pattern = %08x", value); + res = test_loop_size(&value, 1, (u32 *)addr, bufsize); + if (res != TEST_PASSED) + return res; + } + if (test_loop_end(&loop, nb_loop, 1)) + break; + } + sprintf(string, "no error for %d loops at 0x%08x length 0x%x", + loop, addr, bufsize); + + return res; +} + +static enum test_result test_walkbit0(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + enum test_result res = TEST_PASSED; + u32 bufsize, nb_loop, loop = 0, addr, value; + int i; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) + return TEST_ERROR; + if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + printf("running %d loops at 0x%08x length 0x%x\n", + nb_loop, addr, bufsize); + while (1) { + for (i = 0; i < 64; i++) { + if (i < 32) + value = 1 << i; + else + value = 1 << (63 - i); + + printf("pattern = %08x", value); + res = test_loop_size(&value, 1, (u32 *)addr, bufsize); + if (res != TEST_PASSED) + return res; + } + if (test_loop_end(&loop, nb_loop, 1)) + break; + } + sprintf(string, "no error for %d loops at 0x%08x length 0x%x", + loop, addr, bufsize); + + return res; +} + +static enum test_result test_walkbit1(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + enum test_result res = TEST_PASSED; + u32 bufsize, nb_loop, loop = 0, addr, value; + int i; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 4)) + return TEST_ERROR; + if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + printf("running %d loops at 0x%08x length 0x%x\n", + nb_loop, addr, bufsize); + while (1) { + for (i = 0; i < 64; i++) { + if (i < 32) + value = ~(1 << i); + else + value = ~(1 << (63 - i)); + + printf("pattern = %08x", value); + res = test_loop_size(&value, 1, (u32 *)addr, bufsize); + if (res != TEST_PASSED) + return res; + } + if (test_loop_end(&loop, nb_loop, 1)) + break; + } + sprintf(string, "no error for %d loops at 0x%08x length 0x%x", + loop, addr, bufsize); + + return res; +} + +/* + * try to catch bad bits which are dependent on the current values of + * surrounding bits in either the same word32 + */ +static enum test_result test_bitspread(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + enum test_result res = TEST_PASSED; + u32 bufsize, nb_loop, loop = 0, addr, bitspread[4]; + int i, j; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 32)) + return TEST_ERROR; + if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + printf("running %d loops at 0x%08x length 0x%x\n", + nb_loop, addr, bufsize); + while (1) { + for (i = 1; i < 32; i++) { + for (j = 0; j < i; j++) { + if (i < 32) + bitspread[0] = (1 << i) | (1 << j); + else + bitspread[0] = (1 << (63 - i)) | + (1 << (63 - j)); + bitspread[1] = bitspread[0]; + bitspread[2] = ~bitspread[0]; + bitspread[3] = ~bitspread[0]; + printf("pattern = %08x", bitspread[0]); + + res = test_loop_size(bitspread, 4, (u32 *)addr, + bufsize); + if (res != TEST_PASSED) + return res; + } + } + if (test_loop_end(&loop, nb_loop, 1)) + break; + } + sprintf(string, "no error for %d loops at 0x%08x length 0x%x", + loop, addr, bufsize); + + return res; +} + +static enum test_result test_bitflip(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + enum test_result res = TEST_PASSED; + u32 bufsize, nb_loop, loop = 0, addr; + int i; + + u32 bitflip[4]; + + if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024, 32)) + return TEST_ERROR; + if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1)) + return TEST_ERROR; + if (get_addr(string, argc, argv, 2, &addr)) + return TEST_ERROR; + + printf("running %d loops at 0x%08x length 0x%x\n", + nb_loop, addr, bufsize); + while (1) { + for (i = 0; i < 32; i++) { + bitflip[0] = 1 << i; + bitflip[1] = bitflip[0]; + bitflip[2] = ~bitflip[0]; + bitflip[3] = bitflip[2]; + printf("pattern = %08x", bitflip[0]); + + res = test_loop_size(bitflip, 4, (u32 *)addr, bufsize); + if (res != TEST_PASSED) + return res; + } + if (test_loop_end(&loop, nb_loop, 1)) + break; + } + sprintf(string, "no error for %d loops at 0x%08x length 0x%x", + loop, addr, bufsize); + + return res; +} + +/********************************************************************** + * + * Function: infinite read access to DDR + * + * Description: continuous read the same pattern at the same address + * + **********************************************************************/ +static enum test_result test_read(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 *addr; + u32 data; + u32 loop = 0; + int i, size = 1024 * 1024; + bool random = false; + + if (get_addr(string, argc, argv, 0, (u32 *)&addr)) + return TEST_ERROR; + + if (get_pattern(string, argc, argv, 1, &data, 0xA5A5AA55)) + return TEST_ERROR; + + if ((u32)addr == ADDR_INVALID) { + printf("running random\n"); + random = true; + } else { + printf("running at 0x%08x with pattern=0x%08x\n", + (u32)addr, data); + writel(data, addr); + } + + while (1) { + for (i = 0; i < size; i++) { + if (random) + addr = (u32 *)(STM32_DDR_BASE + + (rand() & (STM32_DDR_SIZE - 1) & ~0x3)); + data = readl(addr); + } + if (test_loop_end(&loop, 0, 1)) + break; + } + if (random) + sprintf(string, "%d loops random", loop); + else + sprintf(string, "%d loops at 0x%x: %x", loop, (u32)addr, data); + + return TEST_PASSED; +} + +/********************************************************************** + * + * Function: infinite write access to DDR + * + * Description: continuous write the same pattern at the same address + * + **********************************************************************/ +static enum test_result test_write(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 *addr; + u32 data; + u32 loop = 0; + int i, size = 1024 * 1024; + bool random = false; + + if (get_addr(string, argc, argv, 0, (u32 *)&addr)) + return TEST_ERROR; + + if (get_pattern(string, argc, argv, 1, &data, 0xA5A5AA55)) + return TEST_ERROR; + + if ((u32)addr == ADDR_INVALID) { + printf("running random\n"); + random = true; + } else { + printf("running at 0x%08x with pattern 0x%08x\n", + (u32)addr, data); + } + + while (1) { + for (i = 0; i < size; i++) { + if (random) { + addr = (u32 *)(STM32_DDR_BASE + + (rand() & (STM32_DDR_SIZE - 1) & ~0x3)); + data = rand(); + } + writel(data, addr); + } + if (test_loop_end(&loop, 0, 1)) + break; + } + if (random) + sprintf(string, "%d loops random", loop); + else + sprintf(string, "%d loops at 0x%x: %x", loop, (u32)addr, data); + + return TEST_PASSED; +} + +#define NB_TEST_INFINITE 2 +static enum test_result test_all(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + enum test_result res = TEST_PASSED, result; + int i, j, nb_error = 0, len; + u32 loop = 0, nb_loop; + int argc_test; + char *argv_test[4]; + char loop_string[] = "1"; + char pattern_string[] = PATTERN_DEFAULT; + u32 *addr; + + if (get_nb_loop(string, argc, argv, 0, &nb_loop, 1)) + return TEST_ERROR; + + if (get_addr(string, argc, argv, 2, (u32 *)&addr)) + return TEST_ERROR; + + while (!nb_error) { + /* execute all the test except the lasts which are infinite */ + for (i = 1; i < test_nb - NB_TEST_INFINITE; i++) { + argc_test = 0; + j = 0; + len = strlen(test[i].usage); + if (argc > 1 && j < len && + !strncmp("[size]", &test[i].usage[j], 6)) { + argv_test[argc_test++] = argv[1]; + j += 7; + } + if (argc > 2) { + if (j < len && + !strncmp("[loop]", &test[i].usage[j], 6)) { + argv_test[argc_test++] = loop_string; + j += 7; + } + if (j < len && + !strncmp("[pattern]", &test[i].usage[j], + 9)) { + argv_test[argc_test++] = pattern_string; + j += 10; + } + if (j < len && + !strncmp("[addr]", &test[i].usage[j], 6)) { + argv_test[argc_test++] = argv[2]; + j += 7; + } + } + printf("execute %d:%s\n", (int)i, test[i].name); + result = test[i].fct(ctl, phy, string, + argc_test, argv_test); + printf("result %d:%s = ", (int)i, test[i].name); + if (result != TEST_PASSED) { + nb_error++; + res = TEST_FAILED; + puts("Failed"); + } else { + puts("Passed"); + } + puts("\n\n"); + } + printf("loop %d: %d/%d test failed\n\n\n", + loop + 1, nb_error, test_nb - NB_TEST_INFINITE); + if (test_loop_end(&loop, nb_loop, 1)) + break; + } + if (res != TEST_PASSED) { + sprintf(string, "loop %d: %d/%d test failed", loop, nb_error, + test_nb - NB_TEST_INFINITE); + } else { + sprintf(string, "loop %d: %d tests passed", loop, + test_nb - NB_TEST_INFINITE); + } + return res; +} + +/**************************************************************** + * TEST Description + ****************************************************************/ + +const struct test_desc test[] = { + {test_all, "All", "[loop] [size] [addr]", "Execute all tests", 3 }, + {test_databus, "Simple DataBus", "[addr]", + "Verifies each data line by walking 1 on fixed address", + 1 + }, + {databuswalk0, "DataBusWalking0", "[loop] [addr]", + "Verifies each data bus signal can be driven low (32 word burst)", + 2 + }, + {databuswalk1, "DataBusWalking1", "[loop] [addr]", + "Verifies each data bus signal can be driven high (32 word burst)", + 2 + }, + {test_addressbus, "AddressBus", "[size] [addr]", + "Verifies each relevant bits of the address and checking for aliasing", + 2 + }, + {test_memdevice, "MemDevice", "[size] [addr]", + "Test the integrity of a physical memory (test every storage bit in the region)", + 2 + }, + {test_sso, "SimultaneousSwitchingOutput", "[size] [addr] ", + "Stress the data bus over an address range", + 2 + }, + {test_noise, "Noise", "[pattern] [addr]", + "Verifies r/w while forcing switching of all data bus lines.", + 3 + }, + {test_noise_burst, "NoiseBurst", "[size] [pattern] [addr]", + "burst transfers while forcing switching of the data bus lines", + 3 + }, + {test_random, "Random", "[size] [loop] [addr]", + "Verifies r/w and memcopy(burst for pseudo random value.", + 3 + }, + {test_freq_pattern, "FrequencySelectivePattern", "[size] [addr]", + "write & test patterns: Mostly Zero, Mostly One and F/n", + 2 + }, + {test_blockseq, "BlockSequential", "[size] [loop] [addr]", + "test incremental pattern", + 3 + }, + {test_checkboard, "Checkerboard", "[size] [loop] [addr]", + "test checker pattern", + 3 + }, + {test_bitspread, "BitSpread", "[size] [loop] [addr]", + "test Bit Spread pattern", + 3 + }, + {test_bitflip, "BitFlip", "[size] [loop] [addr]", + "test Bit Flip pattern", + 3 + }, + {test_walkbit0, "WalkingOnes", "[size] [loop] [addr]", + "test Walking Ones pattern", + 3 + }, + {test_walkbit1, "WalkingZeroes", "[size] [loop] [addr]", + "test Walking Zeroes pattern", + 3 + }, + /* need to the the 2 last one (infinite) : skipped for test all */ + {test_read, "infinite read", "[addr] [pattern]", + "basic test : infinite read access (random: addr=0xFFFFFFFF)", 2}, + {test_write, "infinite write", "[addr] [pattern]", + "basic test : infinite write access (random: addr=0xFFFFFFFF)", 2}, +}; + +const int test_nb = ARRAY_SIZE(test); diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.h b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.h new file mode 100644 index 000000000..55f5d6d93 --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tests.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#ifndef _RAM_STM32MP1_TESTS_H_ +#define _RAM_STM32MP1_TESTS_H_ + +#include "stm32mp1_ddr_regs.h" + +enum test_result { + TEST_PASSED, + TEST_FAILED, + TEST_ERROR +}; + +struct test_desc { + enum test_result (*fct)(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, + int argc, char *argv[]); + const char *name; + const char *usage; + const char *help; + u8 max_args; +}; + +extern const struct test_desc test[]; +extern const int test_nb; + +extern const struct test_desc tuning[]; +extern const int tuning_nb; + +#endif diff --git a/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tuning.c b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tuning.c new file mode 100644 index 000000000..c8cd7c3ce --- /dev/null +++ b/roms/u-boot/drivers/ram/stm32mp1/stm32mp1_tuning.c @@ -0,0 +1,1540 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_RAM + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32mp1_ddr_regs.h" +#include "stm32mp1_ddr.h" +#include "stm32mp1_tests.h" + +#define MAX_DQS_PHASE_IDX _144deg +#define MAX_DQS_UNIT_IDX 7 +#define MAX_GSL_IDX 5 +#define MAX_GPS_IDX 3 + +/* Number of bytes used in this SW. ( min 1--> max 4). */ +#define NUM_BYTES 4 + +enum dqs_phase_enum { + _36deg = 0, + _54deg = 1, + _72deg = 2, + _90deg = 3, + _108deg = 4, + _126deg = 5, + _144deg = 6 +}; + +/* BIST Result struct */ +struct BIST_result { + /* Overall test result: + * 0 Fail (any bit failed) , + * 1 Success (All bits success) + */ + bool test_result; + /* 1: true, all fail / 0: False, not all bits fail */ + bool all_bits_fail; + bool bit_i_test_result[8]; /* 0 fail / 1 success */ +}; + +/* a struct that defines tuning parameters of a byte. */ +struct tuning_position { + u8 phase; /* DQS phase */ + u8 unit; /* DQS unit delay */ + u32 bits_delay; /* Bits deskew in this byte */ +}; + +/* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */ +const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12}; + +static u8 BIST_error_max = 1; +static u32 BIST_seed = 0x1234ABCD; + +static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl) +{ + u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK; + u8 nb_bytes = NUM_BYTES; + + switch (data_bus) { + case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF: + nb_bytes /= 2; + break; + case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER: + nb_bytes /= 4; + break; + default: + break; + } + + return nb_bytes; +} + +static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl) +{ + /* Count bank address bits */ + u8 bits = 0; + u32 reg, val; + + reg = readl(&ctl->addrmap1); + /* addrmap1.addrmap_bank_b1 */ + val = (reg & GENMASK(5, 0)) >> 0; + if (val <= 31) + bits++; + /* addrmap1.addrmap_bank_b2 */ + val = (reg & GENMASK(13, 8)) >> 8; + if (val <= 31) + bits++; + /* addrmap1.addrmap_bank_b3 */ + val = (reg & GENMASK(21, 16)) >> 16; + if (val <= 31) + bits++; + + return bits; +} + +static u8 get_nb_col(struct stm32mp1_ddrctl *ctl) +{ + u8 bits; + u32 reg, val; + + /* Count column address bits, start at 2 for b0 and b1 (fixed) */ + bits = 2; + + reg = readl(&ctl->addrmap2); + /* addrmap2.addrmap_col_b2 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b3 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b4 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b5 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + reg = readl(&ctl->addrmap3); + /* addrmap3.addrmap_col_b6 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b7 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b8 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b9 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + reg = readl(&ctl->addrmap4); + /* addrmap4.addrmap_col_b10 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap4.addrmap_col_b11 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + + return bits; +} + +static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) +{ + /* Count row address bits */ + u8 bits = 0; + u32 reg, val; + + reg = readl(&ctl->addrmap5); + /* addrmap5.addrmap_row_b0 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 11) + bits++; + /* addrmap5.addrmap_row_b1 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 11) + bits++; + /* addrmap5.addrmap_row_b2_10 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 11) + bits += 9; + else + printf("warning: addrmap5.addrmap_row_b2_10 not supported\n"); + /* addrmap5.addrmap_row_b11 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 11) + bits++; + + reg = readl(&ctl->addrmap6); + /* addrmap6.addrmap_row_b12 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b13 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b14 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b15 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + return bits; +} + +static void itm_soft_reset(struct stm32mp1_ddrphy *phy) +{ + stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST); +} + +/* Read DQ unit delay register and provides the retrieved value for DQS + * We are assuming that we have the same delay when clocking + * by DQS and when clocking by DQSN + */ +static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit) +{ + u32 index; + u32 addr = DXNDQTR(phy, byte); + + /* We are assuming that we have the same delay when clocking by DQS + * and when clocking by DQSN : use only the low bits + */ + index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)) + & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK; + + log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index); + + return index; +} + +/* Sets the DQS phase delay for a byte lane. + *phase delay is specified by giving the index of the desired delay + * in the dx_dll_phase array. + */ +static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx) +{ + u8 sdphase_val = 0; + + /* Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */ + sdphase_val = dx_dll_phase[phase_idx]; + clrsetbits_le32(DXNDLLCR(phy, byte), + DDRPHYC_DXNDLLCR_SDPHASE_MASK, + sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT); +} + +/* Sets the DQS unit delay for a byte lane. + * unit delay is specified by giving the index of the desired delay + * for dgsdly and dqsndly (same value). + */ +static void DQS_unit_delay(struct stm32mp1_ddrphy *phy, + u8 byte, u8 unit_dly_idx) +{ + /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */ + clrsetbits_le32(DXNDQSTR(phy, byte), + DDRPHYC_DXNDQSTR_DQSDLY_MASK | + DDRPHYC_DXNDQSTR_DQSNDLY_MASK, + (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) | + (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT)); + + /* After changing this value, an ITM soft reset (PIR.ITMSRST=1, + * plus PIR.INIT=1) must be issued. + */ + stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST); +} + +/* Sets the DQ unit delay for a bit line in particular byte lane. + * unit delay is specified by giving the desired delay + */ +static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy, + u8 byte, u8 bit, + u8 dq_delay_index) +{ + u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2); + + /* same value on delay for clock DQ an DQS_b */ + clrsetbits_le32(DXNDQTR(phy, byte), + DDRPHYC_DXNDQTR_DQDLY_MASK + << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit), + dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)); +} + +static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy, + u8 byte, u8 r0dgsl_idx) +{ + clrsetbits_le32(DXNDQSTR(phy, byte), + DDRPHYC_DXNDQSTR_R0DGSL_MASK, + r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT); +} + +static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy, + u8 byte, u8 r0dgps_idx) +{ + clrsetbits_le32(DXNDQSTR(phy, byte), + DDRPHYC_DXNDQSTR_R0DGPS_MASK, + r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT); +} + +/* Basic BIST configuration for data lane tests. */ +static void config_BIST(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy) +{ + u8 nb_bank = get_nb_bank(ctl); + u8 nb_row = get_nb_row(ctl); + u8 nb_col = get_nb_col(ctl); + + /* Selects the SDRAM bank address to be used during BIST. */ + u32 bbank = 0; + /* Selects the SDRAM row address to be used during BIST. */ + u32 brow = 0; + /* Selects the SDRAM column address to be used during BIST. */ + u32 bcol = 0; + /* Selects the value by which the SDRAM address is incremented + * for each write/read access. + */ + u32 bainc = 0x00000008; + /* Specifies the maximum SDRAM rank to be used during BIST. + * The default value is set to maximum ranks minus 1. + * must be 0 with single rank + */ + u32 bmrank = 0; + /* Selects the SDRAM rank to be used during BIST. + * must be 0 with single rank + */ + u32 brank = 0; + + /* Specifies the maximum SDRAM bank address to be used during + * BIST before the address & increments to the next rank. + */ + u32 bmbank = (1 << nb_bank) - 1; + /* Specifies the maximum SDRAM row address to be used during + * BIST before the address & increments to the next bank. + */ + u32 bmrow = (1 << nb_row) - 1; + /* Specifies the maximum SDRAM column address to be used during + * BIST before the address & increments to the next row. + */ + u32 bmcol = (1 << nb_col) - 1; + + u32 bmode_conf = 0x00000001; /* DRam mode */ + u32 bdxen_conf = 0x00000001; /* BIST on Data byte */ + u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */ + + /*Setup BIST for DRAM mode, and LFSR-random data pattern.*/ + /*Write BISTRR.BMODE = 1?b1;*/ + /*Write BISTRR.BDXEN = 1?b1;*/ + /*Write BISTRR.BDPAT = 2?b10;*/ + + /* reset BIST */ + writel(0x3, &phy->bistrr); + + writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17), + &phy->bistrr); + + /*Setup BIST Word Count*/ + /*Write BISTWCR.BWCNT = 16?b0008;*/ + writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */ + + writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0); + writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1); + writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2); +} + +/* Select the Byte lane to be tested by BIST. */ +static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8) +{ + clrsetbits_le32(&phy->bistrr, + DDRPHYC_BISTRR_BDXSEL_MASK, + datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT); + + /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/ + /* Write BISTRR.BDXSEL = datx8; */ +} + +/* Perform BIST Write_Read test on a byte lane and return test result. */ +static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte, + struct BIST_result *bist) +{ + bool result = true; /* BIST_SUCCESS */ + u32 cnt = 0; + u32 error = 0; + u32 val; + int ret; + + bist->test_result = true; + +run: + itm_soft_reset(phy); + + /*Perform BIST Reset*/ + /* Write BISTRR.BINST = 3?b011; */ + clrsetbits_le32(&phy->bistrr, + 0x00000007, + 0x00000003); + + /*Re-seed LFSR*/ + /* Write BISTLSR.SEED = 32'h1234ABCD; */ + if (BIST_seed) + writel(BIST_seed, &phy->bistlsr); + else + writel(rand(), &phy->bistlsr); + + /* some delay to reset BIST */ + udelay(10); + + /*Perform BIST Run*/ + clrsetbits_le32(&phy->bistrr, + 0x00000007, + 0x00000001); + /* Write BISTRR.BINST = 3?b001; */ + + /* poll on BISTGSR.BDONE and wait max 1000 us */ + ret = readl_poll_timeout(&phy->bistgsr, val, + val & DDRPHYC_BISTGSR_BDDONE, 1000); + + if (ret < 0) { + printf("warning: BIST timeout\n"); + result = false; /* BIST_FAIL; */ + /*Perform BIST Stop */ + clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002); + } else { + /*Check if received correct number of words*/ + /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */ + if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) + == readl(&phy->bistwcr)) { + /*Determine if there is a data comparison error*/ + /* if (Read BISTGSR.BDXERR = 1?b0) */ + if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR) + result = false; /* BIST_FAIL; */ + else + result = true; /* BIST_SUCCESS; */ + } else { + result = false; /* BIST_FAIL; */ + } + } + + /* loop while success */ + cnt++; + if (result && cnt != 1000) + goto run; + + if (!result) + error++; + + if (error < BIST_error_max) { + if (cnt != 1000) + goto run; + bist->test_result = true; + } else { + bist->test_result = false; + } +} + +/* After running the deskew algo, this function applies the new DQ delays + * by reading them from the array "deskew_delay"and writing in PHY registers. + * The bits that are not deskewed parfectly (too much skew on them, + * or data eye very wide) are marked in the array deskew_non_converge. + */ +static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte, + u8 deskew_delay[NUM_BYTES][8], + u8 deskew_non_converge[NUM_BYTES][8]) +{ + u8 bit_i; + u8 index; + + for (bit_i = 0; bit_i < 8; bit_i++) { + set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]); + index = DQ_unit_index(phy, byte, bit_i); + log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]", + byte, bit_i, deskew_delay[byte][bit_i], + index, index - 3); + printf("Byte %d, bit %d, DQ delay = %d", + byte, bit_i, deskew_delay[byte][bit_i]); + if (deskew_non_converge[byte][bit_i] == 1) + log_debug(" - not converged : still more skew"); + printf("\n"); + } +} + +/* DQ Bit de-skew algorithm. + * Deskews data lines as much as possible. + * 1. Add delay to DQS line until finding the failure + * (normally a hold time violation) + * 2. Reduce DQS line by small steps until finding the very first time + * we go back to "Pass" condition. + * 3. For each DQ line, Reduce DQ delay until finding the very first failure + * (normally a hold time fail) + * 4. When all bits are at their first failure delay, we can consider them + * aligned. + * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions + * at any step) + * TODO Provide a return Status. Improve doc + */ +static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, char *string) +{ + /* New DQ delay value (index), set during Deskew algo */ + u8 deskew_delay[NUM_BYTES][8]; + /*If there is still skew on a bit, mark this bit. */ + u8 deskew_non_converge[NUM_BYTES][8]; + struct BIST_result result; + s8 dqs_unit_delay_index = 0; + u8 datx8 = 0; + u8 bit_i = 0; + s8 phase_idx = 0; + s8 bit_i_delay_index = 0; + u8 success = 0; + struct tuning_position last_right_ok; + u8 force_stop = 0; + u8 fail_found; + u8 error = 0; + u8 nb_bytes = get_nb_bytes(ctl); + /* u8 last_pass_dqs_unit = 0; */ + + memset(deskew_delay, 0, sizeof(deskew_delay)); + memset(deskew_non_converge, 0, sizeof(deskew_non_converge)); + + /*Disable DQS Drift Compensation*/ + clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); + /*Disable all bytes*/ + /* Disable automatic power down of DLL and IOs when disabling + * a byte (To avoid having to add programming and delay + * for a DLL re-lock when later re-enabling a disabled Byte Lane) + */ + clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); + + /* Disable all data bytes */ + clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); + + /* Config the BIST block */ + config_BIST(ctl, phy); + log_debug("BIST Config done.\n"); + + /* Train each byte */ + for (datx8 = 0; datx8 < nb_bytes; datx8++) { + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + datx8 + 1, nb_bytes, error); + return TEST_FAILED; + } + log_debug("\n======================\n"); + log_debug("Start deskew byte %d .\n", datx8); + log_debug("======================\n"); + /* Enable Byte (DXNGCR, bit DXEN) */ + setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN); + + /* Select the byte lane for comparison of read data */ + BIST_datx8_sel(phy, datx8); + + /* Set all DQDLYn to maximum value. All bits within the byte + * will be delayed with DQSTR = 2 instead of max = 3 + * to avoid inter bits fail influence + */ + writel(0xAAAAAAAA, DXNDQTR(phy, datx8)); + + /* Set the DQS phase delay to 90 DEG (default). + * What is defined here is the index of the desired config + * in the PHASE array. + */ + phase_idx = _90deg; + + /* Set DQS unit delay to the max value. */ + dqs_unit_delay_index = MAX_DQS_UNIT_IDX; + DQS_unit_delay(phy, datx8, dqs_unit_delay_index); + DQS_phase_delay(phy, datx8, phase_idx); + + /* Issue a DLL soft reset */ + clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST); + setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST); + + /* Test this typical init condition */ + BIST_test(phy, datx8, &result); + success = result.test_result; + + /* If the test pass in this typical condition, + * start the algo with it. + * Else, look for Pass init condition + */ + if (!success) { + log_debug("Fail at init condtion. Let's look for a good init condition.\n"); + success = 0; /* init */ + /* Make sure we start with a PASS condition before + * looking for a fail condition. + * Find the first PASS PHASE condition + */ + + /* escape if we find a PASS */ + log_debug("increase Phase idx\n"); + while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) { + DQS_phase_delay(phy, datx8, phase_idx); + BIST_test(phy, datx8, &result); + success = result.test_result; + phase_idx++; + } + /* if ended with success + * ==>> Restore the fist success condition + */ + if (success) + phase_idx--; /* because it ended with ++ */ + } + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + datx8 + 1, nb_bytes, error); + return TEST_FAILED; + } + /* We couldn't find a successful condition, its seems + * we have hold violation, lets try reduce DQS_unit Delay + */ + if (!success) { + /* We couldn't find a successful condition, its seems + * we have hold violation, lets try reduce DQS_unit + * Delay + */ + log_debug("Still fail. Try decrease DQS Unit delay\n"); + + phase_idx = 0; + dqs_unit_delay_index = 0; + DQS_phase_delay(phy, datx8, phase_idx); + + /* escape if we find a PASS */ + while (!success && + (dqs_unit_delay_index <= + MAX_DQS_UNIT_IDX)) { + DQS_unit_delay(phy, datx8, + dqs_unit_delay_index); + BIST_test(phy, datx8, &result); + success = result.test_result; + dqs_unit_delay_index++; + } + if (success) { + /* Restore the first success condition*/ + dqs_unit_delay_index--; + /* last_pass_dqs_unit = dqs_unit_delay_index;*/ + DQS_unit_delay(phy, datx8, + dqs_unit_delay_index); + } else { + /* No need to continue, + * there is no pass region. + */ + force_stop = 1; + } + } + + /* There is an initial PASS condition + * Look for the first failing condition by PHASE stepping. + * This part of the algo can finish without converging. + */ + if (force_stop) { + printf("Result: Failed "); + printf("[Cannot Deskew lines, "); + printf("there is no PASS region]\n"); + error++; + continue; + } + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + datx8 + 1, nb_bytes, error); + return TEST_FAILED; + } + + log_debug("there is a pass region for phase idx %d\n", + phase_idx); + log_debug("Step1: Find the first failing condition\n"); + /* Look for the first failing condition by PHASE stepping. + * This part of the algo can finish without converging. + */ + + /* escape if we find a fail (hold time violation) + * condition at any bit or if out of delay range. + */ + while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) { + DQS_phase_delay(phy, datx8, phase_idx); + BIST_test(phy, datx8, &result); + success = result.test_result; + phase_idx++; + } + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + datx8 + 1, nb_bytes, error); + return TEST_FAILED; + } + + /* if the loop ended with a failing condition at any bit, + * lets look for the first previous success condition by unit + * stepping (minimal delay) + */ + if (!success) { + log_debug("Fail region (PHASE) found phase idx %d\n", + phase_idx); + log_debug("Let's look for first success by DQS Unit steps\n"); + /* This part, the algo always converge */ + phase_idx--; + + /* escape if we find a success condition + * or if out of delay range. + */ + while (!success && dqs_unit_delay_index >= 0) { + DQS_unit_delay(phy, datx8, + dqs_unit_delay_index); + BIST_test(phy, datx8, &result); + success = result.test_result; + dqs_unit_delay_index--; + } + /* if the loop ended with a success condition, + * the last delay Right OK (before hold violation) + * condition is then defined as following: + */ + if (success) { + /* Hold the dely parameters of the the last + * delay Right OK condition. + * -1 to get back to current condition + */ + last_right_ok.phase = phase_idx; + /*+1 to get back to current condition */ + last_right_ok.unit = dqs_unit_delay_index + 1; + last_right_ok.bits_delay = 0xFFFFFFFF; + log_debug("Found %d\n", dqs_unit_delay_index); + } else { + /* the last OK condition is then with the + * previous phase_idx. + * -2 instead of -1 because at the last + * iteration of the while(), + * we incremented phase_idx + */ + last_right_ok.phase = phase_idx - 1; + /* Nominal+1. Because we want the previous + * delay after reducing the phase delay. + */ + last_right_ok.unit = 1; + last_right_ok.bits_delay = 0xFFFFFFFF; + log_debug("Not Found : try previous phase %d\n", + phase_idx - 1); + + DQS_phase_delay(phy, datx8, phase_idx - 1); + dqs_unit_delay_index = 0; + success = true; + while (success && + (dqs_unit_delay_index < + MAX_DQS_UNIT_IDX)) { + DQS_unit_delay(phy, datx8, + dqs_unit_delay_index); + BIST_test(phy, datx8, &result); + success = result.test_result; + dqs_unit_delay_index++; + log_debug("dqs_unit_delay_index = %d, result = %d\n", + dqs_unit_delay_index, success); + } + + if (!success) { + last_right_ok.unit = + dqs_unit_delay_index - 1; + } else { + last_right_ok.unit = 0; + log_debug("ERROR: failed region not FOUND"); + } + } + } else { + /* we can't find a failing condition at all bits + * ==> Just hold the last test condition + * (the max DQS delay) + * which is the most likely, + * the closest to a hold violation + * If we can't find a Fail condition after + * the Pass region, stick at this position + * In order to have max chances to find a fail + * when reducing DQ delays. + */ + last_right_ok.phase = MAX_DQS_PHASE_IDX; + last_right_ok.unit = MAX_DQS_UNIT_IDX; + last_right_ok.bits_delay = 0xFFFFFFFF; + log_debug("Can't find the a fail condition\n"); + } + + /* step 2: + * if we arrive at this stage, it means that we found the last + * Right OK condition (by tweeking the DQS delay). Or we simply + * pushed DQS delay to the max + * This means that by reducing the delay on some DQ bits, + * we should find a failing condition. + */ + printf("Byte %d, DQS unit = %d, phase = %d\n", + datx8, last_right_ok.unit, last_right_ok.phase); + log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n", + last_right_ok.unit, last_right_ok.phase, + last_right_ok.bits_delay); + + /* Restore the last_right_ok condtion. */ + DQS_unit_delay(phy, datx8, last_right_ok.unit); + DQS_phase_delay(phy, datx8, last_right_ok.phase); + writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8)); + + /* train each bit + * reduce delay on each bit, and perform a write/read test + * and stop at the very first time it fails. + * the goal is the find the first failing condition + * for each bit. + * When we achieve this condition< for all the bits, + * we are sure they are aligned (+/- step resolution) + */ + fail_found = 0; + for (bit_i = 0; bit_i < 8; bit_i++) { + if (ctrlc()) { + sprintf(string, + "interrupted at byte %d/%d, error=%d", + datx8 + 1, nb_bytes, error); + return error; + } + log_debug("deskewing bit %d:\n", bit_i); + success = 1; /* init */ + /* Set all DQDLYn to maximum value. + * Only bit_i will be down-delayed + * ==> if we have a fail, it will be definitely + * from bit_i + */ + writel(0xFFFFFFFF, DXNDQTR(phy, datx8)); + /* Arriving at this stage, + * we have a success condition with delay = 3; + */ + bit_i_delay_index = 3; + + /* escape if bit delay is out of range or + * if a fatil occurs + */ + while ((bit_i_delay_index >= 0) && success) { + set_DQ_unit_delay(phy, datx8, + bit_i, + bit_i_delay_index); + BIST_test(phy, datx8, &result); + success = result.test_result; + bit_i_delay_index--; + } + + /* if escape with a fail condition + * ==> save this position for bit_i + */ + if (!success) { + /* save the delay position. + * Add 1 because the while loop ended with a --, + * and that we need to hold the last success + * delay + */ + deskew_delay[datx8][bit_i] = + bit_i_delay_index + 2; + if (deskew_delay[datx8][bit_i] > 3) + deskew_delay[datx8][bit_i] = 3; + + /* A flag that states we found at least a fail + * at one bit. + */ + fail_found = 1; + log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n", + bit_i, bit_i_delay_index + 1, + datx8, bit_i, + deskew_delay[datx8][bit_i]); + } else { + /* if we can find a success condition by + * back-delaying this bit, just set the delay + * to 0 (the best deskew + * possible) and mark the bit. + */ + deskew_delay[datx8][bit_i] = 0; + /* set a flag that will be used later + * in the report. + */ + deskew_non_converge[datx8][bit_i] = 1; + log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n", + bit_i, datx8, bit_i, + deskew_delay[datx8][bit_i]); + } + } + log_debug("**********byte %d tuning complete************\n", + datx8); + /* If we can't find any failure by back delaying DQ lines, + * hold the default values + */ + if (!fail_found) { + for (bit_i = 0; bit_i < 8; bit_i++) + deskew_delay[datx8][bit_i] = 0; + log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n"); + } + + apply_deskew_results(phy, datx8, deskew_delay, + deskew_non_converge); + /* Restore nominal value for DQS delay */ + DQS_phase_delay(phy, datx8, 3); + DQS_unit_delay(phy, datx8, 3); + /* disable byte after byte bits deskew */ + clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN); + } /* end of byte deskew */ + + /* re-enable all data bytes */ + setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); + setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); + setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); + setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); + + if (error) { + sprintf(string, "error = %d", error); + return TEST_FAILED; + } + + return TEST_PASSED; +} /* end function */ + +/* Trim DQS timings and set it in the centre of data eye. + * Look for a PPPPF region, then look for a FPPP region and finally select + * the mid of the FPPPPPF region + */ +static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, char *string) +{ + /*Stores the DQS trim values (PHASE index, unit index) */ + u8 eye_training_val[NUM_BYTES][2]; + u8 byte = 0; + struct BIST_result result; + s8 dqs_unit_delay_index = 0; + s8 phase_idx = 0; + s8 dqs_unit_delay_index_pass = 0; + s8 phase_idx_pass = 0; + u8 success = 0; + u8 left_phase_bound_found, right_phase_bound_found; + u8 left_unit_bound_found, right_unit_bound_found; + u8 left_bound_found, right_bound_found; + struct tuning_position left_bound, right_bound; + u8 error = 0; + u8 nb_bytes = get_nb_bytes(ctl); + + /*Disable DQS Drift Compensation*/ + clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); + /*Disable all bytes*/ + /* Disable automatic power down of DLL and IOs when disabling a byte + * (To avoid having to add programming and delay + * for a DLL re-lock when later re-enabling a disabled Byte Lane) + */ + clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); + + /*Disable all data bytes */ + clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); + + /* Config the BIST block */ + config_BIST(ctl, phy); + + for (byte = 0; byte < nb_bytes; byte++) { + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + byte + 1, nb_bytes, error); + return TEST_FAILED; + } + right_bound.phase = 0; + right_bound.unit = 0; + + left_bound.phase = 0; + left_bound.unit = 0; + + left_phase_bound_found = 0; + right_phase_bound_found = 0; + + left_unit_bound_found = 0; + right_unit_bound_found = 0; + + left_bound_found = 0; + right_bound_found = 0; + + /* Enable Byte (DXNGCR, bit DXEN) */ + setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN); + + /* Select the byte lane for comparison of read data */ + BIST_datx8_sel(phy, byte); + + /* Set DQS phase delay to the nominal value. */ + phase_idx = _90deg; + phase_idx_pass = phase_idx; + + /* Set DQS unit delay to the nominal value. */ + dqs_unit_delay_index = 3; + dqs_unit_delay_index_pass = dqs_unit_delay_index; + success = 0; + + log_debug("STEP0: Find Init delay\n"); + /* STEP0: Find Init delay: a delay that put the system + * in a "Pass" condition then (TODO) update + * dqs_unit_delay_index_pass & phase_idx_pass + */ + DQS_unit_delay(phy, byte, dqs_unit_delay_index); + DQS_phase_delay(phy, byte, phase_idx); + BIST_test(phy, byte, &result); + success = result.test_result; + /* If we have a fail in the nominal condition */ + if (!success) { + /* Look at the left */ + while (phase_idx >= 0 && !success) { + phase_idx--; + DQS_phase_delay(phy, byte, phase_idx); + BIST_test(phy, byte, &result); + success = result.test_result; + } + } + if (!success) { + /* if we can't find pass condition, + * then look at the right + */ + phase_idx = _90deg; + while (phase_idx <= MAX_DQS_PHASE_IDX && + !success) { + phase_idx++; + DQS_phase_delay(phy, byte, + phase_idx); + BIST_test(phy, byte, &result); + success = result.test_result; + } + } + /* save the pass condition */ + if (success) { + phase_idx_pass = phase_idx; + } else { + printf("Result: Failed "); + printf("[Cannot DQS timings, "); + printf("there is no PASS region]\n"); + error++; + continue; + } + + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + byte + 1, nb_bytes, error); + return TEST_FAILED; + } + log_debug("STEP1: Find LEFT PHASE DQS Bound\n"); + /* STEP1: Find LEFT PHASE DQS Bound */ + while ((phase_idx >= 0) && + (phase_idx <= MAX_DQS_PHASE_IDX) && + !left_phase_bound_found) { + DQS_unit_delay(phy, byte, + dqs_unit_delay_index); + DQS_phase_delay(phy, byte, + phase_idx); + BIST_test(phy, byte, &result); + success = result.test_result; + + /*TODO: Manage the case were at the beginning + * there is already a fail + */ + if (!success) { + /* the last pass condition */ + left_bound.phase = ++phase_idx; + left_phase_bound_found = 1; + } else if (success) { + phase_idx--; + } + } + if (!left_phase_bound_found) { + left_bound.phase = 0; + phase_idx = 0; + } + /* If not found, lets take 0 */ + + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + byte + 1, nb_bytes, error); + return TEST_FAILED; + } + log_debug("STEP2: Find UNIT left bound\n"); + /* STEP2: Find UNIT left bound */ + while ((dqs_unit_delay_index >= 0) && + !left_unit_bound_found) { + DQS_unit_delay(phy, byte, + dqs_unit_delay_index); + DQS_phase_delay(phy, byte, phase_idx); + BIST_test(phy, byte, &result); + success = result.test_result; + if (!success) { + left_bound.unit = + ++dqs_unit_delay_index; + left_unit_bound_found = 1; + left_bound_found = 1; + } else if (success) { + dqs_unit_delay_index--; + } + } + + /* If not found, lets take 0 */ + if (!left_unit_bound_found) + left_bound.unit = 0; + + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + byte + 1, nb_bytes, error); + return TEST_FAILED; + } + log_debug("STEP3: Find PHase right bound\n"); + /* STEP3: Find PHase right bound, start with "pass" + * condition + */ + + /* Set DQS phase delay to the pass value. */ + phase_idx = phase_idx_pass; + + /* Set DQS unit delay to the pass value. */ + dqs_unit_delay_index = dqs_unit_delay_index_pass; + + while ((phase_idx <= MAX_DQS_PHASE_IDX) && + !right_phase_bound_found) { + DQS_unit_delay(phy, byte, + dqs_unit_delay_index); + DQS_phase_delay(phy, byte, phase_idx); + BIST_test(phy, byte, &result); + success = result.test_result; + if (!success) { + /* the last pass condition */ + right_bound.phase = --phase_idx; + right_phase_bound_found = 1; + } else if (success) { + phase_idx++; + } + } + + /* If not found, lets take the max value */ + if (!right_phase_bound_found) { + right_bound.phase = MAX_DQS_PHASE_IDX; + phase_idx = MAX_DQS_PHASE_IDX; + } + + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d, error=%d", + byte + 1, nb_bytes, error); + return TEST_FAILED; + } + log_debug("STEP4: Find UNIT right bound\n"); + /* STEP4: Find UNIT right bound */ + while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) && + !right_unit_bound_found) { + DQS_unit_delay(phy, byte, + dqs_unit_delay_index); + DQS_phase_delay(phy, byte, phase_idx); + BIST_test(phy, byte, &result); + success = result.test_result; + if (!success) { + right_bound.unit = + --dqs_unit_delay_index; + right_unit_bound_found = 1; + right_bound_found = 1; + } else if (success) { + dqs_unit_delay_index++; + } + } + /* If not found, lets take the max value */ + if (!right_unit_bound_found) + right_bound.unit = MAX_DQS_UNIT_IDX; + + /* If we found a regular FAil Pass FAil pattern + * FFPPPPPPFF + * OR PPPPPFF Or FFPPPPP + */ + + if (left_bound_found || right_bound_found) { + eye_training_val[byte][0] = (right_bound.phase + + left_bound.phase) / 2; + eye_training_val[byte][1] = (right_bound.unit + + left_bound.unit) / 2; + + /* If we already lost 1/2PHASE Tuning, + * let's try to recover by ++ on unit + */ + if (((right_bound.phase + left_bound.phase) % 2 == 1) && + eye_training_val[byte][1] != MAX_DQS_UNIT_IDX) + eye_training_val[byte][1]++; + log_debug("** found phase : %d - %d & unit %d - %d\n", + right_bound.phase, left_bound.phase, + right_bound.unit, left_bound.unit); + log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n", + eye_training_val[byte][0], + eye_training_val[byte][1]); + } else { + /* PPPPPPPPPP, we're already good. + * Set nominal values. + */ + eye_training_val[byte][0] = 3; + eye_training_val[byte][1] = 3; + } + DQS_phase_delay(phy, byte, eye_training_val[byte][0]); + DQS_unit_delay(phy, byte, eye_training_val[byte][1]); + + printf("Byte %d, DQS unit = %d, phase = %d\n", + byte, + eye_training_val[byte][1], + eye_training_val[byte][0]); + } + + if (error) { + sprintf(string, "error = %d", error); + return TEST_FAILED; + } + + return TEST_PASSED; +} + +static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte) +{ + u8 i = 0; + + printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n ", + byte); + + for (i = 0; i < 8; i++) + printf("%d ", DQ_unit_index(phy, byte, i)); + printf("\n"); + + printf("dxndllcr: [%08x] val:%08x\n", + DXNDLLCR(phy, byte), + readl(DXNDLLCR(phy, byte))); + printf("dxnqdstr: [%08x] val:%08x\n", + DXNDQSTR(phy, byte), + readl(DXNDQSTR(phy, byte))); + printf("dxndqtr: [%08x] val:%08x\n", + DXNDQTR(phy, byte), + readl(DXNDQTR(phy, byte))); +} + +/* analyse the dgs gating log table, and determine the midpoint.*/ +static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte, + u8 dqs_gating[NUM_BYTES] + [MAX_GSL_IDX + 1] + [MAX_GPS_IDX + 1]) +{ + /* stores the dqs gate values (gsl index, gps index) */ + u8 dqs_gate_values[NUM_BYTES][2]; + u8 gsl_idx, gps_idx = 0; + u8 left_bound_idx[2] = {0, 0}; + u8 right_bound_idx[2] = {0, 0}; + u8 left_bound_found = 0; + u8 right_bound_found = 0; + u8 intermittent = 0; + u8 value; + + for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) { + for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) { + value = dqs_gating[byte][gsl_idx][gps_idx]; + if (value == 1 && left_bound_found == 0) { + left_bound_idx[0] = gsl_idx; + left_bound_idx[1] = gps_idx; + left_bound_found = 1; + } else if (value == 0 && + left_bound_found == 1 && + !right_bound_found) { + if (gps_idx == 0) { + right_bound_idx[0] = gsl_idx - 1; + right_bound_idx[1] = MAX_GPS_IDX; + } else { + right_bound_idx[0] = gsl_idx; + right_bound_idx[1] = gps_idx - 1; + } + right_bound_found = 1; + } else if (value == 1 && + right_bound_found == 1) { + intermittent = 1; + } + } + } + + /* if only ppppppp is found, there is no mid region. */ + if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 && + right_bound_idx[0] == 0 && right_bound_idx[1] == 0) + intermittent = 1; + + /*if we found a regular fail pass fail pattern ffppppppff + * or pppppff or ffppppp + */ + if (!intermittent) { + /*if we found a regular fail pass fail pattern ffppppppff + * or pppppff or ffppppp + */ + if (left_bound_found || right_bound_found) { + log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n", + left_bound_found, + right_bound_idx[0], left_bound_idx[0], + right_bound_found, + right_bound_idx[1], left_bound_idx[1]); + dqs_gate_values[byte][0] = + (right_bound_idx[0] + left_bound_idx[0]) / 2; + dqs_gate_values[byte][1] = + (right_bound_idx[1] + left_bound_idx[1]) / 2; + /* if we already lost 1/2gsl tuning, + * let's try to recover by ++ on gps + */ + if (((right_bound_idx[0] + + left_bound_idx[0]) % 2 == 1) && + dqs_gate_values[byte][1] != MAX_GPS_IDX) + dqs_gate_values[byte][1]++; + /* if we already lost 1/2gsl tuning and gps is on max*/ + else if (((right_bound_idx[0] + + left_bound_idx[0]) % 2 == 1) && + dqs_gate_values[byte][1] == MAX_GPS_IDX) { + dqs_gate_values[byte][1] = 0; + dqs_gate_values[byte][0]++; + } + /* if we have gsl left and write limit too close + * (difference=1) + */ + if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) { + dqs_gate_values[byte][1] = (left_bound_idx[1] + + right_bound_idx[1] + + 4) / 2; + if (dqs_gate_values[byte][1] >= 4) { + dqs_gate_values[byte][0] = + right_bound_idx[0]; + dqs_gate_values[byte][1] -= 4; + } else { + dqs_gate_values[byte][0] = + left_bound_idx[0]; + } + } + log_debug("*******calculating mid region: system latency: %d phase: %d********\n", + dqs_gate_values[byte][0], + dqs_gate_values[byte][1]); + log_debug("*******the nominal values were system latency: 0 phase: 2*******\n"); + } + } else { + /* if intermitant, restore defaut values */ + log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n"); + dqs_gate_values[byte][0] = 0; + dqs_gate_values[byte][1] = 2; + } + set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]); + set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]); + printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n", + byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]); + + /* return 0 if intermittent or if both left_bound + * and right_bound are not found + */ + return !(intermittent || (left_bound_found && right_bound_found)); +} + +static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string) +{ + /* stores the log of pass/fail */ + u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1]; + u8 byte, gsl_idx, gps_idx = 0; + struct BIST_result result; + u8 success = 0; + u8 nb_bytes = get_nb_bytes(ctl); + + memset(dqs_gating, 0x0, sizeof(dqs_gating)); + + /*disable dqs drift compensation*/ + clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); + /*disable all bytes*/ + /* disable automatic power down of dll and ios when disabling a byte + * (to avoid having to add programming and delay + * for a dll re-lock when later re-enabling a disabled byte lane) + */ + clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); + + /* disable all data bytes */ + clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); + clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); + + /* config the bist block */ + config_BIST(ctl, phy); + + for (byte = 0; byte < nb_bytes; byte++) { + if (ctrlc()) { + sprintf(string, "interrupted at byte %d/%d", + byte + 1, nb_bytes); + return TEST_FAILED; + } + /* enable byte x (dxngcr, bit dxen) */ + setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN); + + /* select the byte lane for comparison of read data */ + BIST_datx8_sel(phy, byte); + for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) { + for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) { + if (ctrlc()) { + sprintf(string, + "interrupted at byte %d/%d", + byte + 1, nb_bytes); + return TEST_FAILED; + } + /* write cfg to dxndqstr */ + set_r0dgsl_delay(phy, byte, gsl_idx); + set_r0dgps_delay(phy, byte, gps_idx); + + BIST_test(phy, byte, &result); + success = result.test_result; + if (success) + dqs_gating[byte][gsl_idx][gps_idx] = 1; + itm_soft_reset(phy); + } + } + set_midpoint_read_dqs_gating(phy, byte, dqs_gating); + /* dummy reads */ + readl(0xc0000000); + readl(0xc0000000); + } + + /* re-enable drift compensation */ + /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */ + return TEST_PASSED; +} + +/**************************************************************** + * TEST + **************************************************************** + */ +static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, + char *argv[]) +{ + u32 rfshctl3 = readl(&ctl->rfshctl3); + u32 pwrctl = readl(&ctl->pwrctl); + u32 derateen = readl(&ctl->derateen); + enum test_result res; + + writel(0x0, &ctl->derateen); + stm32mp1_refresh_disable(ctl); + + res = read_dqs_gating(ctl, phy, string); + + stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); + writel(derateen, &ctl->derateen); + + return res; +} + +static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 rfshctl3 = readl(&ctl->rfshctl3); + u32 pwrctl = readl(&ctl->pwrctl); + u32 derateen = readl(&ctl->derateen); + enum test_result res; + + writel(0x0, &ctl->derateen); + stm32mp1_refresh_disable(ctl); + + res = bit_deskew(ctl, phy, string); + + stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); + writel(derateen, &ctl->derateen); + + return res; +} + +static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + u32 rfshctl3 = readl(&ctl->rfshctl3); + u32 pwrctl = readl(&ctl->pwrctl); + u32 derateen = readl(&ctl->derateen); + enum test_result res; + + writel(0x0, &ctl->derateen); + stm32mp1_refresh_disable(ctl); + + res = eye_training(ctl, phy, string); + + stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); + writel(derateen, &ctl->derateen); + + return res; +} + +static enum test_result do_display(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + int byte; + u8 nb_bytes = get_nb_bytes(ctl); + + for (byte = 0; byte < nb_bytes; byte++) + display_reg_results(phy, byte); + + return TEST_PASSED; +} + +static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl, + struct stm32mp1_ddrphy *phy, + char *string, int argc, char *argv[]) +{ + unsigned long value; + + if (argc > 0) { + if (strict_strtoul(argv[0], 0, &value) < 0) { + sprintf(string, "invalid nbErr %s", argv[0]); + return TEST_FAILED; + } + BIST_error_max = value; + } + if (argc > 1) { + if (strict_strtoul(argv[1], 0, &value) < 0) { + sprintf(string, "invalid Seed %s", argv[1]); + return TEST_FAILED; + } + BIST_seed = value; + } + printf("Bist.nbErr = %d\n", BIST_error_max); + if (BIST_seed) + printf("Bist.Seed = 0x%x\n", BIST_seed); + else + printf("Bist.Seed = random\n"); + + return TEST_PASSED; +} + +/**************************************************************** + * TEST Description + **************************************************************** + */ + +const struct test_desc tuning[] = { + {do_read_dqs_gating, "Read DQS gating", + "software read DQS Gating", "", 0 }, + {do_bit_deskew, "Bit de-skew", "", "", 0 }, + {do_eye_training, "Eye Training", "or DQS training", "", 0 }, + {do_display, "Display registers", "", "", 0 }, + {do_bist_config, "Bist config", "[nbErr] [seed]", + "configure Bist test", 2}, +}; + +const int tuning_nb = ARRAY_SIZE(tuning); -- cgit